WO2007128075A2

WO2007128075A2 - Method and apparatus for manufacture of semiconductors and resulting structures, devices, circuits, and components

Info

Publication number: WO2007128075A2
Application number: PCT/AU2007/000613
Authority: WO
Inventors: Shaun Joseph Cunningham
Original assignee: Epitactix Pty Ltd
Priority date: 2006-05-08
Filing date: 2007-05-08
Publication date: 2007-11-15
Also published as: WO2007128075A3

Abstract

The present invention relates to semiconductor structures, devices, circuits and components and the manufacture or fabrication of same. In one form, the invention is suitable for use in structures, devices, integrated circuits, components and manufacturing processes relating to compound semiconductor materials such as gallium arsenide (GaAs) and may equally apply to other semiconductor materials such as, for instance, indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC) and also silicon (Si). A first embodiment relates, in particular, to improved means of fabrication of bipolar transistor devices such as for example, npn and pnp bipolar transistors in a single process. A second preferred embodiment is related in general to control mechanisms for use in relation to HBT's, for example those used in power amplifiers. A third preferred embodiment provides a manufacturing method and structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size, reduced manufacturing complexity and increased operating voltage. Fourth and fifth preferred embodiment relates to integrated HBT/FET fabrication technologies.

Description

METHOD AND APPARATUS FOR MANUFACTURE OF SEMICONDUCTORS AND RESULTING STRUCTURES, DEVICES, CIRCUITS, AND COMPONENTS FIELD OF INVENTION

The present invention relates to semiconductor structures, devices, circuits and components and the manufacture or fabrication of same. In one form, the invention is suitable for use in structures, devices, integrated circuits, components and manufacturing processes relating to compound semiconductor materials such as gallium arsenide (GaAs) and it will be convenient to hereinafter describe the invention in relation to that application. It should be appreciated, however, that the present invention is not limited to that application, only. BACKGROUND ART

The discussion throughout this specification comes about due to the realisation of the inventor and/or the identification by the inventor of certain related art and its problems. Accordingly, the inventor has identified the following as related art.

Designers of high performance integrated circuits often require both npn and pnp transistors to implement complex circuit functions. Conventionally, these are known as complementary transistors. For many years designers of silicon chips have had access to such complementary devices. However, this is not necessarily the case in the area of compound semiconductor device design. Designers may regularly use npn devices made from materials such as gallium arsenide (GaAs) but rarely have access to the complimentary pnp devices. This is because pnp devices may be difficult and costly to fabricate within the same process. The problem of manufacturing to include the option of providing pnp devices relates to the difficulty of arranging p-doped and n-doped compound semiconductor layers in a sequence that can be used to make both types of device. In particular, it may be unacceptable for npn transistor performance to be compromised in any way by the introduction of epi-layers on the surface of a wafer that may be required to make pnp transistors, however this may often unavoidably be the case. It is also undesirable to remedy this by adding complexity to the fabrication process which may adversely affect cost.

Attempts at making complementary compound semiconductor HBTs have used lateral structures for both pnp and npn devices. For example US patent No 5,362,657 entitled "Lateral complementary heterojunction bipolar transistor and processing procedure" granted to Henderson et al describes lateral GaAs / InGaAs/GaAs HBTs. Although this innovation provides complementary devices, both types of device are lateral, that is: they are arranged with their conductive regions distributed across the surface of the wafer. In this respect, lateral devices have a significant drawback, namely that the emitter, base and collector regions of the device are restricted to certain physical dimensions allowed by photolithography. This means that device dimensions may not be reduced to anywhere near the limits that may be achieved in conventional HBTs having conductive regions that are grown layer by layer on the surface of a wafer in a vertical arrangement. Hence, for example, the high frequency performance of lateral devices may be significantly lower than that of conventional devices. i Circuit designers also often need components other than transistors per se such as varactor diodes. These devices may, for example, be useful in controlling the frequency of osciliators and in providing capacitive correction for certain types of circuits.

In general, there may be a number of difficulties faced in fabricating and producing integrated circuits comprising, for example, HBT based devices. For instance, there is a requirement to provide well defined layers which in turn calls for accurate etching of materials. Given there are various materials used to produce functional devices, the processes for etching are not necessarily straightforward. For example, means may be required for stopping the etch process at a known point being ordinarily the surface of a particular layer and controls are also required for the etch process to prevent the etch process continuing into further or other material layers which would reduce the desired properties of the formed layers. It is also desirable to provide for control over the formation of layers giving the ability of forming devices for specific purposes. Defining and confining regions of certain materials within the layered arrangements may be problematic given the nature of materials and etching processes. The inventor has recognised that manufacturers of conventional compound semiconductor devices may encounter difficulties when etching away portions of the epi-layers on the surface of wafers, particularly if the etching depth can only be controlled by etch timing. This may lead to a situation that creates process and device variability which may compromise device yield.

The inventor has also identified that HBTs made from materials such as Gallium Arsenide (GaAs) are known to have thermal instability issues when multiple devices are connected in parallel. These issues may be considered as related to the characteristic that, when a HBT gets hot, Its base emitter voltage is reduced, and can potentially draw more current from the bias supply, thereby causing the device to conduct more current and making it even hotter. This undesired positive feedback characteristic is known as thermal runaway and can be destructive. One approach to solve this problem is to introduce a series resistor in the emitter of the HBT. This may create a degree of negative feedback and stabilises the device's operating point, However this also reduces gain available from the HBT which is undesirable. Another approach commonly used is to put a resistor in series with the base of the HBT. An example circuit using this approach is shown in figure 15a with reference to resistor R2. This allows maximum gain to be obtained from the HBT but creates the problem that this resistor needs to be bypassed for the RF signal applied to the base of the transistor. The capacitor/capacitance, C1 in figure 15a, required for this is likely to be physically large and will take up a significant amount of the chip's space, thereby increasing chip cost. There is therefore a need for improved methods of controlling the bias point of HBTs when connected in parallel, for example, in power amplifying circuits.

The inventor has also identified that compound semiconductor material systems based on gallium arsenide (GaAs), indium phosphide (InP) and other elemental compounds have been widely used in the manufacture of high performance HBTs. In this regard, epitaxial layers may be grown on wafers made from these materials at the beginning of the manufacturing process and then patterned to form individual HBT devices. The choice of materials for these epitaxial layers is often taken into account such that the resulting device performance is optimised. On gallium arsenide wafers for example, related art HBTs may be made using layers of materials such as indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminium gallium arsenide (AiGaAs) and aluminium arsenide (AIAs). On indium phosphide wafers, HBTs may be made using indium gallium arsenide material. In each case the materials are chosen to achieve desired electrical properties of the transistors and desired chemical properties for the fabrication process. Although there have been significant improvements in related art fabrication processes, many limitations still exist and additional improvement is desired. Figure 1 shows a typical layer structure used to form related art npn GaAs HBTs. Typically, layer structures are devised which not only achieve desired electronic properties of a transistor but which also offer wafer processing advantages such as selective etching. Selective etching techniques allow one layer to be removed in certain areas of the wafer without affecting underlying or surrounding layers. This may be particularly important in controlling etching processes which need to stop abruptly on the boundaries of layers which might be very thin (e.g. 100 - 500 angstroms).

Transistor performance may not only be determined by the choice of layer material but also layer thickness. Selection of layer thickness may sometimes involve a compromise between certain transistor parameters. For example, in related art devices, high speed devices often need thin layers to shorten electron transit times while high power devices generally need thick layers to withstand high voltages. Therefore, in genera!, it is not possible to easily completely optimise a transistor for both high speed and high operating voltage. Typical layer thicknesses for npn GaAs / InGaP HBT devices are also shown in Figure 1 , which is not drawn to scale. Transistor performance may also be affected by device geometry. For example it is advantageous to make devices as small as possible in order to maximise their operating frequency. As devices become smaller, their maximum operating frequency increases because both junction capacitance and spreading resistance are reduced by making the device smaller. Spreading resistance is the resistance encountered between the lateral base contacts and the central, active area of the device due to the resistivity of typical semiconductor materials and the physical displacement of the contacts. Figure 2 provides an example of a certain related art device structure. The emitter mesa structure 200 of figure 2 is comprised of four semiconductor layers:

• layer 204 forms the emitter side of the emitter/base heterojunction and is made of a material which has different etching characteristics than the adjacent layers, • layer 203 is a buffer/spacer layer,

• layer 202 is a graded structure which varies from the crystal lattice spacing of GaAs at the interface to layer 203 to the lattice spacing of InGaAs (50% Ga) at the interface to layer 201 , and • layer 201 which allows a non-alloyed ohmic contact to be made to the emitter structure.

The emitter mesa 200 may be formed by firstly depositing and patterning emitter contact layer 205 on the surface of a wafer which has a layer structure as shown in Figure 1. Next, emitter layers 201 , 202 and 203 are selectively etched by way of being etched away except where protected by the emitter contact 205. Etching stops at layer 204 because it is unaffected by the etchant used to remove layers 201 - 203. However etching continues horizontally and helps to produce undercut sidewalls of the emitter mesa structure.

Layer 204 may then be selectively removed using an etchant which does not affect the underlying base layer 207. In this way, the emitter mesa can be formed without degrading the very thin base layer 207. The base contact layer 206b may be deposited over the entire base and emitter area using a directional deposition process. Since the sidewalls of the emitter mesa structure are undercut, the emitter contact layer 205 creates a shadow which allows the base contact layer 206b to be deposited in close proximity to the emitter without touching it, except harmlessly on top of the emitter ohmic, 206a. In this fashion, related art devices may achieve self alignment of base emitter junction connections thereby enhancing device performance by minimising base spreading resistance. A problem may be often encountered in the above process, however. The etching profile of the emitter mesa is determined by the crystalline structure of the emitter layers. This can cause the emitter to be etched differently in X and Y dimensions corresponding to the plane of the layers as shown in Figure 3. The side view of the emitter mesa looking along the Y axis 301 shows etching profile 303 caused by the crystal orientation in this dimension. The emitter mesa is undercut on these sides with respect to the emitter contact. This creates a shadow during base contact 302 deposition which ensures separation 304 from the emitter mesa. The side view of the same emitter mesa looking along the X axis 311 shows a different etching profile 313 caused by the crystal orientation. If the emitter contact bonds to the top surface well, it can prevent the mesa from being etched along the crystal plane originating from this point. This means that the sidewalis of the emitter mesa can protrude outside the perimeter of the emitter contact such that the base contact 312 comes into contact with the emitter mesa causing unwanted parasitic junctions 314 to form. These parasitic junctions may be a significant problem which limits device and circuit yields in related art HBT fabrication.

Manufacturers of related art HBTs may also experience problems in making connections to emitter contacts because they are vertically displaced from the insulating plane on which metal interconnects are deposited on the wafer, as shown in Figure 4. In order to electrically isolate devices from each other on the above mentioned wafer, epitaxial layers are sometimes etched to form mesa structures on the underlying semi-insulating substrate which are physically isolated from each other. This results in a structure similar to that shown in Figure 4a. Emitter mesa 401 rests on base-collector mesa 402 which in turn rests on semi-insulating substrate 403. Connections to the emitter ohmic contact 409 are made by metal deposited in the form of an arch 404. This arch structure may be formed as either an "air bridge" or as a similar structure supported by an underlying polymer (not shown). The arch is positioned to achieve a horizontal displacement from the wall of the transistor mesas to provide electrical isolation while spanning the vertical displacement from the emitter ohmic to the surface of the semi-insulating substrate. These connections can be partially unsupported 407 and fragile which may limit device fabrication yields. Implantation may also be used to isolate transistors as shown in Figure 4b. Instead of etching away unwanted base - collector mesa layers, certain elements are implanted into redundant portions of the base and collector layers 418 to make them insulating. This reduces the vertical profile of the transistors and lessens the problems described above, but does not necessarily overcome them. Because the emitter interconnect metal 404 1414 tends to be thick (e.g. 2-3 microns) to strengthen the resulting structure, it is difficult to pattern this layer to form sub-micron-sized connections to the emitter ohmic 409/419. The emitter ohmic 409/419 also needs to be larger than the foot of the interconnect arch 404/414 to allow for possible afignment errors during fabrication. The emitter arch structure therefore sets a limit below which the emitter dimensions cannot be decreased. This limits device scaling to around 1 micron emitter widths and prevents improvement of transistor high frequency performance by making devices smaller. The complexity of the processes required to form the device mesas and surrounding ohmic and interconnect structures may be costly and may significantly compromise device and circuit fabrication yield. For example, circuits containing thousands of HBTs typically have less than 50% yield. The performance of HBTs formed on GaAs substrates may also tend to be compromised by the relatively poor thermal conductivity of the substrate material, particularly in high power applications. Because of the poor thermal conductivity, device junction temperatures may rise and degrade parametric performance and reduce mean time to failure. It is therefore desirable to improve the thermal characteristics of HBT devices so that junction temperatures are lowered. Attempts have been made to overcome these problems. An example of one such attempt is found in applicant's co-pending International (PCT) patent application No. PCT/AU2006/001976 entitled "Method and Structure for a High Performance Semiconductor Device" and filed 29 December 2006. However the inventor has realised that additional problems are encountered in the manufacture of HBTs which need to have very low parasitic leakage across the device junctions. The inventor recognises that high voltage HBTs in particular may experience this problem.

The inventor has also identified that compound semiconductor HBT Technology, for example, involving devices comprising InGaP/GaAs and other such compounds is useful in many commercial applications given the excellent reliability and thermal stability of these devices. By way of example, a first generation of InGaP/GaAs-based power amplifiers for wireless handsets, wireless LAN, broadband gain blocks, and high-speed fibre optic products have been successfully developed and marketed. For the ongoing development of these products, it is considered important to reduce overall size and cost as well as to provide additional functionality with improved circuit performance. In this respect, it is desirable to provide for the integration of bipolar (HBT) and field effect transistors (FET, MESFET or HEMT and other such devices) on the same chip. Many attempts have been made at integrating compound semiconductor FETs and bipolar transistors on the same chip for large volume commercial applications. Examples of these attempts are disclosed in US patent number 7,015,519 entitled "Structures and methods for fabricating vertically integrated HBT/FET device" in the name of Krutko et ai and US patent number 6,906,359 entitled "BiFET including a FET having increased linearity and manufacturability" in the name of Zampardi et al. The disclosures of these US patents are incorporated herein by reference. As noted in Krutko, several methods of integrating AIGaAsZGaAs HBT with field effect devices have been discussed in the literature. In one approach described in Ho et al., "A GaAs BiFET LSI technology", GaAs 1C Sym. Tech. Dig., 1994, p. 47, and D. Cheskis et al., "Co- integration of GaAIAs/GaAs HBT's and GaAs FETs with a simple manufacturabie process", IEDM Tech. Dig., 1992, p. 91 , the HBT emitter cap layer is used as a FET channel. This approach had two major drawbacks. First, the emitter resistance of the HBT is high and second, the parasitic effect of the base layer degrades FET performance and limits its applications. Another approach is to grow HBT and HEMT structures by selective MBE growth. (See Streit, et al., "Monolithik HEMT-HBT integration by selective MBE", IEEE Trans. Electron Devices, vol. 42, 1995, p. 618 and Streit, et al., "35 GHz HEMT amplifiers fabricated using integration HEMT-HBT material grown by selective MBE", IEEE Microwave Guided Wave Lett., vol. 4, 1994, p. 361.) The problem with this approach is the requirement of epi-growth interruption, wafer processing and epi re-growth. These steps render this approach unconducive to manufacturabie ends (i.e. high cost) with poor epi quality control. Krutko further notes it has also been shown that AIGaAs/GaAs HBT may be grown on top of the HEMT in a single growth run. (See K, Jtakura. Y. Shimamolo, T. Ueda, S. Katsu, D. Ueda, "A GaAs Bi-FET technology for large scale integration", IEDM Tech. Dig., 1989, p. 389.) In this approach the FET is merged into the collector of the HBT through a single epitaxial growth. Several attempts have also been made to integrate InGaP/GaAs HBT with MESFET and HEMT. (See J. H, Tsai, "Characteristics of InGaP/GaAs co-integrated d-doped heterojunction bipolar transistor and doped- channel field effect transistor," Solid State Electronics, vol. 46., 2002, p. 45 and Yang et al., "Integration of GalnP/GaAs heterojunction bipolar transistors and high electron mobility transistors", IEEE Electron Device Lett., vol. 17, no, 7, July 1996, p. 363.) In these approaches the channel of the field effect devices used an InGaP layer with low mobility and saturation velocity which results in high linear resistance and poor high frequency performance. These devices also show threshold voltages lower than -2 Volts. It is considered that these characteristics, however, make them largely unsuitable for commercial applications. Krutko et al describes a FET made by layers introduced beneath the HBT structure where one of the layers (the source and drain contact layer) is shared with the HBT as its subcollector layer. Although this arrangement may allow a FET to be implemented, the inventor has identified that the gate contact is not pianar with the source and drain contacts and it may be difficult to make the FET with close spacing between these contacts. Zampardi et al describes a FET made on top of a HBT structure using a complex arrangement of epilayers to form the FET. The inventor considers that although this arrangement may allow finer resolution of Gate Source and Drain features because the device contacts are on the uppermost surface of the wafer, there is considerable complexity with respect to the FET layers, which may add to manufacturing cost and introduce emitter resistance to the HBT structure which may decrease performance. It is therefore . considered that there is a need for improved methods and epitaxial structures for fabricating integrated pairs of compound semiconductor-based HBT and FET devices that are suitable for commercial applications.

The inventor has further recognised that in an effort to optimise design efficiency in the semiconductor industry, manufacturers have provided substrates for semiconductors comprising combined vias and capacitors to save area in the layout of the fabricated devices. An example of this is shown in figure 5 where a via structure or hole is formed from the back side of the semiconductor substrate, which for example may comprise GaAs. However in the related art design shown in figure 5, there are limits to the effectiveness of such components fabricated in this fashion. Any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or before the priority date of the disclosure and claims herein. SUMMARY OF INVENTION

It is an object of the present invention to overcome or at least alleviate at least one disadvantage associated with arrangements discussed in the above disclosure and other related art arrangements discussed herein.

In one preferred aspect there is a method of manufacturing a HBT device structure comprising a layered material arrangement, the method comprising the steps of: fabricating a first semiconductor device region upon a substrate where the first device region comprises: a) at least one n-doped layer for forming a collector region supported by the substrate; b) a p-doped layer disposed over the n-doped layer for forming a base layer,.and; c) at least one further n-doped layer disposed over the p-doped layer for forming an emitter layer, fabricating at least one second semiconductor device region upon the substrate comprising the steps of: removing the further n-doped layer from the second region; selectively removing portions of the p-doped layer to form exposed p- doped structures.

In another preferred aspect there is a method of manufacturing a HBT device structure comprising a layered material arrangement, the method comprising the steps of: fabricating at least a sub collector region comprising a first compound semiconductor material for providing at feast one contact layer for a HBT device; providing at least one interposing layer adjacent the sub collector region comprising a second compound semiconductor material; fabricating further layers proximate the interposing layer wherein the further layers comprise the first compound semiconductor material.

In another preferred aspect there is a method of fabricating a compound semiconductor HBT device structure comprising the steps of: providing a substrate materia! comprising at least n and p-doped regions, and; providing proximate at feast one substrate layer, a gain enhancement layer adapted to selectively reduce charge carrier flow away from at least one p-doped region of the substrate.

In yet a further preferred aspect there is a layered material arrangement suitable for the fabrication of a compound semiconductor HBT device, the arrangement comprising: a supporting substrate layer; a first n-doped layer operatively coupled to the supporting substrate; a second n-doped layer selectively operatively coupled to the first n-doped layer; a p-doped layer operatively coupled to the second n-doped layer; and an interposing layer residing between the first and second n-doped layers.

In yet another preferred aspect there is a varactor device comprising an anode; a cathode; and an interposing layer of material adjacent the anode and in operative contact with the conducting region, serving in operation to assist in the formation of a depletion region between the anode and the cathode.

In a preferred embodiment, the present invention provides a lateral pnp transistor produced by using the p-type base layer of a conventional vertically disposed npn HBT and an epi-layer introduced adjacent or proximate the npn transistor's subcoliector layer which enhances pnp transistor current gain.

This aspect of the present invention stems from the realisation that it is possible to form a lateral pnp structure from epitaxial features which are not restricted to the same plane of layered materials and that it is possible to enhance the current gain of lateral transistors by suitable choice of heterojunction.

In one further preferred aspect there is a method of controlling a transistor, the transistor forming at least one part of an electric circuit, the method comprising the steps of coupling an input of an emission sensitive element to a first transistor, the coupling of the input being electrically isolated from the first transistor, and providing feedback for the first transistor wherein the feedback comprises an output of the emission sensitive efement.

In another preferred aspect there is a method of fabricating an electric circuit comprising the steps of: providing a layered arrangement of semiconductor materials comprising a collector region, a base layer and at least one emitter structure supported on a substrate; forming a first transistor structure from the layered arrangement; forming an emission sensitive element from the layered arrangement; isolating the emission sensitive element from the first transistor.

In a further preferred aspect there is apparatus for controlling a transistor, the transistor forming at least one part of an electric circuit, the apparatus comprising: an emission sensitive element; first coupling means for coupling a first transistor to the emission sensitive element through a pathway electrically isolated from the electric circuit; feedback means for providing feedback for the first transistor wherein the feedback comprises an output of the emission sensitive element. In yet another preferred aspect there is a HBT circuit comprising: a layered arrangement of semiconductor materials comprising a collector region, a base layer and at least one emitter structure supported on a substrate; a first transistor structure formed from the layered arrangement; an emission sensitive element formed from the layered arrangement; isolating means operatively associated with the layered arrangement for isolating the emission sensitive element from the first transistor.

One preferred aspect stems from the realisation that, for example, a light emission characteristic of a direct bandgap transistor can be used to control the DC bias point of HBT devices In preferred embodiments, there is a means of controlling DC bias currents in HBT cells of circuits such as RF power amplifiers by optically sensing the operating current of the device and using this to prevent thermal runaway.

The preferred embodiments in one aspect serve to control a thermal runaway effect and/or control a bias level of the first transistor. An advantage of preferred aspects is the compact layout of the transistors used. A key advantage is that the transistors used to control the bias point of a transistor are much smaller than the equivalent area of the bias bypass capacitor or other such circuit components that they replace, hence allowing the size and cost of the chip to be reduced.

Another object of the present invention is to provide an improved integrated circuit device and manufacturing process and according to a further preferred aspect, improved integrated circuits are provided. Accordingly, there is a method of isolating layers of a HBT device the method comprising the steps of: separating an edge of a base layer from an edge of a collector region. In another preferred aspect there is a layered material arrangement . suitable for use in fabricating a HBT device, the arrangement comprising: a plurality of material layers adapted to form a HBT device; at least one first attenuation layer applied to a portion of the plurality of material layers and adapted to attenuate an implantation process applied the plurality of materia) layers.

In further preferred aspect there is a HBT device structure comprising: a layered material arrangement comprising a collector region, a base layer and an emitter structure supported by a substrate; wherein at least one edge of the base layer is separated from an edge of the collector region.

In still another preferred aspect, there is a method of forming a HBT device, comprising the step of providing a mask to restrict the penetration depth of an implant process.

In yet another preferred aspect, there is a HBT device comprising a number of layers, at least one layer being an base layer and another layers being a collector layer, wherein one edge of the base layer is separated from an edge of the coilector layer. In yet another preferred aspect there is a HBT device structure comprising: a layered material arrangement comprising a collector region, a base layer and an emitter structure supported by a substrate; a peripheral isolated portion proximate the layered arrangement wherein the peripheral isolated portion comprises a variable depth within the layered arrangement.

In another preferred aspect there is a bipolar transistor device structure for an integrated circuit comprising a semiconductor substrate having a layered arrangement of semiconductor material comprising, a subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcoliector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer, wherein an active region of the device is defined by a surrounding electrically isoiating portion of the layered arrangement of variable thickness and the at least one emitter layer comprises an emitter having an emitter mesa structure which extends outside of the active region and into the isolating portion.

More particularly, the embodiments in one particular form provide a fabrication method and structure for a high performance heterojunction bipolar transistor which may be suited to compound semiconductor material systems such as gallium arsenide and which preferably utilises ion implantation as a means of device isolation such that the resulting device comprises minimal vertical profile and scalable feature size. In a specific embodiment, the invention provides a structure for a HBT device where the periphery of the device is defined by either a single stage or dual stage ion implantation process which forms an isolating region of varying depth, The thickness of the shallower of the ion implantation depths in the isoiating region is chosen to be slightly greater than the combined thickness of the emitter and base layers. This implant renders the emitter and base, layers insulating but does not significantly affect the collector and subcollector layers. The deeper of the isolating or implant regions also renders the collector and subcollector layers insulating. In one preferred form of the present invention, the term "insulating" means the resistivity of these layers is increased by a factor of at least 100 compared to their original value, In this respect, "insulating" may serve to isolate a portion of a device, layered arrangement or structure.

In a preferred structure, metal is deposited on the emitter and base regions of the device forming ohmic contacts which extend beyond the periphery of the device onto the implanted region where they make contact with other metal interconnection features. In this manner, the width of the emitter ohmic contact metal can be made very narrow over the active area of the device but can be easily connected to wide metal interconnect layers located on the implanted region surrounding the device. From another perspective, embodiments described herein provide a process for forming a variable thickness isolation implanted region by sequentially performing at least two separate lithography and implantation functions at different implant energies whether that occurs in one or more process steps. From another perspective, an embodiment herein provides a process for forming a variable thickness isolation implanted region where a "semi-transparent" implant mask layer is used to reduce the penetration depth of a single implant process in certain areas. In essence, the present embodiment stems from the realisation that a varying depth implant process can increase the effective length of an isolating (eg implant) boundary around the periphery of a HBT thereby increasing breakdown voltages and decreasing leakage currents. The use of implantation in this manner allows a highly planar high voltage HBT to be fabricated which overcomes the difficulties associated with related art HV HBTs which have excessive mesa height profiles and poor metallisation manufacturing yield. The present embodiment provides the advantage in that it lowers the leakage current of HBTs particularly in high voltage applications.

In one other preferred aspect there is a method of fabricating a combined integrated HBT and FET device, the method comprising the steps of: providing a number of first layers adapted to form a HBT device; providing, in addition to the first layers, second layer(s) which are adapted to form a FET device.

In a further preferred aspect, there is a layer material resulting from the method as disclosed herein. In another preferred aspect there is a method of manufacturing an integrated HBT and FET device comprising the steps of: providing a layered material arrangement upon a substrate; adapting a number of first layers of the arrangement to form a HBT device; adapting an ohmic contact layer of the HBT device to form at least one layer of a FET device.

In a further preferred aspect there is a layered material arrangement suitabfe for use in fabricating an integrated HBT/FET device structure, the arrangement comprising: a substrate; a number of first layers operativeiy coupled to the substrate and adapted to form a FET device; a number of second layers above the first layers adapted to form a HBT device. In yet another preferred aspect there is a layered material arrangement suitable for use in fabricating an integrated HBT/FET device structure, the arrangement comprising: a substrate; a number of first layers operativeiy coupled to the substrate and adapted to form a HBT device; an ohmic contact layer of the HBT device adapted to form at least one layer of a FET device.

From a particular aspect, certain embodiments described herein provide a means of making FETs (both MESFETs and pHEMTs) as part of a HBT process. In one embodiment a FET is produced from layers beneath the HBT where these layers are specifically provided for the FET structure and are not used in common for the above HBT. in another embodiment, there is a FET provided above the HBT where the FET conducting channel is formed by the HBT ohmic contact layer. The present embodiments have resulted in a number of advantages such as no changes are made to the final HBT structure which can be freely optimised for desired performance. In particular emitter resistance can be made very low as opposed to related art schemes such as that disclosed by Zampardi et al. Another advantage is that the epilayer structure is very simple and low cost and the corresponding fabrication sequence is low cost. Further preferred aspects relate to improvements in the methods, devices and apparatus of the disclosures of one or more of US Patent No 6,919,261 , US Patent No 6,960,490, International (PCT) Application No. PCT/AU03/00298, International (PCT) No PCT/AU2004/000309 and International (PCT) Application No PCT/AU2004/001184 each being commonly assigned to the present applicant and incorporated herein by reference.

In essence, further preferred embodiments disclosed herein stem from the realisation that utilising the volume within a via hole as part of a circuit element, for example, a capacitor, allows for improved efficiency in the layout and fabrication of semiconductor devices.

Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention.

Embodiments of the present invention provide apparatus adapted for manufacturing compound semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform the method steps as disclosed herein.

Further embodiments of the present invention provide a computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing the method steps as disclosed herein. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention wiil become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

Further disclosure, objects, advantages and aspects of the present application may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are not shown to scale for the benefit of explanation and given by way of illustration only, and thus are not limiting to the scope of the present invention, and in which: Figure 1 is a simplified diagram showing a related art epitaxial layer structure suitable for the manufacture of a compound semiconductor;

Figure 2 is a simplified diagram showing a cross sectional view of a related art compound semiconductor device after fabrication; Figure 3 is a simplified diagram of a related art emitter mesa etching profile shown along the X and Y axes, respectively;

Figures 4a and 4b are simplified diagrams of related art HBT structures with mesa-etched and implant isolation, respectively;

Figure 5 is a simplified cross sectional diagram of a related art via structure;

Figure 6 shows a cross sectional view of complementary GaAs/lnGaP npn and pnp devices made according to a first preferred embodiment;

Figure 7 shows an alternate version in cross sectional view of complementary GaAs/lnGaP npn and pnp devices made according to a preferred embodiment of the present invention;

Figure 8a shows the band structure of a conventional GaAs/lnGaP HBT device under zero bias;

Figure 8b shows the band structure of a GaAs/lnGaP npn HBT device made according to embodiments described herein and under zero bias; Figure 9a shows the band structure of a conventional GaAs/lnGaP HBT device under forward bias;

Figure 9b shows the band structure of a GaAs/lnGaP npn HBT device made according to embodiments described herein and under forward bias;

Figure 10a shows the band structure of the base emitter junction of a pnp transistor made according to embodiments herein and under zero bias;

Figure 10b shows the band structure of the base emitter junction of a pnp transistor made according to embodiments herein and under forward bias.

Figure 11 shows a conventional Silicon based lateral pnp semiconductor device structure; Figure 12 shows a pnp semiconductor device structure in accordance with an embodiment described herein;

Figure 13 shows a conventional semiconductor device structure in the form of a varactor; Figure 14 shows a HBT device structure comprising a varactor in accordance with an embodiment described herein;

Figure 15a shows a circuit diagram of a related art transistor circuit used for stabilising the operating point of a transistor; Figure 15b shows a circuit diagram of a circuit used for controlling a transistor in accordance with a second preferred embodiment described herein;

Figure 16 shows a device structure of a preferred embodiment comprising a combined power transistor and optical sensing circuit;

Figures 17a to 17c are plan views showing a comparison of. example related art isolation implanted HBTs, figures 17a and 17b, and the location of dual implant boundaries, figure 17c, according to a third preferred embodiment;

Figure 18a shows a side view of a dual layer implant mask used to form an implant of varying depth in accordance with an embodiment of the present invention; Figure 18b shows a side view of a resulting structure with different implant depths in accordance with an embodiment of the present invention after use of the implant mask of figure 18a;

Figure 19 shows a side view of a preferred connection between an emitter mesa and an interconnect metal showing different implant depths in accordance with an embodiment of the present invention;

Figure 20 describes the characteristics of each layer in an epitaxial structure as disclosed in the related art of Krutko et al;

Figure 21 shows a cross-section view of an integrated pair of HBT and FET formed as disclosed in the related art of Krutko et al; Figure 22 illustrates a cross sectional view of a BiFET including an HBT and a FET situated over a substrate in accordance with the disclosure of the related art of Zampardi et al;

Figure 23 shows an epilayer arrangement for an integrated HBT/FET device structure in accordance with a fourth embodiment; Figure 24 shows an epilayer arrangement for an integrated HBT/FET device in accordance with a fifth embodiment;

Figure 25 is a side view of the resulting integrated device structure comprising FET and HBT devices made according to the fourth embodiment; Figure 26 is a side view of the resulting integrated device structure comprising FET and HBT devices made according to the fifth embodiment;

Figure 27 is a simplified cross sectional diagram of a via structure in accordance with a sixth preferred embodiment of the present invention; DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, material and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. Certain- embodiments are described in the following detailed description with reference to the specific example of the manufacture and/or fabrication of devices and/or integrated circuits and components using gallium arsenide (GaAs) compound as the relevant semiconductor material and related compound semiconductor devices stemming therefrom. The present invention, however, is not limited in its application to GaAs and may equally apply to other semiconductor materials such as, for instance, indium phosphide (InP)₁ gallium nitride (GaN), silicon carbide (SiC) and also silicon (Si).

A first embodiment relates, in particular, to improved means of fabrication of bipolar transistor devices such as for example, npn and pnp bipolar transistors in a single process. This embodiment aims to provide a simple, low cost compound semiconductor device structure and method of manufacture which yields complementary bipolar transistors in compound semiconductor materia! systems where the performance of the npn transistors is not adversely affected by the inclusion of pnp device features. Other embodiments of the present invention aim to provide a structure and method of manufacture for compound semiconductors which yield varactor diodes. Further embodiments of the present invention aim to provide an improved means of controlling etch processing of compound semiconductor wafers. Figures 1 and 2 show the epi-layer and device structure respectively, for a conventional GaAs InGaP HBT. An n+ GaAs sub-collector layer 210 is normally grown on a semi-insulating GaAs substrate 211 , followed by an n collector layer 208, a p+ base layer 207 and a number of emitter layers 201 , 202, 203 and 204. npn HBTs are normally fabricated by etching off unwanted portions of these layers to leave the resultant structure of Figure 2. Metal contacts 206, 209 are deposited to make eiectrical connection to the device terminals as shown.

With respect to figure 6, according to a first embodiment, a lateral pnp transistor 623 is formed by first etching off epi-layers 601 , 602, 603 and 604 associated with the emitter of npn devices, and then etching off portions of the npn's p+ layer 607 to form emitter 620 and collector 621 features of the pnp. The base contact 622 of the pnp is made by a conventional connection made to the npn's n+ subcollector layer. Structure 615 serves to isolate the npn device from the pnp device and may be formed, for example, by way of ion implantation. Other means of producing this isolation between npn and pnp devices would be recognised by the person skilled in the art. In normal operation of the pnp device, holes are injected from the emitter contact as a result of a potential applied to the base emitter junction. These holes are swept, through the n layer 608 corresponding to the npn's collector layer, toward the collector of the pnp device as a result of the strong electric field in this region. Lateral pnp devices would be recognised by the person skilled in the art in the silicon semiconductor industry,

With reference to figure 11, these devices are typically fabricated by implanting or diffusing p-type dopants into an n-type substrate comprising typically Collector (n type) and underlying Sub-Collector (n+ type) layers in localised regions where the emitter E and collector C are to be formed. The resulting structure of such a device therefore has p-type regions located within an n-type surface layer such that the edges of the emitter E and collector C are positioned opposite each other with intervening n-type material. Contrary to this arrangement, the inventor has realised that lateral pnp devices can be fabricated from epi-layer structures where p-type emitter and collector features sit above the surface of the n-type base layer. This is considered unconventional in as much as there is no n-type material between the edges of the emitter and collector and holes are injected downward from the emitter toward the highly conductive underlying n+ layer. Holes injected in this direction accordingly have a strong chance of entering the n+ base layer and recombining, thereby degrading device current gain. In order to overcome this problem, a preferred embodiment provides an introduced interposing layer of material or, specifically for the above noted pnp device structure, a pnp Gain Enhancement (PGE) Layer. This layer is made from a wide bandgap material which is grown or otherwise introduced on top of the n+ base layer. Examples of this arrangement are shown by device 723 in situ in figure 7 and in more focussed detail in figure 12. In figure 12, the npn device layers are indicated to the left of the diagram for the purposes of illustration and comparison of the pnp device structure with the related art npn device structure. For pnp devices such as those depicted in figures 7 and 12, the characteristics of this interposing or gain enhancement PGE layer are as follows:

• Holes injected from the p+ emitter are blocked from entering the n+ base layer by the valence band offset of the chosen PGE layer. Holes are therefore trapped in the base layer and therefore have a higher chance of being swept toward the collector region of the device.

• Electron injection from the n+ base layer is reduced by the conduction band barrier presented by the PGE layer. It is noted that electron current flow from pnp base to pnp emitter deceases current gain.

The behaviour of the interposing (PGE) layer in this respect according to its band structure is shown in Figure 10. In npn devices, the PGE is designed and characterised by its composition to have minimal effect on the flow of electrons through the device. The PGE layer may be either:

• a uniform lightly doped or intrinsic layer or

• a layer whose composition or doping is graded across the thickness of the layer.

In the case of a uniform layer grown on a GaAs n+ layer, the PGE layer may be made from AiGaAs, InGaP or from other ternary or quaternary compounds made from Af, Ga, In, As and P, Consequently, the conduction band offset of the PGE layer is preferably designed to avoid an abrupt step which would to some extent increase collector resistance for an npn device.

In another preferred embodiment, a graded doping or graded composition iayer may be provided such that a step increase in the conduction band is avoided for electrons travelling across the PGE layer in an npn device. For example, the PGE layer may be made from AIGaAs where the doping density is high at the emitter side of the PGE layer and low at the base side. Such a layer will create a ramp in the conduction band and will avoid the step that would otherwise increase coilector resistance in an npn device. The band structure of such a layer is shown in figures 8b and 9b for npn devices under zero and forward bias, respectively. The PGE layer may typically be around 100 angstroms thick. The only effect of the PGE layer in npn devices noted by the inventor is a slight increase in collector saturation voltage which will not be critical in most applications. In this way a pnp transistor may be fabricated without degrading the performance of the associated npn. The pnp device is also able to be made at low cost because complex manufacturing sequences such as selective epitaxy are avoided. The only difference in the manufacturing process compared to that used for npn devices is the need for a shallow etch of the p+ layer and the inclusion of an additional epi-layer. The inventor recognises that these manufacturing adjustments can be done at little cost.

In another embodiment, the present invention provides a means of controlling etching of compound semiconductor wafers. For conventional npn . devices as shown in Figures 1 and 2, the process of etching away layers to expose the surface of the subcollector layer is normally controlled by etch timing and hence may have relatively poor reproducibility. In addressing this, the interposing (PGE) layer also serves as a selective etch barrier that allows the fabrication process to automatically stop at the right layer. For example if the PGE layer is made from AIGaAs, InGaP or a related compound, it is possible to use selective etching to control patterning of the npn subcollector layer because of the etch selectivity of these compounds with respect to compounds such as GaAs. In Figures 7, 12 and 14 there is shown the introduction of an interposing layer of material (PGE). Suitable materials for the introduced layer are noted above. The interposing layer (PGE) is situated preferably above the sub-collector layer in accordance with preferred embodiments. Materials may be used for the interposing layer with the property of having different etch chemistry to that of the material upon which the device structure is based, like for example, arsenides such as GaAs. In the case of the introduced layer comprising InGaP, given that it is a phosphide it will not be etched away by etchants that are used to etch away _, arsenides like GaAs. Conversely, once an etchant that reacts with the InGaP is used such as concentrated HCL it will stop very accurately on the surface of an underlying arsenide layer such as GaAs. Therefore, the introduced interposing layer (PGE) provides a means of stopping the etch process at a known point being the surface of the sub-collector and controls the etch process to prevent the etch process continuing into the sub-coliector layer which would reduce the natural resistivity of the sub-collector layer.

In another embodiment, a means of manufacturing low loss varactor diodes is provided. The inventor recognises that in making low loss varactor diodes it is important to reduce the series resistance of the epi-layers used to form the diode. The inventor has realised that an ideal place to locate a varactor diode is adjacent to the highly conductive n+ npn subcoilector layer. Because the

PGE layer described above can be lightly doped, this layer can be used to form a varactor diode. For example, GaAs layers above the PGE layer would be removed by an etching process that stops on the surface of the PGE layer. Then a metallic contact may be deposited on the PGE layer to form schottky contacts and hence varactor diodes. With reference to figure 13, ordinarily a varactor diode, being a diode with variable capacitance, is formed through etching down through to an n-type layer of semiconductor and then a metal contact VM for the varactor anode is placed on the exposed n-type semiconductor. Under the metal contact VM a depletion region DR is formed. This is a region where the semiconductor is devoid of carriers and it now acts as a capacitor in this region.

Specifically the depletion region exists between the n-type semiconductor where there are charge carriers and the contact metal V_M that is on the surface of the semiconductor and this combination emulates a parallel plate capacitor. By varying the voltage across this device the depletion region DR grows and shrinks according to the level voltage across the region thus forming a voltage dependent capacitance. Varactors formed in this way are quite useful for application in tuning the operating frequency of components such as oscillators. Although the varactor structure formed conventionally works quite weil in forming the varactor itself, by forming a depletion region DR that may be modulated to vary capacitance, the depletion region is actually in series with the remaining n-type layer which is quite resistive as depicted by the resistor symbol shown in Figure 13. Thus the structure of Figure 13 emulates more than simply a varactor but a variable capacitor in series with a high value resistor and this detracts from the function of a varactor as would be understood by the person skilled in the art. The in situ structure shown in Figure 7, and the more detailed example in figure 14, shows a well controlled arrangement by way of use of the introduced layer (PGE) illustrated in which now a highly conductive, as opposed to resistive, semiconductor and a region of depletion or capacitance in a well defined region are formed, Accordingly, the example structures of Figures 7 and 14 comprise structures which have been etched down to an introduced InGaP layer (PGE) to allow for a deposit of a metal on the InGaP layer as a varactor contact (see VM.IΠ figure 14). The sub-collector layer which is highly conductive or having very low resistance may couple the collector contact as a cathode of a varactor diode (see Kv in figure 14) where the anode of the varactor diode is formed by the schottky metal contact VM. The depletion region DR is now confined to the introduced InGaP layer that is well restricted or controlled in dimension and there is minimal equivalent resistance in series due to the highly conductive n+ region having very low resistance and connecting VM to the Collector contact or now the varactor cathode Kv as depicted in figure 14. The resultant device is a varactor diode with the characteristics of low resistance and low loss. A second preferred embodiment is related in general to control mechanisms for use in relation to HBT's, for example those used in power amplifiers. It will be appreciated, however, that there can be many variations, modifications, and alternatives. Again it is noted that the present embodiment, however, is not limited to its application to GaAs and, as would be recognised by the person skilled in the art, may equally apply to other direct bandgap semiconductor materials such as, for instance, indium phosphide (InP), and gallium nitride (GaN). Compound semiconductors such as GaAs have direct bandgaps which means that devices made from these materials are relatively efficient light emitters and detectors. This property has been used to measure the operating conditions of HBT devices. For example a paper entitled "Direct observation of gain collapse phenomena in multi-finger HBTs using digital cameras" by Sugiyama et al published at the 2002 GaAs MANTECH Conference describes a process of monitoring power dissipation in HBTs using emitted light, in another paper entitled "Light-emitting transistor: Light emission from InGaP/GaAs heterojunction bipolar transistors" Applied Physics Letters Volume 84, No.1, January 2004, an observation of light emitted from recombination in the base layer of a HBT was described.

Figure 15b shows a circuit diagram of the present embodiment. In this circuit Q1 represents the power transistor being controlled. This device may be a single HBT with multiple emitter fingers to increase power handling capability. L1 provides a DC operating current for Q1 and high RF impedance. Q2 is a device located physically close to Q1 and is preferably arranged to be part of Q1's structure. The circuit operates as follows: DC bias current is applied to the base of Q1 through resistor R1 to establish the device operating point. Q1 emits light as a result of charge carrier recombination in the device which is proportional to operating current. This light is coupled to Q2 which conducts in proportion to the operating current of Q1. As Q2 conducts, Q3 also conducts, deflecting a portion of the base current of Q1 thereby providing negative feedback and stabilising the operating point of Q1. Additional resistive and capacitive elements (not shown) may be introduced in this negative feedback path to obtain the appropriate DC and high frequency AC characteristics and to ensure the feedback loop is stable. In particular, additional elements may be connected to the base of Q2 or Q3. Figure 16 shows one physical layout of the present embodiment where Q1 1600 is formed from multiple emitter fingers 1606 and 1607 and surrounding base contacts 1608-1610. Q2 1601 is shown located between the two elements of Q1. In practice Q1 may have more than two emitter fingers and the diagram represents a simple case of only two emitter fingers. The base layer of Q2 1604 is disconnected from the base portions of Q1 1602 by etching away portions of the layer 1613 next to Q2. In operation, light is generated in regions 1603 of Q1 and propagates in part to the active area 1604 of Q2.

A third preferred embodiment provides a manufacturing method and structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size, reduced manufacturing complexity and increased operating voltage. It will be convenient to hereinafter describe this embodiment in relation to what the inventor has termed a "High Voltage Scalable Heterojunction Bipolar Transistor (HVSHBT)" comprising, for example, a GaAs substrate. More particularly, this embodiment provides a method and structure for a high performance high voltage heterojunction bipolar transistor which is suited to compound semiconductor material systems such as gallium arsenide and which utilises ion implantation at the beginning of the fabrication sequence to define the perimeter of the device thereby electrically isolating the HBT from surrounding semiconductor structures on the wafer. The present embodiment preferably uses compound semiconductor wafers with equivalent emitter, base, collector and sub-collector layers, as shown in Figure 1. However this preferred embodiment differs, in at least one preferred aspect, from related art in the way these layers are patterned. In related art devices as shown in Figure 2, the emitter layer structure is patterned first to form an emitter mesa structure 200. This patterning is performed using either standard gaseous dry etching or aqueous wet etching techniques. The size of the emitter mesa is determined by a material which is impervious to the etching process and which is deposited on the surface of the wafer and patterned by photolithography. This materia! may be photoresist or a composite metal layer 205 that forms the emitter ohmic contact of the device. In related art HBTs that are isolated by etching away all active device layers, the base, collector and subcollector are patterned in a similar fashion. In related art devices that are isolated using ion implantation, the base and collector layers are not etched away. Instead they are rendered insulating by exposure to high energy ions such as oxygen, hydrogen or helium. Figure 17a shows a plan view of a related art ion impfant isolated HBT.

The emitter region 1701 is patterned so it is smaller than the base region 1702 which is smaller than the subcollector region 1703 which is surrounded by implanted regions 1704 forming an isolation implant boundary 1705. Figure 17b shows equivalent emitter 1711, base 1712, subcollector 1713 implanted regions 1714 and implant boundary 1715 of another related art ion implant isolated HBT.

Figure 17c shows a preferred embodiment where 1725 shows the boundary of a shallow implant region and 1727 shows the boundary of a deep implant region.

Figure 18a shows a side view of this same area of figure 17c. Emitter layers 1811 are arranged on top of base layer 1812 which are in turn arranged on top of collector layers 1813 and 1814. In accordance with a preferred embodiment, two implant mask layers are deposited on the surface of the wafer. Layer 1821 is chosen to be semi-transparent to the implant process meaning that implanted ions penetrate this layer and reach the underlying semiconductor layer rendering it insulating to a certain depth. This layer is preferably photoresist or some other polymer, which is preferably photo-imageable and resistant to the implant process. The layer may also be a metallic material such as titanium or a dielectric material such as silicon nitride. The thickness of this layer is chosen to provide the desired implant depth underneath this layer and accordingly acts as an attenuator for the isolating process. Layer 1820 is a second implant masking layer which is designed to prevent any implant ions from reaching the central active area of the device. This layer is also preferably chosen from the materials mentioned above for layer 1821. Figure 18b shows the resulting implant profile of the present embodiment. Implanted area 1817 does not penetrate as deeply into the semiconductor wafer as implanted region 1818 because of the partial blocking or attenuating effect of mask layer 1821. A key aspect of the embodiment shown in figure 18b is the horizontal separation 1819 that is provided between the edge of the base layer and the edge of the subcollector layer. This increased physical separation provides lower device leakage currents and higher breakdown voltages. Figure 19 shows the side view of the present embodiment after fabrication of emitter mesa 1911 , emitter ohmic 1911a and emitter interconnect metallisation 1930 has been performed.

IP 13 Fourth and fifth preferred embodiment relates to integrated HBT/FET fabrication technologies. In one form, fabrication of integrated InGaP/GaAs HBT/FET's on the same chip is provided for and it will be convenient to hereinafter describe the embodiment in relation to that application.

In figure 20 there is shown a summary of the characteristics of each layer in the epitaxial structure in the related art structure of a vertically integrated HBT/FET device as disclosed in Krutko et al noted above. The related art structure per se, as disclosed in Krutko et a; is illustrated in figure 21 in which as described in the illustration of Krutko et al a contact layer '104' is shared between a HBT device, generally indicated by the features of emitter, base and collector, and a FET device, generally indicated by the features of gate, source and drain, wherein the shared layer serves as a cap layer for the FET device and as a sub- collector layer for the HBT device. In figure 22 there is shown a side or cross sectional view of a related art BiFET including an HBT device, generally indicted by '104' of the diagram of figure 22, and a FET device, generally indicated by '106' as disclosed in Zampardi et al noted above. As shown in figure 22, the HBT '104' of Zampardi et al is situated over substrate '108' between isoiation regions '110' and '112' and FET '106' is also situated over substrate '108' between isolation regions '112' and '1 14'. The BiFET of Zampardi et al discloses an etch stop layer '126/146' where a first segment of the etch stop layer resides above the emitter of the HBT '104' and a second segment of the etch stop layer resides below the source and drain regions of the FET '106'.

Figure 23 shows the layered material arrangement or epi layer structure of a fourth embodiment as disclosed herein. The layers above and including the Subcollector layer are those normally used to form a HBT device structure, as would be recognised by the person skilled in the art. Two layers are introduced separate from these HBT layers beiow the subcollector layer. In this example being the FET barrier layer and the FET channel layer shown in figure 23. These are used as an etch stop for the FET which allows an etchant to stop immediately on the layer used to deposit the gate of the FET device, and a channel layer, respectively. Figure 25 shows the resulting structure of the HBT and FET. The HBT is formed using conventional fabrication processes as would be recognised by the person skilled in the art. The FET is made by etching down through the HBT layers to reach the layer 2525. This layer is used as both an etch stop feature and a layer which increases the schottky barrier height of the gate contact thereby enhancing the behaviour of the FET, This layer, in the example of a

GaAs based structure, may be made of InGaP or any material which allows selective etching and is crystal matched to the underlying substrate. In other compound semiconductor based device structures, it is envisaged that likewise alternate materials may be chosen to serve as an etch stop layer depending on the particular compound semiconductor upon which the device structure is based.

In order to make the FET the gate 2523 and source/drain contacts 2522 are deposited directly on the surface of the etch stop layer 2525. The gate

^■ contact 2523 is made from a material which forms a schottky contact on the etch stop layer, importantly, in accordance with this embodiment, the source and drain contacts 2522 are made of a metal structure which is designed to form ohmic contacts to the FET channel layer 2526. These contacts are made from a material structure which diffuses through the etch stop layer 2525 and into the channel layer 2526 when heated as indicated at 2521. The material(s) utilised for these contacts may be a combination of nickel germanium and gold.

In certain applications it may be desirable to remove the etch stop layer entirely before depositing the gate 2523 and source/drain connections 2522. In this case source and drain ohmic contacts 2522 are made by diffusing metallic contacts into the surface of the channel layer 2526. The gate contact 2523 may also be self aligned to the source and drain contacts 2522 to increase device performance. The gate contact 2523 may comprise titanium/platinum/gold or platinum/titanium/platinum/gold, or other suitable combinations of these elements.

In another or fifth preferred embodiment, a layer structure or layered material arrangement as shown in Figure 24 is used to make the FET device. This epilayer structure uses a conventional HBT layer structure except an additional layer indicated as a FET barrier layer is grown on top. This layer is designed to have a higher schottky barrier height than would be achievable from the underlying ohmic contact layer. Wide bandgap materials such as InGaP, and AIGaAs are possible however it is advantageous to choose a material which is easily etched relative to the underlying emitter contact layer. Figure 26 shows a side view of the resulting combined HBT and FET structure using the layered material arrangement of figure 24. The emitter contact layer 2601 serves as the FET channel layer. In this embodiment, the material properties of InGaAs are advantageous in lowering the channel resistance of the device. In a preferred form, a gate contact is made by depositing a material 2623 on the surface of the FET barrier layer 2625. This material forms a schottky barrier contact and may comprise titanium/platinum/go!d or platinum/titanium/platinum/gold, or other suitable combinations of these elements. The FET barrier layer 2625 may be etched to leave exposed ledges 2626 at either side. These provide improved device performance including lower channel device leakage when the FET is off. Source and Drain connections 2622 may be made upon the surface of the channel layer 2601 in the same process step in which the emitter contact 2605 of the HBT is formed. In both the fourth and fifth embodiments FETs and other devices such as the HBT devices are preferably isolated either by mesa etching or by isolation impfants 2520 see figure 25 and 2620, see figure 26.

A sixth preferred embodiment provides a manufacturing method and structure for a Via hole arrangement in a composite substrate comprising a substantially metallic substrate suitable for a compound semiconductor device. It will be appreciated, however, that there can be many variations, modifications, and alternatives. It will be convenient to hereinafter describe the invention in relation to an integrated circuit arrangement comprising a composite GaAs/metallic substrate, however it should be appreciated that the present invention is not limited to that use only. Accordingly, improved integrated circuits of various composition and structure may be provided.

In this preferred embodiment a composite substrate is provided in which it is possible to provide front-side vias. Accordingly, and with reference to figure 27, there is provided a substrate structure where a first metal layer associated with a via structure forms a first conductor side of a circuit element, namely a capacitor. Further, a second metal layer associated with a via structure forms a second conductor side of a circuit element, namely a capacitor. A layer of dielectric material is then provided to form a dielectric for a circuit element, namely a capacitor. The resultant capacitor of figure 27 comprises the following features. The capacitor (to ground only eg power supply bypass cap) shares the area of the via as per related art to utilise the space available on a substrate. Advantageously, in this preferred embodiment, the capacitor's bottom plate is directly connected to the "heavy" (-good) ground plane of the metallic portion of the composite substrate, therefore excellent bypassing to ground is provided for this circuit element. Furthermore, the resultant capacitor is formed as a 3D element. In this respect, it is noted that the circuit designer may consider the cylindrical cavity of the via hole, as follows. In a related art circuit element as shown in figure 5 a planar capacitor area is provided and the resultant capacitance may be calculated according to:

Ci = Kπr²

The capacitor as shown in figure 27 approximates to a capacitor with a cylindrical surface area and therefore its capacitance may be given by: C₂ = Kπr² + K2πrd

So, for example, if the height of the capacitor cylinder.d = 2r, then it follows that:

C₂ = K^r² + 21^) = 3C₁

It is evident that a capacitor formed according to the present embodiment, by way of the front side via structures, has an effective capacitance of the order of three times greater than the related art equivalent element. In yet a further preferred form the present embodiment provides a method of forming a capacitive device in a semiconductive substrate, the method comprising the steps of: forming a via hole' in the semiconductive substrate; utilising the via hole as at least a part of the capacitive device.

Advantageously, capacitive material may be provided in the via hole and further at least part of the electrical plates of the capacitive device may be formed at each end of the via hole. At least one plate is directly connected to a substrate layer of the semiconductive substrate to provide excellent bypassing to ground for the circuit element. Furthermore, a distributed capacitor may be formed by utilising more than one via hole. Accordingly, the plates may be coupled to a plurality of via holes having capacitive material therefn. As above, for a given via hole, the capacitive device comprises a capacitance given by:

C₂ = Kπr² + K2πrd where r = radius of a substantially cylindrical shape corresponding to a via hole; and d = height of the substantially cylindrical shape. A person skilled in the art will recognise that embodiments of the invention described above can be implemented using a computer. In that case, the method is embodied as instructions that make up a program. The program may be stored on computer-readable media, such as floppy disks, optical discs (such as compact discs), or fixed disks (such as hard drives), and can be resident in memory, such as random access memory (RAM), read-only memory (ROM), firmware, or flash RAM memory. The program as software can then be executed on a computer to implement the method. The program, or portions of its execution, can be distributed over multiple computers in a network. For the purposes of this disclosure, including the appended daims, the term "integrated circuit" shall be defined as a combination of interconnected circuit elements inseparably associated on or within a continuous substrate. For the purposes of this disclosure, including the appended claims, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, comprising, but not limited to, bulk semiconductive materials such as semiconductive wafer (either alone or in assemblies comprising other. materials thereon), or composite layers of any composition of material(s) and/or semiconductive material layers (either aione or in assemblies comprising other materials). For the purposes of this disclosure, including the appended claims, the term "substrate" refers to any structure, including supporting structures comprising, but not limited to, the substrates described above. While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to^' which the invention pertains and as may be applied to the essential features hereinbefore set forth.

As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the specific embodiments are to be understood to be illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-plus-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be

^• structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures. "Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof." Thus, unless the context clearly requires otherwise, throughout the description and the claims, the words 'comprise', 'comprising¹, and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A method of manufacturing a HBT device structure comprising a layered material arrangement, the method comprising the steps of: fabricating a first semiconductor device region upon a substrate where the first device region comprises: a) at least one n-doped layer for forming a collector region supported by the substrate; b) a p-doped layer disposed over the n-doped layer for forming a base layer, and; c) at least one further n-doped layer disposed over the p-doped layer for forming an emitter layer, fabricating at least one second semiconductor device region upon the substrate comprising the steps of: removing the further n-doped layer from the second region; selectively removing portions of the p-doped layer to form exposed p- doped structures.

2. A method as claimed in claim 1 wherein the first semiconductor device region comprises at least one npn junction.

3. A method as claimed in claim 1 wherein the second semiconductor device region comprises at least one pnp junction.

4. A method as claimed in claim 1 wherein the exposed p-doped structures are adapted to form at least one of an emitter and a collector.

5. A method as claimed in claim 4 further including the step of: introducing a gain enhancement layer comprising a material comprising a relatively wide bandgap and adapted to deflect charge carriers towards at least one of the emitter or the collector.

6. A method as claimed in claim 5 wherein the introduced layer comprises a thickness of about 10θA.

7. A method as claimed in claim 5 wherein the charge carriers comprise holes.

8. A method of manufacturing a HBT device structure comprising a layered material arrangement, the method comprising the steps of: fabricating at least a sub collector region comprising a first compound semiconductor material for providing at least one contact layer for a HBT device; providing at least one interposing layer adjacent the sub collector region comprising a second compound semiconductor material; fabricating further layers proximate the interposing layer wherein the further layers comprise the first compound semiconductor material.

9. A method as claimed in claim 8 wherein the second compound semiconductor material is characterised by one or more of: different etch characteristics to the first compound semiconductor material; different electrical properties to the first compound semiconductor material.

10. A method as claimed in claim 8 further comprising the step of: providing the at least one interposing layer between the sub collector region and a collector region of the HBT device structure.

11. A method as claimed in claim 8 further comprising the steps of: selectively etching through the layered material arrangement of the HBT device structure with a first etchant adapted to remove the first compound semiconductor material; selectively etching through the layered material arrangement of the HBT device structure with a second etchant adapted to remove the second compound semiconductor material.

12. A method as claimed in claim 11 further comprising the steps of: selectively depositing a contact layer over an exposed portion of the interposing layer to form an anode; selectively depositing a contact layer over an exposed portion of the sub collector region to form a cathode; wherein, in combination, the anode, cathode, and at least a portion of the interposing layer and sub collector region respectively provide a varactor diode with a depletion region restricted to the portion of the interposing layer.

13, A method as claimed in claim 11 further comprising the steps of: selectively etching a base layer of the HBT device structure overlying a collector region adjacent the interposing layer to form respective emitter and collector features; wherein, in combination, the emitter and collector features, at least a portion of the collector region and, at least a portion of the interposing layer provide a pnp transistor device where charge carriers emitted by the emitter feature are deflected by the portion of the interposing layer so as to provide a current at the collector feature.

14. A method as claimed in claim 13 wherein the charge carriers comprise holes.

15. A method as claimed in claim 11 further comprising the step of: selectively depositing a contact layer over the sub collector region to form a base contact.

16. A method as claimed in claim 8 wherein the interposing layer comprises a thickness of about 100A.

17. A method as claimed in claim 8 wherein the interposing layer comprises a uniformly lightly doped composition of material.

18. A method as claimed in claim 8 wherein the interposing layer comprises a graded composition of material.

19. A method as claimed in claim 18 wherein the graded composition of materia! is graded in the direction of the thickness of the layer.

20. A method as claimed in claim 8 wherein the first compound semiconductor material comprises an arsenide.

21. A method as claimed in claim 8 wherein the second compound semiconductor material comprises a phosphide.

22. A method as claimed in claim 8 wherein the second compound material comprises one or a combination of: Indium (in);

Gallium (Ga);

Aluminium (Al);

Phosphorous (P);

Arsenic (As).

23. A method of fabricating a compound semiconductor HBT device structure comprising the steps of: providing a substrate material comprising at least n and p-doped regions, and; providing proximate at least one substrate layer, a gain enhancement layer adapted to selectively reduce charge carrier flow away from at least one p-doped region of the substrate.

24. A method as claimed in claim 23 wherein the HBT device structure comprises at least one npn junction .

25. A method as claimed in claim 23 wherein the HBT device structure comprises at least one pnp junction.

26. A method as claimed in claim 23 wherein the HBT device structure comprises at least one pnp junction and/or at least one npn junction.

27. A method as claimed in claim 26 wherein the HBT device structure comprises at least one pnp junction in a lateral formation and at least one npn junction in a vertical formation.

28. A method as claimed in any one of claims 26 or 27 wherein the npn and pnp junctions are adapted to be fabricated proximate each other.

29. A method as claimed in claim 23 wherein the substrate comprises a compound semiconductor material comprising an arsenide.

30. A method as claimed in claim 23 wherein the gain enhancement layer comprises a compound semiconductor material comprising a phosphide.

31. A method as claimed in claim 23 wherein the gain enhancement layer comprises a compound semiconductor material comprising one or a combination of: Indium (In);

Gallium (Ga);

Aluminium (Al);

Phosphorous (P);

Arsenic (As).

32. A layered material arrangement suitable for the fabrication of a compound semiconductor HBT device, the arrangement comprising: a supporting substrate layer; a first n-doped layer operatively coupled to the supporting substrate; a second n-doped layer selectively operatively coupled to the first n-doped layer; a p-doped layer operativeiy coupled to the second n-doped layer; an interposing layer residing between the first and second n-doped layers.

33. An arrangement as claimed in claim 32 wherein the interposing layer comprises a material having a relatively wide bandgap as compared to the material(s) of the n-doped and p-doped layers.

34. An arrangement as claimed in claim 32 wherein the interposing layer comprises a material characterised by one or more of: different etch characteristics to the material of the n-doped and p-doped layers; different electrical properties to the material of the n-doped and p-doped layers.

35. An arrangement as claimed in claim 32 wherein the n-doped and p-doped layers comprise compound semiconductor material comprising an arsenide.

36. An arrangement as claimed in claim 32 wherein the interposing layer comprises a compound semiconductor material comprising a phosphide.

37. An arrangement as claimed in claim 32 wherein the interposing layer comprises a compound semiconductor material comprising one or a combination of:

Indium (In);

Gallium (Ga);

Aluminium (Ai);

Phosphorous (P); Arsenic (As).

38. An arrangement as claimed in claim 32 wherein the interposing layer comprises a thickness of about 100A.

39. An arrangement as claimed in claim 32 wherein the interposing layer resides in a collector region of the material arrangement.

40. A varactor device comprising: an anode; a cathode; and an interposing layer of material adjacent the anode and in operative contact with the conducting region, serving in operation to assist in the formation of a depletion region between the anode and the cathode.

41. A varactor device as claimed in claim 40 wherein the interposing layer is a gain enhancement layer and serves to controi, in operation, a depletion region of the varactor.

42. A varactor device as claimed in claim 41 wherein the depletion region is confined to the interposing layer.

43. A varactor device as claimed in claim 40 wherein the conducting region comprises a compound semiconductor material comprising an arsenide.

44. A varactor device as claimed in claim 40 wherein the interposing layer comprises a compound semiconductor materia) comprising a phosphide.

45. A varactor as claimed in claim 40 wherein the interposing layer comprises a compound semiconductor material comprising one or a combination of: indium (In); Gallium (Ga); Aluminium (Al);

Phosphorous (P); Arsenic (As).

46. A varactor as claimed in claim 40 wherein at least one of the anode and the cathode comprise a Schottky contact.

47. A varactor device comprising a layered material arrangement as claimed in any one of claims 32 to 39.

48. A compound semiconductor wafer comprising at least one of a pnp and an npn device wherein the wafer comprises a layered materia! arrangement as claimed in any one claims 32 to 39.

49. An integrated circuit comprising one or a combination of HBT devices fabricated in accordance with a method as claimed in any one of claims 1 to 31.

50. A circuit as claimed in claim 47 wherein at least one of the HBT devices is in a vertical formation as opposed to a lateral formation.

51. A method of controlling a transistor, the transistor forming at least one part of an electric circuit, the method comprising the steps of: coupling an input of an emission sensitive element to a first transistor, the coupling of the input being electrically isolated from the first transistor; providing feedback for the first transistor wherein the feedback comprises an output of the emission sensitive element.

52. A method as claimed in claim 51 wherein the step of providing feedback comprises the step of coupling the output of the emission sensitive element to the electric circuit.

53. A method as claimed in claim 51 or 52 wherein the step of coupling the first transistor to an emission sensitive element comprises detecting an emission from the first transistor at the emission sensitive element.

54. A method as claimed in claim 53 wherein the detected emission comprises an emission of radiation from the first transistor.

55. A method as claimed in claim 54 wherein the detected emission of radiation comprises one of: an optical emission; an infra-red emission; an ultra-violet emission.

56. A method as claimed in claim 53 wherein the detected emission comprises an emission of heat from the first transistor.

57. A method as claimed in claim 56 wherein the detected emission of heat comprises an emission of one of: radiative heat; convective heat.

58. A method as claimed in claim 51 wherein the emission sensitive element is a second transistor.

59. A method as claimed in claim 58 wherein the first and second transistors reside on the same semiconductive substrate.

60. A method as claimed in claim 51 wherein the step of providing feedback comprises: providing negative feedback to the first transistor to stabilise an operating point of the first transistor.

61. A method as claimed in claim 60 wherein the step of providing negative feedback comprises the steps of: applying a DC bias current to the base of the first transistor for establishing the operating point; coupling an emission of the first transistor proportional to its operating current to the emission sensitive element; coupling an output of the emission sensitive element proportional to a detected emission of the first transistor to a third transistor forming a part of the electric circuit where the electric circuit is configured such that the third transistor is adapted to conduct in proportion to the output of the emjssion sensitive element and deflect a corresponding proportion of the first transistor's base current.

62. A method as claimed in claim 60 further comprising the step of: providing additional circuit elements to the electric circuit for stabilising a negative feedback loop formed by the first transistor, the emission sensitive element and the third transistor.

63. A method of fabricating an electric circuit comprising the steps of: providing a layered arrangement of semiconductor materials comprising a collector region, a base layer and at ieast one emitter structure supported on a substrate; forming a first transistor structure from the layered arrangement; forming an emission sensitive element from the layered arrangement; isolating the emission sensitive element from the first transistor.

64. A method as claimed in claim 63 wherein the step of isolating the emission sensitive element comprises the steps of: disconnecting the base layer of the emission sensitive element from the base layer of the first transistor.

65. A method as claimed in claim 64 further comprising the step of: forming the first transistor from multiple fingers of the emitter structure.

.

66. A method as claimed in any one of claims 51 to 65, wherein the method controls a thermal runaway effect.

67. A method as claimed in any one of claims 51 to 65, wherein the method controls a bias level of the first transistor.

68. Apparatus for controlling a transistor, the transistor forming at least one part of an electric circuit, the apparatus comprising: an emission sensitive element; first coupling means for coupling a first transistor to the emission sensitive element through a pathway electrically isolated from the electric circuit; feedback means for providing feedback for the first transistor wherein the feedback comprises an output of the emission sensitive element.

69. Apparatus as claimed in claim 68 further comprising: second coupling means for coupling the output of the emission sensitive element to the electric circuit.

70. Apparatus as claimed in claim 69 wherein the second coupling means comprises a third transistor forming part of the electric circuit wherein the third transistor is adapted to conduct in proportion to the output of the emission sensitive element and deflect a corresponding proportion of the first transistor's base current.

71. A HBT circuit comprising: a layered arrangement of semiconductor materials comprising a collector region, a base layer and at least one emitter structure supported on a substrate; a first transistor structure formed from the layered arrangement; an emission sensitive element formed from the layered arrangement; isolating means operatively associated with the layered arrangement for isolating the emission sensitive element from the first transistor

72. A HBT circuit as claimed in claim 71 wherein the isolating means comprises etched portions of the layered arrangement adapted to disconnect the base layer of. the emission sensitive element from the base layer of the first transistor.

73. A HBT circuit as claimed in claim 71 or 72 wherein the first transistor comprises multiple fingers of an emitter structure of the layered arrangement.

74. A HBT device manufactured in accordance with the method steps as claimed in any one of claims 63 to 67.

75. Apparatus adapted for controlling HBT semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform the method steps of any one of claims 51 to 62.

76. A computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for controlling HBT semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing the method steps of any one of claims 51 to 62.

77. A method of isolating layers of a HBT device the method comprising the steps of: separating an edge of a base layer from an edge of a collector region.

78. A method as claimed in claim 77 wherein the step of separating comprises the step of: converting a portion of the layers to an insulating state.

79. A method as claimed in claim 78 wherein the converted portion comprises an isolating region peripheral of the HBT device.

80. A method as claimed in claim 78 or 79 wherein the step of converting comprises an implantation process.

81. A method as claimed in claim 80 wherein the implantation process forms a peripheral isolating region comprising a varying depth.

82. A method as claimed in claim 80 or 81 wherein the step of converting further comprises the steps of: implanting a first region of the converted portion to a first depth; implanting a second region of the converted portion to a second depth.

83. A method as claimed in claim 82 further comprising the steps of: applying a first attenuation layer to the HBT device corresponding to the first region for restricting the implantation process to the first depth within the first region.

84. A method as claimed in claim 83 further comprising the step of: selecting a thickness of the first attenuation layer for correspondingly selecting the magnitude of the first depth.

85. A method as claimed in claim 83 or 84 further comprising the step of: applying a second attenuation layer to a region corresponding to an active region of the HBT device for restricting the implantation process to the second attenuation layer,

86. A method as claimed in claim 83 wherein the first attenuation layer comprises material(s) semi-transparent to an implantation process.

87. A method as claimed in claim 85 wherein the second attenuation layer comprises material(s) for blocking an implantation process.

88. A method as claimed in any one of claims 83 to 87 wherein the attenuation layers comprise masking material(s).

89. A method as claimed in claim 88 wherein the masking material(s) comprise one or a combination of: photoresist; photo-imageable polymer; a substantially metallic material; a substantially dielectric material.

90. A method as claimed in claim 82 wherein the second depth is greater than the first depth.

91. A method as claimed in claim 90 wherein the thickness of the first region of the converted portion substantially corresponds to a thickness slightly greater than a combined thickness of the emitter and base layers of the HBT device.

92. A method as claimed in claim 90 wherein the thickness of the second region of the converted portion substantially corresponds to a thickness slightly greater than a combined thickness of the emitter, base and collector layers of the HBT device.

93. A layered material arrangement suitable for use in fabricating a HBT device, the arrangement comprising: a plurality of material layers adapted to form a HBT device; at least one first attenuation layer applied to a portion of the plurality of material layers and adapted to attenuate an implantation process applied the plurality of material layers.

94. An arrangement as claimed in claim 93 wherein the at least one first attenuation layer comprises a material semi-transparent to the implantation process

95. An arrangement as claimed in claim 94 wherein the thickness of the at least one first attenuation layer determines a depth of a first implanted region within a peripheral isolated portion of the plurality of material layers.

96. An arrangement as claimed in claim 95 wherein the peripheral isolated portion comprises a variable depth within the plurality of layers and corresponding, in part, to the depth of the first implanted region.

97. An arrangement as claimed in claim 95 wherein the first implanted region is adapted to separate at least one edge of a base layer of the HBT device from a at least one edge of a collector region of the HBT device.

98. An arrangement as claimed in claim 96 or 97 further comprising a second implanted region within the peripheral isolated portion.

99. An arrangement as claimed in claim 98 wherein the second implanted region comprises a depth within the peripheral isolated portion substantially greater than the depth of the first implanted region.

100. An arrangement as claimed in claim 99 wherein the depth of the second implanted region corresponds to part of the depth of the peripheral isolated portion.

101. An arrangement as claimed in claim 99 or 100 wherein the depth of the first implanted region extends to slightly below the base layer of the HBT.

102. An arrangement as claimed in claim 99, 100 or 101 wherein the depth of the second implanted region extends to slightly below the collector region of the HBT.

103. An arrangement as claimed in claim 93 further comprising at least one second attenuation layer applied to a portion of the first attenuation layer and adapted to attenuate an implantation process applied the plurality of material layers such that the implantation process is restricted from affecting the underlying plurality of material layers adapted to form a HBT device.

104. A HBT device structure comprising: a layered material arrangement comprising a collector region, a base layer and an emitter structure supported by a substrate; wherein at least one edge of the base layer is separated from an edge of the collector region,

105. A HBT device structure comprising: a layered material arrangement comprising a collector region, a base layer and an emitter structure supported by a substrate; a peripheral isolated portion proximate the layered arrangement wherein the peripheral isolated portion comprises a variable depth within the layered arrangement.

106. A structure as claimed in claim 105 wherein the peripheral isolated portion comprises at least a first and a second implanted region(s).

107. A structure as claimed in claim 106 wherein the first implanted region is adapted to separate at least one edge of the base layer from at least one edge of the collector region.

108. A structure as claimed in claim 106 wherein the second implanted region comprises a depth within the peripheral isolated portion substantially greater than the depth of the first implanted region

109. A structure as claimed in claim 108 wherein the depth of the first implanted region extends to slightly below the base layer.

110. A structure as claimed in claim 108 wherein the depth of the second implanted region extends to slightly below the collector region.

111. A structure as claimed in claim 105 further comprising: an ohmic contact for the emitter, and; an interconnecting metalisation portion operatively associated with the emitter ohmic contact wherein the interconnecting metalisation portion is disposed only in the peripheral isolated portion.

112. A structure as claimed in claim 105 wherein the collector region and the base layer comprises one or more compound semiconductor materials.

113. A structure as claimed in claim 105 wherein the emitter layer comprises one or more compound semiconductor materials.

114. A structure as claimed in claim 112 or 113 wherein the compound semiconductor material comprises at least one or more of:

GaAs; InGaAs; InGaP;

AIGaAs.

115. A bipolar transistor device structure for an integrated circuit comprising a semiconductor substrate having a layered arrangement of semiconductor material comprising, a subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcoflector region, at least one base layer overlying the collector layer and at least one emitter iayer overlying the base layer, wherein an active region of the device is defined by a surrounding electrically isolating portion of the layered arrangement of variable thickness and the at least one emitter layer comprises an emitter having an emitter mesa structure which extends outside of the active region and into the isolating portion.

116. A method of manufacturing a semiconductor device comprising the steps of any one of claims 77 to 92.

117. A method of forming a HBT device, comprising the step of: providing a mask to restrict the penetration depth of an implant process.

118. A method as claimed in claim 116, wherein the thickness of the mask also determines implant depth.

119. A HBT device comprising: a number of layers, at least one layer being an base layer and another layers being a collector layer, wherein one edge of the base layer is separated from an edge of the collector layer.

120. A device as claimed in claim 119, wherein the separation is vertical and/or horizontal with respect to the number of layers.

121. A method of fabricating a combined integrated HBT and FET device, the method comprising the steps of: providing a number of first layers adapted to form a HBT device; providing, in addition to the first layers, second layer(s) which are adapted to form a FET device.

122. A method as claimed in claim 121, wherein the second layers are provided above a substrate layer of the first layers.

123. A method as claimed in claim 121, wherein the second layer(s) are above the first layers.

124. A method as claimed in claim 121 , 122 or 123, wherein the second layer(s) comprise a FET barrier layer.

125. A method as claimed in any one of claims 121 to 124, wherein the second layer(s) further comprise an additional FET channel layer.

126. A method as claimed in claim 121 wherein the step of adapting a number of second layers of the arrangement to form a FET device comprises the step of: etching the first layers.

127. A method as claimed in claim 126 wherein at least one of the second layers is adapted to serve as an etch stop.

128. A method as claimed in claim 121 wherein at least one of the second layers is adapted to increase a Schottky barrier height of a gate contact of the

FET device with respect to another one of the second layers.

129. A method as claimed in claim 127 or 128 wherein the at least one of the second layers comprises a FET barrier material that is crystal matched to the substrate.

130. A method as claimed in claim 121 further comprising the steps of: depositing a first contact on the second layers; depositing second contacts on the second layers.

131. A method as claimed in claim 130 wherein the first contact is adapted to form a Schottky contact to a first FET barrier layer of the second layers.

132. A method as claimed in claim 130 wherein the step of depositing second contacts further comprises the step of: forming ohmic contacts to a second FET channel layer of the second layers.

133. A method as claimed in claim 132 wherein the step of forming ohmic contacts further comprises the step of: heating the second contacts so as to diffuse material of the second contacts into the FET channel layer to form the ohmic contacts.

134. A method as claimed in claim 130 wherein, prior to the steps of depositing contacts, the method further comprises the step of: removing a FET barrier layer of the second layers.

135. A method of manufacturing an integrated HBT and FET device comprising the steps of: providing a layered material arrangement upon a substrate; adapting a number of first layers of the arrangement to form a HBT device; adapting an ohmic contact layer of the HBT device to form at least one layer of a FET device.

136. A method as claimed in 135 wherein the at least one layer of the FET device comprises a FET conducting channel layer.

137. A method as claimed in claim 135 or 136 further comprising the step of: providing an additional FET barrier layer over the layered material arrangement in the vicinity of the FET device.

138. A method as claimed in claim 137 wherein the FET barrier layer is adapted to provide a higher Schottky barrier height for the FET device with respect to the ohmic contact layer of the HBT device which forms a conducting channel of the FET device.

139. A method as claimed in claim 137 wherein the FET barrier layer comprises a material that is readily etched as compared to underlying layers.

140. A method as claimed in claim 139 further comprising the steps of: selectively etching the FET barrier layer to expose edges of the FET barrier layer.

141. A method as claimed in claim 137 further comprising the steps of: depositing a first contact on the FET barrier layer; depositing second contacts on the FET conducting channel layer.

142. A method as claimed in claim 141 wherein the step of depositing second contacts on the FET conducting channel layer comprises the same process step as depositing an emitter contact for the HBT device.

143. A method as claimed in claim 126 or 134 wherein the FET barrier material comprises one or a combination of:

InGaP; AIGaAs.

144. A method as claimed in claim 130 or 141 wherein the material of the second contacts comprises one or a combination of:

Nickel; Germanium; Gold.

145. A method as claimed in claim 130 or 141 wherein the material of the first contact comprises one of the following combinations:

Titanium/Platinum/Gold; Platinum/Titanium/Platinum/Gold

146. A method as claimed in claim 130 or 141 wherein the first contact comprises a gate of the FET.

147. A method as claimed in claim 130 or 141 wherein the second contacts comprise a source and a drain of the FET.

148. A method as claimed in claim 121 or 135 further comprising the step of: Isolating the HBT from the FET.

149. A method as claimed in claim 121 , 135 or 148 wherein the HBT and/or the FET are in a lateral formation.

150. A layered material arrangement suitable for use in fabricating an integrated HBT/FET device structure, the arrangement comprising: a plurality of first layers; one or more second layer(s) disposed in addition to the first layers, the first layers being adapted to form a HBT device, and the second layer(s) being adapted to form a FET device.

151. An arrangement as claimed in claim 150, wherein the second layers are provided above a substrate layer of the first layers.

152. An arrangement as claimed in claim 150, wherein the second layer(s) are above the first layers.

153. An arrangement as claimed in claim 150, 151 or 152, wherein the second layer(s) comprise a FET barrier layer.

154. An arrangement as claimed in any one of claims 150 to 153, wherein the second layer(s) further comprise an additional FET channel layer.

155. An arrangement as claimed in claim 154 wherein the FET barrier layer is adapted to form an etch stop.

156. An arrangement as claimed in claim 150 wherein the second layers comprise: a subcollector layer; a collector layer; a base layer; an emitter layer.

157. An arrangement as claimed in claim 154 wherein the FET barrier material comprises one or a combination of: InGaP; AIGaAs.

158. A layered material arrangement suitable for use in fabricating an integrated HBTYFET device structure, the arrangement comprising: a substrate; a number of first layers operatively coupled to the substrate and adapted to form a HBT device; an ohmic contact layer of the HBT device adapted to form at least one layer of a FET device.

159. An arrangement as claimed in claim 158 wherein the at least one layer of the FET device comprises a FET conducting channel layer.

160. An arrangement as claimed in claim 159 further comprising an additional FET barrier layer deposited over the FET conducting channel layer.

161. An arrangement as claimed in claim 160 wherein the FET barrier material comprises one or a combination of:

InGaP;

AIGaAs;

InP; GaAs.

162. An electronic circuit comprising a heterojunction bipolar transistor and a field effect transistor wherein the transistors comprise a layered material arrangement as claimed in any one of claims 150 to 161.

163. A semiconductive wafer comprising a layered material arrangement as claimed in any one of claims 150 to 161.

164. A semiconductive substrate comprising a layered material arrangement as claimed in any one of claims 150 to 161.

165. A semiconductive wafer manufactured in accordance with a method as claimed in any one of claims 121 to 149.

166. A semiconductive substrate manufactured in accordance with a method as claimed in any one of claims 121 to 149.

167. An integrated compound semiconductor device comprising a HBT and one of a MESFETs, pHEMT or a FET manufactured in accordance with a method as claimed in any one of claims 121 to 149.

168. A method of fabricating a semiconductor device comprising the steps of: providing a composite substrate, the composite substrate comprising a semiconductive wafer bonded to a substantially metallic substrate for supporting the semiconductive wafer: providing at least one via structure disposed from the wafer side of the composite substrate towards the substantially metallic substrate side of the composite substrate; providing a layered arrangement of material within the via structure wherein the arrangement comprises an electric circuit component.

169. A method as claimed in claim 168 further comprising the step of: providing an electric connection between a portion of the electric circuit component and the substantially metallic substrate.

170. A method as claimed in claim 168 wherein the layered arrangement comprises; a first metallic layer; a second metallic layer, and; a substantially dielectric material layer interposed the first and second metallic layers.

171. A method as claimed in claim 168 wherein the layered arrangement comprises a volume of substantially cylindrical shape.

172. A method as claimed in claim 171 wherein the electric circuit component comprises a capacitor.

173. A method as claimed in claim 172 wherein the capacitor comprises a capacitance given by:

C₂ = Kτv² + K2πrύ where r = radius of the substantially cylindrical shape; d = height of the substantially cylindrical shape.

174. A method of forming a capacitive device in a semiconductive substrate, the method comprising the steps of: forming a via hole in the semiconductive substrate; utilising the via hole as at least a part of the capacitive device.

175. A method as claimed in claim 174 further comprising the step of: providing capacitive material in the via hole and forming at least part of the electrical plates of the capacitive device at each end of the via hole.

176_t A method as claimed in claim 175 wherein at least one plate is directly connected to a substrate layer of the semiconductive substrate.

177. A method as claimed in 175 or 176 wherein the plates are coupled to a plurality of via holes having capacitive material therein.

178. A method as claimed in any one of claims 174 to 177 wherein the capacitive device comprises a capacitor having a capacitance given by:

C₂ = Kπr² + K2πrd where r = radius of a substantially cylindrical shape corresponding to a via hole; d = height of the substantially cylindrical shape.

179. A semiconductor device comprising: a composite substrate, the composite substrate comprising a semiconductive wafer bonded to a substantially metallic substrate for supporting the semiconductive wafer; at least one via structure disposed from the wafer side of the composite substrate towards the substantially metallic substrate side of the composite substrate; a layered arrangement of material within the via structure wherein the arrangement comprises an electric circuit component.

180. A device as claimed in claim 179 further comprising: an electric connection between a portion of the electric circuit component and the substantially metallic substrate.

181. A device as claimed in claim 179 wherein the layered arrangement comprises; a first metallic layer; a second metallic layer, and; a substantially dielectric material layer interposed the first and second metallic layers.

182. A device as claimed in claim 179 wherein the layered arrangement comprises a volume of substantially cylindrical shape.

183. A device as claimed in claim 181 or 182 wherein the electric circuit component comprises a capacitor.

184. A device as claimed in claim 183 wherein the capacitor comprises a capacitance given by:

C₂ = Kπr² + K2πrd where r = radius of the substantially cylindrical shape; d = height of the substantially cylindrical shape.

185. A capacitive device suitable for use in a semiconductive substrate, the device comprising: a via hole in the semiconductor material adapted to form at least a part of the capacitive device.

186. A device as claimed in claim 185 further comprising- capacitive material disposed in the via hole and; wherein each end of the via hole is adapted to form at least part of the electrical plates of the capacitive device.

187. A device as claimed in claim 186 wherein at least one plate is directly connected to a substrate layer of the semiconductive substrate.

188. A device as claimed in claim 186 or 187 wherein the plates are coupled to a plurality of via holes having capacitive material therein.

189. A device as claimed in any one of claims 185 to 188 wherein the capacitive device comprises a capacitor having a capacitance given by:

C₂ = Kπr² + K2πrd ^• where r = radius of a substantially cylindrical shape corresponding to a via hole; d = height of the substantially cylindrical shape.

190. Apparatus adapted for manufacturing compound semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform the method steps of any one of claims 1 to 31 , 63 to 67, 77 to 92, 11.6 to 118, 121 to 149 and 168 to 178.

191. A computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing the method steps of any one of claims 1 to 31 , 63 to 67, 77 to 92, 116 to 118, 121 to 149 and 168 to 178.

192. A method or protocol substantially as herein described with reference to at least one of the accompanying drawings.

193. An apparatus, device, arrangement, substrate, article, circuit or assembly substantially as herein described with reference to at least one of the accompanying drawings.