WO2006129135A1

WO2006129135A1 - An interconnection structure for electronic components, an electronic component and methods for producing the same

Info

Publication number: WO2006129135A1
Application number: PCT/IB2005/001559
Authority: WO
Inventors: Alfred Swain Hong Yeo; Kai Chong Chan
Original assignee: Infineon Technologies Ag
Priority date: 2005-06-02
Filing date: 2005-06-02
Publication date: 2006-12-07

Abstract

An interconnection structure (3; 44) for electronic components comprises a contact pad (6; 46) and an electrically insulating layer (7; 48) which covers the peripheral regions (8; 49) of the contact pad (6; 46). The interconnection structure (3; 44) further comprises an electrically conductive layer (12; 53) disposed on the central portion (9; 52) of the contact pad (6; 46) and on adjacent regions of the electrically insulating layer (7; 48). The inner surface (16; 58) of the electrically conductive layer (12; 53) comprises at least one protrusion (15; 57) disposed in a peripheral region (20; 59).

Description

An interconnection structure for electronic components, an electronic component and methods for producing the same

The invention relates to electronic components and, in particular, to interconnection structures for electronic components .

Electronic components such as semiconductor packages can have a variety of different types of interconnection structures which- enable the semiconductor chip to be mounted on, and electrically connected to, a circuit carrier. The interconnection structure may electrically connect the semiconductor chip to a substrate within the semiconductor package or enable the package to be mounted on a higher level substrate such as a printed circuit board. An example of an interconnection structure is a contact pad with a solder ball disposed on the contact pad.

The materials of the semiconductor package, including the interconnection structure, have different coefficients of thermal expansion. If the package is subjected to thermal loading, cracks can form at the interfaces between the different mate- rials . Thermal loading can be caused by the solder reflow process which connects the chip to the circuit carrier, for example, or by heat generated by the chip during its operation. Cracks may form at the interface between the semiconductor chip and the encapsulation material or at the interface between the solder ball and the contact pad, for example. In semiconductor packages which further include under bump metallization (UBM) positioned on the contact pad, it has been found that cracks can also form at the interface between the under bump metallization and the passivation layer as well as at the interface between the under bump metallization and the solder ball. These cracks can result in the delamination of the flip chip contact from the bond pad and to failure of the semiconductor package.

US 6,744,142 discloses an under bump metallization which includes two or three layers of different metals to improve the adhesion of the under bump metallization to the contact pad. Additionally, a tin-based solder which includes copper particles is provided in order to improve the reliability of the interface between the under bump metallization and the solder ball.

However, the improvements to the reliability of the interconnection structure which can be achieved by adjusting the met- allurgy of the interfaces is limited. The multi-layer structure is also complex and complicated to manufacture which increases the cost of manufacturing the package.

It is, therefore, an object of the invention to provide a more reliable interconnection structure and an interconnection structure which can be more easily produced.

It is a further object of the invention to provide a semiconductor chip and a semiconductor package including a more reli- able interconnection structure. It is a further object of the invention to provide methods by which the interconnection structure, the semiconductor chip and the semiconductor package can be produced.

According to the invention, an interconnection structure for electronic components comprises a contact pad and an electrically insulating layer covering the peripheral regions of the contact pad. The central region of the contact pad remains exposed from the electrically insulating layer and provides an electrically conductive surface. An electrically conductive layer is disposed on the central portion of the contact pad and on regions of the electrically insulating layer adjacent the exposed central portion of the contact pad. The electrically conductive layer comprises an inner surface which faces towards the contact pad and the electrically insulating layer and an opposing outer surface which faces away from the contact pad and the electrically insulating layer. The inner surface of the electrically conductive layer comprises at least one protrusion which is disposed in a peripheral region of the electrically conductive layer.

The electrically conductive layer has defined lateral limits and can be described as a cap which includes a central region which is mechanically and electrically connected to a periph- eral region.

The protrusion extends from the inner surface of the electrically conductive layer and provides a mechanical anchoring or interlocking of the electrically conductive layer with the un- derlying element or elements of the interconnection structure.

The mechanical interlocking improves the structural integrity of the interconnection structure as the risk of delamination at the interfaces between the different layers is reduced. A more reliable interconnection structure and, therefore, a more mechanically and electrically reliable contact is provided.

The interconnection structure according to the invention can be advantageously used for an interconnection structure disposed on the active surface of a semiconductor chip such as flip chip type contacts . Alternatively, the interconnection structure can be disposed on the wiring substrate of a semi- conductor package, for example the rewiring substrate of a ball grid array (BGA) package. If, however, the interconnection structure is disposed on the active surface of a semiconductor chip, the electrically insulating layer is a passivation layer and the electrically conductive layer is, typi- cally, referred to as under bump metallization.

If the interconnection structure is disposed on the outer surface of the wiring substrate of a ball grid array package the electrically insulating layer is, typically, a solder resist layer.

In an embodiment, the electrically conductive layer comprises a depression in its central region and a raised annular ring in its peripheral region. The central depression of the elec- trically conductive layer is mechanically and electrically connected by side walls to the raised peripheral region. The electrically conductive layer, therefore, conforms to the underlying structure provided by the contact pad and electrically insulating layer. In this embodiment, the thickness of the electrically conductive layer is approximately the same in the central region and in the peripheral regions . Alternatively, the outer surface of the electrically conductive layer in the central and peripheral region is essentially coplanar. In this embodiment, the central region of the electrically conductive layer is thicker than the peripheral re- gion.

The exposed central region of the contact pad is, preferably, laterally essentially circular. Alternatively, the lateral shape of the exposed central region may be an n-sided polygon. The external contact which will be disposed on the interconnection structure is, typically, a solder ball. Therefore, a laterally essentially circular contact pad has the advantage of providing a uniform and homogenous strain distribution between the contact pad, electrically conductive layer and ex- ternal contact which further improves the reliability of the interconnection structure.

The outer edges of the electrically conductive layer are, preferably, concentric with the central portion of the elec- trically conductive layer and the exposed central region of the contact pad. This also provides a more uniform distribution of the interfacial strain and improves the reliability of the structure.

In an embodiment, the electrically conductive layer is, preferably, laterally essentially circular. This further improves the uniformity of the strain distribution, since the strain distribution at the interface between the outer surface of the electrically conductive layer and the solder ball is more uni- form. The electrically conductive layer may be laterally larger than the contact pad, laterally smaller than the contact pad or a laterally approximately the same size as the contact pad. For each of these embodiments, the advantage of an improved me- chanical anchoring or interlocking between the electrically conductive layer and the underlying element of the interconnection structure is provided by the protrusion disposed in the peripheral region of the inner surface of the electrically conductive layer.

In an embodiment of the invention, the protrusion is an annular ring. An annular ring has the advantage that a uniform mechanical interlocking between the electrically conductive layer and the underlying interconnection structure is pro- vided. Alternatively, the protrusion comprises a plurality of protrusions. This embodiment has the advantage that the inter- facial area between the inner surface of the electrically conductive layer and the underlying interconnection structure is increased. This further improves the mechanical interlocking and further reduces the risk of delamination at the interface.

The protrusion is, preferably, concentrically positioned around the central region of the electrically conductive layer. This arrangement advantageously provides a uniform me- chanical interlocking.

In an embodiment of the invention, the protrusion is positioned at the periphery of the electrically conductive layer. This has the advantage that the mechanical anchoring between the electrically conductive layer and the underlying interconnection structure is provided at the outside page of the electrically conductive layer. The cross-section of the peripheral edge of the electrically conductive layer, therefore, has an L-shape. This embodiment has the advantage that the risk of delamination of the electrically conductive layer from the electrically insulating layer due to undercutting is reduced.

It has been found that, in some situations, an undercut or small crack can be produced at the peripheral edge of the electrically conductive layer and, more specifically, at the interface between the electrically insulating layer and the electrically conductive layer. The formation of an under cut or crack is thought to be caused by the processing conditions, such as the etching process while removing the electrically conductive layer. The formation of an undercut can lead to de- lamination of the electrically conductive layer from the con- tact pad. This problem can be reduced by positioning the protrusion at the periphery of the electrically conductive layer.

Preferably, the protrusion is in contact with the electrically insulating layer. This further reduces the risk of delamina- tion at the interface. The electrically insulating layer, therefore, preferably includes at least one depression. The lateral size and arrangement of the depression, therefore, corresponds to the lateral size and arrangement of the protrusion. The depression in the passivation layer is, therefore, essentially filled by the material of the protrusion.

This structure provides an improved mechanical interlocking between the electrically conductive layer and the electrically insulating layer. This is particularly advantageous as the mismatch between the coefficients of thermal expansion of the materials of the electrically conductive layer and the electrically insulating layer is, typically, relatively large. W

In an embodiment, the outer surface of the electrically conductive layer comprises a depression located above the protrusion. In this embodiment, the electrically conductive layer conforms with the underlying shape of the interconnection structure and has a more homogenous thickness.

In an embodiment, the protrusion in the inner surface of the electrically conductive layer is disposed above the contact pad. The protrusion may be in contact with the electrically insulating layer or may be in contact with the contact pad. This arrangement provides an improved mechanical interlocking between the electrically conductive layer and the underlying structure of the interconnection structure towards the centre of the interconnection structure. The underlying structure can be the electrically insulating layer. Alternatively, an interlocking arrangement between an upper electrically conductive layer and the contact pad may be provided.

Alternatively, the protrusion is disposed laterally adjacent the contact pad. In this embodiment, the electrically conductive layer has the form of a cap which is laterally larger than the contact pad. An improved interlocking of the electrically conductive layer with the electrically insulating layer is provided towards the periphery of the interconnection structure.

The contact may comprise aluminium or copper or an alloy comprising aluminium or copper. The electrically conductive layer may comprise at least two layers. A multi-layer structure has the advantage that by selecting the appropriate combination of materials for the different layers, the metallurgical reac- tions between the materials can provide improved adhesion and can act as a protective layer for the contact pad. The electrically conductive layer may comprise a layer of Cr and a layer of Cu.

The interconnection structure may also further comprise a solder bump or solder ball disposed on the outer surface of the electrically conductive layer. The solder bump or ball enables the interconnection structure to be electrically and mechani- cally connected to a further circuit carrier.

The invention also provides a semiconductor chip which comprises an active surface and a passive surface. The active surface comprises a plurality of integrated circuit devices and a plurality of interconnection structures according to one of the embodiments already described. The active surface, therefore, comprises a plurality of contact pads. Preferably, the contact pads have a flip chip arrangement.

The invention also relates to a semiconductor wafer comprising a plurality of semiconductor chips which include a plurality of interconnection structures according to one of the embodiment already described. A plurality of solder bumps or solder balls may be disposed on the interconnection structures at the wafer level. This has the advantage that the interconnection structures as well as the contacts can be produced for a large number of chips in the same process step. This reduces the production costs of the semiconductor chip and, consequently, also a semiconductor package including the chip.

The invention also provides a semiconductor package comprising a semiconductor chip according to one of the embodiments pre- viously described. The semiconductor chip, therefore, comprises a plurality of contact pads each comprising an interconnection structure according to an embodiment of the invention.

The package further comprises a substrate having an upper surface and a lower surface. The substrate comprises a plurality of inner contact pads disposed on the upper surface and a plurality of outer contact pads disposed on the lower surface. The plurality of inner contact pads have a lateral arrangement corresponding to the lateral arrangement of the contact pads on the semiconductor chip. The substrate further includes a rewiring structure comprising conductor tracks and vias which electrically connect the inner contact pads with the outer contact pads.

The semiconductor chip is electrically connected to the upper surface of the substrate by a plurality of flip chip connections which, preferably, comprises a solder ball or a solder bump. A flip chip connection is disposed between each of the plurality of inner contact pads and the electrically conductive layer of the interconnection structure which is disposed on each of the plurality of contact pads on the semiconductor chip .

The semiconductor package may also further comprise underfill material which encapsulates at least the flip chip connections and, preferably, essentially fills the cavity formed between the active surface of the semiconductor chip and the upper surface of the substrate. The underfill material, preferably, comprises epoxy resin and provides additional mechanical strength for the flip chip connections. The package may further comprise mold material, typically a plastic, which encapsulates at least the passive surface of the semiconductor chip. The mold material provides the plastic housing of the package and protects the semiconductor chip from environmental and mechanical damage.

The invention also relates to methods to fabricate an interconnection structure for an electronic component. A method comprises providing at least one contact pad. An electrically insulating layer is then deposited on the contact pad so that the central portion of the contact pad remains exposed from the electrically insulating layer. The peripheral regions of the contact pad are covered by the insulating layer.

An electrically conductive layer is then disposed on the central portion of the contact pad and on regions of the electrically insulating layer adjacent to the exposed central portion of the contact pad. The central and peripheral regions of the electrically conductive layer are conjoined. The electrically conductive layer has an inner surface which faces towards the contact pad and insulating layer and an opposing outer surface which faces away from the contact pad and insulating layer.

The electrically conductive layer has a thickness and lateral dimensions. The inner surface of the electrically conductive layer comprises at least one protrusion disposed in a peripheral region of the electrically conductive layer. The protrusion, therefore, protrudes from the electrically conductive layer towards the electrically insulating layer and the contact pad. Preferably, at least one depression is formed in the outer surface of the electrically insulating layer in a region which is laterally adjacent the exposed central portion of the contact pad. This provides a structure so that during the deposi- tion of the electrically conductive layer, the depression is essentially filled by a portion of the electrically conductive layer. This forms the protrusion on the inner surface of the electrically conductive layer.

Typically, a plurality of interconnection structures are fabricated in parallel or at essentially simultaneously. Therefore, in order to create a plurality of electrically conductive layers, each electrically and physically isolated from the others, a closed electrically conductive layer may be de- posited and then portions removed by, for example, etching to produce an electrically conductive layer on each contact pad. Alternatively, a mask may be used to selectively deposit an electrically conductive layer having a thickness and lateral dimensions on each contact pad.

The electrically conductive layer is, preferably, deposited by a vacuum deposition technique. In an embodiment, the electrically conductive layer is formed by the sequential deposition of at least two electrically conductive layers, preferably, comprising different materials.

The structured electrically insulating layer is, in an embodiment, formed by depositing a closed electrically insulating layer. Typically, the entire surface which includes the con- tact pads is covered by a closed electrically insulating layer. Portions of the electrically insulating layer are then removed to expose the central portion of the contact pad and to form the depression.

If the contact pad is disposed on the active surface of a semiconductor chip, the electrically insulating layer is, typically, a passivation layer. If the contact pads are located on a rewiring substrate, the electrically insulating layer is, typically, a solder resist layer.

The method may also comprise the following further steps to form a solder ball on the electrically conductive layer of the interconnection structure. A closed photoresist coating is deposited on the electrically conductive layer. Portions of the resist coating are removed to form a through-opening which exposes the central portion of the electrically conductive layer.

Solder is then deposited to at least fill the opening. The resist coating is then removed to create a solder column or, more preferably, a solder bump with a mushroom-shape. The electrically conductive layer which is exposed at the periphery of the interconnection structure is removed. This is, preferably, performed by an etching technique. The solder is then reflowed creating a solder ball due to the effect of surface tension.

Advantageously, the solder is deposited by an electro- deposition technique. This has the advantage of producing a large number of solder connections in the same process step.

The invention also provides a method of fabricating a semiconductor chip. A semiconductor wafer is provided which comprises a plurality of semiconductor chips, each semiconductor chip comprising a plurality of contact pads. An interconnection structure, according to the invention, is produced for each of the plurality of contact pads by one of the methods previously described. The semiconductor chips are then singulated from the wafer. This is typically performed by a sawing process.

The invention also provides a method to assemble a semiconductor package. A semiconductor chip is provided which comprises an active surface and a passive surface. The active surface comprises a plurality of integrated circuit devices and a plurality of interconnection structures according to one of the embodiments previously described. Each interconnect structure, therefore, comprises a contact pad, an electrically insulating layer and an electrically conductive layer with a protrusion disposed in the peripheral region of its inner surface.

A plurality of flip chip contacts comprising solder bumps or solder balls are disposed on the outer surface of each of the electrically conductive layers of the plurality of interconnection structures.

A substrate having an upper surface and a lower surface is provided. The substrate comprises a plurality of inner contact pads on the upper surface and a plurality of outer contact pads on the lower surface. The plurality of inner contact pads have a lateral arrangement corresponding to the lateral arrangement of the contact pads on the semiconductor chip. The substrate also comprises a rewiring structure including con- ductor tracks and vias which electrically connect the plurality of inner contact pads and the plurality of outer contact pads . The semiconductor chip is mounted on the upper surface of the substrate so that a flip chip contact is disposed between the plurality of electrically conductive layers disposed on the plurality of chip contact pads and the inner contact pads disposed on the substrate. The solder is then reflowed to electrically and mechanically connect the semiconductor chip to the substrate.

In a possible further step, after the chip is mounted to the substrate, the plurality of flip chip contacts are encapsulated in underfill material. This provides an additional mechanical protection for the flip chip connections. In an embodiment, a molded semiconductor package is provided by encap- sulating at least the passive surface of the semiconductor chip in mold material. This provides a further mechanical and environmental protection for the semiconductor chip.

The interconnection structure according to the invention pro- vides an improved mechanical anchoring between an electrically conducting layer, an electrically insulating layer and a contact pad. This structure is advantageously used in the flip chip connections of a semiconductor chip as delamination can occur between the under bump metallization or electrically conducting layer and the passivation or electrically insulating layer.

Delamination can occur as the flip chip solder interconnects are subjected to a high shear deformation mode. This is caused by the large mismatch in coefficients of thermal expansion. At the elevated temperatures which can occur during the assembly process, for example during the solder reflow process and dur- ing the curing of the underfill material, the mismatch causes a shear stress in the flip chip connections .

If the shear load exceeds a certain threshold interfacial strength value, cracks can be initiated at the undercut area, i.e. between the passivation layer and the peripheral regions of the under bump metallization. This undercut area is vulnerable to interfacial crack propagation upon thermal loading as, it is believed, there is a high stress concentration in this region.

The invention provides an improved mechanical interlocking and anchoring between the under bump metallization and the passivation layer by providing a protrusion in the inner surface of the under bump metallization. The protrusion of the under bump metallization is able to better interlock with the passivation layer. In an embodiment, the protrusion is located at the periphery of the under bump metallization, which practically eliminates the possibility of undercutting at the pe- riphery of the under bump metallization. Therefore, a more reliable and more robust interconnection structure is provided.

Embodiments of the invention will now be described with reference to the diagrams .

Figure 1 shows a semiconductor package with interconnection structures according to a first embodiment of the invention, and

Figure 2 shows a detailed view of the interconnection structure of the package of Figure 1. Figures 3 to 8 illustrate an interconnection structure according to a second embodiment of the invention and steps in a method of producing the interconnection structure.

Figure 3 shows the formation of a structured passivation layer above a chip contact pad,

Figure 4 illustrates the deposition of under bump metallization on the structured passivation layer,

Figure 5 depicts the deposition of a photoresist layer,

Figure 6 illustrates the formation of a through-opening above the under bump metallization,

Figure 7 shows the electro-deposition of a solder bump in the through-opening of Figure 7, and

Figure 8 illustrates the removal of the photoresist layer.

Figure 9 shows an interconnection structure according to a third embodiment of the invention.

Figure 1 illustrates a semiconductor package 1 including a semiconductor chip 2 which includes a plurality of interconnection structures 3 according to a first embodiment of the invention. Each of the plurality of interconnection structures 3 is essentially the same.

The various features of the semiconductor package 1 are not drawn to scale and, in particular, the size of the interconnection structures 3 and flip chip contacts 4 are exaggerated in order to more clearly illustrate the invention. The interconnection structure 3 is illustrated in more detail in Figure 2. The same reference number is used to denote the same feature in all of the figures .

The semiconductor chip 2 has an active surface 5 including integrated circuit elements (which are not illustrated in the figures) and plurality of interconnection structures 3. An interconnection structure 3 comprises a chip contact pad 6, por- tions of a passivation layer 7 and an under bump metallization 12 which comprises at least one electrically conductive layer. The chip contact pads 6 comprise aluminium.

The passivation layer 7 is disposed on peripheral regions 8 of the chip contact pad 6 and the under bump metallization 12 is disposed on the central region 9 of the chip contact pad 6 and on regions of the passivation layer 7 contiguous to the central region 9 of the chip contact pad 6.

The inner surface 16 of the under bump metallization 12 includes a protrusion 15 in its peripheral region which essentially fills a depression 10 located in the outer surface 11 of the passivation layer 7. The protrusion 15 provides an improved mechanical interlocking between the under bump metalli- zation 12 and the passivation layer 7 and provides a more mechanically robust and, therefore, reliable interconnection structure.

The interconnection structure 3 will now be described in more detail with reference to the detailed view of Figure 2. Figure

2 shows a single interconnection structure 3 disposed on the active surface 5 of a semiconductor chip 2. The passivation layer 7 is disposed on the active surface 5 of the semiconductor chip 2 and covers the peripheral regions 8 of each of the chip contact pads 6. The central region 9 of each of the chip contact pads 6 remains free from the passivation layer 7. The plurality of chip contact pads 6 and the plurality of central portions 9 which lie exposed in the passivation layer 7 are laterally essentially circular. The exposed central potion 9 is located in the approximate lateral centre of the contact pad 6.

The passivation layer 7 is deposited essentially conformerly on the active surface of the semiconductor chip 2. The thickness of the passivation layer 7 is, therefore, essentially the same in the portion deposited directly on the active surface 5 of the semiconductor chip and in the portion disposed on the peripheral regions 8 of the chip contact pads 6. Therefore, the outer surface 11 of the portion of the passivation layer 7 disposed on the peripheral regions 8 of the contact pads 6 lies in a plane at a greater distance from the active surface 5 of the semiconductor chip 2 than the outer surface 11 of the portion disposed directly on the active surface 5 of the semiconductor chip 2.

The passivation layer 7 also includes a depression 10 posi- tioned in the outer surface 11. The depression 10 is positioned in the passivation layer 7 above the peripheral regions 8 of the chip contact pad 6 and is concentrically arranged laterally surrounding the central region 9. In this embodiment of the invention, the depression 10 has the form of an annular ring, which cannot be seen in the cross-section of figures 1 and 2. The depression 10 has a cross-section which is essentially rectangular. The under bump metallization 12 comprises two electrically conductive layers 13, 14, each comprising a different metal. The under bump metallization 12 is disposed on the central re- gion 9 of the chip contact pad 6 and on the outer surface 11 of the passivation layer 7 which is positioned above the peripheral regions 8 of the chip contact pad 6. The under bump metallization 12 is in electrical contact with the central region 9 of the chip contact pad 6. The lateral extent of the under bump metallization 12 is, in this embodiment of the invention, approximately the same as that of the chip contact pad 6.

The under bump metallization 12 has approximately the same thickness in its central region 19 and in its peripheral regions 20. The under bump metallization 12, therefore, comprises a central depression 21 mechanically linked by side walls 22 to a raised peripheral region 23. In this embodiment, the central depression 22 is laterally essentially circular and the raised peripheral region 23 is a concentrically arranged annular ring.

The first layer 13 of the under bump metallization 12 is an adhesion layer and comprises, in this example, chromium and is disposed directly on the exposed central portion 9 of the chip contact pad 6 and on the outer surface 11 of the portion of the passivation layer 7 disposed on the peripheral regions 8 of the chip contact pad 6. The first electrically conductive layer 13 is in contact with the side faces and base of the de- pression 10 formed in the outer surface 11 of the passivation layer 7. The second electrically conductive layer 14 is the wetting layer of the under bump metallization 12 and, in this example, comprises copper. The second electrically conductive layer 14 is disposed on the first electrically conductive layer 13. The inner surface 16 of the under bump metallization 12, therefore, includes a protrusion 15 which essentially fills the depression 10 in the outer surface of the passivation layer 7. The protrusion 15 provides an improved mechanical interlocking between the under bump metallization 12 and the passivation layer 7. The outer surface 17 of the under bump metallization 12 includes a depression 18 located above the depression 10 in the passivation layer 7. A flip chip contact 4 which comprises a solder ball is disposed on the outer surface 17 of the under bump metallization 12.

As is illustrated in the cross-sectional view of the semiconductor package 1 in Figure 1, the semiconductor chip 2 including a plurality of interconnection structures 3 is mounted on a re-wiring substrate 24. The re-wiring substrate 24 includes a plurality of inner contact areas 25 on its upper surface and a plurality of outer contact areas 26 on its lower surface. The inner contact areas 25 are electrically connected by metallic conductor tracks 27 and plated vias 28, which stretch from the upper surface to the lower surface of the substrate 24, to the outer contact areas 26. The conductor tracks 27 and vias 28 provide the rewiring structure of the substrate 24. The inner contact areas 25, outer contact areas 26, conductor tracks 27 and vias 27 typically comprise copper or a copper alloy.

The upper surface of the substrate 24 further includes a solder resist layer 29 which covers the upper surface leaving the plurality of inner contact areas 25 exposed from the solder resist layer 29. The plurality of inner contact areas 25 has a lateral arrangement which corresponds to the lateral arrangement of the chip contact pads 6 and interconnection structures 3 which are disposed on the active surface 5 of the semiconductor chip 2. A flip chip contact 4, which comprises a solder ball, is disposed between each of the plurality of inner contact areas 25 and each of the plurality of interconnection structures 3 disposed on the active surface 5 of the semicon- duetor chip 2.

In this embodiment of the invention, the cavity formed between the upper surface of the substrate 24 in the region which includes the inner contact areas 25 and the active surface 5 of the semiconductor chip 2 is filled by underfill material 30.

The underfill material further protects the flip chip contacts 4 from mechanical stress caused by, for example, thermal cycling.

The passive rear surface of the semiconductor chip 2 and the remaining peripheral regions of the upper surface of the rewiring substrate 24 are embedded in a plastic encapsulation compound 31. The plastic encapsulation or mold compound 31 protects the semiconductor chip 2 from the environment and from mechanical damage. The outer surfaces of the plastic encapsulation material 31 provide the upper and side faces of the semiconductor package 1.

Figures 3 to 8 illustrate steps in a method to produce an in- terconnect structure 3 according to a second embodiment of the invention. For clarity, the method is described in relation to a single chip contact pad 6 located on the active surface of a semiconductor chip 2. However, in practice each step is carried out for a plurality of chip contact pads 6 disposed on the semiconductor chip 2 essentially simultaneously. Additionally, the semiconductor chip 2 can be one of a plurality of semiconductor chips in the form of a semiconductor wafer. In this embodiment, a plurality of interconnection structures 3, are formed for a plurality of semiconductor chips 2 at the wafer level. The method may also be carried out for a plurality of contact pads disposed on one or more rewiring substrates .

Figure 3 shows a cross-sectional view of a portion of the active surface 5 of a semiconductor chip 2 including a chip contact pad 6 comprising, in this example, aluminium. A passivation layer 7 is deposited on the active surface 5 of the semi- conductor chip 2 and the outer surface 31 of the chip contact pad 6. The passivation layer 7 is then structured by known techniques such as laser grooving or photolithographic techniques using a mask structure 32. The mask structure 32 includes, for each chip contact pad 6, a central essentially circular opening 33 which is concentrically surrounded by a ring aperture 34. A developing or etching process is carried out in which the passivation layer 7 is removed in the region exposed by the central opening 33 in the mask structure 32.

The mask structure is aligned with the chip contact pad 6 so that a through-opening 35 is formed in the passivation layer in the approximate lateral centre of the chip contact pad 6. The through-opening 35 exposes the outer surface 31 of the chip contact pad 6. The developing or etching process also forms a depression 10 in the outer surface 11 of the passivation layer 7 by developing or etching through the annular aperture 34. The depression 10, therefore, has the form of an annular ring which is concentrically arranged with respect to the through-opening 35. The depression 10 is laterally positioned above the peripheral region 8 of the chip contact pad 6. The peripheral region 8 of the chip contact pad 6 remains covered by the passivation layer 7.

The through-opening 35 and depression 10 may be formed using a multiple mask and etch process as the depth to which the passivation layer is etched is larger in the central opening 33 than in the ring aperture 34.

Figure 4 shows the deposition of an electrically conductive layer 36 on the outer surface 11 of the passivation layer 7 and on the exposed outer surface 31 of the chip contact pad 6. The electrically conductive layer 36 fills the depression 10 formed in the outer surface 11 of the passivation layer 7. The electrically conductive layer 36 in the region of the chip contact pad 6 provides the under bump metallization 12 of the interconnect structure 3.

The inner surface 16 of the electrically conductive layer 36 which comprises the under bump metallization 12, therefore, includes a protrusion 15 which fills the depression 10 and provides a mechanical interlocking of the electrically conduc- tive layer 36 with the passivation layer 7. The electrically conductive layer 36 can comprise two or more layers although only one layer is shown in Figures 4 to 8 for clarity.

Figure 5 shows the next stage in the process in which a photo- resist layer 37 is deposited on the outer surface 38 of the electrically conductive layer 36. The photoresist layer 37 can be structured using known photolithographic techniques. As can be seen in figure 6, a through opening 39 is then made in the outer surface of the photo resist layer 37 in order to expose the central region 19 of the electrically conductive layer 36 which will form the under bump metallization 12. The through-opening 39 has an inner diameter which is approximately the same as the diameter of the outer side wall of the annular protrusion 15 in the inner surface 16 of the electrically conductive layer 36 and, therefore, approximately the same as the diameter of the outer side wall of the depression 10 in the passivation layer 7. Therefore, a central region of the electrically conductive layer 12 which will form the under bump metallization 12 for the contact pad 6 is exposed by the through-opening 39. The exposed region includes a base 21, side wall 22 and inner portion 40 of the raised peripheral region 23 of the under bump metallization 12.

The outer surface 17 of the under bump metallization remains covered by the photo resist layer 37 in its peripheral region 20. The protrusion 15 located in the inner surface of the under bump metallization 12 lies under the region which is uncovered by the through-opening 39 in the photoresist layer 37.

As shown in figure 7, a solder bump 41 is then deposited which fills the through-opening 39 in the photoresist layer 37. The solder bump 41 further includes a head portion 42 which protrudes above the outer surface of the photoresist layer 37 and which is laterally larger than the through-opening 39. The solder bump 41, therefore, has a mushroom type shape. The base 43 of the solder bump 41 has a cylindrical form and is in mechanical contact with the outer surface 17 of the under bump metallization 12 exposed by the through-opening 39. The edge of the base 43 of the solder bump 41, therefore, includes a step and a centrally positioned circular protrusion.

The photoresist layer 37 is then removed, as shown in figure 8 , to leave a mushroom-shaped solder bump 41 disposed on the central region 19 of the under bump metallization 12. The electrically conductive layer 36 is then etched to provide a plurality of electrically and physically isolated under bump metallization 12 for the plurality of chip contact pads 6.

The portion of the electrically conductive layer 36 which is covered by the solder bump 41 provides the under bump metallization 12 of the contact pad 6 as the covered region is not removed by the etching process . The lateral dimensions of the under bump metallization 12 are, therefore, approximately the same as the lateral dimensions of the base 43 of the solder bump 41.

In contrast to the first interconnection structure, illus- trated in Figures 1 and 2, the protrusion 15 in the inner surface 16 of the under bump metallization 12 is positioned at the extreme periphery of the under bump metallization 12. The edge of the under bump metallization 12 can be described as having an L-shape. This embodiments has the advantage that a horizontal interface between the under bump metallization 12 and the electrically insulating layer 7, in this case the passivation layer 7, at the peripheral edge of the under bump metallization 12 is avoided. This virtually eliminates the problem of under cutting during the etching process in which the exposed electrically conducting layer 36 is removed. The regions of the electrically conductive layer 36 which are uncovered by the solder bump are removed to produce a plurality of isolated under bump metallization 12 on each of the chip contact pads 6. The solder bump 41 is reflowed to produce the interconnection structure 3 shown in figures 1 and 2. The solder ball 4 is in mechanical and electrical contact with the chip contact pad 6.

Figure 9 shows an interconnection structure 44 according to a third embodiment of the invention. The interconnection structure 44 is shown for a rewiring substrate 45 of a semiconductor package such as a ball grid array (BGA) type package. The rewiring substrate 45 includes a plurality of outer contact areas 46 disposed on its lower surface 47. The outer contact areas 46 comprise copper.

A solder resist layer 48, which is electrically insulating, is disposed on the lower surface 47 of the rewiring substrate 45. The solder resist layer 48 includes a plurality of through- openings 51 which uncover the central region 52 of the outer contact areas 46. The exposed central region 52 is laterally essentially circular. The solder resist layer 48 covers the peripheral regions 49 of the outer contact areas 46.

The solder resist layer 48 further includes a depression 15 in its outer surface. The depression 50 has the form of an annular ring which is laterally concentric with the outer contact area 46 and the through opening 51 in the solder resist layer 48. The depression 50 lies laterally adjacent to the outer contact areas 46 and, therefore, has a diameter greater than the diameter of the outer contact areas 46. The interconnection structure 44 further comprises an electrically conductive layer 53. The electrically conductive layer 53 is laterally larger than the outer contact area 46 and fills the central opening 51 and the depression 50 formed in the solder resist layer 48. The electrically conductive layer 53 has a thickness so that the outer surface 54 of the electrically conductive layer 53 protrudes slightly above the plane of the outer surface 55 of the solder resist layer 48. The outer surface 54 of the central region 59 and peripheral region of the electrically conductive layer 56 is essentially coplanar.

The electrically conductive layer 53, therefore, has a central protruding portion 56 and a protruding annular ring 57 in its inner surface 58. The inner surface 58 faces towards the lower surface 47 of the rewiring substrate 45. The annular ring 57 has a rectangular cross-section. Similarly to the embodiment shown in Figures 3 to 8, the annular protrusion 57 is positioned at the periphery of the electrically insulating layer 53. The cross-section of the periphery of the electrically conductive layer 53 can, therefore, be described as having an L-shape.

The central protruding portion 56 of the electrically conduc- tive layer 53 is in mechanical and electrical contact with the central portion of the outer contact area 46. The protruding annular ring 57 at the periphery 59 of the electrically conductive layer 53 fills the depression 50 formed in the solder resist layer 48. The protruding annular ring 57 is in mechani- cal contact with the depression 50 and provides an interlocking of the electrically conductive layer 53 with the solder resist layer 48. The thickness of the protruding central portion 56 is greater than the thickness of the annular ring 57. In this embodiment of the invention, the base of the protruding ring lies later- ally adjacent to and in essentially the same plane as the outer surface of the contact area 46.

The combination of the outer contact area 46, a solder resist layer 48 and electrically conductive layer 53 with a protru- sion 57 provides an interconnection structure which is more mechanically robust and which is less likely to suffer from delamination at the interface between the electrically conductive layer 53 and the solder resist layer 48 as well as at the interface between the electrically conductive layer 53 and the outer contact area 46. A solder ball can be applied to the outer surface of the electrically conductive layer 53 to provide the external contact from the rewiring substrate 45 and external higher-level circuit carrier such as a printed circuit board.

Although the interconnection structures 3 of the first and second embodiments of the invention have been described for a semiconductor chip 2 and the interconnection structure 44 according to a third embodiment of the invention has been de- scribed in relation to a rewiring substrate 45, the interconnection structures 3, 44 are not limited to the specific applications described. The first and second interconnection structures 3 can also be used for a rewiring substrate and the third interconnection structure 44 can also be used for a semiconductor chip. Reference numbers

1 semiconductor package

2 semiconductor chip 3 interconnection structure

4 a flip chip contact

5 active surface

6 chip contact pad

7 passivation layer 8 peripheral region of chip contact pad

9 central region of chip contact pad

10 depression

11 outer surface of passivation layer

12 under bump metallization (UBM) 13 first electrically conductive layer

14 second electrically conductive layer

15 protrusion

16 inner surface of UBM

17 outer surface of UBM 18 depression in outer surface of UBM 19 central region of UBM 20 peripheral region of UBM

21 central depression of UBM

22 side wall of UBM 23 raised peripheral region of UBM

24 wiring substrate

25 inner contact area

26 outer contact area 27 conductor track 28 plated via

29 solder resist layer

30 underfill material 31 mould material

32 mask structure

33 circular opening in mask structure

34 ring aperture in mask structure 35 through opening in passivation layer 36 electrically conductive layer

37 photo resist layer

38 outer surface of the electrically conductive layer

39 through opening in the photo resist layer 40 inner portion of raised peripheral region of UBM

41 solder bump

42 head of the solder bump

43 base of solder bump

44 second interconnection 45 rewiring substrate

46 outer contact area

47 lower surface of rewiring substrate

48 solder resist layer

49 peripheral region of outer contact area 50 depression in outer surface of solder resist layer

51 through opening in solder resist layer

52 central region of outer contact area

53 electrically conductive layer

54 outer surface of electrically conductive layer 55 outer surface of solder resist layer

56 central protruding portion of electrically conductive layer 53

57 peripheral protruding ring of electrically conductive layer 53 58 inner surface of electrically conductive layer

59 peripheral region of electrically conductive layer

Claims

Patent claims

1. An interconnection structure (3; 44) for electronic components comprising: a contact pad (6; 46) ; an electrically insulating layer (7; 48) covering the peripheral regions (8; 49) of the contact pad (6; 46), the central region (9; 52) of the contact pad (6; 46) remaining exposed from the electrically insulating layer (7; 48); an electrically conductive layer (12; 53) comprising an inner surface (16; 58) and an outer surface (17; 54), wherein the electrically conductive layer (12; 53) is disposed on the central portion (9; 52) of the contact pad (6; 46) and on regions of the electrically insulating layer (7; 48) adjacent the exposed central portion (9; 52) of the contact pad (6; 46); wherein the inner surface (16; 58) of the electrically conductive layer (12; 53) comprises at least one protrusion (15; 57) disposed in a peripheral region (20; 59) of the electrically conductive layer (12; 53).

2. An interconnection structure (3) according to claim 1, characterised in that the electrically conductive layer (12) comprises a depression (21) in its central region (19) and a raised annular ring (23) in its peripheral region (20).

3. An interconnection structure (3; 44) according to claim 1 or claim 2 , characterised in that the exposed central region (9; 52) of the contact pad (6; 46) is laterally essentially circular.

4. An interconnection structure (3; 44) according to one of the previous claims, characterised in that the electrically conductive layer (12; 53) is laterally essentially circular or has a laterally an n-sided polygon shape .

5. An interconnection structure (3; 44) according to one of the previous claims, characterised in that the electrically conductive layer (12; 53) is laterally larger than the contact pad (6; 46) or laterally smaller than the contact pad (6; 46) or laterally approximately the same size as the contact pad (6; 46) .

6. An interconnection structure (3; 44) according to one of the previous claims, characterised in that the protrusion is an annular ring (15; 57) .

7. An interconnection structure (3; 44) according to one of the claims 1 to 6, characterised in that the protrusion comprises a plurality of protrusions.

8. An interconnection structure (3; 44) according to one of the previous claims, characterised in that the protrusion (15; 57) is concentrically positioned around the central region (19; -)of the electrically conductive layer (12; 53).

9. An interconnection structure (44) according to one of the previous claims, characterised in that the protrusion (57) is positioned at the periphery of the electrically conductive layer (53).

10.An interconnection structure (3; 44) according to one of the previous claims , characterised in that the protrusion (15; 57) is in contact with the electri- cally insulating layer (7; 48) .

11.An interconnection structure (3; 44) according to one of the previous claims, characterised in that the electrically insulating layer (7; 48) includes at least one depression (15; 50) which is filled by the protrusion (15; 57).

12.An interconnection structure (3; 44) according to one of the previous claims, characterised in that the outer surface (17; 54) of the electrically conductive layer (12, 53) comprises a depression (18; -) located above the protrusion (15; -) .

13.An interconnection structure (3) according to one of the previous claims, characterised in that the protrusion (15) is disposed above the contact pad (6) .

14.An interconnection structure (44) according to one of claims 1 to 13 , characterised in that the protrusion (57) is disposed laterally adjacent the contact pad (46) .

15.An interconnection structure (3) according to one of the previous claims, characterised in that the contact pad (6) comprises aluminium or copper or an alloy of aluminium or an alloy of copper.

16. An interconnection structure (3) according to one of the previous claims, characterised in that the electrically conductive layer (12) comprises at least two electrically conductive layers (13, 14) .

17.An interconnection structure (3) according to one of the previous claims, characterised in that the electrically conductive layer (12) comprises Cr and Cu.

18.An interconnection structure (3) according to one of the previous claims, characterised in that the interconnection structure (3) is located on the active surface (5) of a semiconductor chip (2) .

19.An interconnection structure (3; 44) according to one of the previous claims, characterised in that the interconnection structure (3; 44) further comprises a solder bump or a solder ball (4; -) disposed on the outer surface (17; 54) of the electrically conductive layer (12; 53) .

20. A semiconductor chip (2) comprising: an active surface (5) comprising integrated circuit devices and a plurality of interconnection structures (3; 44) of one of claims 1 to 19, and a passive surface.

21. Semiconductor chip (2) according to claim 20, characterised in that the contact pads (6) have a flip chip arrangement.

22.A semiconductor wafer comprising: a plurality of semiconductor chips (2) of claim 20 or claim 21.

23.A semiconductor package (1) comprising: - the semiconductor chip (2) of claim 20 or claim 21; a substrate (24) having an upper surface and a lower surface, the substrate (24) comprising: a plurality of inner contact pads (25) on the upper surface, the plurality of inner contact pads (25) having a lateral arrangement corresponding to the lateral arrangement of the contact pads (6) on the semiconductor chip (2); a plurality of outer contact pads (26) on the lower surface; and a rewiring structure (27, 28), wherein the semiconductor chip (2) is electrically connected to the upper surface of the substrate (24) by a plurality of flip chip connections (4) , a flip chip connection (4) being disposed between each of the plurality of inner contact pads (25) and the electrically conductive layer (12) disposed on each of the plurality of contact pads (6) on the semiconductor chip (2) .

24. Semiconductor package (1) according to claim 23, characterised in that the package (1) further comprises underfill material (30) encapsulating at least the flip chip connections (4) .

25. Semiconductor package (1) according to claim 23 or claim' 24, characterised in that the package (1) further comprises mold material (31) encapsulating at least the passive surface of the semiconductor chip (1) .

26. Method to fabricate an interconnection structure (3; 44) for an electronic component comprising: providing at least one contact pad (6; 46); depositing an electrically insulating layer (7; 48) on the contact pad (6; 46) so that the central portion (9; 52) of the contact pad (6; 46) is exposed from the electrically insulating layer (7; 48); depositing an electrically conductive layer (12; 53) on the central portion of the contact pad (6; 46) and on regions of the electrically insulating layer (7; 48) adjacent to the exposed central portion of the contact pad (6; 46), the electrically conductive layer (12; 53) having an inner surface (16; 58) and an outer surface (17; 54); wherein the inner surface (16; 58) of the electrically conductive layer (12; 53) comprises at least one protrusion (15; 57) disposed in a peripheral region (20; 59) of the electrically conductive layer (12; 53).

27. Method to fabricate an interconnection structure (3; 44) according to claim 26 characterised in that at least one depression (10; 50) is formed in the outer surface (11; 55) of the electrically insulating layer (7;

48) laterally adjacent the exposed central portion (9; 52) of the contact pad (6; 46) .

28. Method to fabricate an interconnection structure (3; 44) according to claim 26 or claim 27 characterised in that a closed electrically insulating layer (7; 48) is deposited and portions of the electrically insulating layer are removed to expose the central portion (9; 52) of the contact pad (6; 46) and to form the depression (10; 50) .

29. Method to fabricate an interconnection structure (3; 44) according to one of claims 26 to 28 characterised in that the electrically conductive layer (12; 53) is deposited to fill the at least one depression (10; 50) and to form at least one protrusion (15; 57) on the inner surface (16; 58) of the electrically conductive layer (12; 53).

30. Method to fabricate an interconnection structure (3; 44) according to one of claims 26 to 29 characterised in that the electrically conductive layer (12; 53) is deposited by a vacuum deposition technique.

31. Method to fabricate an interconnection structure (3; 44) according to one of claims 26 to 30 characterised in that the electrically conductive layer (12; 53) is formed by the sequential deposition of at least two electrically conductive layers .

32. Method to fabricate an interconnection structure (3; 44) according to one of claims 26 to 31, further comprising: forming a solder ball (4) on the electrically conductive layer (12; 53) by: depositing a closed resist coating (37) on the electrically conductive layer (12; 53); - removing portions of the resist coating to form a through-opening (39) which exposes the central portion of the electrically conductive layer (12; 53); depositing solder (41) in the through-opening (39); removing the resist coating (37); - etching the electrically conductive layer (12, 53), and reflowing the solder (41) .

33. Method to fabricate an interconnection structure (3; 44) according to claim 32 characterised in that the solder (41) is deposited by an electroplating tech- nique.

34. Method to fabricate a semiconductor chip (2), comprising: providing a wafer comprising a plurality of semiconductor chips (2), each semiconductor chip (2) comprising a plurality of contact pads (6); carrying out the method of one of claims 26 to 33 to provide an interconnection structure (3; 44) for each the plurality of contact pads (6); singulating the semiconductor chips (2) from the wafer.

35.Method to assemble a semiconductor package (1), comprising: providing a semiconductor chip (2) comprising: an active surface (5) comprising integrated circuit devices and a plurality of interconnection struc- tures (§; 44) of one of claims 1 to 18; a passive surface; and a plurality of flip chip contacts (4) comprising solder bumps or solder balls disposed on the outer surface (17) of the electrically conductive layer (12) of the interconnection structure (3), providing a substrate (24) having an upper surface and a lower surface, the substrate (24) comprising: a plurality of inner contact pads (25) on the upper surface, the plurality of inner contact pads (25) having a lateral arrangement corresponding to the lateral arrangement of the contact pads (6) on the semiconductor chip (2); a plurality of outer contact pads (26) on the lower surface; and a rewiring structure (27, 28), mounting the semiconductor chip (2) on the upper sur- face of the substrate (24) so that a flip chip contact (4) is disposed between the electrically conductive layer (12) and the inner contact pads (25); and reflowing the solder.

36. Method to assemble a semiconductor package (1) according to claim 35 including the further step of: encapsulating the plurality of flip chip contacts (4) in underfill material (30) .

37. Method to assemble a semiconductor package (1) according to claim 35 or claim 36 including the further step of: encapsulating at least the passive surface of the semiconductor chip (2) in mold material (31) .