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WO2006009025A1 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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Publication number
WO2006009025A1
WO2006009025A1 PCT/JP2005/012890 JP2005012890W WO2006009025A1 WO 2006009025 A1 WO2006009025 A1 WO 2006009025A1 JP 2005012890 W JP2005012890 W JP 2005012890W WO 2006009025 A1 WO2006009025 A1 WO 2006009025A1
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WIPO (PCT)
Prior art keywords
metal
semiconductor device
film
metal compound
heat treatment
Prior art date
Application number
PCT/JP2005/012890
Other languages
French (fr)
Japanese (ja)
Inventor
Masayuki Terai
Motofumi Saitoh
Ayuka Tada
Hirohito Watanabe
Original Assignee
Nec Corporation
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Publication date
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Priority to JP2006529077A priority Critical patent/JPWO2006009025A1/en
Publication of WO2006009025A1 publication Critical patent/WO2006009025A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device, and more particularly, a MOSFET (Metal—Oxide—Semiconductor Field Effect Transistor) that realizes high performance and low power consumption. And a method for manufacturing the semiconductor device, in which the reliability of the gate insulating film constituting the semiconductor device is improved.
  • MOSFET Metal—Oxide—Semiconductor Field Effect Transistor
  • a silicon oxide film is useful as a gate insulating film material for a MOSFET because of its high process stability and excellent insulating properties.
  • the gate insulation film has become thinner with the miniaturization of devices, and for devices with a gate length of lOOnm or less, the required power of the scaling rule is also less than 2. Onm. It is necessary to be.
  • the tunnel current force flowing through the insulating layer when a gate bias is applied is a value that cannot be ignored with respect to the source Z drain current. Therefore, in order to improve the performance and power consumption of MOS FETs, the effective (electrical) gate insulating film thickness is reduced and the tunnel current is kept within the allowable range in device design. At present, research and development is actively underway.
  • nitrogen is added to the silicon oxide film to increase the dielectric constant and reduce the physical film thickness compared to pure silicon oxide film.
  • a method for forming such a silicon oxynitride film after forming an oxide film on the surface of the silicon substrate, nitrogen is introduced by performing high-temperature heat treatment in a nitrogen-containing gas such as ammonia (H).
  • a technique in which a silicon oxide film is exposed to elementary plasma and the surface side is selectively nitrided is being studied.
  • the relative dielectric constant of a pure silicon nitride film is about twice that of a silicon oxide film, it has a high dielectric constant due to nitrogen addition to the silicon oxide film. Has a limit and the relative permittivity It is impossible in principle to make it 10 or more.
  • Silicate materials in which silicon is mixed into these metal oxides are also considered as candidate materials because they have improved thermal stability although their relative permittivity is reduced. If these materials are used, it is possible to achieve a physical thickness that can reduce the tunnel current while maintaining the gate insulating film capacitance consistent with the scaling law even if the gate length is made fine.
  • the threshold voltage (VT) of the transistor changes during operation, making it difficult to ensure long-term stability of the output current of the transistor.
  • a high dielectric constant film is directly deposited on the surface of a silicon substrate, or an extremely thin (usually less than lnm) silicon oxide film is used.
  • an extremely thin (usually less than lnm) silicon oxide film is used.
  • a high dielectric constant film is deposited, and the reaction between the deposited high dielectric constant film and the base is suppressed as much as possible (see, for example, Patent Document 1).
  • the deposition method of high dielectric constant gate insulating film on the silicon substrate surface is mainly researched and developed using MOCVD (Metal Organic and Chemical Vapor Deposition) and ALCVD (Atomic Layer Chemical Vapor Deposition) equipment.
  • Metal oxide (or oxygen concentration is not excessive or deficient in the stoichiometric composition of the high dielectric constant film deposited by optimizing the deposition temperature and deposition sequence.
  • the conditions are set so as to coincide with the silicate composition because structural defects such as oxygen vacancies in the film are considered to be one of the causes of electron traps in the film.
  • a silicon oxide film is formed in advance on the surface of the silicon substrate, at least one kind of metal is ion-implanted into the formed silicon oxide film, and the injected metal is converted into silicon oxide by heat treatment.
  • a method for manufacturing a semiconductor device that diffuses into a film, has a good interface state with a semiconductor substrate, and has a good leak characteristic see, for example, Patent Document 2).
  • a semiconductor with excellent interfacial properties between a silicon substrate and a metal silicate layer which can contain metal atoms in the silicon oxide film as necessary and sufficiently to control, forms a metal silicate layer with a high dielectric constant
  • Patent Document 3 There is a device manufacturing method (see, for example, Patent Document 3).
  • Patent Document 1 Japanese Patent Laid-Open No. 2002-289844
  • Patent Document 2 JP 2002-314074 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2001-332547
  • Non-Patent Document 1 A. Morioka et. All, ⁇ High Mobility MISFET with Low Trapped Charge in HfSiO FilmsJ, 2003 Symposium on VLSI Technological Digest oi fechnical Papers, p. Up 5
  • the silicon oxide film improves the interfacial thermal stability.
  • the relative dielectric constant of the silicon oxide film is low, It is considered important that the initial silicon oxide film formed on the substrate surface has a thickness of 0.6 nm or less.
  • Patent Document 2 described above is that when a metal is ion-implanted into a silicon oxide film, a defect is generated and the diffusion of the metal element cannot be controlled immediately during the heat treatment. It becomes.
  • Patent Document 3 described above controls metal atoms by suppressing diffusion due to a solid solution limit. Although it can be contained in the silicon oxide film with sufficient and sufficient properties, a metal silicate layer with a high dielectric constant will be formed, but there will be a region where metal atoms cannot be contained in the silicon oxide film. In such a case, there is a risk of causing characteristic deterioration.
  • the present invention has been made in view of the above circumstances, and enables the formation of a high-quality gate insulating film at the interface of a silicon substrate, and the manufacture of a semiconductor device and a semiconductor device with improved interface electrical characteristics It is intended to provide a method.
  • the present invention has the following features.
  • a semiconductor device is a semiconductor device having a gate insulating film that electrically insulates a gate electrode from a silicon substrate, wherein a base layer containing silicon is formed on the silicon substrate, A metal compound as a metal diffusion source is deposited on the formed underlayer and heat treated to diffuse the metal element of the metal compound into the underlayer and form a high dielectric constant gate insulating film on the silicon substrate.
  • the metal atomic weight in the metal compound is in the range of 1.5E + 15 cm- 2 force and 2.6E + 15 cm- 2 .
  • the semiconductor device according to the present invention has a thickness (nm) of a metal compound as a metal diffusion source.
  • the amount of metal in the metal compound is 0.6 or more and 0.9 or less. To do.
  • the underlayer also has a silicon oxide or silicon oxynitride force.
  • the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby a metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed. It is a feature.
  • the heat treatment is performed in an inert gas, and then the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby the metal element of the metal compound is applied to the underlayer.
  • a diffused metal diffusion film is formed.
  • the semiconductor device according to the present invention performs the heat treatment performed in an atmosphere containing at least ammonia or oxygen at 700 ° C. or higher and 950 ° C. or lower, so that the metal element of the metal compound is A metal diffusion film diffused in the underlayer is formed.
  • the heat treatment is performed at 750 ° C. or more and 900 ° C. or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 2.3E + 15 cm- 2 force or the like. 2. It is characterized by being in the range of 6E + 15cm- 2 .
  • the heat treatment is performed at 700 ° C. or more and less than 750 ° C. in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 1.5E + 15 cm- 2 force or the like. 1. 7E + 15cm- 2 range.
  • the heat treatment is performed in an inert gas, and thereafter, the metal element of the metal compound is diffused into the underlying layer by exposure to an atmosphere containing nitrogen radicals. A diffusion film is formed.
  • the heat treatment is performed in an atmosphere containing at least oxygen, and then exposed to an atmosphere containing nitrogen radicals, whereby the metal element of the metal compound diffuses into the underlayer.
  • a metal diffusion film is formed.
  • the semiconductor device according to the present invention is characterized in that the lower part of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
  • the semiconductor device according to the present invention is characterized in that the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more.
  • the semiconductor device according to the present invention has an oxide layer equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment, the underlying layer used when forming the high dielectric constant gate oxide film. It is characterized by becoming thinner.
  • the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, It is characterized by containing at least one metal element of Dy, Ho, Er, Tm, Yb, and Lu.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a silicon substrate, and includes silicon on the silicon substrate.
  • a step of forming an underlayer to be deposited, a step of depositing a metal compound as a metal diffusion source on the underlayer, a heat treatment to the underlayer and the metal compound, and diffusing the metal element of the metal compound into the underlayer A high dielectric constant gate insulating film on the silicon substrate.
  • the amount of metal atoms in the metal compound is from 1.5E + 15cm to 2.6
  • the amount of the metal in the metal compound determined by the product of is in the range of 0.6 or more and 0.9 or less.
  • the underlayer is made of silicon oxide.
  • the silicon oxynitride force is also obtained.
  • the heat treatment is performed in an atmosphere containing at least ammonia or oxygen so that the metal element of the metal compound diffuses into the underlayer. A film is formed.
  • the heat treatment is performed in an inert gas, and then performed in an atmosphere containing at least ammonia or oxygen, so that the metal element of the metal compound is applied to the underlayer. It is characterized by forming a diffused metal diffusion film.
  • the heat treatment performed in an atmosphere containing at least ammonia or oxygen is performed at 700 ° C or higher and 950 ° C or lower. is there.
  • the heat treatment is performed at 750 ° C or more and 900 ° C or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 2. is characterized in that in the range of from 3E + 15cm- 2 of 2. 6E + 15cm- 2.
  • the heat treatment is performed at 700 ° C or more and less than 750 ° C in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1. is characterized in that in the range of 1. 7E + 15cm- 2 from 5E + 15cm- 2.
  • the heat treatment is performed in an inert gas, and then exposed to an atmosphere containing nitrogen radicals, so that the metal compound gold is exposed.
  • a metal diffusion film in which a metal element is diffused in an underlayer is formed.
  • the heat treatment is performed in an atmosphere containing at least oxygen, and then the metal element of the metal compound is exposed to an atmosphere containing nitrogen radicals. It is characterized by forming a diffused metal film in the underlayer.
  • the lower portion of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
  • the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more. It is.
  • a gate oxide film having a high dielectric constant in terms of an oxide film equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment is obtained. It is characterized by being thinner than the underlying layer used for forming.
  • the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, It contains at least one metal element of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.
  • a base silicon oxide film is formed on the silicon substrate, and the formed base silicon oxide
  • a metal oxide, metal silicon oxynitride, or nitride containing at least one metal element of Lu is deposited, and heat treatment is performed to promote the interfacial silicate reaction.
  • the metal atomic weight in the metal oxide film (nitride film) is 1.5E + 15cm— is characterized in that it is 2 ⁇ 2. 6E + 15cm- 2 range.
  • the deposition method of the metal silicon oxide film or the metal nitride film used as the metal diffusion source can be any metal deposition method including any metal deposition method. In order to form a solid phase reaction film, it is essential to set the amount of metal contained in the oxide or metal nitride to an appropriate value. The same applies when a silicon oxynitride film is used as the base layer instead of the base silicon oxide film.
  • the present invention may employ a low-cost and excellent reproducibility method of forming a metal silicon oxynitride after metal diffusion or during metal diffusion. By nitriding the metal oxide, the dielectric constant is greatly increased.
  • the relationship between the Hf concentration, the film thickness, and the Hf amount in the present invention is not just a design matter. For example, even if a film is formed with a film thickness or Si concentration, a solid-phase reaction must be performed. Therefore, it will not be possible to reduce electronic traps.
  • a semiconductor device and a method for manufacturing a semiconductor device according to the present invention include forming a base layer containing silicon on a silicon substrate in a semiconductor device having a gate insulating film that electrically insulates the gate electrode of the gate electrode. Then, a metal compound is deposited as a metal diffusion source on the formed underlayer, heat treatment is performed on the underlayer and the metal compound, the metal element of the metal compound is diffused into the underlayer, and a high concentration is formed on the silicon substrate.
  • forming a gate insulating film of a dielectric constant a metal atom content in the metal compound is characterized in range der Rukoto of 1. 5E + 15cm 2 power et al 2. 6E + 15cm- 2. In this way, by optimizing the film formation conditions, it is possible to form a high-quality gate insulating film on the interface of the silicon substrate, and to improve the interface electrical characteristics.
  • the semiconductor device in this embodiment includes a step (FIG. 1 (a)) of forming a base layer (oxide film or oxynitride film) (102) containing silicon on the surface of a silicon substrate (101), and a base layer (102 )
  • the process (Fig. 1 (a) of forming a base layer (oxide film or oxynitride film) (102) containing silicon on the surface of a silicon substrate (101), and a base layer (102 )
  • a high-quality gate insulating film (106) can be formed on the interface of the silicon substrate (101), and the electrical interface characteristics can be improved (FIG. L (d)).
  • the gate insulating film (106) is composed of an Hf rich region (104) and an Si rich region (105).
  • the semiconductor device according to the present embodiment is not directly deposited on a silicon substrate (101) with a high dielectric constant gate insulating film made of silicate, as shown in FIG. 1 (c).
  • a high-quality silicate film formed by the interfacial reaction between the base layer (102) and the metal compound layer (103) is used as the gate insulating film (106).
  • This gate insulating film (106) has a high dielectric constant, and can be an extremely thin insulating film.
  • the metal compound in the metal compound layer (103) has a metal atom amount in the range of 1.5E + 15 cm— 2 forces and 2.6E + 15 cm— 2 as a metal diffusion source.
  • the amount of metal in the metal compound determined by the product of the film thickness (nm) of the metal compound and the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is not less than 0.6. It is characterized by a range of 9 or less.
  • metal compounds with different film thicknesses (nm) and concentrations can be used as metal diffusion sources to maximize electron trap reduction and leakage current reduction. A method for forming a solid phase reaction film will be described.
  • FIG. 1 suggests a manufacturing process of a high-quality HfSiO gate insulating film in the present embodiment.
  • the silicon substrate (101) is washed with sulfuric acid-hydrogen peroxide and ammonia-hydrogen peroxide, and then subjected to thermal oxidation to form silicon oxide that becomes the base oxide film layer (102).
  • the film thickness is 1.8 nm (Fig. L (a)).
  • hafnium silicate (103) HfSiO film or HfO film with different Hf concentration is applied to the surface of the base oxide film layer (102).
  • MOCVD Metal Organic Chemical Vapor Deposition
  • ALCVD Atomic Layer Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • HTB tertiary butoxy hafnium
  • Si source silane or disilane
  • Hf SiO layer (103) is formed. accumulate. Then, annealing is performed in an oxygen or ozone atmosphere.
  • TDEAH is used as the Hf source gas.
  • the HfSiO film (103) is deposited using TDMAS as the Si raw material.
  • the deposition method using the ALCVD method includes a step of oxidizing the HF source material and the Si source material after depositing the Hf source material and the Si source material using TEMAH as the Hf source gas. By repeating, the HfSiO film (103) is formed.
  • sputtering is performed by sputtering Hf atoms.
  • the Hf layer is oxidized to form the HfO film (103).
  • the heat treatment for the metal diffusion reaction in the present embodiment was performed under conditions of 800 ° C and 10 minutes in an ammonia atmosphere so that the metal element in the metal diffusion source could be sufficiently diffused.
  • FIGS. 2 to 4 were prepared by fixing the thickness of the HfSiO film (103) deposited on the base oxide film layer (102) to 1.5 nm and changing the amount of supplied Hf. This suggests the results of MISFET characterization of solid phase reaction HfSiON film (103).
  • FIG. 2 suggests the dependence of the gate-side insulating film (106) on the reverse leakage current reduction effect on the amount of Hf with respect to a SiON film having an equivalent electrical oxide film equivalent film thickness.
  • FIG. 3 suggests hysteresis measurement results at various Hf amounts.
  • Hysteresis corresponds to the phenomenon that charges are trapped in the electron traps in the gate insulating film (106) when a voltage is applied.
  • Figure 3 suggests the measurement results when the voltage sweep width is changed to 1.8V.
  • Fig. 3 shows that the hysteresis decreases as the Hf amount decreases. This is because the unreacted surplus Hf atoms left in the HfSiO film (103) serving as the metal diffusion source are reduced.
  • Hf amount 2.
  • Hf amount for 6E + 15cm 2 hysteresis is several mV or less in the following and a very Teigu hysteresis suppressed 2.
  • 6E + 15cm - it can be seen that it is necessary to 2 or less.
  • FIG. 4 shows the comparison of the on-current (Ion) of the transistor with the characteristics of the transistor having the reference SiON gate insulating film, normalized by the inversion capacitance. It can be seen that the Hf amount has a peak of on-current at 2.3E + 15cm " 2 to 2.6E + 15cm- 2, and that the on-state current deteriorates abruptly at Hf amounts greater than 2.6E + 15cm- 2 . [0069] In other words, it is completely consistent with the hysteresis tendency suggested in Fig. 3, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. .
  • the amount of metal that can be supplied is reduced by lowering the heat treatment temperature because the amount of Hf that can be subjected to solid-phase reaction is reduced, resulting in an increase in electron traps due to excess Hf. This is because the lowering of the crystallization temperature cannot be suppressed by lowering. Below 700 ° C, no solid phase reaction of Hf occurred, and there was no improvement in property deterioration.
  • the metal atom of the metal compound is in the range of 1. 5E + 15cm- 2 ⁇ 2. 6E + 15cm 2, and the thickness of the metal compound as a metal diffusion source (nm), If the amount of metal in the metal compound determined by the product of the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is in the range of 0.6 or more and 0.9 or less, it is different. It can be seen that no matter how the Hf SiO film with the film thickness and composition is deposited, the film quality is the same after solid phase diffusion.
  • the heat treatment for the solid phase reaction of the metal diffusion source is performed in an atmosphere containing ammonia, but the diffusion reaction is performed in an inert gas such as nitrogen, Ar, or He instead of ammonia. And then heat treatment in an atmosphere containing at least ammonia. Similar results can be obtained by introducing nitrogen by exposure to nitrogen radicals. In other words, the electron traps are reduced by the solid phase reaction by the first heat treatment, and the heat resistance is improved by introducing nitrogen into the film in the next nitriding treatment. In particular, the final nitrogen concentration profile in the film when nitrogen radicals are used decreases as the substrate interface increases on the surface.
  • the nitrogen concentration at the substrate interface can be reduced, the BT reliability of the PMOS (VT shift amount after 10 years under the conditions of operating temperature 85 ° C and operating voltage 1. IV) is treated with ammonia. Compared to the case, it can be improved by 5mV or more.
  • a silicon oxide film is used for the base layer (102).
  • a silicon oxynitride film is used for the base layer (102)
  • the same electron trap reduction effect can be obtained.
  • the layer (102) has a high dielectric constant due to nitriding, it can be made thinner.
  • Hf nitride (HfN) or Hf silicon nitride (HfSiN) is used as the metal diffusion source.
  • thermal oxidation was performed to form a silicon oxide film of 1.8 nm, which becomes the base oxide film layer (102) (FIG. 1 (a)).
  • Any apparatus may be used to form the base oxide film layer (102).
  • a single-wafer type lamp aligner apparatus is used, and 50% nitrogen-diluted oxygen is used.
  • a base oxide film layer (102) is formed by heat treatment at 900 ° C. in an atmosphere.
  • an HfN layer (103) or an HfSiN layer (103) is deposited in a thickness of 0.5 nm to 2. Onm on the surface of the base oxide film layer (102) (FIG. 1 (b)).
  • the HfN layer (103) is formed using a metal Hf target and a mixed gas of argon and nitrogen as a sputtering gas (reactive gas).
  • the HfSiN layer (103) is formed by alternately using a metal Hf target and a Si target and using a mixed gas of argon and nitrogen as a reaction gas.
  • TEMAH is used as the Hf source gas, and after depositing the Hf source and the Si source, the process of nitriding in an ammonia atmosphere is repeated to form the HfSiN film layer (103) Then, the HfN film layer (103) is formed by eliminating the Si raw material deposition step.
  • the PVD method is mainly used.
  • the method of dividing the metal atom diffusing step and the nitriding step realizes the heat treatment conditions, the desired nitrogen concentration, and the nitrogen profile for sufficiently diffusing the metal atoms. Therefore, there is an advantage that the nitriding conditions can be controlled independently.
  • FIGS. 7 to 9 show the effects of reducing the gate leakage current when the amount of Hf in the 1.5 nm Hf nitride and Hf silicon nitride used as a metal diffusion source is changed (FIG. 7). ), Hysteresis (Fig. 8), and transistor on-current (Fig. 9) were evaluated.
  • FIG. 7 suggests the dependence of the gate insulating film on the inversion side leakage current with respect to the Hf amount dependence on the SiON film having the equivalent electrical oxide film equivalent film thickness.
  • the Hf content of the deposited HfSiO film must be at least 2.3E + 15cm.
  • Fig. 8 suggests hysteresis measurement results at various Hf amounts.
  • Hysteresis corresponds to the phenomenon that charges are trapped in electron traps in the gate insulating film when a voltage is applied.
  • Figure 8 suggests the measurement results when the voltage sweep width is changed to 1.8V.
  • Hf amount: 2. 3E + 15cm 2 indicates that it is necessary to set the amount of Hf of metal diffusion source 2. 3E + 15cm- 2 or less for very small sag hysteresis suppression and hysteresis of several mV or less in the following ing.
  • FIG. 9 is a graph in which the on-current (Ion) of the transistor is normalized by the inversion capacitance and compared with the characteristics of the transistor having the reference SiO N gate insulating film. So the suggested in Figure 9, there is a peak of Hf weight 2. 3E + 15cm- 2 ⁇ 2. 6E + 15cm- 2 near the on-current, 2. 6 E + 15cm- 2 or more on-current abruptly in the amount of Hf It turns out that it deteriorates. In other words, it is completely consistent with the hysteresis trend suggested in Fig. 8, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. In addition, as suggested in Fig. 9, when the Hf content is in the range of 2.3E + 15cm- 2 to 2.6E + 15cm- 2 , it is possible to achieve characteristics of about 90% of SiON.
  • the deterioration of TZDB decreases the strength of nitriding, This is because the decrease in the conversion temperature cannot be suppressed.
  • the hysteresis and defect density in the low-temperature solid-phase diffusion is possible to improve by reducing the amount of Hf, 5 mv or less hysteresis by the amount of Hf to 1. 5E + 15cm 2 ⁇ 1. 7E + 15cm- 2 It is possible to improve the defect density to 1 / cm 2 .
  • the processing temperature for the solid phase reaction is 700 ° C or more and less than 750 ° C
  • the optimum amount of Hf for Hf diffusion reaction is lower than that of 750 ° C or more 1.5E + 15cm— 2 to 1.7E + 15 cm— 2 .
  • solid phase diffusion did not occur.
  • the silicon oxide film is used as the underlayer.
  • the same electron trap reduction effect can be obtained by using a silicon oxynitride film instead of the silicon oxide film. Become. In this case, since the underlayer has a high dielectric constant due to nitriding, it becomes thinner.
  • metal is diffused from the metal diffusion layer (203) to the underlayer (202) by solid phase diffusion.
  • heat treatment is performed in an atmosphere containing at least oxygen.
  • Figure 10 shows a high-quality HfSiO gate insulating film when a solid phase diffusion of metal from the metal diffusion layer (203) to the underlayer (202) is performed in an atmosphere containing at least oxygen ( 206) is shown.
  • a silicon oxide film to be the underlayer (202) is formed to 1.5 nm (FIG. 10 (a)). Then, the metal diffusion of HfSiO film, HfO film, HfN film, or HfSiN film, which becomes a metal diffusion source, is formed on the surface of the underlying silicon oxide film (202).
  • a scattering layer (203) is deposited (Fig. 10 (b)).
  • the Hf content in the film is 2.5E + 15 cm 2 HfSiO film or HfSiN film 1.5 Deposit nm.
  • the decrease in inversion layer capacitance due to an oxide film increase of 1 angstrom or more offsets the increase in mobility, and the transistor on-current improvement was about 4%. Therefore, it is necessary to make the underlying silicon oxide film (202) thin for at least 1 angstrom or more and adjust the final oxide film equivalent film thickness to a desired film thickness.
  • the interface silicate reaction proceeds to the silicate region at the interface between the base layer (202) for forming the gate insulating film (206) and the metal compound layer (203), and the Hf-rich region. (204) and Si-rich region (205).
  • HfSiN Metal diffusion sources are Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm Similar results are obtained when using metal oxides, metal nitrides, or silicate materials characterized by containing at least one element of Yb, Lu.
  • the gate electrode is electrically connected from the silicon substrate.
  • a base silicon oxide film is formed on a silicon substrate, and a metal oxide, metal nitride or a silicate thereof is used as a metal diffusion source on the formed base silicon oxide film.
  • the interfacial silicate reaction is promoted, and the metal element is diffused into the underlying silicon oxide film to form a high dielectric constant gate insulating film on the silicon substrate.
  • the metal diffusion source having the film thickness containing Hf and the composition ratio shown in this embodiment the maximum gate leakage reduction is possible regardless of the method of forming the metal diffusion source.
  • the effect and transistor on-current can be realized.
  • the base oxide film thickness can be set larger than the equivalent oxide film thickness of the gate dielectric film having a high dielectric constant, it is possible to have a thin film characteristic.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present invention can be applied to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device.
  • FIG. 1 A diagram suggesting a manufacturing process of a Hf silicate high dielectric constant film in the present embodiment.
  • FIG. 2 This figure suggests the dependence of the gate leakage reduction effect on the amount of Hf compared to the SiON film when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 3 This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 4 A graph showing the dependence of the transistor on-current on the Hf content compared to the SiON film, normalized by the inversion capacitance, when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 5 is a diagram suggesting the processing temperature dependence of hysteresis.
  • FIG. 6 This figure suggests the optimum film thickness and composition ratio of the HfSiO film when used as a metal diffusion source.
  • FIG. 8 This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiN) is 1.5 nm.
  • FIG. 9 This figure is normalized by the inversion capacitance when the film thickness of the metal diffusion source (HfSiN) is 1.5 nm, and suggests the dependence of the transistor on-current on the Hf amount compared to the SiON film.
  • FIG. 10 is a diagram suggesting a manufacturing process of the Hf silicate high dielectric constant film in the third embodiment.

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Abstract

A semiconductor device wherein a high-quality gate insulating film can be formed on an interface of a silicon substrate and interface electrical characteristics are improved. On the surface of a silicon substrate (101), a base layer (oxide film or oxynitride film) (102) including silicon is formed. On the surface of the formed base layer (102), a metal compound layer (103) composed of a metal compound is deposited as a metal supplying source or metal diffusion source. The base layer (102) and the metal compound layer (103) are heat-treated to diffuse a metal element of the metal compound included in the metal compound layer (103) into the base layer (102). Then, on the silicon substrate (101), a gate insulating film (106) having a high dielectric constant is formed, and a semiconductor device having a metal atom quantity in the metal compound in the metal compound layer (103) within a range of 1.5E+15cm-2 to 2.6E+15cm-2 is formed.

Description

半導体装置及び半導体装置の製造方法  Semiconductor device and manufacturing method of semiconductor device
技術分野  Technical field
[0001] 本発明は、高誘電率薄膜を有した半導体装置及び半導体装置の製造方法に関す るものであり、特に、高性能で低消費電力を実現する MOSFET (Metal— Oxide— Semiconductor Field Effect Transistor)を構成するゲート絶縁膜の信頼性 を高めた半導体装置及び半導体装置の製造方法に関するものである。  TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device, and more particularly, a MOSFET (Metal—Oxide—Semiconductor Field Effect Transistor) that realizes high performance and low power consumption. And a method for manufacturing the semiconductor device, in which the reliability of the gate insulating film constituting the semiconductor device is improved.
背景技術  Background art
[0002] シリコン酸ィ匕膜は、プロセス上の安定性が高ぐまた、優れた絶縁特性を有するため 、 MOSFETのゲート絶縁膜材料として有用である。近年、素子微細化と共にゲート 絶縁膜の薄膜化が進んでおり、ゲート長が lOOnm以下のデバイスでは、スケーリン グ則の要請力もゲート絶縁膜であるシリコン酸ィ匕膜の厚さは 2. Onm以下であることが 必要となっている。  A silicon oxide film is useful as a gate insulating film material for a MOSFET because of its high process stability and excellent insulating properties. In recent years, the gate insulation film has become thinner with the miniaturization of devices, and for devices with a gate length of lOOnm or less, the required power of the scaling rule is also less than 2. Onm. It is necessary to be.
[0003] このような極薄の絶縁膜を用いた場合、ゲートバイアス印加時に絶縁層を挿んで流 れるトンネル電流力 ソース Zドレイン電流に対して無視できない値となる。従って M OSFETの高性能化と低消費電力化を図るために、実効的 (電気的)なゲート絶縁膜 の膜厚を薄くし、かつ、トンネル電流をデバイス設計上の許容値内に抑えるための研 究開発が盛んに進められているのが現状である。  [0003] When such an extremely thin insulating film is used, the tunnel current force flowing through the insulating layer when a gate bias is applied is a value that cannot be ignored with respect to the source Z drain current. Therefore, in order to improve the performance and power consumption of MOS FETs, the effective (electrical) gate insulating film thickness is reduced and the tunnel current is kept within the allowable range in device design. At present, research and development is actively underway.
[0004] その研究開発の 1つとして、シリコン酸ィ匕膜中に窒素を添加することで、純粋なシリ コン酸化膜に比べて誘電率を増加させ、物理的な膜厚を薄層化することなしに実効 的 (電気的)なゲート絶縁層の膜厚を減少させる方法がある。このようなシリコン酸窒 化膜の形成手法としては、シリコン基板表面に酸化膜を形成した後、アンモニア H )などの窒素を含有したガス中で高温熱処理することで窒素導入する方法や、窒 [0004] As one of the research and development, nitrogen is added to the silicon oxide film to increase the dielectric constant and reduce the physical film thickness compared to pure silicon oxide film. There is a method of reducing the effective (electrical) gate insulating layer thickness without any problem. As a method for forming such a silicon oxynitride film, after forming an oxide film on the surface of the silicon substrate, nitrogen is introduced by performing high-temperature heat treatment in a nitrogen-containing gas such as ammonia (H).
3 Three
素プラズマにシリコン酸ィ匕膜を曝し、表面側を選択的に窒化する技術 (プラズマ窒化 技術)が検討されている。  A technique (plasma nitriding technique) in which a silicon oxide film is exposed to elementary plasma and the surface side is selectively nitrided is being studied.
[0005] し力しながら、純粋なシリコン窒化膜の比誘電率でもシリコン酸ィ匕膜の 2倍程度であ るため、シリコン酸ィ匕膜への窒素添カ卩による高誘電率ィ匕には限界があり、比誘電率を 10以上にすることは原理的に不可能である。 However, since the relative dielectric constant of a pure silicon nitride film is about twice that of a silicon oxide film, it has a high dielectric constant due to nitrogen addition to the silicon oxide film. Has a limit and the relative permittivity It is impossible in principle to make it 10 or more.
[0006] 従って、さらに素子の微細化が進んだ世代の技術として、シリコン酸化膜や酸窒化 膜に代えて比誘電率が 10以上の薄膜材料をゲート絶縁膜に採用する試みがなされ ている。このような高誘電率材料としては Al O [0006] Therefore, as a technology of a generation in which device miniaturization has further progressed, an attempt has been made to employ a thin film material having a relative dielectric constant of 10 or more instead of a silicon oxide film or an oxynitride film as a gate insulating film. Such high dielectric constant materials include Al 2 O 3
2 3、 ZrOや HfO、および Y Oなどの数  2 3, numbers such as ZrO, HfO, and Y O
2 2 2 3 多くの希土類元素酸化物、さら〖こは、 La Oなどのランタノイド系希土類元素の酸ィ匕  2 2 2 3 Many rare earth oxides, Sarasako, are lanthanoid rare earth elements such as La O
2 3  twenty three
物が候補材料として検討されている。また、これらの金属酸化物にシリコンを混入した シリケート材料も比誘電率が低下するものの熱安定性が向上することから候補材料と して検討されて 、る。これらの材料を用いればゲート長を微細にしてもスケーリング則 に矛盾しないゲート絶縁膜容量を保持しつつトンネル電流を低減可能な物理的な厚 さにすることは可能である。  Things are being considered as candidate materials. Silicate materials in which silicon is mixed into these metal oxides are also considered as candidate materials because they have improved thermal stability although their relative permittivity is reduced. If these materials are used, it is possible to achieve a physical thickness that can reduce the tunnel current while maintaining the gate insulating film capacitance consistent with the scaling law even if the gate length is made fine.
[0007] し力しながら、高誘電率酸化膜の移動度は、シリコン酸ィ匕膜に比べて低ぐ MOSF ETの電流駆動能力の低下によりゲート絶縁膜を薄層化した効果が相殺されてしまう ことが問題となっており、この問題は、高誘電率酸ィ匕膜の移動度劣化の主要因が膜 中電子トラップによるリモートクーロン散乱であることが判明し (例えば、非特許文献 1 参照）、膜中電子トラップを低減するための努力がなされているのが現状である。  However, the mobility of the high-dielectric-constant oxide film is lower than that of the silicon oxide film, and the effect of thinning the gate insulating film is offset by the decrease in MOSF ET current drive capability. This problem has been found to be caused by remote Coulomb scattering caused by electron traps in the film (see, for example, Non-Patent Document 1). ) Currently, efforts are being made to reduce electron traps in the film.
[0008] また、電子トラップが存在すると、トランジスタの閾値電圧 (VT)が動作時に変化し、 トランジスタの出力電流の長期安定性を確保することが難しくなる。  [0008] In addition, when an electron trap is present, the threshold voltage (VT) of the transistor changes during operation, making it difficult to ensure long-term stability of the output current of the transistor.
[0009] なお、シリコン基板表面への高誘電率ゲート絶縁膜の堆積手法として、シリコン基 板表面に高誘電率膜を直接堆積するか、もしくは、極薄 (通常 lnm未満)のシリコン 酸化膜を堆積した後で、高誘電率膜を堆積し、該堆積した高誘電率膜と下地との反 応を極力抑制して形成する方法がある（例えば、特許文献 1参照)。  [0009] As a method for depositing a high dielectric constant gate insulating film on the surface of a silicon substrate, a high dielectric constant film is directly deposited on the surface of a silicon substrate, or an extremely thin (usually less than lnm) silicon oxide film is used. There is a method in which after deposition, a high dielectric constant film is deposited, and the reaction between the deposited high dielectric constant film and the base is suppressed as much as possible (see, for example, Patent Document 1).
[0010] シリコン基板表面への高誘電率ゲート絶縁膜の堆積手法は、主に、 MOCVD (Me tal Organic し hemical Vapor Depositionリ装食や ALCVD (Atomic Layer Chemical Vapor Deposition)装置を用いて研究開発が進められており、プリカ 一サーゃ成膜温度、成膜シーケンスを最適化することで堆積する高誘電率膜が化学 量論的な組成を有する金属酸化物（あるいは、酸素濃度に過不足のないシリケート 組成）と一致するように条件出しが行われている。これは、膜中酸素欠損などの構造 欠陥が膜中電子トラップの要因の 1つと考えられているからである。 [0011] また、シリコン基板表面に予めシリコン酸ィ匕膜を形成した後に、該形成したシリコン 酸化膜内に少なくとも一種類の金属をイオン注入し、熱処理により、該注入した金属 をシリコン酸ィ匕膜内に拡散させ、半導体基板との間の界面状態の良好な、かつ、リー ク特性の良好な半導体装置の製造方法がある (例えば、特許文献 2参照)。 [0010] The deposition method of high dielectric constant gate insulating film on the silicon substrate surface is mainly researched and developed using MOCVD (Metal Organic and Chemical Vapor Deposition) and ALCVD (Atomic Layer Chemical Vapor Deposition) equipment. Metal oxide (or oxygen concentration is not excessive or deficient in the stoichiometric composition of the high dielectric constant film deposited by optimizing the deposition temperature and deposition sequence. The conditions are set so as to coincide with the silicate composition because structural defects such as oxygen vacancies in the film are considered to be one of the causes of electron traps in the film. [0011] Further, after a silicon oxide film is formed in advance on the surface of the silicon substrate, at least one kind of metal is ion-implanted into the formed silicon oxide film, and the injected metal is converted into silicon oxide by heat treatment. There is a method for manufacturing a semiconductor device that diffuses into a film, has a good interface state with a semiconductor substrate, and has a good leak characteristic (see, for example, Patent Document 2).
[0012] また、シリコン基板上にシリコン酸ィ匕膜を形成する工程と、前記シリコン酸ィ匕膜上に 、前記シリコン酸化膜に対する固溶限界以上の金属原子を有する金属膜又は金属 シリサイド膜を形成する工程と、前記金属膜真又は金属シリサイド膜中の金属原子を 前記シリコン酸化膜中に拡散させて金属シリケイト層を形成する工程と、を有し、固溶 限界による拡散の抑制作用により、金属原子を制御性よぐ必要十分にシリコン酸ィ匕 膜中に含有させることができ、誘電率の高い金属シリケイト層を形成し、シリコン基板 と金属シリケイト層との間の界面特性に優れた半導体装置の製造方法がある (例えば 、特許文献 3参照)。 [0012] Further, a step of forming a silicon oxide film on a silicon substrate, and a metal film or a metal silicide film having a metal atom having a solid solution limit or more with respect to the silicon oxide film on the silicon oxide film. And a step of diffusing metal atoms in the metal film true or metal silicide film into the silicon oxide film to form a metal silicate layer, and by suppressing the diffusion due to the solid solution limit, A semiconductor with excellent interfacial properties between a silicon substrate and a metal silicate layer, which can contain metal atoms in the silicon oxide film as necessary and sufficiently to control, forms a metal silicate layer with a high dielectric constant There is a device manufacturing method (see, for example, Patent Document 3).
特許文献 1：特開 2002— 289844号公報  Patent Document 1: Japanese Patent Laid-Open No. 2002-289844
特許文献 2：特開 2002— 314074号公報  Patent Document 2: JP 2002-314074 A
特許文献 3：特開 2001— 332547号公報  Patent Document 3: Japanese Patent Laid-Open No. 2001-332547
非特許文献 1 :A. Morioka et. all,「High Mobility MISFET with Low Tr apped Charge in HfSiO FilmsJ , 2003 Symposium on VLSI Technol ogy Digest oi fechnical Papers, p.上り 5  Non-Patent Document 1: A. Morioka et. All, `` High Mobility MISFET with Low Trapped Charge in HfSiO FilmsJ, 2003 Symposium on VLSI Technological Digest oi fechnical Papers, p. Up 5
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0013] し力しながら、上記特許文献 1の方法は、シリコン酸ィ匕膜が界面熱安定性を向上さ せることになるが、シリコン酸ィ匕膜の比誘電率が低いために、シリコン基板表面に形 成する初期シリコン酸化膜の膜厚を 0. 6nm以下にすることが重要であると考えられ る。 However, in the method of Patent Document 1 described above, the silicon oxide film improves the interfacial thermal stability. However, since the relative dielectric constant of the silicon oxide film is low, It is considered important that the initial silicon oxide film formed on the substrate surface has a thickness of 0.6 nm or less.
[0014] また、上記特許文献 2の方法は、シリコン酸ィ匕膜内に金属をイオン注入する際に、 欠陥が生じやすぐまた、熱処理時に金属元素の拡散の制御を行うことが出来ないこ とになる。  [0014] Further, the method of Patent Document 2 described above is that when a metal is ion-implanted into a silicon oxide film, a defect is generated and the diffusion of the metal element cannot be controlled immediately during the heat treatment. It becomes.
[0015] また、上記特許文献 3は、固溶限界による拡散の抑制作用により、金属原子を制御 性よく必要十分にシリコン酸ィ匕膜中に含有させることができ、誘電率の高い金属シリ ケイト層を形成することになるが、金属原子をシリコン酸化膜中に含有できない領域 が発生してしまった場合には、特性劣化を引き起こす虞がある。 [0015] In addition, Patent Document 3 described above controls metal atoms by suppressing diffusion due to a solid solution limit. Although it can be contained in the silicon oxide film with sufficient and sufficient properties, a metal silicate layer with a high dielectric constant will be formed, but there will be a region where metal atoms cannot be contained in the silicon oxide film. In such a case, there is a risk of causing characteristic deterioration.
[0016] 本発明は、上記事情に鑑みてなされたものであり、シリコン基板の界面に良質のゲ ート絶縁膜の形成を可能とし、界面電気特性を改善した半導体装置及び半導体装 置の製造方法を提供することを目的とするものである。  The present invention has been made in view of the above circumstances, and enables the formation of a high-quality gate insulating film at the interface of a silicon substrate, and the manufacture of a semiconductor device and a semiconductor device with improved interface electrical characteristics It is intended to provide a method.
課題を解決するための手段  Means for solving the problem
[0017] かかる目的を達成するために、本発明は以下の特徴を有することとする。 In order to achieve such an object, the present invention has the following features.
[0018] 本発明にかかる半導体装置は、ゲート電極をシリコン基板から電気的に絶縁するゲ ート絶縁膜を有する半導体装置であって、シリコン基板上にシリコンを含有する下地 層を形成し、該形成した下地層上に、金属拡散源としての金属化合物を堆積し、熱 処理を施すことで、金属化合物の金属元素を下地層に拡散させ、シリコン基板上に 高誘電率のゲート絶縁膜が形成されてなり、金属化合物中の金属原子量が、 1. 5E + 15cm— 2力ら 2. 6E+ 15cm— 2の範囲であることを特徴とするものである。 [0018] A semiconductor device according to the present invention is a semiconductor device having a gate insulating film that electrically insulates a gate electrode from a silicon substrate, wherein a base layer containing silicon is formed on the silicon substrate, A metal compound as a metal diffusion source is deposited on the formed underlayer and heat treated to diffuse the metal element of the metal compound into the underlayer and form a high dielectric constant gate insulating film on the silicon substrate. Thus, the metal atomic weight in the metal compound is in the range of 1.5E + 15 cm- 2 force and 2.6E + 15 cm- 2 .
[0019] また、本発明にかかる半導体装置は、金属拡散源としての金属化合物の膜厚 (nmIn addition, the semiconductor device according to the present invention has a thickness (nm) of a metal compound as a metal diffusion source.
)と、金属濃度 (金属原子数 Z (シリコン原子数 +金属原子数)）と、の積により決定す る金属化合物中の金属量が、 0. 6以上 0. 9以下であることを特徴とするものである。 ) And the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)), the amount of metal in the metal compound is 0.6 or more and 0.9 or less. To do.
[0020] また、本発明にかかる半導体装置において、下地層は、シリコン酸ィ匕物、または、シ リコン酸窒化物力もなることを特徴とするものである。 [0020] Further, in the semiconductor device according to the present invention, the underlayer also has a silicon oxide or silicon oxynitride force.
[0021] また、本発明にかかる半導体装置において、熱処理は、アンモニアまたは酸素を少 なくとも含む雰囲気で行うことで、金属化合物の金属元素が下地層に拡散した金属 拡散膜が形成されることを特徴とするものである。 [0021] Further, in the semiconductor device according to the present invention, the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby a metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed. It is a feature.
[0022] また、本発明にかかる半導体装置において、熱処理は、不活性ガス中で行い、そ の後に、アンモニアまたは酸素を少なくとも含む雰囲気で熱処理を施すことで、金属 化合物の金属元素が下地層に拡散した金属拡散膜が形成されることを特徴とするも のである。 In the semiconductor device according to the present invention, the heat treatment is performed in an inert gas, and then the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby the metal element of the metal compound is applied to the underlayer. A diffused metal diffusion film is formed.
[0023] また、本発明にかかる半導体装置は、アンモニアまたは酸素を少なくとも含む雰囲 気で行う熱処理を、 700°C以上 950°C以下で行うことで、金属化合物の金属元素が 下地層に拡散した金属拡散膜が形成されることを特徴とするものである。 In addition, the semiconductor device according to the present invention performs the heat treatment performed in an atmosphere containing at least ammonia or oxygen at 700 ° C. or higher and 950 ° C. or lower, so that the metal element of the metal compound is A metal diffusion film diffused in the underlayer is formed.
[0024] また、本発明にかかる半導体装置において、熱処理は、アンモニアを少なくとも含 む雰囲気において 750°C以上 900°C以下で行われ、金属化合物中の金属原子量 1S 2. 3E+ 15cm— 2力ら 2. 6E+ 15cm— 2の範囲であることを特徴とするものである。 In the semiconductor device according to the present invention, the heat treatment is performed at 750 ° C. or more and 900 ° C. or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 2.3E + 15 cm- 2 force or the like. 2. It is characterized by being in the range of 6E + 15cm- 2 .
[0025] また、本発明にかかる半導体装置において、熱処理は、アンモニアを少なくとも含 む雰囲気において 700°C以上 750°C未満で行われ、金属化合物中の金属原子量 1S 1. 5E+ 15cm— 2力ら 1. 7E+ 15cm— 2の範囲であることを特徴とするものである。 In the semiconductor device according to the present invention, the heat treatment is performed at 700 ° C. or more and less than 750 ° C. in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 1.5E + 15 cm- 2 force or the like. 1. 7E + 15cm- 2 range.
[0026] また、本発明にかかる半導体装置において、熱処理は、不活性ガス中で行い、そ の後に、窒素ラジカルを含む雰囲気に暴露することで、金属化合物の金属元素が下 地層に拡散した金属拡散膜が形成されることを特徴とするものである。  [0026] Further, in the semiconductor device according to the present invention, the heat treatment is performed in an inert gas, and thereafter, the metal element of the metal compound is diffused into the underlying layer by exposure to an atmosphere containing nitrogen radicals. A diffusion film is formed.
[0027] また、本発明にかかる半導体装置において、熱処理は、酸素を少なくとも含む雰囲 気で行い、その後に、窒素ラジカルを含む雰囲気に暴露することで、金属化合物の 金属元素が下地層に拡散した金属拡散膜が形成されることを特徴とするものである。  [0027] Further, in the semiconductor device according to the present invention, the heat treatment is performed in an atmosphere containing at least oxygen, and then exposed to an atmosphere containing nitrogen radicals, whereby the metal element of the metal compound diffuses into the underlayer. A metal diffusion film is formed.
[0028] また、本発明にかかる半導体装置は、酸素を少なくとも含む雰囲気での熱処理の 際に、下地層の下部を酸ィ匕してなることを特徴とするものである。  In addition, the semiconductor device according to the present invention is characterized in that the lower part of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
[0029] また、本発明にかかる半導体装置は、金属化合物の金属濃度 (金属原子数 Z (シリ コン原子数 +金属原子数)）が 0. 3以上であることを特徴とするものである。  The semiconductor device according to the present invention is characterized in that the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more.
[0030] また、本発明にかかる半導体装置は、熱処理後における、高誘電率ゲート酸化膜 の酸ィ匕膜換算膜厚が、高誘電率ゲート酸ィ匕膜を形成する際に用いた下地層よりも薄 くなることを特徴とするものである。  [0030] In addition, the semiconductor device according to the present invention has an oxide layer equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment, the underlying layer used when forming the high dielectric constant gate oxide film. It is characterized by becoming thinner.
[0031] また、本発明に力かる半導体装置において、金属化合物は、 Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、 Luの少 なくとも 1つの金属元素を含有することを特徴とするものである。  [0031] In the semiconductor device according to the present invention, the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, It is characterized by containing at least one metal element of Dy, Ho, Er, Tm, Yb, and Lu.
[0032] また、本発明にかかる半導体装置の製造方法は、ゲート電極をシリコン基板から電 気的に絶縁するゲート絶縁膜を有する半導体装置の製造方法であって、シリコン基 板上にシリコンを含有する下地層を形成する工程と、下地層上に金属拡散源として 金属化合物を堆積する工程と、下地層と、金属化合物と、に熱処理を施し、金属化 合物の金属元素を下地層に拡散させ、シリコン基板上に高誘電率のゲート絶縁膜を 形成する工程と、を行い、金属化合物中の金属原子量が、 1. 5E+ 15cm から 2. 6[0032] Further, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a silicon substrate, and includes silicon on the silicon substrate. A step of forming an underlayer to be deposited, a step of depositing a metal compound as a metal diffusion source on the underlayer, a heat treatment to the underlayer and the metal compound, and diffusing the metal element of the metal compound into the underlayer A high dielectric constant gate insulating film on the silicon substrate. The amount of metal atoms in the metal compound is from 1.5E + 15cm to 2.6
E+ 15cm— 2の範囲であることを特徴とするものである。 It is characterized by being in the range of E + 15cm- 2 .
[0033] また、本発明にかかる半導体装置の製造方法において、金属拡散源として用いる 金属化合物の膜厚 (nm)と、金属濃度 (金属原子数 Z (シリコン原子数 +金属原子 数)）と、の積により決定する金属化合物中の金属量は、 0. 6以上 0. 9以下の範囲で あることを特徴とするものである。 [0033] Further, in the method for manufacturing a semiconductor device according to the present invention, the film thickness (nm) of the metal compound used as the metal diffusion source, the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)), The amount of the metal in the metal compound determined by the product of is in the range of 0.6 or more and 0.9 or less.
[0034] また、本発明にかかる半導体装置の製造方法において、下地層は、シリコン酸化物[0034] In the method for manufacturing a semiconductor device according to the present invention, the underlayer is made of silicon oxide.
、または、シリコン酸窒化物力もなることを特徴とするものである。 Alternatively, the silicon oxynitride force is also obtained.
[0035] また、本発明に力かる半導体装置の製造方法にぉ 、て、熱処理は、アンモニアま たは酸素を少なくとも含む雰囲気で行うことで、金属化合物の金属元素が下地層に 拡散した金属拡散膜を形成することを特徴とするものである。 [0035] Further, according to the method for manufacturing a semiconductor device according to the present invention, the heat treatment is performed in an atmosphere containing at least ammonia or oxygen so that the metal element of the metal compound diffuses into the underlayer. A film is formed.
[0036] また、本発明にかかる半導体装置の製造方法において、熱処理は、不活性ガス中 で行い、その後に、アンモニアまたは酸素を少なくとも含む雰囲気で行うことで、金属 化合物の金属元素が下地層に拡散した金属拡散膜を形成することを特徴とするもの である。 [0036] In the method for manufacturing a semiconductor device according to the present invention, the heat treatment is performed in an inert gas, and then performed in an atmosphere containing at least ammonia or oxygen, so that the metal element of the metal compound is applied to the underlayer. It is characterized by forming a diffused metal diffusion film.
[0037] また、本発明に力かる半導体装置の製造方法にぉ 、て、アンモニアまたは酸素を 少なくとも含む雰囲気で行う熱処理は、 700°C以上 950°C以下で行うことを特徴とす るものである。  [0037] Further, according to the method for manufacturing a semiconductor device according to the present invention, the heat treatment performed in an atmosphere containing at least ammonia or oxygen is performed at 700 ° C or higher and 950 ° C or lower. is there.
[0038] また、本発明に力かる半導体装置の製造方法にぉ 、て、熱処理は、アンモニアを 少なくとも含む雰囲気において、 750°C以上 900°C以下で行われ、金属化合物中の 金属原子量が、 2. 3E+ 15cm— 2から 2. 6E+ 15cm— 2の範囲であることを特徴とする ものである。 [0038] Further, in the method for manufacturing a semiconductor device according to the present invention, the heat treatment is performed at 750 ° C or more and 900 ° C or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 2. is characterized in that in the range of from 3E + 15cm- 2 of 2. 6E + 15cm- 2.
[0039] また、本発明に力かる半導体装置の製造方法にぉ 、て、熱処理は、アンモニアを 少なくとも含む雰囲気において、 700°C以上 750°C未満で行われ、金属化合物中の 金属原子量が、 1. 5E+ 15cm— 2から 1. 7E+ 15cm— 2の範囲であることを特徴とする ものである。 [0039] Further, in the method of manufacturing a semiconductor device according to the present invention, the heat treatment is performed at 700 ° C or more and less than 750 ° C in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1. is characterized in that in the range of 1. 7E + 15cm- 2 from 5E + 15cm- 2.
[0040] また、本発明に力かる半導体装置の製造方法にぉ 、て、熱処理は、不活性ガス中 で行い、その後に、窒素ラジカルを含む雰囲気に暴露することで、金属化合物の金 属元素が下地層に拡散した金属拡散膜を形成することを特徴とするものである。 [0040] Further, in the method of manufacturing a semiconductor device according to the present invention, the heat treatment is performed in an inert gas, and then exposed to an atmosphere containing nitrogen radicals, so that the metal compound gold is exposed. A metal diffusion film in which a metal element is diffused in an underlayer is formed.
[0041] また、本発明にかかる半導体装置の製造方法において、熱処理は、酸素を少なくと も含む雰囲気で行い、その後に、窒素ラジカルを含む雰囲気に暴露することで、金 属化合物の金属元素が下地層に拡散した金属拡散膜を形成することを特徴とするも のである。  [0041] Further, in the method for manufacturing a semiconductor device according to the present invention, the heat treatment is performed in an atmosphere containing at least oxygen, and then the metal element of the metal compound is exposed to an atmosphere containing nitrogen radicals. It is characterized by forming a diffused metal film in the underlayer.
[0042] また、本発明にかかる半導体装置の製造方法において、酸素を少なくとも含む雰 囲気での熱処理の際に、下地層の下部を酸ィ匕することを特徴とするものである。  [0042] Further, in the method for manufacturing a semiconductor device according to the present invention, the lower portion of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
[0043] また、本発明にかかる半導体装置の製造方法において、金属化合物の金属濃度（ 金属原子数 Z (シリコン原子数 +金属原子数)）は、 0. 3以上であることを特徴とする ものである。  [0043] In the method for manufacturing a semiconductor device according to the present invention, the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more. It is.
[0044] また、本発明にかかる半導体装置の製造方法は、熱処理後における、高誘電率ゲ 一ト酸ィ匕膜の酸ィ匕膜換算膜厚が、高誘電率のゲート酸ィ匕膜を形成する際に用いた 下地層よりも薄くなることを特徴とするものである。  [0044] In addition, in the method for manufacturing a semiconductor device according to the present invention, a gate oxide film having a high dielectric constant in terms of an oxide film equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment is obtained. It is characterized by being thinner than the underlying layer used for forming.
[0045] また、本発明に力かる半導体装置の製造方法にぉ 、て、金属化合物は、 Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、Luの少なくとも 1つの金属元素を含有することを特徴とするものである。  [0045] In addition, according to the method of manufacturing a semiconductor device according to the present invention, the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, It contains at least one metal element of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.
[0046] このように、本発明は、ゲート電極をシリコン基板力も電気的に絶縁するゲート絶縁 膜を有する半導体装置において、シリコン基板上に、下地シリコン酸化膜を形成し、 該形成した下地シリコン酸化膜上に、金属拡散源として、 Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、 Luの少なくと も 1つの金属元素を含有する金属酸化物、金属シリコン酸ィヒ物、あるいは、窒化物を 堆積し、界面シリケート反応を促進するための熱処理を行い、下地シリコン酸化膜中 に、金属元素を拡散させることで、シリコン基板上に、高誘電率のゲート絶縁膜が形 成されることになり、金属酸ィ匕膜 (窒化膜）中の金属原子量が、 1. 5E+ 15cm—2〜 2 . 6E+ 15cm— 2の範囲であることを特徴とするものである。つまり、電子トラップのほ とんど無い固相反応膜形成にとって、ウェハ上に生成された下地シリコン酸ィ匕膜に供 給する金属原子量が重要となる。金属拡散源として用いる金属シリコン酸ィ匕膜、また は、金属窒化膜の堆積法は、どのような堆積法を用いても良ぐ拡散源である金属含 有酸化物、あるいは、金属窒化物中に含まれる金属量を適正な値にすることが固相 反応膜を形成する上で必須となる。なお、下地シリコン酸ィ匕膜に代えてシリコン酸窒 化膜を下地層として用 、た場合も同様である。 As described above, according to the present invention, in a semiconductor device having a gate insulating film that electrically insulates a gate electrode from a silicon substrate force, a base silicon oxide film is formed on the silicon substrate, and the formed base silicon oxide As a metal diffusion source on the film, Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb A metal oxide, metal silicon oxynitride, or nitride containing at least one metal element of Lu is deposited, and heat treatment is performed to promote the interfacial silicate reaction. By diffusing the metal element, a high dielectric constant gate insulating film is formed on the silicon substrate, and the metal atomic weight in the metal oxide film (nitride film) is 1.5E + 15cm— is characterized in that it is 2 ~ 2. 6E + 15cm- 2 range. In other words, the amount of metal atoms supplied to the underlying silicon oxide film formed on the wafer is important for forming a solid-phase reaction film with almost no electron trap. The deposition method of the metal silicon oxide film or the metal nitride film used as the metal diffusion source can be any metal deposition method including any metal deposition method. In order to form a solid phase reaction film, it is essential to set the amount of metal contained in the oxide or metal nitride to an appropriate value. The same applies when a silicon oxynitride film is used as the base layer instead of the base silicon oxide film.
[0047] また、本発明は、金属拡散した後に、あるいは、金属拡散している間に、金属シリコ ン酸窒化物を形成する低コストで再現性に優れた方法を採用して ヽる。金属酸化物 を窒化処理することで、誘電率が大幅に増加することになる。  [0047] Further, the present invention may employ a low-cost and excellent reproducibility method of forming a metal silicon oxynitride after metal diffusion or during metal diffusion. By nitriding the metal oxide, the dielectric constant is greatly increased.
[0048] このため、固相反応膜下部に用いるシリコン酸窒化膜、あるいは、シリコン酸ィ匕膜に 、厚い膜厚を適用しても、薄い電気的酸化膜厚を形成することが可能となる。また、 金属酸化物を窒化処理することで、結晶化温度を高めることも可能となるため、半導 体装置の製造工程時の温度マージンを広げることが可能となる。特に、固相反応し た膜は、窒化に加えて Siが膜中に拡散してくるため、 CVD等で成長した膜に比べて 緻密な膜となっており、窒化処理した後の非晶質性を維持する限界温度が、従来の MOCVDや ALDを使用した結晶化温度に比べて高くなる。一方、純粋な金属窒化 物は、リーク電流が大きぐ絶縁膜としての機能に乏しいことになる。したがって、金属 酸窒化物の形成が必要となる。  [0048] Therefore, even if a thick film thickness is applied to the silicon oxynitride film or the silicon oxide film used in the lower part of the solid phase reaction film, it is possible to form a thin electric oxide film thickness. . In addition, since the crystallization temperature can be increased by nitriding the metal oxide, it is possible to widen the temperature margin during the manufacturing process of the semiconductor device. In particular, a film that has undergone a solid-phase reaction has a dense film compared to a film grown by CVD or the like because Si diffuses into the film in addition to nitriding. The critical temperature to maintain the properties is higher than the crystallization temperature using conventional MOCVD and ALD. On the other hand, pure metal nitride has a poor function as an insulating film with a large leakage current. Therefore, it is necessary to form a metal oxynitride.
[0049] また、本発明における、 Hf濃度と膜厚、及び、 Hf量の関係は、単なる設計事項で はなぐ例えば、膜厚や Si濃度で膜を形成しても、固相反応させなければ、電子トラッ プの低減を実現することはできないことになる。  [0049] In addition, the relationship between the Hf concentration, the film thickness, and the Hf amount in the present invention is not just a design matter. For example, even if a film is formed with a film thickness or Si concentration, a solid-phase reaction must be performed. Therefore, it will not be possible to reduce electronic traps.
発明の効果  The invention's effect
[0050] 本発明にかかる半導体装置及び半導体装置の製造方法は、ゲート電極をシリコン 基板力も電気的に絶縁するゲート絶縁膜を有する半導体装置において、シリコン基 板上にシリコンを含有する下地層を形成し、該形成した下地層上に金属拡散源とし て金属化合物を堆積し、下地層と、金属化合物と、に熱処理を施し、金属化合物の 金属元素を下地層に拡散させ、シリコン基板上に高誘電率のゲート絶縁膜を形成し 、金属化合物中の金属原子量が、 1. 5E+ 15cm 2力ら 2. 6E+ 15cm— 2の範囲であ ることを特徴とするものである。このように、成膜条件を最適化することで、シリコン基 板の界面に良質のゲート絶縁膜の形成を可能とし、界面電気特性の改善を図ること が可能となる。 発明を実施するための最良の形態 [0050] A semiconductor device and a method for manufacturing a semiconductor device according to the present invention include forming a base layer containing silicon on a silicon substrate in a semiconductor device having a gate insulating film that electrically insulates the gate electrode of the gate electrode. Then, a metal compound is deposited as a metal diffusion source on the formed underlayer, heat treatment is performed on the underlayer and the metal compound, the metal element of the metal compound is diffused into the underlayer, and a high concentration is formed on the silicon substrate. forming a gate insulating film of a dielectric constant, a metal atom content in the metal compound is characterized in range der Rukoto of 1. 5E + 15cm 2 power et al 2. 6E + 15cm- 2. In this way, by optimizing the film formation conditions, it is possible to form a high-quality gate insulating film on the interface of the silicon substrate, and to improve the interface electrical characteristics. BEST MODE FOR CARRYING OUT THE INVENTION
[0051] まず、図 1を参照しながら、本実施形態における半導体装置について説明する。本 実施形態における半導体装置は、シリコン基板（101)表面にシリコンを含む下地層（ 酸化膜、または、酸窒化膜）（102)を形成する工程 (図 1 (a) )と、下地層（102)表面 上に金属供給源または金属拡散源として金属化合物力 なる金属化合物層（103) を堆積する工程（図 1 (b) )と、下地層（102)と、金属化合物層（103)と、に熱処理を 施すことで、金属化合物層（103)に含まれる金属化合物の金属元素を下地層（102 )に拡散させ、シリコン基板（101)上に高誘電率のゲート絶縁膜（106)を形成するェ 程（図 1 (c) )と、を行うことになる。これにより、シリコン基板（101)の界面に良質のゲ ート絶縁膜（106)の形成を可能とし、界面電気特性の改善を図ることが可能となる（ 図 l (d) )。なお、ゲート絶縁膜（106)は、 Hfリッチ領域（104)と、 Siリッチ領域（105) と、で構成されること〖こなる。  First, the semiconductor device according to the present embodiment will be described with reference to FIG. The semiconductor device in this embodiment includes a step (FIG. 1 (a)) of forming a base layer (oxide film or oxynitride film) (102) containing silicon on the surface of a silicon substrate (101), and a base layer (102 ) A step of depositing a metal compound layer (103) having a metal compound force as a metal supply source or metal diffusion source on the surface (FIG. 1 (b)), an underlayer (102), a metal compound layer (103), Heat treatment is performed to diffuse the metal element of the metal compound contained in the metal compound layer (103) into the base layer (102), thereby forming a high dielectric constant gate insulating film (106) on the silicon substrate (101). The process (Fig. 1 (c)) is performed. As a result, a high-quality gate insulating film (106) can be formed on the interface of the silicon substrate (101), and the electrical interface characteristics can be improved (FIG. L (d)). Note that the gate insulating film (106) is composed of an Hf rich region (104) and an Si rich region (105).
[0052] なお、本実施形態における半導体装置は、シリケートからなる高誘電率のゲート絶 縁膜をシリコン基板（101)上に直接堆積するのではなぐ図 1 (c)に示唆するように、 下地層（102)と金属化合物層（103)との界面反応によって形成した高品質なシリケ 一ト膜をゲート絶縁膜（106)として用いることになる。このゲート絶縁膜（106)は、高 誘電率であり、極めて薄い絶縁膜にすることが可能となる。なお、本実施形態におけ る半導体装置は、金属化合物層（103)の金属化合物中の金属原子量が、 1. 5E + 15cm— 2力ら 2. 6E+ 15cm— 2の範囲で、金属拡散源としての金属化合物の膜厚（nm )と、金属濃度 (金属原子数 Z (シリコン原子数 +金属原子数)）と、の積により決定す る金属化合物中の金属量が、 0. 6以上 0. 9以下の範囲であることを特徴とするもの である。以下、添付図面を参照しながら、膜厚 (nm)と濃度の異なる金属化合物を、 金属拡散源として適用し、電子トラップの低減とリーク電流低減効果とを最大限に引 き出すことが可能な固相反応膜の形成方法について説明する。 It should be noted that the semiconductor device according to the present embodiment is not directly deposited on a silicon substrate (101) with a high dielectric constant gate insulating film made of silicate, as shown in FIG. 1 (c). A high-quality silicate film formed by the interfacial reaction between the base layer (102) and the metal compound layer (103) is used as the gate insulating film (106). This gate insulating film (106) has a high dielectric constant, and can be an extremely thin insulating film. In the semiconductor device according to the present embodiment, the metal compound in the metal compound layer (103) has a metal atom amount in the range of 1.5E + 15 cm— 2 forces and 2.6E + 15 cm— 2 as a metal diffusion source. The amount of metal in the metal compound determined by the product of the film thickness (nm) of the metal compound and the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is not less than 0.6. It is characterized by a range of 9 or less. In the following, referring to the attached drawings, metal compounds with different film thicknesses (nm) and concentrations can be used as metal diffusion sources to maximize electron trap reduction and leakage current reduction. A method for forming a solid phase reaction film will be described.
[0053] (第 1の実施形態）  [0053] (First embodiment)
まず、第 1の実施形態における半導体装置について説明する。  First, the semiconductor device according to the first embodiment will be described.
第 1の実施形態では、特に、金属拡散源として HfO  In the first embodiment, in particular, as a metal diffusion source, HfO
2、 HfSiOを用いた場合につい て説明する。 [0054] なお、図 1は、本実施形態における高品質の HfSiOゲート絶縁膜の作製工程を示 唆するものである。 2. The case of using HfSiO will be explained. Note that FIG. 1 suggests a manufacturing process of a high-quality HfSiO gate insulating film in the present embodiment.
[0055] 図 1に示唆するように、まず、シリコン基板（101)を硫酸過水、及び、アンモニア過 水によって洗浄した後、熱酸化を施すことにより下地酸化膜層 (102)となるシリコン酸 化膜をここでは 1. 8nm形成することになる（図 l (a) )。そして、下地酸化膜層（102) 表面に Hf濃度の異なるハフニウムシリケ一ト（103) (HfSiO膜、もしくは、 HfO膜)を  As suggested in FIG. 1, first, the silicon substrate (101) is washed with sulfuric acid-hydrogen peroxide and ammonia-hydrogen peroxide, and then subjected to thermal oxidation to form silicon oxide that becomes the base oxide film layer (102). In this case, the film thickness is 1.8 nm (Fig. L (a)). Then, hafnium silicate (103) (HfSiO film or HfO film) with different Hf concentration is applied to the surface of the base oxide film layer (102).
2 堆積する（図 l (b) )。  2 Deposits (Fig. L (b)).
[0056] なお、 Si濃度の異なる HfSiO膜（103)の堆積には、 MOCVD (Metal Organic Chemical Vapor Deposition)法、 ALCVD (Atomic Layer Chemical Vap or Deposition)法もしくは PVD (Physical Vapor Deposition)法を用いるのが 好ましい。  [0056] It should be noted that the MOCVD (Metal Organic Chemical Vapor Deposition) method, ALCVD (Atomic Layer Chemical Vapor Deposition) method or PVD (Physical Vapor Deposition) method is used for the deposition of the HfSiO film (103) having different Si concentrations. Is preferred.
[0057] MOCVD法を用いた場合の第 1の堆積方法としては、 Hf原料ガスとして HTB (Ter tiary Butoxy Hafnium)、 Si原料として、シラン、もしくは、ジシランを用いて、 Hf SiO層（103)を堆積する。そして、酸素、もしくは、オゾン雰囲気でァニールすること になる。  [0057] As the first deposition method using the MOCVD method, HTB (tertiary butoxy hafnium) is used as the Hf source gas, silane or disilane is used as the Si source, and the Hf SiO layer (103) is formed. accumulate. Then, annealing is performed in an oxygen or ozone atmosphere.
[0058] MOCVD法を用いた場合の第 2の堆積方法としては、 Hf原料ガスとして TDEAH [0058] As a second deposition method using the MOCVD method, TDEAH is used as the Hf source gas.
、 Si原料として TDMASを用いて、 HfSiO膜（103)を堆積することになる。 The HfSiO film (103) is deposited using TDMAS as the Si raw material.
[0059] ALCVD法を用いた場合の堆積方法としては、 Hf原料ガスとして TEMAHを用い て、 Hf原料と、 Si原料と、を堆積した後に、 HF原料と、 Si原料と、を酸化する工程を 繰り返すことで、 HfSiO膜（103)を形成することになる。 [0059] The deposition method using the ALCVD method includes a step of oxidizing the HF source material and the Si source material after depositing the Hf source material and the Si source material using TEMAH as the Hf source gas. By repeating, the HfSiO film (103) is formed.
[0060] PVD法を用いた場合の堆積方法としては、 Hf原子をスパッタリングして堆積し、 70[0060] As a deposition method using the PVD method, sputtering is performed by sputtering Hf atoms.
0°Cの酸素雰囲気で、 Hf層を酸ィ匕して HfO膜（103)を形成することになる。 In an oxygen atmosphere at 0 ° C., the Hf layer is oxidized to form the HfO film (103).
2  2
[0061] Hf SiO膜（ 103)、もしくは、 HfO膜（ 103)の堆積後、熱処理を施すことで（図 1 (c)  [0061] After the Hf SiO film (103) or HfO film (103) is deposited, heat treatment is performed (FIG. 1 (c)
2  2
)、下地酸ィ匕膜層（102)と、 HfSiO膜（103)、もしくは、 HfO膜（103)と、の界面反  ), Interface between the base oxide film layer (102) and the HfSiO film (103) or HfO film (103)
2  2
応 (金属拡散反応)を促進させ、ゲート絶縁膜 (106)を作製することになる（図 1 (d) ) 。なお、ゲート絶縁膜 (106)を作製する下地層（102)と、金属化合物層（103)と、の 界面においては、界面シリケート反応が進行してシリケート領域となり、 Hfリッチ領域 (104)と、 Siリッチ領域（105)と、に区分されることになる。 [0062] 次に、金属拡散源として 1. 5nmの HfSiO膜（103)を堆積した場合に、電子トラッ プの低減とリーク電流低減効果とを最大限に引き出すことが可能となる Hf量を決定 する際の実験結果について説明する。 The reaction (metal diffusion reaction) is promoted, and a gate insulating film (106) is produced (Fig. 1 (d)). At the interface between the base layer (102) for forming the gate insulating film (106) and the metal compound layer (103), an interface silicate reaction proceeds to become a silicate region, and an Hf rich region (104) It is divided into the Si rich region (105). [0062] Next, when a 1.5 nm HfSiO film (103) is deposited as a metal diffusion source, the amount of Hf that can maximize the reduction of the electron trap and the leakage current is determined. The experimental results when doing this will be described.
[0063] なお、本実形態における金属拡散反応のための熱処理は、アンモニア雰囲気にお いて 800°C、 10分の条件を用い、金属拡散源中の金属元素が十分拡散できるように した。 [0063] The heat treatment for the metal diffusion reaction in the present embodiment was performed under conditions of 800 ° C and 10 minutes in an ammonia atmosphere so that the metal element in the metal diffusion source could be sufficiently diffused.
[0064] なお、図 2から図 4は、下地酸ィ匕膜層（102)上に堆積する HfSiO膜（103)の膜厚 を 1. 5nmに固定し、供給 Hf量を変化させて作製した固相反応 HfSiON膜（103)の MISFETの特性評価結果を示唆するものである。  Note that FIGS. 2 to 4 were prepared by fixing the thickness of the HfSiO film (103) deposited on the base oxide film layer (102) to 1.5 nm and changing the amount of supplied Hf. This suggests the results of MISFET characterization of solid phase reaction HfSiON film (103).
[0065] 図 2は、電気的酸ィ匕膜換算膜厚が同等な SiON膜に対するゲート絶縁膜 (106)の 反転側リーク電流低減効果の Hf量依存性を示唆するものである。  [0065] FIG. 2 suggests the dependence of the gate-side insulating film (106) on the reverse leakage current reduction effect on the amount of Hf with respect to a SiON film having an equivalent electrical oxide film equivalent film thickness.
[0066] 図 2に示唆するように、 Hf量の低下とともに固相反応後の HfSiO膜（103)の誘電 率が減少し、ゲートリーク低減効果が低下していくことになる。なお、図 2に示唆する ように、 Hf量が 2. 3E+ 15cm 2未満でゲートリーク低減効果が急激に減るため、下 地酸ィ匕膜層（102)上に堆積する HfSiO膜（103)の Hf量は、少なくとも 2. 3E+ 15c m 2以上にする必要があることがわかる。 [0066] As suggested in FIG. 2, as the amount of Hf decreases, the dielectric constant of the HfSiO film (103) after the solid-phase reaction decreases, and the gate leakage reduction effect decreases. Incidentally, the so suggests 2, because it reduces drastically the gate leakage reduction effect Hf content is less than 2. 3E + 15cm 2, HfSiO film deposited on the lower Chisani匕膜layer (102) of (103) It can be seen that the amount of Hf needs to be at least 2.3E + 15 cm 2 or more.
[0067] 図 3は、種々の Hf量におけるヒステリシス測定結果を示唆したものである。ヒステリシ スは、電圧印加時にゲート絶縁膜（106)中の電子トラップに電荷が捕獲される現象 に対応することになる。なお、図 3は、電圧スイープ幅を 1. 8Vまで変化させた場合の 測定結果を示唆している。図 3では、 Hf量が低くなるに従って、ヒステリシスが減少す ることがわ力る。これは、金属拡散源となる HfSiO膜（103)中に残された未反応の余 剰 Hf原子が減少するためである。特に、 Hf量： 2. 6E+ 15cm 2以下においてヒステ リシスが数 mV以下と非常に低ぐヒステリシス抑制のためには Hf量を 2. 6E+ 15cm — 2以下にする必要があることがわかる。 [0067] FIG. 3 suggests hysteresis measurement results at various Hf amounts. Hysteresis corresponds to the phenomenon that charges are trapped in the electron traps in the gate insulating film (106) when a voltage is applied. Figure 3 suggests the measurement results when the voltage sweep width is changed to 1.8V. Fig. 3 shows that the hysteresis decreases as the Hf amount decreases. This is because the unreacted surplus Hf atoms left in the HfSiO film (103) serving as the metal diffusion source are reduced. In particular, Hf amount: 2. Hf amount for 6E + 15cm 2 hysteresis is several mV or less in the following and a very Teigu hysteresis suppressed 2. 6E + 15cm - it can be seen that it is necessary to 2 or less.
[0068] 図 4は、トランジスタのオン電流 (Ion)を反転容量で規格化し、参照用の SiONゲー ト絶縁膜を有したトランジスタの特性と比較したものである。 Hf量が 2. 3E+ 15cm"2 〜2. 6E+ 15cm— 2にオン電流のピークがあり、 2. 6E+ 15cm— 2以上の Hf量ではォ ン電流が急激に劣化することがわかる。 [0069] つまり、図 3に示唆するヒステリシスの傾向と完全に一致しており、金属拡散源中の 余剰 Hf原子を減らして電子トラップを低減することで移動度が向上していることがわ かる。 [0068] FIG. 4 shows the comparison of the on-current (Ion) of the transistor with the characteristics of the transistor having the reference SiON gate insulating film, normalized by the inversion capacitance. It can be seen that the Hf amount has a peak of on-current at 2.3E + 15cm " 2 to 2.6E + 15cm- 2, and that the on-state current deteriorates abruptly at Hf amounts greater than 2.6E + 15cm- 2 . [0069] In other words, it is completely consistent with the hysteresis tendency suggested in Fig. 3, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. .
[0070] 即ち、図 4に示唆するように、 Hf量が 2. 3E+ 15cm— 2〜2. 6E+ 15cm— 2の範囲の ときに、 SiONの 90%程度の特性を維持することが可能となる。 That is, as suggested in FIG. 4, when the Hf amount is in the range of 2.3E + 15 cm- 2 to 2.6E + 15 cm- 2 , it is possible to maintain the characteristics of about 90% of SiON. .
[0071] この図 2〜図 4の測定結果を総合すると、 Hf拡散源となる HfSiON膜中の Hf量を、 2. 3E+ 15cm— 2力ら 2. 6E+ 15cm 2の範囲にすることで電子トラップの低減とリーク 電流低減効果とを最大限に引き出した固相反応膜を形成することが可能となることが ゎカゝる。 [0071] Taken together, measurement results of FIGS. 2-4, the amount of Hf of HfSiON film serving as the Hf diffusion source, 2. 3E + 15cm- 2 Power et al 2. electron trapping by a range of 6E + 15cm 2 It is possible to form a solid-phase reaction film that maximizes the effect of reducing the leakage current and reducing the leakage current.
[0072] また、 Hf量を、 2. 3E+ 15cm 2力ら 2. 6E+ 15cm 2の範囲とした場合は、 NMOS BT不安定性（Bias Temperature Instability)の実験から得られる予測値（動作 温度 85°C、動作電圧 1. IVの条件における 10年後の VTシフト量）は、 20mV以下 であった。この値は、本実施形態において作製したゲート絶縁膜（106)が非常に優 れたな信頼性を有することを示唆している。これは、本実施形態において作製したゲ ート絶縁膜（106)中の電子トラップが少ないことに起因するためである。 [0072] When the amount of Hf is in the range 2.3E + 15cm 2 force 2.6E + 15cm 2 , the predicted value (operating temperature 85 ° C) obtained from the experiment of NMOS BT instability (Bias Temperature Instability) The VT shift after 10 years under the condition of operating voltage 1. IV was 20mV or less. This value suggests that the gate insulating film (106) manufactured in this embodiment has extremely excellent reliability. This is because there are few electron traps in the gate insulating film (106) fabricated in this embodiment.
[0073] さらに、本実施形態において、 1. 8nmの下地酸化膜層 (102)に対して、 Hf量原 子量 2. 4E+ 15Cm 2のHfSiOをl. 5nm堆積した場合、固相反応後の酸化膜換算 膜厚が 1. 7nmとなり、下地酸ィ匕膜層（102)の酸ィ匕膜換算膜厚よりも薄膜ィ匕すること が可能となる。これは、固相反応と窒化により下地酸化膜層（102)も高誘電率化した ためである。 [0073] Further, in the present embodiment, 1 to and from the bottom oxide layer of 8 nm (102), if the HfSiO of Hf per basic molecular weight 2. 4E + 15 C m 2 and l. 5 nm deposited, solid-phase reaction The oxide equivalent film thickness after that becomes 1.7 nm, and it becomes possible to make the film thickness thinner than the oxide film equivalent film thickness of the base oxide film layer (102). This is because the underlying oxide film layer (102) has also been increased in dielectric constant by solid phase reaction and nitridation.
[0074] 次に、図 5を参照しながら、固相反応処理の温度を下げた場合における、供給可能 な Hf量の変化について説明する。なお、固相拡散のための熱処理は、すべてアンモ ユア雰囲気で 10分間行った。図 5は、ヒステリシスの固相拡散温度、及び、 Hf量依存 性を示唆する。  [0074] Next, changes in the amount of Hf that can be supplied when the temperature of the solid-phase reaction treatment is lowered will be described with reference to FIG. All heat treatments for solid phase diffusion were performed in an ammonia atmosphere for 10 minutes. Figure 5 suggests that the hysteresis depends on the solid phase diffusion temperature and Hf content.
[0075] 図 5に示唆するように、金属拡散源の Hf量が、 2. 3E+ 15cm— 2〜2. 6E+ 15cm"2 の場合、固相拡散処理温度が 750°C未満になると、ヒステリシスが急激に増大し、特 性が劣化することになる。このため、図 5に示唆するように、固相拡散処理温度が 750 °C未満の場合には、 Hf量を 1. 5E+ 15cm— 2〜1. 7E+ 15cm— 2に減らすことで、ヒス テリシスの劣化を抑制することが可能となる。 [0075] As suggested in FIG. 5, when the Hf amount of the metal diffusion source is 2.3E + 15cm— 2 to 2.6E + 15cm " 2 , the hysteresis is reduced when the solid phase diffusion treatment temperature is less than 750 ° C. As shown in Fig. 5, when the solid phase diffusion treatment temperature is less than 750 ° C, the amount of Hf is 1.5E + 15 cm- 2 to 1. 7E + 15cm— 2 It becomes possible to suppress the degradation of teresis.
[0076] なお、熱処理温度を下げることで、供給可能な金属量が減少するのは、固相反応 可能な Hf量の低下により、余剰 Hfによる電子トラップの増大が起こるためと、窒化の 強度が低下することで、結晶化温度の低下を抑制しきれないためである。なお、 700 °C未満では Hfの固相反応が起きず、特性劣化の改善は見られな力つた。  [0076] Note that the amount of metal that can be supplied is reduced by lowering the heat treatment temperature because the amount of Hf that can be subjected to solid-phase reaction is reduced, resulting in an increase in electron traps due to excess Hf. This is because the lowering of the crystallization temperature cannot be suppressed by lowering. Below 700 ° C, no solid phase reaction of Hf occurred, and there was no improvement in property deterioration.
[0077] 上記と同様な実験を、 HfSiO膜（103)の成膜法、膜厚、及び、濃度を変化させ、固 相反応に最適な Hf拡散源が成膜法に関係なく Hf量によって決定される図 6に示唆 する結果を導いた。なお、図 6に示唆する、 Hf量： 1. 5E+ 15cm 2〜2. 6E+ 15cm" 2の範囲は、金属シリコン酸化物膜厚 (nm)と、金属濃度 (金属原子数 Z (金属原子数 +シリコン原子数)）と、の積により決定する金属化合物中の金属量が 0. 6から 0. 9 になるような金属拡散源の膜厚と、金属濃度と、の組み合わせに対応することになる [0077] An experiment similar to the above was performed by changing the film formation method, film thickness, and concentration of the HfSiO film (103), and the optimum Hf diffusion source for the solid phase reaction was determined by the amount of Hf regardless of the film formation method. The results suggested in Fig. 6 were derived. As suggested in Fig. 6, the range of Hf amount: 1.5E + 15cm 2 to 2.6E + 15cm "2 is the metal silicon oxide film thickness (nm) and metal concentration (number of metal atoms Z (number of metal atoms + This corresponds to the combination of the metal concentration and the metal diffusion source thickness so that the amount of metal in the metal compound determined by the product of the number of silicon atoms))) is from 0.6 to 0.9.
[0078] 図 6に示唆するように、金属化合物中の金属原子量が 1. 5E+ 15cm— 2〜2. 6E + 15cm 2の範囲で、金属拡散源としての金属化合物の膜厚 (nm)と、金属濃度 (金属 原子数 Z (シリコン原子数 +金属原子数)）と、の積により決定する金属化合物中の 金属量が、 0. 6以上 0. 9以下の範囲の Hf量であれば、異なる膜厚と、組成と、の Hf SiO膜をいかなる方法で堆積しても、固相拡散後には同一の膜質となることがわかる 。つまり、 MOCVD法を用いて、 Hf濃度 0. 6の HfSiO膜を 1. 5nm堆積後、 850°C の少なくともアンモニアを含む雰囲気で固相反応させた場合でも、 PVD法を用いて、 HfO膜 (Hf濃度： 1. 0)を 0. 9nm堆積後、 850°Cのアンモニア雰囲気で固相反応さ[0078] As indicated in FIG. 6, the metal atom of the metal compound is in the range of 1. 5E + 15cm- 2 ~2. 6E + 15cm 2, and the thickness of the metal compound as a metal diffusion source (nm), If the amount of metal in the metal compound determined by the product of the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is in the range of 0.6 or more and 0.9 or less, it is different. It can be seen that no matter how the Hf SiO film with the film thickness and composition is deposited, the film quality is the same after solid phase diffusion. That is, even when a 1.5-nm HfSiO film with a Hf concentration of 0.6 nm is deposited using MOCVD, and a solid-phase reaction is performed in an atmosphere containing at least ammonia at 850 ° C, the HfO film ( Hf concentration: 1.0) after 0.9 nm deposition, solid phase reaction in 850 ° C ammonia atmosphere
2 2
せた場合でも、同様の性能の固相反応膜を形成することが可能となる。  Even in such a case, it is possible to form a solid-phase reaction film having the same performance.
[0079] しかし、金属拡散層の金属濃度が 0. 3以下では、最適な金属量を得るための膜厚 力^ nm以上となり、固相拡散をする上で非常に厚くなる。そのため、金属拡散層上部 が固相拡散しにくぐ完全に固相拡散させるためには長時間の熱処理を必要とし、生 産効率上望ましくない。 [0079] However, when the metal concentration of the metal diffusion layer is 0.3 or less, the film thickness force ^ nm or more for obtaining the optimum amount of metal is exceeded, and it becomes very thick for solid phase diffusion. For this reason, in order for the upper part of the metal diffusion layer to be completely solid-phase diffused, which is difficult to solid-phase diffuse, a long-time heat treatment is required, which is undesirable in terms of production efficiency.
[0080] なお、上記実施形態では、金属拡散源の固相反応のための熱処理に、アンモニア を含む雰囲気で行ったが、アンモニアの替わりに窒素や Ar、 He等の不活性ガス中 で拡散反応を行い、その後に、少なくともアンモニアを含む雰囲気で熱処理を行うか 、または、窒素ラジカルへの曝露を行って窒素を導入することでも同様の結果が得ら れることになる。つまり、初めの熱処理による固相反応で電子トラップが低減し、次の 窒化処理で、膜中に窒素が導入されることで耐熱性が向上することになる。特に、窒 素ラジカルを用いた場合の最終的な膜中窒素濃度プロファイルは、表面で高ぐ基 板界面にいくに従って低くなる。この場合、基板界面の窒素濃度を低減することがで きるため、 PMOSの BT信頼性 (動作温度 85°C、動作電圧 1. IVの条件における 10年後 VTシフト量）を、アンモニア処理を行った場合に比べて 5mV以上改善するこ とが可能となる。 [0080] In the above embodiment, the heat treatment for the solid phase reaction of the metal diffusion source is performed in an atmosphere containing ammonia, but the diffusion reaction is performed in an inert gas such as nitrogen, Ar, or He instead of ammonia. And then heat treatment in an atmosphere containing at least ammonia. Similar results can be obtained by introducing nitrogen by exposure to nitrogen radicals. In other words, the electron traps are reduced by the solid phase reaction by the first heat treatment, and the heat resistance is improved by introducing nitrogen into the film in the next nitriding treatment. In particular, the final nitrogen concentration profile in the film when nitrogen radicals are used decreases as the substrate interface increases on the surface. In this case, since the nitrogen concentration at the substrate interface can be reduced, the BT reliability of the PMOS (VT shift amount after 10 years under the conditions of operating temperature 85 ° C and operating voltage 1. IV) is treated with ammonia. Compared to the case, it can be improved by 5mV or more.
[0081] なお、上記実施形態では下地層（102)にシリコン酸化膜を用いたが、下地層（102 )にシリコン酸窒化膜を用いても同様の電子トラップ低減効果を得ることになり、下地 層（102)が窒化によって高誘電率ィ匕しているためより薄膜ィ匕することが可能となる。  In the above embodiment, a silicon oxide film is used for the base layer (102). However, even if a silicon oxynitride film is used for the base layer (102), the same electron trap reduction effect can be obtained. Since the layer (102) has a high dielectric constant due to nitriding, it can be made thinner.
[0082] (第 2の実施形態）  [0082] (Second Embodiment)
次に、第 2の実施形態について説明する。  Next, a second embodiment will be described.
[0083] 第 2の実施形態では、金属拡散源として Hf窒化物 (HfN)もしくは Hfシリコン窒化 物 (HfSiN)を用いることとする。シリコン基板（101)を硫酸過水、及び、アンモニア 過水で洗浄後、熱酸化を施して下地酸化膜層（102)となるシリコン酸化膜 1. 8nmを 形成した（図 l (a) )。なお、下地酸ィ匕膜層（102)の形成にはどのような装置を用いて も良いが、本実施形態では、枚葉式のランプア-一ラー装置を用い、 50%の窒素希 釈酸素雰囲気中で 900°Cの熱処理を行うことで下地酸化膜層 (102)を形成する。  [0083] In the second embodiment, Hf nitride (HfN) or Hf silicon nitride (HfSiN) is used as the metal diffusion source. After cleaning the silicon substrate (101) with sulfuric acid / water and ammonia / water, thermal oxidation was performed to form a silicon oxide film of 1.8 nm, which becomes the base oxide film layer (102) (FIG. 1 (a)). Any apparatus may be used to form the base oxide film layer (102). In this embodiment, a single-wafer type lamp aligner apparatus is used, and 50% nitrogen-diluted oxygen is used. A base oxide film layer (102) is formed by heat treatment at 900 ° C. in an atmosphere.
[0084] 次に、下地酸化膜層（102)表面に HfN層（103)もしくは HfSiN層（103)を 0. 5n m〜2. Onm堆積する（図 l (b) )。  Next, an HfN layer (103) or an HfSiN layer (103) is deposited in a thickness of 0.5 nm to 2. Onm on the surface of the base oxide film layer (102) (FIG. 1 (b)).
[0085] なお、 PVD法を用いた場合の HfN層（103)の形成は、金属 Hfターゲットと、スパッ タガス (反応ガス）としてアルゴンと窒素との混合ガスを用いて成膜する。また、 HfSi N層（103)の形成は、金属 Hfターゲットと Siターゲットとを交互に用い、反応ガスとし てアルゴンと窒素の混合ガスを用いて成膜することになる。  [0085] Note that when the PVD method is used, the HfN layer (103) is formed using a metal Hf target and a mixed gas of argon and nitrogen as a sputtering gas (reactive gas). The HfSiN layer (103) is formed by alternately using a metal Hf target and a Si target and using a mixed gas of argon and nitrogen as a reaction gas.
[0086] また、 ALD法を用いた場合は、 Hf原料ガスとして TEMAHを用い、 Hf原料と Si原 料とを堆積後、アンモニア雰囲気で窒化する工程を繰り返すことで HfSiN膜層 (103 )を形成し、 Si原料の堆積工程を無くすことで、 HfN膜層（103)を形成する。なお、 本実施形態では主に PVD法を用いることとする。 [0086] When the ALD method is used, TEMAH is used as the Hf source gas, and after depositing the Hf source and the Si source, the process of nitriding in an ammonia atmosphere is repeated to form the HfSiN film layer (103) Then, the HfN film layer (103) is formed by eliminating the Si raw material deposition step. In addition, In this embodiment, the PVD method is mainly used.
[0087] 金属拡散層の堆積後、窒素や Ar、 Heなどの希ガス等の不活性ガス雰囲気で 800 °Cの熱処理を 10分間行い、下地シリコン酸ィ匕膜層 (102)に Hf金属を拡散した (図 1 (c) ) 0なお、熱処理では、下地酸ィ匕膜層（102)に堆積した HfN膜（103)、もしくは、 HfSiN膜（103)中の窒素の大部分が膜外に放出され、最終的な HfSiON膜中の窒 素濃度は、 5%まで減少することになる。 HfN膜（103)そのものは非常にリーク電流 の大きい膜であるが、逆に、膜中窒素濃度が非常に少ない場合、耐熱性劣化の原因 となるため、膜中窒素量を補充する目的で Hf拡散後に、窒素ラジカルに曝したり、ァ ンモニァ雰囲気で 800°Cの熱処理を施したりすることで、最終的な窒素濃度を 10% 〜20%にすることになる。 [0087] After the metal diffusion layer is deposited, heat treatment is performed at 800 ° C for 10 minutes in an inert gas atmosphere such as nitrogen, Ar, or He, and a Hf metal is applied to the underlying silicon oxide film layer (102). (Fig. 1 (c)) 0 In the heat treatment, most of the nitrogen in the HfN film (103) or HfSiN film (103) deposited on the base oxide film layer (102) The released nitrogen concentration in the final HfSiON film will be reduced to 5%. The HfN film (103) itself is a film with a very large leakage current, but conversely, if the nitrogen concentration in the film is very low, it will cause heat resistance deterioration. After diffusion, exposure to nitrogen radicals or heat treatment at 800 ° C in an ammonia atmosphere will result in a final nitrogen concentration of 10% to 20%.
[0088] このように、金属原子を拡散する工程と、窒化する工程と、を分ける方法は、金属原 子を十分に拡散するための熱処理条件と所望の窒素濃度、及び、窒素プロファイル を実現するための窒化条件をそれぞれ独立に制御できる利点がある。  [0088] As described above, the method of dividing the metal atom diffusing step and the nitriding step realizes the heat treatment conditions, the desired nitrogen concentration, and the nitrogen profile for sufficiently diffusing the metal atoms. Therefore, there is an advantage that the nitriding conditions can be controlled independently.
[0089] 一方、金属原子の拡散を、アンモニアを少なくとも含む雰囲気で行うことで、上述し たような独立した制御はできないものの、金属原子の拡散と、窒素原子の補充と、を 同時に行うことが可能となり、処理時間を短縮することが可能となる。なお、本実施形 態では、主に、枚葉式ランプアニール装置を用いてアンモニアを含む雰囲気で 850 °C、 2分間の熱処理を行い、金属原子の拡散と窒素原子との補充を同時に行った。 縦型炉を用いてアンモニアを含む雰囲気で 800°C、 30分の処理を行っても同様の 結果が得られた。このとき最終的な窒素濃度は、 15%〜20%となる。  [0089] On the other hand, by performing diffusion of metal atoms in an atmosphere containing at least ammonia, although independent control as described above cannot be performed, diffusion of metal atoms and replenishment of nitrogen atoms can be performed simultaneously. This makes it possible to shorten the processing time. In this embodiment, heat treatment was performed at 850 ° C. for 2 minutes in an atmosphere containing ammonia mainly using a single-wafer lamp annealing apparatus, and diffusion of metal atoms and replenishment with nitrogen atoms were performed at the same time. . Similar results were obtained even if the treatment was performed at 800 ° C for 30 minutes in an atmosphere containing ammonia using a vertical furnace. At this time, the final nitrogen concentration is 15% to 20%.
[0090] なお、図 7から図 9は、金属拡散源として用いる 1. 5nmの Hf窒化物、および、 Hfシ リコン窒化物中の Hf量を変化させた場合におけるゲートリーク電流低減効果（図 7)、 ヒステリシス（図 8)、トランジスタオン電流（図 9)を評価した測定結果を示唆する。  FIGS. 7 to 9 show the effects of reducing the gate leakage current when the amount of Hf in the 1.5 nm Hf nitride and Hf silicon nitride used as a metal diffusion source is changed (FIG. 7). ), Hysteresis (Fig. 8), and transistor on-current (Fig. 9) were evaluated.
[0091] なお、図 7は、電気的酸ィ匕膜換算膜厚が同等な SiON膜に対するゲート絶縁膜の 反転側リーク電流低減効果について Hf量依存性を示唆したものである。  FIG. 7 suggests the dependence of the gate insulating film on the inversion side leakage current with respect to the Hf amount dependence on the SiON film having the equivalent electrical oxide film equivalent film thickness.
[0092] 図 7に示唆するように、 Hf量の低下とともに固相反応後の HfSiO膜の誘電率が減 少し、ゲートリーク低減効果が低下して 、くことがわかる。  As suggested in FIG. 7, it can be seen that as the amount of Hf decreases, the dielectric constant of the HfSiO film after the solid-phase reaction decreases, and the effect of reducing gate leakage decreases.
[0093] 図 7に示唆するように、 Hf量が 2. 3E+ 15cm 2未満でゲートリーク低減効果が急激 に減るため、堆積する HfSiO膜の Hf量は少なくとも 2. 3E+ 15cm 以上にする必要 がある。 [0093] As suggested in Fig. 7, when the amount of Hf is less than 2.3E + 15cm 2 Therefore, the Hf content of the deposited HfSiO film must be at least 2.3E + 15cm.
[0094] また、図 8は、種々の Hf量におけるヒステリシス測定結果を示唆したものである。ヒス テリシスは、電圧印加時にゲート絶縁膜中の電子トラップに電荷が捕獲される現象に 対応すること〖こなる。図 8は、電圧スイープ幅を 1. 8Vまで変化させた場合の測定結 果を示唆している。図 8に示唆するように、 Hf量が低くなるに従って、ヒステリシスが減 少することがわかる。これは、金属拡散源となる HfSiO膜中に残された未反応の余剰 Hf原子が減少するためである。特に、 Hf量： 2. 3E+ 15cm 2以下においてヒステリ シスが数 mV以下と非常に小さぐヒステリシス抑制のためには金属拡散源の Hf量を 2. 3E+ 15cm— 2以下にする必要があること示している。 [0094] Fig. 8 suggests hysteresis measurement results at various Hf amounts. Hysteresis corresponds to the phenomenon that charges are trapped in electron traps in the gate insulating film when a voltage is applied. Figure 8 suggests the measurement results when the voltage sweep width is changed to 1.8V. As suggested in Fig. 8, it can be seen that the hysteresis decreases as the amount of Hf decreases. This is because the unreacted surplus Hf atoms left in the HfSiO film serving as the metal diffusion source are reduced. In particular, Hf amount: 2. 3E + 15cm 2 indicates that it is necessary to set the amount of Hf of metal diffusion source 2. 3E + 15cm- 2 or less for very small sag hysteresis suppression and hysteresis of several mV or less in the following ing.
[0095] また、図 9は、トランジスタのオン電流 (Ion)を反転容量で規格化し、参照用の SiO Nゲート絶縁膜を有したトランジスタの特性と比較したものである。図 9に示唆するよう に、 Hf量が 2. 3E+ 15cm— 2〜2. 6E+ 15cm— 2付近にオン電流のピークがあり、 2. 6 E+ 15cm— 2以上の Hf量ではオン電流が急激に劣化することがわかる。つまり、図 8 に示唆するヒステリシスの傾向と完全に一致しており、金属拡散源中の余剰 Hf原子 を減らして電子トラップを低減することで移動度が向上することがわかる。また、図 9に 示唆するように、 Hf量が 2. 3E+ 15cm— 2〜2. 6E+ 15cm— 2の範囲のときに、 SiON の 90%程度の特性を実現することが可能となる。 FIG. 9 is a graph in which the on-current (Ion) of the transistor is normalized by the inversion capacitance and compared with the characteristics of the transistor having the reference SiO N gate insulating film. So the suggested in Figure 9, there is a peak of Hf weight 2. 3E + 15cm- 2 ~2. 6E + 15cm- 2 near the on-current, 2. 6 E + 15cm- 2 or more on-current abruptly in the amount of Hf It turns out that it deteriorates. In other words, it is completely consistent with the hysteresis trend suggested in Fig. 8, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. In addition, as suggested in Fig. 9, when the Hf content is in the range of 2.3E + 15cm- 2 to 2.6E + 15cm- 2 , it is possible to achieve characteristics of about 90% of SiON.
[0096] 図 7〜図 9に示唆する測定結果を総合すると、 Hf拡散源となる HfSiON膜中の Hf 量を 2. 3E+ 15cm— 2〜2. 6E+ 15cm— 2とすることで電子トラップの低減とリーク電流 低減効果とを最大限に引き出した固相反応膜を形成することが可能なことが判明し、 第 1の実施形態と同様の結果を得ることになる。 [0096] Taken together indicate measurement results in FIGS. 7 to 9, the reduction of electron traps by the amount of Hf of HfSiON film serving as the Hf diffusion source and 2. 3E + 15cm- 2 ~2. 6E + 15cm- 2 As a result, it has been found that it is possible to form a solid-phase reaction film that maximizes the effect of reducing leakage current, and the same result as in the first embodiment is obtained.
[0097] なお、 Hf量が 2. 3E+ 15cm 2の HfSiN膜を金属拡散層として堆積し、 TZDB (初 期破壊)測定の固相拡散温度依存性を評価した。その結果、 750°C以上では 1個 Z cm2の欠陥密度であった力 750°C未満で激増し、 700°Cでは 5000個/ cm2となつ た。また、 750°C未満でヒステリシスも急激に増加し、 10mV以上となった。熱処理温 度を下げること〖こよる電子トラップの増加は、第 1の実施形態と同様に、固相反応が 起こる量が低下するためである。また、 TZDBの劣化は窒化の強度が低下し、結晶 化温度の低下を抑制しきれな 、ためである。上記低温固相拡散でのヒステリシスと欠 陥密度とは Hf量の低減により改善することは可能であり、 Hf量を 1. 5E+ 15cm 2〜 1. 7E+ 15cm— 2にすることでヒステリシスを 5mv以下、欠陥密度を 1個/ cm2まで改 善することが可能となる。つまり、固相反応のための処理温度を 700°C以上 750°C未 満とした場合、 Hf拡散反応に最適な Hf量は、 750°C以上の場合に比べて低く 1. 5E + 15cm— 2〜1. 7E+ 15cm— 2であった。 700°C以下においては、固相拡散は発生し なかった。 [0097] An HfSiN film with an Hf content of 2.3E + 15cm 2 was deposited as a metal diffusion layer, and the dependence of the TZDB (initial fracture) measurement on the solid phase diffusion temperature was evaluated. As a result, the force density was less than 750 ° C, which was a defect density of 1 piece Z cm 2 above 750 ° C, and increased to 5000 pieces / cm 2 at 700 ° C. In addition, the hysteresis increased rapidly below 750 ° C, exceeding 10 mV. The increase in the number of electron traps due to the lowering of the heat treatment temperature is due to a decrease in the amount of solid phase reaction, as in the first embodiment. In addition, the deterioration of TZDB decreases the strength of nitriding, This is because the decrease in the conversion temperature cannot be suppressed. The hysteresis and defect density in the low-temperature solid-phase diffusion is possible to improve by reducing the amount of Hf, 5 mv or less hysteresis by the amount of Hf to 1. 5E + 15cm 2 ~ 1. 7E + 15cm- 2 It is possible to improve the defect density to 1 / cm 2 . In other words, when the processing temperature for the solid phase reaction is 700 ° C or more and less than 750 ° C, the optimum amount of Hf for Hf diffusion reaction is lower than that of 750 ° C or more 1.5E + 15cm— 2 to 1.7E + 15 cm— 2 . At 700 ° C or lower, solid phase diffusion did not occur.
[0098] また、本実施形態と同様の実験を、 HfSiN膜の成膜法、膜厚、及び、濃度を変化さ せて行い、固相反応に最適な Hf拡散源が成膜法に関係なく Hf量によって決まり、 H f拡散源中の Hf原子量を 1. 5E+ 15cm— 2〜2. 6E+ 15cm— 2にしなければならないと いう結論に至った。 In addition, the same experiment as this embodiment was performed by changing the film formation method, the film thickness, and the concentration of the HfSiN film, and the optimum Hf diffusion source for the solid-phase reaction was independent of the film formation method. determined by the amount of Hf, led to the conclusion that say that the Hf atomic weight in H f diffusion source 1. 5E + 15cm- 2 ~2. must be to 6E + 15cm- 2.
[0099] なお、本実施形態では下地層にシリコン酸ィ匕膜を用いたが、シリコン酸ィ匕膜に換え てシリコン酸窒化膜を用いても、同様の電子トラップ低減効果が得られることになる。 この場合は、下地層が窒化によって高誘電率ィ匕しているためより薄膜ィ匕することにな る。  In this embodiment, the silicon oxide film is used as the underlayer. However, the same electron trap reduction effect can be obtained by using a silicon oxynitride film instead of the silicon oxide film. Become. In this case, since the underlayer has a high dielectric constant due to nitriding, it becomes thinner.
[0100] (第 3の実施形態）  [0100] (Third embodiment)
次に、第 3の実施形態について説明する。  Next, a third embodiment will be described.
[0101] 第 3の実施形態は、金属拡散層（203)から下地層（202)に金属を固相拡散する際[0101] In the third embodiment, metal is diffused from the metal diffusion layer (203) to the underlayer (202) by solid phase diffusion.
、もしくは、固相拡散後において、少なくとも酸素を含む雰囲気で熱処理を行うことを 特徴とするものである。 Alternatively, after solid phase diffusion, heat treatment is performed in an atmosphere containing at least oxygen.
[0102] 図 10は、金属拡散層（203)から下地層（202)に金属を固相拡散する際に、少なく とも酸素を含む雰囲気で熱処理を行った場合の高品質の HfSiOゲート絶縁膜 (206 )を作製する工程を示して 、る。  [0102] Figure 10 shows a high-quality HfSiO gate insulating film when a solid phase diffusion of metal from the metal diffusion layer (203) to the underlayer (202) is performed in an atmosphere containing at least oxygen ( 206) is shown.
[0103] 図 10に示唆するように、まず、シリコン基板（201)を洗浄後、下地層（202)となるシ リコン酸化膜を 1. 5nm形成する（図 10 (a) )。そして、この下地シリコン酸ィ匕膜 (202) 表面に金属拡散源となる HfSiO膜、 HfO膜、 HfN膜、もしくは、 HfSiN膜の金属拡  [0103] As suggested in FIG. 10, first, after cleaning the silicon substrate (201), a silicon oxide film to be the underlayer (202) is formed to 1.5 nm (FIG. 10 (a)). Then, the metal diffusion of HfSiO film, HfO film, HfN film, or HfSiN film, which becomes a metal diffusion source, is formed on the surface of the underlying silicon oxide film (202).
2  2
散層（203)を堆積する（図 10 (b) )。本実施形態では、それぞれ、 MOCVD法と PV D法とを用いて、膜中 Hf量が、 2. 5E+ 15cm 2の HfSiO膜、または、 HfSiN膜 1. 5 nmを堆積する。 A scattering layer (203) is deposited (Fig. 10 (b)). In this embodiment, using the MOCVD method and the PVD method, respectively, the Hf content in the film is 2.5E + 15 cm 2 HfSiO film or HfSiN film 1.5 Deposit nm.
[0104] その後、枚様式のランプア-一ラーを用いて窒素希釈した酸素雰囲気 (0. 5%0 )  [0104] Then, oxygen atmosphere diluted with nitrogen using a single-plate lamp-arler (0.5% 0)
2 中 800°C、 10分間の熱処理を行い（図 10 (c) )、金属拡散源中の Hf原子を、完全に 下地シリコン酸ィ匕膜 (202)中に固相拡散する。拡散雰囲気中に酸素が含まれる場合 、図 10 (d)に示唆するように、金属原子の下地シリコン酸ィ匕膜 (202)への拡散による 膜中電子トラップの低減に加えて、酸素原子もしくは酸素分子の拡散によりシリコン 基板 (201)と下地シリコン酸ィ匕膜層（202)の界面が新たに酸化され、界面酸化膜層 (207)が形成されることになり、界面準位が改善することになる。このため、移動度が 界面酸ィ匕をしない場合に比べて約 8%向上することになる。ただし、 1オングストロー ム以上の酸化膜増加に起因した反転層容量の低下により、移動度の向上分は相殺 され、トランジスタオン電流の改善は、 4%程度であった。よって、少なくとも 1オングス トローム以上は下地シリコン酸ィ匕膜 (202)を薄くしておき、最終的な酸ィ匕膜換算膜厚 が所望の膜厚になるように調整する必要がある。なお、ゲート絶縁膜 (206)を作製す る下地層（202)と、金属化合物層（203)と、の界面にお 1、ては、界面シリケート反応 が進行してシリケート領域となり、 Hfリッチ領域（204)と、 Siリッチ領域（205)と、に区 分されること〖こなる。  2) Heat treatment is performed at 800 ° C for 10 minutes in Fig. 10 (c), and Hf atoms in the metal diffusion source are completely solid-phase diffused into the underlying silicon oxide film (202). When oxygen is contained in the diffusion atmosphere, as suggested in FIG. 10 (d), in addition to the reduction of electron traps in the film due to diffusion of metal atoms into the underlying silicon oxide film (202), oxygen atoms or Due to the diffusion of oxygen molecules, the interface between the silicon substrate (201) and the underlying silicon oxide film layer (202) is newly oxidized to form an interface oxide film layer (207), which improves the interface state. It will be. For this reason, the mobility is improved by about 8% compared to the case without interfacial acid. However, the decrease in inversion layer capacitance due to an oxide film increase of 1 angstrom or more offsets the increase in mobility, and the transistor on-current improvement was about 4%. Therefore, it is necessary to make the underlying silicon oxide film (202) thin for at least 1 angstrom or more and adjust the final oxide film equivalent film thickness to a desired film thickness. In addition, the interface silicate reaction proceeds to the silicate region at the interface between the base layer (202) for forming the gate insulating film (206) and the metal compound layer (203), and the Hf-rich region. (204) and Si-rich region (205).
[0105] なお、上記実施形態において、金属原子の固相拡散を窒素や Ar、 Heなどの不活 性ガスで行い、その後、酸素を少なくとも含む雰囲気で熱処理を行うことでも界面に 新たな酸ィ匕膜が形成され同様の効果が得られることになる。ただし、 HfSiO膜、 HfO 膜を金属拡散源として使用した場合、膜中に窒素が含まれないため、金属原子の拡 [0105] Note that in the above embodiment, solid-phase diffusion of metal atoms is performed with an inert gas such as nitrogen, Ar, or He, and then a heat treatment is performed in an atmosphere containing at least oxygen, so that a new acid is added to the interface. A capsule is formed and the same effect is obtained. However, when an HfSiO film or an HfO film is used as a metal diffusion source, since the film does not contain nitrogen, the metal atoms are expanded.
2 2
散による耐熱性の劣化を抑制できないことになる。従って、酸素雰囲気での固相反 応後、窒素ラジカル等を用いて膜中に窒素を導入することが望ま 、。  Therefore, it is impossible to suppress deterioration of heat resistance due to scattering. Therefore, it is desirable to introduce nitrogen into the film using a nitrogen radical or the like after the solid phase reaction in an oxygen atmosphere.
[0106] なお、上記第 1から第 3の実施形態では、金属拡散源として HfSiO、 HfO、 HfN、 [0106] In the first to third embodiments, HfSiO, HfO, HfN,
2 2
HfSiNを用いて説明した力 金属拡散源が Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、 Luの少なくとも 1つの元 素を含有することを特徴とする金属酸化物、金属窒化物、またはそれらの、シリケート 材料を用いた場合も同様の結果が得られることになる。 Forces explained using HfSiN Metal diffusion sources are Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm Similar results are obtained when using metal oxides, metal nitrides, or silicate materials characterized by containing at least one element of Yb, Lu.
[0107] このように、本実施形態における半導体装置は、ゲート電極をシリコン基板から電気 的に絶縁するゲート絶縁膜を有する半導体装置において、シリコン基板上に下地シ リコン酸化膜を形成し、該形成した下地シリコン酸化膜上に金属拡散源として金属酸 化物、金属窒化物あるいはそれらのシリケート材料を堆積し、熱処理を施すことで、 界面シリケート反応を促進させ、下地シリコン酸ィ匕膜中に金属元素を拡散させること でシリコン基板上に高誘電率のゲート絶縁膜を形成することになる。そして、本実施 形態において示された Hf量を含有する膜厚と、組成比と、の金属拡散源を用いるこ とで、どのような金属拡散源の形成方法を用いても最大のゲートリーク低減効果とトラ ンジスタオン電流とを実現することが可能となる。また、下地酸化膜厚を高誘電率の ゲート絶縁膜の酸ィ匕膜換算膜厚よりも厚めに設定することが可能となるため、薄膜ィ匕 しゃす 、特徴をもつことが可能となる。 Thus, in the semiconductor device according to the present embodiment, the gate electrode is electrically connected from the silicon substrate. In a semiconductor device having a gate insulating film to be electrically insulated, a base silicon oxide film is formed on a silicon substrate, and a metal oxide, metal nitride or a silicate thereof is used as a metal diffusion source on the formed base silicon oxide film. By depositing the material and applying heat treatment, the interfacial silicate reaction is promoted, and the metal element is diffused into the underlying silicon oxide film to form a high dielectric constant gate insulating film on the silicon substrate. . In addition, by using the metal diffusion source having the film thickness containing Hf and the composition ratio shown in this embodiment, the maximum gate leakage reduction is possible regardless of the method of forming the metal diffusion source. The effect and transistor on-current can be realized. Further, since the base oxide film thickness can be set larger than the equivalent oxide film thickness of the gate dielectric film having a high dielectric constant, it is possible to have a thin film characteristic.
[0108] なお、上述する実施形態は、本発明の好適な実施形態であり、上記実施形態のみ に本発明の範囲を限定するものではなぐ本発明の要旨を逸脱しない範囲において 種々の変更を施した形態での実施が可能である。 It should be noted that the above-described embodiment is a preferred embodiment of the present invention, and various modifications are made without departing from the scope of the present invention, which is not limited to the above-described embodiment alone. It is possible to implement in the form.
産業上の利用可能性  Industrial applicability
[0109] 本発明にかかる半導体装置及び半導体装置の製造方法は、高誘電率薄膜を有す る半導体装置及びその半導体装置の製造方法に適用可能である。 The semiconductor device and the method for manufacturing the semiconductor device according to the present invention can be applied to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device.
図面の簡単な説明  Brief Description of Drawings
[0110] [図 1]本実施形態における Hfシリケート高誘電率膜の作製工程を示唆する図である。  [0110] [FIG. 1] A diagram suggesting a manufacturing process of a Hf silicate high dielectric constant film in the present embodiment.
[図 2]金属拡散源 (HfSiO)の膜厚が 1. 5nmにおける、 SiON膜と比較したゲートリ ーク低減効果の Hf量依存性を示唆する図である。  [Fig. 2] This figure suggests the dependence of the gate leakage reduction effect on the amount of Hf compared to the SiON film when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
[図 3]金属拡散源 (HfSiO)の膜厚が 1. 5nmにおける、ヒステリシスの Hf量依存性を 示唆する図である。  [Fig. 3] This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiO) is 1.5 nm.
[図 4]金属拡散源 (HfSiO)の膜厚が 1. 5nmにおける、反転容量で規格化し、 SiON 膜と比較したトランジスタオン電流の Hf量依存性を示唆する図である。  [FIG. 4] A graph showing the dependence of the transistor on-current on the Hf content compared to the SiON film, normalized by the inversion capacitance, when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
[図 5]ヒステリシスの処理温度依存性を示唆する図である。  FIG. 5 is a diagram suggesting the processing temperature dependence of hysteresis.
[図 6]金属拡散源として用いた場合に、固相反応に最適な HfSiO膜の膜厚と組成比 を示唆する図である。  [Fig. 6] This figure suggests the optimum film thickness and composition ratio of the HfSiO film when used as a metal diffusion source.
[図 7]金属拡散源 (HfSiN)の膜厚が 1. 5nmにおける、 SiON膜と比較したゲートリ ーク低減効果の Hf量依存性を示唆する図である。 [Fig.7] Gate diffusion compared to SiON film when the thickness of the metal diffusion source (HfSiN) is 1.5 nm. It is a figure which suggests the Hf amount dependence of the peak reduction effect.
[図 8]金属拡散源 (HfSiN)の膜厚が 1. 5nmにおける、ヒステリシスの Hf量依存性を 示唆する図である。  [Fig. 8] This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiN) is 1.5 nm.
[図 9]金属拡散源 (HfSiN)の膜厚が 1. 5nmにおける、反転容量で規格化し、 SiON 膜と比較したトランジスタオン電流の Hf量依存性を示唆する図である。  [Fig. 9] This figure is normalized by the inversion capacitance when the film thickness of the metal diffusion source (HfSiN) is 1.5 nm, and suggests the dependence of the transistor on-current on the Hf amount compared to the SiON film.
圆 10]第 3の実施形態における Hfシリケート高誘電率膜の作製工程を示唆する図で ある。 [10] FIG. 10 is a diagram suggesting a manufacturing process of the Hf silicate high dielectric constant film in the third embodiment.
符号の説明 Explanation of symbols
101、 201 シリコン基板  101, 201 Silicon substrate
102、 202 下地層（下地シリコン酸ィ匕膜層、または、下地シリコン酸窒化膜層） 102, 202 Underlayer (underlying silicon oxide film layer or underlayer silicon oxynitride film layer)
103、 203 ノヽフユウムシリケート（Hf SiO)層（または、 HfO、 HfN) 103, 203 NOF silicate (Hf SiO) layer (or HfO, HfN)
2  2
104、 204 HfUツチ領域  104, 204 HfU
105、 205 Siリッチ領域  105, 205 Si rich region
106、 206 ゲート絶縁膜  106, 206 Gate insulation film
207 界面酸化膜層  207 Interfacial oxide layer

Claims

請求の範囲 The scope of the claims
[1] ゲート電極をシリコン基板力も電気的に絶縁するゲート絶縁膜を有する半導体装置 であって、  [1] A semiconductor device having a gate insulating film that electrically insulates a silicon substrate force from a gate electrode,
前記シリコン基板上にシリコンを含有する下地層を形成し、該形成した下地層上に 、金属拡散源としての金属化合物を堆積し、熱処理を施すことで、前記金属化合物 の金属元素を前記下地層に拡散させ、前記シリコン基板上に高誘電率のゲート絶縁 膜が形成されてなり、  A base layer containing silicon is formed on the silicon substrate, a metal compound as a metal diffusion source is deposited on the formed base layer, and heat treatment is performed, so that the metal element of the metal compound is added to the base layer. A high dielectric constant gate insulating film is formed on the silicon substrate,
前記金属化合物中の金属原子量が、 1. 5E+ 15cm 2力ら 2. 6E+ 15cm— 2の範囲 であることを特徴とする半導体装置。 Metal atomic weight of the metal compound is a semiconductor device which is a range of 1. 5E + 15cm 2 Power et al 2. 6E + 15cm- 2.
[2] 前記金属拡散源としての金属化合物の膜厚 (nm)と、金属濃度 (金属原子数 Z (シ リコン原子数 +金属原子数)）と、の積により決定する前記金属化合物中の金属量が[2] The metal in the metal compound determined by the product of the film thickness (nm) of the metal compound as the metal diffusion source and the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) Amount
、 0. 6以上 0. 9以下であることを特徴とする請求項 1記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor device is 0.6 or more and 0.9 or less.
[3] 前記下地層は、シリコン酸ィ匕物、または、シリコン酸窒化物からなることを特徴とする 請求項 1記載の半導体装置。 [3] The semiconductor device according to [1], wherein the underlayer is made of silicon oxide or silicon oxynitride.
[4] 前記熱処理は、アンモニアまたは酸素を少なくとも含む雰囲気で行うことで、前記 金属化合物の金属元素が前記下地層に拡散した金属拡散膜が形成されることを特 徴とする請求項 1記載の半導体装置。 [4] The metal film according to claim 1, wherein the heat treatment is performed in an atmosphere containing at least ammonia or oxygen to form a metal diffusion film in which the metal element of the metal compound is diffused in the underlayer. Semiconductor device.
[5] 前記熱処理は、 [5] The heat treatment includes
不活性ガス中で行い、その後に、アンモニアまたは酸素を少なくとも含む雰囲気で 熱処理を施すことで、前記金属化合物の金属元素が前記下地層に拡散した金属拡 散膜が形成されることを特徴とする請求項 1記載の半導体装置。  A metal diffusion film in which the metal element of the metal compound is diffused in the underlayer is formed by performing heat treatment in an atmosphere containing at least ammonia or oxygen after being performed in an inert gas. The semiconductor device according to claim 1.
[6] 前記アンモニアまたは酸素を少なくとも含む雰囲気で行う熱処理を、 700°C以上 95[6] The heat treatment performed in an atmosphere containing at least ammonia or oxygen is performed at 700 ° C or higher 95
0°C以下で行うことで、前記金属化合物の金属元素が前記下地層に拡散した金属拡 散膜が形成されることを特徴とする請求項 4または 5記載の半導体装置。 6. The semiconductor device according to claim 4, wherein a metal diffusion film in which the metal element of the metal compound is diffused into the base layer is formed by performing the treatment at 0 ° C. or lower.
[7] 前記熱処理は、 [7] The heat treatment includes
アンモニアを少なくとも含む雰囲気において 750°C以上 900°C以下で行われ、前 記金属化合物中の金属原子量が、 2. 3E+ 15cm— 2力ら 2. 6E+ 15cm 2の範囲であ ることを特徴とする請求項 1記載の半導体装置。 Ammonia carried out in the following 750 ° C or higher 900 ° C in an atmosphere containing at least a metal atom amount before Symbol metal compound is a feature ranges der Rukoto of 2. 3E + 15cm- 2 Power et al 2. 6E + 15cm 2 The semiconductor device according to claim 1.
[8] 前記熱処理は、 [8] The heat treatment includes
アンモニアを少なくとも含む雰囲気において 700°C以上 750°C未満で行われ、前 記金属化合物中の金属原子量が、 1. 5E+ 15cm— 2から 1. 7E+ 15cm 2の範囲であ ることを特徴とする請求項 1記載の半導体装置。 Place at 700 ° less C than 750 ° C at least containing atmosphere ammonia, metal atom amount before Symbol metal compound, wherein the range der Rukoto of 1. 7E + 15cm 2 from 1. 5E + 15cm- 2 The semiconductor device according to claim 1.
[9] 前記熱処理は、 [9] The heat treatment includes
不活性ガス中で行い、その後に、窒素ラジカルを含む雰囲気に暴露することで、前 記金属化合物の金属元素が前記下地層に拡散した金属拡散膜が形成されることを 特徴とする請求項 1記載の半導体装置。  The metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed by performing in an inert gas and then exposing to an atmosphere containing nitrogen radicals. The semiconductor device described.
[10] 前記熱処理は、 [10] The heat treatment includes
酸素を少なくとも含む雰囲気で行い、その後に、窒素ラジカルを含む雰囲気に暴露 することで、前記金属化合物の金属元素が前記下地層に拡散した金属拡散膜が形 成されることを特徴とする請求項 1記載の半導体装置。  The metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed by performing in an atmosphere containing at least oxygen and then exposing to an atmosphere containing nitrogen radicals. 1. The semiconductor device according to 1.
[11] 前記酸素を少なくとも含む雰囲気での熱処理の際に、前記下地層の下部を酸化し てなることを特徴とする請求項 10記載の半導体装置。 11. The semiconductor device according to claim 10, wherein a lower portion of the base layer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
[12] 前記金属化合物の金属濃度 (金属原子数 Z (シリコン原子数 +金属原子数) )が 0[12] The metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.
. 3以上であることを特徴とする請求項 1記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor device is 3 or more.
[13] 前記熱処理後における、前記高誘電率ゲート酸ィ匕膜の酸ィ匕膜換算膜厚が、前記 高誘電率ゲート酸ィ匕膜を形成する際に用いた前記下地層よりも薄くなることを特徴と する請求項 1記載の半導体装置。 [13] After the heat treatment, the equivalent oxide film thickness of the high dielectric gate oxide film is thinner than the underlayer used when forming the high dielectric gate oxide film. The semiconductor device according to claim 1, wherein:
[14] 前記金属ィ匕合物は、 Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu 、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、 Luの少なくとも 1つの金属元素を含有することを 特徴とする請求項 1記載の半導体装置。 [14] The metal compound is Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm. 2. The semiconductor device according to claim 1, comprising at least one metal element of Y, Yb, and Lu.
[15] ゲート電極をシリコン基板力 電気的に絶縁するゲート絶縁膜を有する半導体装置 の製造方法であって、 [15] A method of manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a silicon substrate,
前記シリコン基板上にシリコンを含有する下地層を形成する工程と、  Forming a base layer containing silicon on the silicon substrate;
前記下地層上に金属拡散源として金属化合物を堆積する工程と、  Depositing a metal compound as a metal diffusion source on the underlayer;
前記下地層と、前記金属化合物と、に熱処理を施し、前記金属化合物の金属元素 を前記下地層に拡散させ、前記シリコン基板上に高誘電率のゲート絶縁膜を形成す る工程と、を行い、 The base layer and the metal compound are subjected to heat treatment, and the metal element of the metal compound is diffused into the base layer to form a high dielectric constant gate insulating film on the silicon substrate. And the process of
前記金属化合物中の金属原子量が、 1. 5E+ 15cm— 2力ら 2. 6E+ 15cm— 2の範囲 であることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device, wherein the metal atomic weight in the metal compound is in the range of 1.5E + 15 cm- 2 force and 2.6E + 15 cm- 2 .
[16] 前記金属拡散源として用いる前記金属化合物の膜厚 (nm)と、金属濃度 (金属原 子数 Z (シリコン原子数 +金属原子数)）と、の積により決定する前記金属化合物中 の金属量は、 0. 6以上 0. 9以下の範囲であることを特徴とする請求項 15記載の半導 体装置の製造方法。 [16] In the metal compound determined by the product of the film thickness (nm) of the metal compound used as the metal diffusion source and the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) 16. The method of manufacturing a semiconductor device according to claim 15, wherein the amount of metal is in the range of 0.6 or more and 0.9 or less.
[17] 前記下地層は、シリコン酸ィ匕物、または、シリコン酸窒化物からなることを特徴とする 請求項 15記載の半導体装置の製造方法。  17. The method for manufacturing a semiconductor device according to claim 15, wherein the underlayer is made of silicon oxide or silicon oxynitride.
[18] 前記熱処理は、 [18]
アンモニアまたは酸素を少なくとも含む雰囲気で行うことで、前記金属化合物の金 属元素が前記下地層に拡散した金属拡散膜を形成することを特徴とする請求項 15 記載の半導体装置の製造方法。  16. The method for manufacturing a semiconductor device according to claim 15, wherein a metal diffusion film in which a metal element of the metal compound is diffused in the base layer is formed by performing in an atmosphere containing at least ammonia or oxygen.
[19] 前記熱処理は、 [19]
不活性ガス中で行い、その後に、アンモニアまたは酸素を少なくとも含む雰囲気で 行うことで、前記金属化合物の金属元素が前記下地層に拡散した金属拡散膜を形 成することを特徴とする請求項 15記載の半導体装置の製造方法。  The metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed by performing in an inert gas and thereafter in an atmosphere containing at least ammonia or oxygen. The manufacturing method of the semiconductor device of description.
[20] 前記アンモニアまたは酸素を少なくとも含む雰囲気で行う熱処理は、 700°C以上 9[20] The heat treatment performed in an atmosphere containing at least ammonia or oxygen is at least 700 ° C. 9
50°C以下で行うことを特徴とする請求項 18または 19記載の半導体装置の製造方法 20. The method for manufacturing a semiconductor device according to claim 18, wherein the method is performed at 50 ° C. or lower.
[21] 前記熱処理は、 [21] The heat treatment includes
アンモニアを少なくとも含む雰囲気において、 750°C以上 900°C以下で行われ、前 記金属化合物中の金属原子量が、 2. 3E+ 15cm— 2力ら 2. 6E+ 15cm— 2の範囲であ ることを特徴とする請求項 15記載の半導体装置の製造方法。 In an atmosphere containing at least ammonia is carried out at below 750 ° C or higher 900 ° C, the metal atom amount before Symbol metal compound is, 2. 3E + 15cm- 2 Power et al 2. 6E + 15cm- 2 ranging der Rukoto the 16. The method for manufacturing a semiconductor device according to claim 15, wherein:
[22] 前記熱処理は、 [22] The heat treatment includes
アンモニアを少なくとも含む雰囲気において、 700°C以上 750°C未満で行われ、前 記金属化合物中の金属原子量が、 1. 5E+ 15cm— 2から 1. 7E+ 15cm 2の範囲であ ることを特徴とする請求項 15記載の半導体装置の製造方法。 In at least including ambient ammonia is carried out at less than 700 ° C above 750 ° C, the metal atom amount before Symbol metal compound is a feature ranges der Rukoto of 1. 7E + 15cm 2 from 1. 5E + 15cm- 2 The method of manufacturing a semiconductor device according to claim 15.
[23] 前記熱処理は、 [23] The heat treatment includes
不活性ガス中で行い、その後に、窒素ラジカルを含む雰囲気に暴露することで、前 記金属化合物の金属元素が前記下地層に拡散した金属拡散膜を形成することを特 徴とする請求項 15記載の半導体装置の製造方法。  The metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed by performing in an inert gas and then exposing to an atmosphere containing nitrogen radicals. The manufacturing method of the semiconductor device of description.
[24] 前記熱処理は、 [24]
酸素を少なくとも含む雰囲気で行い、その後に、窒素ラジカルを含む雰囲気に暴露 することで、前記金属化合物の金属元素が前記下地層に拡散した金属拡散膜を形 成することを特徴とする請求項 15記載の半導体装置の製造方法。  The metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed by performing in an atmosphere containing at least oxygen and then exposing to an atmosphere containing nitrogen radicals. The manufacturing method of the semiconductor device of description.
[25] 前記酸素を少なくとも含む雰囲気での熱処理の際に、前記下地層の下部を酸化す ることを特徴とする請求項 24記載の半導体装置の製造方法。 25. The method for manufacturing a semiconductor device according to claim 24, wherein a lower portion of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
[26] 前記金属化合物の金属濃度 (金属原子数 Z (シリコン原子数 +金属原子数) )は、[26] The metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is
0. 3以上であることを特徴とする請求項 15記載の半導体装置の製造方法。 16. The method for manufacturing a semiconductor device according to claim 15, wherein the number is 3 or more.
[27] 前記熱処理後における、前記高誘電率ゲート酸ィ匕膜の酸ィ匕膜換算膜厚が、前記 高誘電率のゲート酸ィ匕膜を形成する際に用いた前記下地層よりも薄くなることを特徴 とする請求項 15記載の半導体装置の製造方法。 [27] The oxide film equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment is thinner than that of the underlayer used when forming the high dielectric gate oxide film. 16. The method for manufacturing a semiconductor device according to claim 15, wherein:
[28] 前記金属ィ匕合物は、 Zr、 Hf、 Ta、 Al、 Ti、 Nb、 Sc、 Y、 La、 Ce、 Pr、 Nd、 Sm、 Eu[28] The metal compound is Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu.
、 Gd、 Tb、 Dy、 Ho、 Er、 Tm、 Yb、 Luの少なくとも 1つの金属元素を含有することを 特徴とする請求項 15記載の半導体装置の製造方法。 16. The method for manufacturing a semiconductor device according to claim 15, comprising at least one metal element of Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
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