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WO2005013352A2 - Method for the production of a semiconductor element with a plastic housing and support plate for carrying out said method - Google Patents

Method for the production of a semiconductor element with a plastic housing and support plate for carrying out said method Download PDF

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Publication number
WO2005013352A2
WO2005013352A2 PCT/DE2004/001667 DE2004001667W WO2005013352A2 WO 2005013352 A2 WO2005013352 A2 WO 2005013352A2 DE 2004001667 W DE2004001667 W DE 2004001667W WO 2005013352 A2 WO2005013352 A2 WO 2005013352A2
Authority
WO
WIPO (PCT)
Prior art keywords
carrier plate
adhesive
semiconductor chips
plastic housing
carrier
Prior art date
Application number
PCT/DE2004/001667
Other languages
German (de)
French (fr)
Other versions
WO2005013352A3 (en
Inventor
Edward FÜRGUT
Thomas Kalin
Carsten Von Koblinski
Holger Wörner
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2005013352A2 publication Critical patent/WO2005013352A2/en
Publication of WO2005013352A3 publication Critical patent/WO2005013352A3/en
Priority to US11/341,895 priority Critical patent/US7202107B2/en
Priority to US11/685,005 priority patent/US7622733B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0101—Neon [Ne]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01052—Tellurium [Te]
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    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/01068—Erbium [Er]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the invention relates to a method for producing a semiconductor component with a plastic housing. Furthermore, the invention relates to a carrier plate.
  • the invention relates in particular to methods for producing semiconductor components with plastic housings, which have the following steps: providing a semiconductor wafer with semiconductor chips arranged in rows and columns and having active top sides and rear sides, the active top sides being provided with contact areas; - Separating the semiconductor wafer into individual semiconductor chips; - equipping a mold plate with the semiconductor chips; - Manufacture of a common carrier made of plastic housing compound on the mold plate for the semiconductor chips; - Manufacture of rewiring lines, external contact areas and separation of the common carrier into individual semiconductor components.
  • Such a method is known for example from DE 101 37 184 AI.
  • the isolated semiconductor components are fitted with their active side onto an adhesive film, which in turn is stretched over a carrier frame.
  • This arrangement is then covered with a synthetic resin. envelops what can happen, for example, in the so-called wafer molding process in the print process or in similar known processes.
  • the plastic mass is then cured.
  • the film is then removed again and the matrix of semiconductor chips, which are now embedded in the common plastic carrier, is removed from the carrier frame.
  • the “reconstituted” semiconductor wafer produced in this way then serves as the starting material for the so-called rewiring processes.
  • the above-mentioned method has the basic advantages that very inexpensive materials and very efficient process steps are used.
  • the direct embedding or the direct encapsulation of the semiconductor chips with a plastic makes this technology known from the prior art very versatile. This means that a wide variety of semiconductor chip sizes can be processed and package sizes can be produced with this technology. Large wafer-shaped panels can be produced, which enable further processing with the conventional equipment.
  • a major disadvantage of this known method is that the positional accuracy of the semiconductor chips on the encapsulated wafer is restricted by the film material. This positional accuracy of the embedded semiconductor chips is negatively influenced by various effects.
  • the carrier film has only very limited dimensional stability. Through storage, handling or processing the carrier film is deformed. Such deformations are, for example, wrinkling or relaxation. These folds and relaxations in turn cause the individual semiconductor chips to shift on the film.
  • the encapsulation process as a rule wafers, is carried out at high temperatures, i. H. under temperatures up to 180 ° C, deformations also occur there. 'The deformations that occur there are usually even stronger than the deformations of the carrier film that result from the storage, handling and processing of the carrier film.
  • the plastic film usually becomes soft in the temperature ranges above 100 ° C to 180 ° C. This softening further reduces their stability.
  • this object is achieved by a method for producing a semiconductor component with a plastic housing, in which at least one semiconductor chip is arranged, with the following steps: providing a semiconductor wafer with semiconductor chips arranged in rows and columns, which have rear sides and active top sides, the active tops are provided with contact surfaces; - Separating the semiconductor wafer into individual semiconductor chips; - Providing a carrier plate which is provided on its top with a thermosensitive adhesive; - equipping this carrier plate with the individual semiconductor chips, the individual semiconductor chips with their active sides being brought onto the upper side of the carrier plate; - Manufacture of a common carrier made of plastic housing compound on the carrier plate, the semiconductor chips being embedded in the plastic housing compound; - Removing the carrier plate by heating the thermosensitive adhesive to a predetermined defined temperature at which the thermosensitive adhesive loses its adhesive effect.
  • thermosensitive adhesive By using a carrier plate made of a dimensionally stable material in the temperature range from 20 ° C to 200 ° C a low thermal expansion quotient, which is provided on the top with a thermosensitive adhesive, the major problems of the prior art mentioned at the outset, which are associated with the use of non-dimensionally stable films, can be completely avoided.
  • thermosensitive adhesives are understood to mean an adhesive that has a strongly adhesive, i.e. "adhesive", has an effect - for example, has an adhesive effect in the temperature range between 20 ° C and 90 ° C. Such an adhesive loses its adhesive effect above 90 ° C.
  • the adhesive can therefore be applied to an object at room temperature, for example.
  • the object provided with the adhesive is then processed. After the processing has been completed, the adhesive is removed by heating it to a temperature above 90 ° C. for several minutes, so that it loses its adhesive effect and can be easily removed from the processed object.
  • the carrier plate consists of a dimensionally stable material that has a thermal expansion coefficient ⁇ 10 • 10 _6 / K at room temperature, so that a thermal mismatch with the semiconductor chips lying on it is avoided.
  • materials which additionally 'a thermal conductivity ⁇ of> 100 W / mK at room temperature, since the carrier plate is used within a process in which high temperatures and high amounts of heat occur.
  • metals and their alloys, in particular KOVAR alloys are conceivable.
  • copper, copper beryllium can also be used or other materials known from leadframe technology.
  • suitable materials are the special ceramics from semiconductor technology, in particular aluminum nitride ceramics or aluminum oxide ceramics (corundum ceramics).
  • glass and silicon have proven to be particularly suitable as the material for the carrier plate. Both materials have an almost identical coefficient of thermal expansion of the enveloping semiconductor chips, so that when using these materials, thermomechanical mismatches and the associated "war pages" are the least likely to occur.
  • the carrier plate has a laminated adhesive film on its upper side, which is provided with a thermosensitive adhesive on its side facing away from the carrier plate and is provided with a permanent adhesive on its side facing the carrier plate.
  • the carrier plate also has a laminated adhesive film on its upper side.
  • the above-mentioned sides have been interchanged, ie the thermosensitive side of the adhesive film is on the carrier plate and the permanent adhesive is on the side facing away from the carrier plate.
  • this can have the advantage that when the thermosensitive adhesive is heated, the film adheres to the reconstituted wafer. There it can be peeled off or peeled off later. If there are residues of the thermosensitive adhesive the reconstituted wafer must not or should not occur, this is advantageous.
  • Adhesive films or adhesive tapes which have a thermosensitive adhesive on one side and a permanent adhesive on the other side are available, for example, from the Nitto company under the Revalpha brand.
  • the semiconductor chips are embedded in the plastic housing compound such that the rear sides of the individual semiconductor chips are completely covered with plastic housing compound.
  • a carrier plate 8 is first provided, which consists of a dimensionally stable material with a low coefficient of thermal expansion.
  • the carrier plate 8 shown consists of silicon. It is a relatively thick silicon wafer.
  • the carrier plate 8 shown is then provided with an adhesive film.
  • the carrier plate 8 is laminated on its top 9 with a double-sided adhesive film 12.
  • the adhesive film 12 has a thermosensitive adhesive 10 on its side facing away from the carrier plate 8. On the side of the adhesive film that faces the carrier plate 8, it has a permanent adhesive.
  • the carrier plate 8 laminated with the adhesive film 12 can be seen in FIG. 1b.
  • the laminated carrier plate 8 is then fitted with semiconductor chips 3.
  • semiconductor chips 3 This is preceded by the fact that a completely processed semiconductor wafer 4 is provided which has semiconductor chips 3 arranged in rows and columns.
  • the semiconductor chips 3 have active top sides 5 and back sides 6.
  • the active top sides 5 are provided with contact surfaces 7.
  • the semiconductor wafer 4 is then separated into individual semiconductor chips 3, for example by sawing.
  • the separated semiconductor chips 3, as can be seen in FIG. 1c, are then brought with their active upper sides 5 onto the thermosensitive side of the laminated adhesive film 12, so that they adhere there.
  • the semiconductor chips 3 are encased in a plastic housing compound, so that a common carrier 11 made of plastic housing compound is formed on the carrier plate 8, in which the semiconductor chips 3 are embedded. This can be seen in FIG. 1d.
  • the individual semiconductor chips 3 can be encased in the wafer molding, in the stencil printing process, in conventional potting processes, in in-on processes and in coating processes.
  • the carrier plate 8 is separated from the common carrier 11 made of plastic housing compound.
  • the carrier plate 8 is now heated to a fixed temperature, so that the side with the thermosensitive adhesive 10 of the laminated adhesive film 12 loses its adhesive effect and the common carrier 11 made of plastic housing compound can be detached from the carrier plate 8 without any great effort.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A method for the production of a semiconductor element with a plastic housing within which at least one semiconductor chip is arranged, is disclosed. The method comprises the following steps: preparation of a semiconductor wafer with semiconductor chips arranged in rows and columns which have active upper faces and back faces, whereby the active upper faces are provided with contact surfaces, separation of the semiconductor wafer into individual semiconductor chips, preparation of a support plate, provided on the upper face thereof with a thermosensitive adhesive, fitting the individual semiconductor chips on said support plate, whereby the individual semiconductor chips are placed with the active upper face thereof on the upper face of the support plate, production of a common support made from plastic housing mass on the support plate, said semiconductor chips being embedded in the plastic housing mass and removal of the support plate by heating the thermosensitive adhesive to a given defined temperature at which the thermosensitive adhesive loses the adhesive effect thereof.

Description

Beschreibungdescription
Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse und Trägerplatte zur Durchführung des Ver- fahrensMethod for producing a semiconductor component with a plastic housing and carrier plate for carrying out the method
Die Erfindung betrifft ein Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse. Des Weiteren betrifft die Erfindung eine Trägerplatte.The invention relates to a method for producing a semiconductor component with a plastic housing. Furthermore, the invention relates to a carrier plate.
Die Erfindung bezieht sich insbesondere auf Verfahren zum Herstellen von Halbleiterbauelementen mit Kunststoffgehäusen, die folgende Schritte aufweisen: - Bereitstellen eines Halbleiterwafers mit in Zeilen und Spalten angeordneten Halbleiterchips, die aktive Oberseiten und Rückseiten aufweisen, wobei die aktiven Oberseiten mit Kontaktflächen versehen sind; - Trennen des Halbleiterwafers in einzelne Halbleiterchips; - Bestücken einer Formplatte mit den Halbleiterchips; - Herstellen eines gemeinsamen Trägers aus Kunststoffgehäu- semasse auf der Formplatte für die Halbleiterchips; - Herstellen von Umverdrahtungsleitungen, Außenkontaktflä- chen sowie Trennen des gemeinsamen Trägers in einzelne Halbleiterbauelemente .The invention relates in particular to methods for producing semiconductor components with plastic housings, which have the following steps: providing a semiconductor wafer with semiconductor chips arranged in rows and columns and having active top sides and rear sides, the active top sides being provided with contact areas; - Separating the semiconductor wafer into individual semiconductor chips; - equipping a mold plate with the semiconductor chips; - Manufacture of a common carrier made of plastic housing compound on the mold plate for the semiconductor chips; - Manufacture of rewiring lines, external contact areas and separation of the common carrier into individual semiconductor components.
Ein solches Verfahren ist beispielsweise aus der DE 101 37 184 AI bekannt.Such a method is known for example from DE 101 37 184 AI.
Bei dem dort beschriebenen Verfahren werden die vereinzelten Halbleiterbauelemente mit ihrer aktiven Seite auf eine Klebefolie bestückt, die wiederum über einen Trägerrahmen gespannt ist. Diese Anordnung wird anschließend mit einem Kunstharz um- hüllt, was beispielsweise im so genannten Wafermoldverfahren im Printverfahren oder in ähnlichen bekannten Verfahren vonstatten gehen kann. Die Kunststoffmasse wird anschließend ausgehärtet.In the method described there, the isolated semiconductor components are fitted with their active side onto an adhesive film, which in turn is stretched over a carrier frame. This arrangement is then covered with a synthetic resin. envelops what can happen, for example, in the so-called wafer molding process in the print process or in similar known processes. The plastic mass is then cured.
Danach wird die Folie wieder abgezogen und die Matrix aus Halbleiterchips, die mittlerweile in den gemeinsamen Kunst- stoffträger eingebettet sind, wird vom Trägerrahmen entfernt.The film is then removed again and the matrix of semiconductor chips, which are now embedded in the common plastic carrier, is removed from the carrier frame.
Der so erzeugte "rekonstituierte" Halbleiterwafer dient dann als Ausgangsmaterial für die so genannten ümverdrahtungspro- zesse.The “reconstituted” semiconductor wafer produced in this way then serves as the starting material for the so-called rewiring processes.
Das oben genannte Verfahren hat die prinzipiellen Vorteile, dass sehr kostengünstige Materialien und sehr effiziente Prozessschritte verwendet werden. Die direkte Einbettung bzw. die direkte Umhüllung der Halbleiterchips mit einem Kunststoff macht diese aus dem Stand der Technik bekannte Technologie sehr vielseitig. Das heißt, es können mit dieser Technologie verschiedenste Halbleiterchipgrößen verarbeitet und Gehäusegrößen hergestellt werden. Es können große waferförmige Paneele erzeugt werden, die eine Weiterverarbeitung mit den herkömmlichen Ausrüstungen ermöglichen.The above-mentioned method has the basic advantages that very inexpensive materials and very efficient process steps are used. The direct embedding or the direct encapsulation of the semiconductor chips with a plastic makes this technology known from the prior art very versatile. This means that a wide variety of semiconductor chip sizes can be processed and package sizes can be produced with this technology. Large wafer-shaped panels can be produced, which enable further processing with the conventional equipment.
Ein großer Nachteil dieses bekannten Verfahrens ist jedoch, dass durch das Folienmaterial die Positionsgenauigkeit der Halbleiterchips auf dem umhüllten Wafer eingeschränkt wird. Diese Positionsgenauigkeit der eingebetteten Halbleiterchips wird durch verschiedene Effekte negativ beeinflusst.A major disadvantage of this known method, however, is that the positional accuracy of the semiconductor chips on the encapsulated wafer is restricted by the film material. This positional accuracy of the embedded semiconductor chips is negatively influenced by various effects.
Zum einen ist die Trägerfolie nur sehr eingeschränkt formstabil. Durch Lagerung, durch Handhabung bzw. durch Prozessierung der Trägerfolie kommt es bei dieser zu Verformungen. Solche Verformungen sind beispielsweise Faltenbildungen bzw. Relaxationen. Durch diese Faltenbildungen und Relaxationen kommt es wiederum zu Verschiebungen der einzelnen .Halbleiterchips auf der Folie.On the one hand, the carrier film has only very limited dimensional stability. Through storage, handling or processing the carrier film is deformed. Such deformations are, for example, wrinkling or relaxation. These folds and relaxations in turn cause the individual semiconductor chips to shift on the film.
Da der Umhüllprozess, in der Regel Wafer olden, unter hohen Temperaturen durchgeführt wird, d. h. unter Temperaturen bis zu 180 °C, treten auch dort Verformungen auf. 'Die dort auftre- tenden Verformungen sind in der Regel sogar stärker als die durch die Lagerung, die Handhabung und die Prozessierung der Trägerfolie entstehenden Verformungen der Trägerfolie. Die Kunststofffolie wird in den Temperaturbereichen oberhalb 100 °C bis 180 °C in der Regel weich. Durch dieses Erweichen wird ihre Stabilität weiter reduziert.Since the encapsulation process, as a rule wafers, is carried out at high temperatures, i. H. under temperatures up to 180 ° C, deformations also occur there. 'The deformations that occur there are usually even stronger than the deformations of the carrier film that result from the storage, handling and processing of the carrier film. The plastic film usually becomes soft in the temperature ranges above 100 ° C to 180 ° C. This softening further reduces their stability.
Ein gleichmäßiges Laminieren der Folie auf den Trägerrahmen ist nur schwer möglich. Eine inhomogene Spannung in der Folie führt zu unkontrollierbaren Verschiebungen der Halbleiter- chips.It is difficult to evenly laminate the film onto the carrier frame. An inhomogeneous tension in the film leads to uncontrollable displacements of the semiconductor chips.
Bislang gibt es für die Folien keinen geeigneten Ersatz, da wiederum die folientypischen Eigenschaften der Folien beim Trennen des Chipträgers vom Basisträger benötigt werden. Ei- genschaften die hier eine besondere Rolle spielen und nahezu unersetzlich sind, sind die einer. Folie inhärente Dela inier- fähigkeit. Eine Folie lässt sich im Gegensatz zu Festträgermaterialien abziehen bzw. abschälen.So far, there has been no suitable replacement for the foils, since the properties of the foils that are typical of the foils are required when the chip carrier is separated from the base carrier. Properties that play a special role here and are almost irreplaceable are one. Film inherent delinability. In contrast to solid support materials, a film can be peeled off or peeled off.
Würde man einen festen, stabileren Träger als Folienersatz ■ verwenden, so wäre das vollflächige Trennen der beiden Träger nach dem Umhüllprozess aufgrund der zu hohen Haftkraft und der großen Flächen nur sehr schwer möglich.If you were to use a firm, more stable support as a film replacement, ■ the full-surface separation of the two supports would be after the wrapping process due to the high adhesive force and the large areas very difficult.
Es besteht demnach ein Bedürfnis, ein neues Herstellverfahren bereitzustellen und ein neues Trägermittel, das die Nachteile der eingesetzten Folien vermeidet.Accordingly, there is a need to provide a new manufacturing process and a new carrier that avoids the disadvantages of the films used.
Erfindungsgemäß wird diese Aufgabe durch ein Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffge- häuse, in dem zumindest ein Halbleiterchip angeordnet ist mit folgenden Schritten gelöst: - Bereitstellen eines Halbleiterwafers mit in Zeilen und Spalten angeordneten Halbleiterchips, die Rückseiten und aktive Oberseiten aufweisen, wobei die aktiven Oberseiten mit Kontaktflächen versehen sind; - Trennen des Halbleiterwafers in einzelne Halbleiterchips; - Bereitstellen einer Trägerplatte, die auf ihrer Oberseite mit einem thermosensitiven Klebstoff versehen ist; - Bestücken dieser Trägerplatte mit den einzelnen Halblei- terchips, wobei die einzelnen Halbleiterchips mit ihren aktiven Seiten auf die Oberseite der Trägerplatte gebracht werden; - Herstellen eines gemeinsamen Trägers aus Kunststoffgehäusemasse auf der Trägerplatte, wobei die Halbleiterchips in die Kunststoffgehäusemasse eingebettet werden; - Entfernen der Trägerplatte durch Erwärmen des thermosensitiven Klebstoffs auf eine vorbestimmte definierte Temperatur, bei der das thermosensitive Klebstoff seine haftende Wirkung verliert.According to the invention, this object is achieved by a method for producing a semiconductor component with a plastic housing, in which at least one semiconductor chip is arranged, with the following steps: providing a semiconductor wafer with semiconductor chips arranged in rows and columns, which have rear sides and active top sides, the active tops are provided with contact surfaces; - Separating the semiconductor wafer into individual semiconductor chips; - Providing a carrier plate which is provided on its top with a thermosensitive adhesive; - equipping this carrier plate with the individual semiconductor chips, the individual semiconductor chips with their active sides being brought onto the upper side of the carrier plate; - Manufacture of a common carrier made of plastic housing compound on the carrier plate, the semiconductor chips being embedded in the plastic housing compound; - Removing the carrier plate by heating the thermosensitive adhesive to a predetermined defined temperature at which the thermosensitive adhesive loses its adhesive effect.
Durch die Verwendung einer Trägerplatte, die aus einem im Temperaturbereich von 20 °C bis 200 °C formstabilen Material mit einem niedrigen thermischen Ausdehnungsquotienten besteht, welche auf ihrer Oberseite mit einem thermosensitiven Klebstoff versehen ist, lassen sich die eingangs erwähnten großen Probleme aus dem Stand der Technik, die mit der Verwendung von nichtformstabilen Folien einhergehen, vollständig vermeiden.By using a carrier plate made of a dimensionally stable material in the temperature range from 20 ° C to 200 ° C a low thermal expansion quotient, which is provided on the top with a thermosensitive adhesive, the major problems of the prior art mentioned at the outset, which are associated with the use of non-dimensionally stable films, can be completely avoided.
Unter thermosensitiven Klebstoffen wird hier und im folgenden ein Klebstoff verstanden, der in einem definierten Temperaturbereich eine stark haftende, d.h. "klebende", Wirkung aufweist - beispielsweise eine klebende Wirkung im Temperaturbereich zwischen 20 °C und 90 °C aufweist. Oberhalb 90 °C verliert ein solcher Klebstoff seine haftende Wirkung. Der Klebstoff kann demnach beispielsweise bei Raumtemperatur auf einen Gegenstand aufgebracht werden. Der mit dem Klebstoff versehene Gegenstand wird dann prozessiert. Nach Fertigstellung der Prozessierung wird der Klebstoff abgelöst, in dem er auf eine Temperatur o- berhalb 90 °C für mehrere Minuten erhitzt wird, so dass er seine klebende Wirkung verliert und problemlos von dem prozessierten Gegenstand abgelöst werden kann.Here and below, thermosensitive adhesives are understood to mean an adhesive that has a strongly adhesive, i.e. "adhesive", has an effect - for example, has an adhesive effect in the temperature range between 20 ° C and 90 ° C. Such an adhesive loses its adhesive effect above 90 ° C. The adhesive can therefore be applied to an object at room temperature, for example. The object provided with the adhesive is then processed. After the processing has been completed, the adhesive is removed by heating it to a temperature above 90 ° C. for several minutes, so that it loses its adhesive effect and can be easily removed from the processed object.
In einer typischen Ausgestaltung der vorliegenden Erfindung besteht die Trägerplatte aus einem formstabilen Material, dass einen thermischen Ausdehnungskoeffizienten < 10 • 10_6/K bei Raumtemperatur aufweist, so daß ein thermischer Mismatch mit den aufliegenden Halbleiterchips vermieden wird.In a typical embodiment of the present invention, the carrier plate consists of a dimensionally stable material that has a thermal expansion coefficient <10 • 10 _6 / K at room temperature, so that a thermal mismatch with the semiconductor chips lying on it is avoided.
Bevorzugt sind Materialien, die zusätzlich ' eine Wärmeleitfähigkeit σ > 100 W/mK bei Raumtemperatur aufweisen, da die Trägerplatte innerhalb eines Verfahrens eingesetzt wird, bei dem hohe Temperaturen und hohe Wärmemengen auftreten. Denkbar sind beispielsweise Metalle und deren Legierungen, insbesondere KO- VAR-Legierungen. Es können jedoch auch Kupfer, Kupferberyllium bzw. andere aus der Leadframe-Technologie bekannte Werkstoffe genommen werden.Preferred are materials, which additionally 'a thermal conductivity σ of> 100 W / mK at room temperature, since the carrier plate is used within a process in which high temperatures and high amounts of heat occur. For example, metals and their alloys, in particular KOVAR alloys, are conceivable. However, copper, copper beryllium can also be used or other materials known from leadframe technology.
Eine andere Gruppe von geeigneten Materialien stellen die Spe- zialkeramiken aus der Halbleitertechnologie dar, insbesondere Aluminiumnitrid-Keramiken bzw. Aluminiumoxid-Keramiken (Korund-Keramiken) . Als besonders geeignet haben sich in ersten Versuchen Glas und Silizium als Material für die Trägerplatte erwiesen. Beide Materialien weisen einen nahezu identischen thermischen Ausdehnungskoeffizienten der umhüllenden Halbleiterchips auf, so dass es bei der Verwendung dieser Materialien am wenigsten zu thermomechanischen Mismatches und den damit einhergehenden "Warpages" kommen kann.Another group of suitable materials are the special ceramics from semiconductor technology, in particular aluminum nitride ceramics or aluminum oxide ceramics (corundum ceramics). In the first attempts, glass and silicon have proven to be particularly suitable as the material for the carrier plate. Both materials have an almost identical coefficient of thermal expansion of the enveloping semiconductor chips, so that when using these materials, thermomechanical mismatches and the associated "war pages" are the least likely to occur.
In einer typischen Ausführungsform der vorliegenden Erfindung weist die Trägerplatte auf ihrer Oberseite eine auflaminierte Klebefolie auf, die auf ihrer der Trägerplatte abgewandten Seite mit einem thermosensitiven Klebstoff versehen ist und auf ihrer der Trägerplatte zugewandten Seite mit einem dauer- haftenden Klebstoff versehen ist.In a typical embodiment of the present invention, the carrier plate has a laminated adhesive film on its upper side, which is provided with a thermosensitive adhesive on its side facing away from the carrier plate and is provided with a permanent adhesive on its side facing the carrier plate.
In einer anderen Ausführungsform der vorliegenden Erfindung weist die Trägerplatte auf ihrer Oberseite ebenfalls eine auflaminierte Klebefolie auf. In dieser Ausführungsform sind je- doch die oben genannten Seiten vertauscht, d. h. die thermosensitive Seite der Klebefolie befindet sich auf der Trägerplatte und auf der Seite, die der Trägerplatte abgewandt ist, befindet sich der dauerhaftende Klebstoff. Dies kann unter Umständen den Vorteil bringen, dass beim Erwärmen des thermosen- sitiven Klebstoffes die Folie am rekonstituierten Wafer haften bleibt. Dort kann sie später separat abgeschält bzw. abgezogen werden. Sofern Rückstände des thermosensitiven Klebers auf dem rekonstituierten Wafer nicht anfallen dürfen oder sollen, ist dies vorteilhaft.In another embodiment of the present invention, the carrier plate also has a laminated adhesive film on its upper side. In this embodiment, however, the above-mentioned sides have been interchanged, ie the thermosensitive side of the adhesive film is on the carrier plate and the permanent adhesive is on the side facing away from the carrier plate. Under certain circumstances, this can have the advantage that when the thermosensitive adhesive is heated, the film adheres to the reconstituted wafer. There it can be peeled off or peeled off later. If there are residues of the thermosensitive adhesive the reconstituted wafer must not or should not occur, this is advantageous.
Klebefolien bzw. Klebebänder, die auf einer Seite einen thermosensitiven Klebstoff aufweisen und auf der anderen Seite einen dauerhaftenden Klebstoff aufweisen, sind beispielsweise unter der Marke Revalpha von der Firma Nitto erhältlich. Die dort erhältlichen Klebefolien bzw. Klebebänder sind bis zu Temperaturen von 180 °C einsetzbar.Adhesive films or adhesive tapes which have a thermosensitive adhesive on one side and a permanent adhesive on the other side are available, for example, from the Nitto company under the Revalpha brand. The adhesive films and tapes available there can be used up to temperatures of 180 ° C.
In einer typischen Ausführungsform des erfindungsgemäßen Verfahrens, werden die Halbleiterchips derart in die Kunststoff- gehäusemasse eingebettet, dass die Rückseiten der einzelnen Halbleiterchips vollständig mit Kunststoffgehäusemasse bedeckt sind.In a typical embodiment of the method according to the invention, the semiconductor chips are embedded in the plastic housing compound such that the rear sides of the individual semiconductor chips are completely covered with plastic housing compound.
Es ist jedoch auch denkbar, das Verfahren so auszugestalten, dass die Rückseiten der einzelnen Halbleiterchips nicht mit Kunststoffgehäusemasse bedeckt sind. Dies birgt den Vorteil, die Halbleiterchips nach dem ersten Umhüllungsschritt mitHowever, it is also conceivable to design the method in such a way that the rear sides of the individual semiconductor chips are not covered with plastic housing compound. This has the advantage that the semiconductor chips are included after the first encapsulation step
Kühlkörpern auf den Rückseiten zu versehen und danach das Umhüllen zu vollenden.To provide heat sinks on the backs and then complete the wrapping.
Typischerweise werden nach dem Ablösen der Trägerplatte durch Erwärmen des thermosensitiven Klebstoffs weitere Verfahrensschritte durchgeführt. Es werden zum einen Umverdrahtungslei- tungen auf der Oberseite des gemeinsamen Trägers erzeugt. Des Weiteren werden Außenkontaktflachen ausgebildet. Danach werden Lotbälle oder Lothöcker auf die Außenkontaktflächen aufge- bracht. Schließlich wird der gemeinsame Kunststoffträger in einzelne Halbleiterbauelemente getrennt. Die Erfindung wird nun anhand von einem Ausführungsbeispiel mit Bezug auf die beiliegenden Zeichnungen näher erläutert. Die Figuren la bis lf zeigen seitliche Querschnittansichten von einem Verfahrensablauf zur Ausbildung eines Halbleiterbau- elements 1 mit einem Kunststoffgehäuse 2 nach der vorliegenden Erfindung.After the carrier plate has been detached, further process steps are typically carried out by heating the thermosensitive adhesive. On the one hand, rewiring lines are generated on the top of the common carrier. External contact surfaces are also formed. Then solder balls or solder bumps are applied to the external contact areas. Finally, the common plastic carrier is separated into individual semiconductor components. The invention will now be explained in more detail using an exemplary embodiment with reference to the accompanying drawings. Figures la to lf show lateral cross-sectional views of a process sequence for forming a semiconductor component 1 with a plastic housing 2 according to the present invention.
Wie der Figur la zu entnehmen ist, wird zunächst eine Trägerplatte 8 bereitgestellt, die aus einem formstabilen Material mit einem niedrigen thermischen Ausdehnungskoeffizienten besteht. Die gezeigte Trägerplatte 8 besteht aus Silizium. Es handelt sich dabei um einen relativ dicken Siliziumwafer.As can be seen from FIG. 1 a, a carrier plate 8 is first provided, which consists of a dimensionally stable material with a low coefficient of thermal expansion. The carrier plate 8 shown consists of silicon. It is a relatively thick silicon wafer.
Die gezeigte Trägerplatte 8 wird dann mit einer Klebefolie versehen. Die Trägerplatte 8 wird dabei auf ihrer Oberseite 9 mit einer doppelseitigen Klebefolie 12 laminiert. Die Klebefolie 12 weist auf ihrer der Trägerplatte 8 abgewandten Seite einen thermosensitiven Klebstoff 10 auf. Auf der Seite der Klebefolie, die der Trägerplatte 8 zugewandt ist, weist sie einen dauerhaftenden Klebstoff auf. Die mit der Klebefolie 12 laminierte Trägerplatte 8 ist der Figur lb zu entnehmen.The carrier plate 8 shown is then provided with an adhesive film. The carrier plate 8 is laminated on its top 9 with a double-sided adhesive film 12. The adhesive film 12 has a thermosensitive adhesive 10 on its side facing away from the carrier plate 8. On the side of the adhesive film that faces the carrier plate 8, it has a permanent adhesive. The carrier plate 8 laminated with the adhesive film 12 can be seen in FIG. 1b.
Aus der Figur 1c ist zu entnehmen, dass anschließend die laminierte Trägerplatte 8 mit Halbleiterchips 3 bestückt wird. Dem geht voraus, dass ein fertig prozessierter Halbleiterwafer 4 bereitgestellt wird, der in Zeilen und Spalten angeordnete Halbleiterchips 3 aufweist. Die Halbleiterchips 3 weisen aktive Oberseiten 5 und Rückseiten 6 auf. Wobei die aktiven Oberseiten 5 mit Kontaktflächen 7 versehen sind.It can be seen from FIG. 1c that the laminated carrier plate 8 is then fitted with semiconductor chips 3. This is preceded by the fact that a completely processed semiconductor wafer 4 is provided which has semiconductor chips 3 arranged in rows and columns. The semiconductor chips 3 have active top sides 5 and back sides 6. The active top sides 5 are provided with contact surfaces 7.
Der Halbleiterwafer 4 wird anschließend in einzelne Halbleiterchips 3 getrennt, beispielsweise durch Sägen. Die vereinzelten Halbleiterchips 3 werden dann, wie in der Figur lc zu sehen ist, mit ihren aktiven Oberseiten 5 auf die thermosensitive Seite der auflaminierten Klebefolie 12 ge- bracht, so dass sie dort haften.The semiconductor wafer 4 is then separated into individual semiconductor chips 3, for example by sawing. The separated semiconductor chips 3, as can be seen in FIG. 1c, are then brought with their active upper sides 5 onto the thermosensitive side of the laminated adhesive film 12, so that they adhere there.
Danach werden die Halbleiterchips 3 mit einer Kunststoffgehäusemasse umhüllt, so dass ein gemeinsamer Träger 11 aus Kunst- stoffgehäusemasse auf der Trägerplatte 8 ausgebildet wird, in den die Halbleiterchips 3 eingebettet sind. Dies ist der Figur ld zu entnehmen. Das Umhüllen der einzelnen Halbleiterchips 3 kann dabei im Wafermolding, im Schablonendruckverfahren, in herkömmlichen Vergussverfahren, in In-On-Verfahren sowie in Coating-Verfahren erfolgen.Thereafter, the semiconductor chips 3 are encased in a plastic housing compound, so that a common carrier 11 made of plastic housing compound is formed on the carrier plate 8, in which the semiconductor chips 3 are embedded. This can be seen in FIG. 1d. The individual semiconductor chips 3 can be encased in the wafer molding, in the stencil printing process, in conventional potting processes, in in-on processes and in coating processes.
Als weiterer Schritt findet dann, was der Figur le zu entnehmen ist, das Abtrennen der Trägerplatte 8 von dem gemeinsamen Träger 11 aus Kunststoffgehäusemasse statt. Dabei wird nun die Trägerplatte 8 auf eine fest definierte Temperatur erwärmt, so dass die Seite mit dem thermosensitiven Klebstoff 10 der auflaminierten Klebefolie 12 ihre haftende Wirkung verliert und der gemeinsame Träger 11 aus Kunststoffgehäusemasse sich problemlos ohne größeren Kraftaufwand von der Trägerplatte 8 lösen lässt .As a further step, as can be seen from FIG. 1e, the carrier plate 8 is separated from the common carrier 11 made of plastic housing compound. The carrier plate 8 is now heated to a fixed temperature, so that the side with the thermosensitive adhesive 10 of the laminated adhesive film 12 loses its adhesive effect and the common carrier 11 made of plastic housing compound can be detached from the carrier plate 8 without any great effort.
Als weitere Schritte schließen sich dann, was der Figur lf zu entnehmen ist, die Ausbildung von Umverdrahtungsmetallisierun- gen 13, von Außenkontaktflachen (nicht gezeigt) sowie das Aufbringen von Lotbällen oder Lothöckern (nicht gezeigt) statt . Letztendlich werden die einzelnen Halbleiterbauelemente 1 aus dem gemeinsamen Träger 11 getrennt. As further steps, as can be seen from FIG. 1f, the formation of rewiring metallizations 13, of external contact areas (not shown) and the application of solder balls or solder bumps (not shown) then take place. Ultimately, the individual semiconductor components 1 are separated from the common carrier 11.

Claims

Patentansprüche claims
1. Verfahren zum Herstellen eines Halbleiterbauelements (1) mit einem Kunststoffgehäuse (2), in dem zumindest ein Halbleiterchip (3) angeordnet ist mit folgenden Schritten: Bereitstellen eines Halbleiterwafers (4) mit in Zeilen und Spalten angeordneten Halbleiterchips (3) , die aktive Oberseiten (5) und Rückseiten (6) aufweisen, wobei die aktiven Oberseiten (5) mit Kontaktflächen (7) ver- sehen sind; Trennen des Halbleiterwafers (4) in einzelne Halbleiterchips (3) ; "- Bereitstellen einer Trägerplatte (8), die auf ihrer 0- berseite (9) mit einem thermosensitiven Klebstoff (10) versehen ist; Bestücken dieser Trägerplatte (8) mit den einzelnen Halbleiterchips (3), wobei die einzelnen Halbleiterchips (3) mit ihren aktiven Seiten (5) auf die Oberseite der Trägerplatte gebracht werden; - Herstellen eines gemeinsamen Trägers (11) aus Kunststoffgehäusemasse auf der Trägerplatte (8), wobei die Halbleiterchips (3) in die Kunststoffgehäusemasse eingebettet werden; Entfernen der Trägerplatte (8) durch Erwärmen des ther- osensitiven Klebstoffs (10) auf eine vorbestimmte definierte Temperatur, bei der das thermosensitive Klebstoff (10) seine klebende Wirkung verliert.1. A method for producing a semiconductor component (1) with a plastic housing (2), in which at least one semiconductor chip (3) is arranged, with the following steps: providing a semiconductor wafer (4) with semiconductor chips (3) arranged in rows and columns that are active Have top sides (5) and back sides (6), the active top sides (5) being provided with contact surfaces (7); Separating the semiconductor wafer (4) into individual semiconductor chips (3); " - Provide a carrier plate (8) which is provided on its 0- top side (9) with a thermosensitive adhesive (10); equip this carrier plate (8) with the individual semiconductor chips (3), the individual semiconductor chips (3) with their active sides (5) are brought to the top of the carrier plate; - producing a common carrier (11) from plastic housing compound on the carrier plate (8), the semiconductor chips (3) being embedded in the plastic housing compound; removing the carrier plate (8) by Heating the thermosensitive adhesive (10) to a predetermined, defined temperature at which the thermosensitive adhesive (10) loses its adhesive effect.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Halbleiterchips (3) derart in die Kunststoffgehäusemasse eingebaut werden, dass die Rückseiten (6) der ein- zelnen Halbleiterchips (3) vollständig mit Kunststoffgehäusemasse bedeckt sind.2. The method according to claim 1, characterized in that the semiconductor chips (3) are installed in the plastic housing compound such that the rear sides (6) of the one individual semiconductor chips (3) are completely covered with plastic housing compound.
3. Verfahren nach Anspruch 1 oder 2 mit folgenden weiteren Schritten: Erzeugen von U verdrahtungsleitungen auf der Oberseite des gemeinsamen Trägers; Ausbilden von Außenkontaktflachen; Aufbringen von Lotbällen oder Lothöckern auf die Außen- kontaktflächen; Trennen des gemeinsamen Trägers in einzelne Halbleiterbauelemente .3. The method according to claim 1 or 2 with the following further steps: generating U wiring lines on the top of the common carrier; Forming external contact surfaces; Applying solder balls or solder bumps to the external contact surfaces; Separation of the common carrier into individual semiconductor components.
4. Verfahren nach einem der Ansprüche 1 bis 3, wobei die Trä- gerplatte (8) auf ihrer Oberseite (9) mit einer Klebefolie (12) laminiert ist, die auf ihrer der Trägerplatte abgewandten Seite mit einem thermosensitiven Klebstoff (10) versehen ist und auf ihrer der Trägerplatte zugewandten Seite mit einem dauerhaftenden Klebstoff versehen ist.4. The method according to any one of claims 1 to 3, wherein the carrier plate (8) on its upper side (9) is laminated with an adhesive film (12) which is provided on its side facing away from the carrier plate with a thermosensitive adhesive (10) and is provided on its side facing the carrier plate with a permanent adhesive.
5. Verfahren nach einem der Ansprüche 1 bis 3, wobei die Trägerplatte auf ihrer Oberseite mit einer Klebefolie laminiert ist, wie auf ihrer der Trägerplatte abgewandten Seite mit einem dauerhaftenden Klebstoff versehen ist und auf ihrer der Trägerplatte zugewandten Seite mit einem thermosensitiven Klebstoff versehen ist.5. The method according to any one of claims 1 to 3, wherein the carrier plate is laminated on its top with an adhesive film, as is provided on its side facing away from the carrier plate with a permanent adhesive and is provided on its side facing the carrier plate with a thermosensitive adhesive.
6. Verfahren nach einem der Ansprüche 1 bis 3, wobei die Trägerplatte (8) auf ihrer Oberseite (9) direkt mit einem thermosensitiven Klebstoff (10) versehen ist. 6. The method according to any one of claims 1 to 3, wherein the carrier plate (8) on its upper side (9) is provided directly with a thermosensitive adhesive (10).
7. Verfahren nach einem der Ansprüche 1 bis 6, wobei eine metallische Trägerplatte bereitgestellt wird.7. The method according to any one of claims 1 to 6, wherein a metallic carrier plate is provided.
8. Verfahren nach einem der Ansprüche 1 bis 6, wobei eine ke- ramische Trägerplatte bereitgestellt wird.8. The method according to any one of claims 1 to 6, wherein a ceramic carrier plate is provided.
9. Verfahren nach einem der Ansprüche 1 bis 6, wobei eine Trägerplatte aus Glas oder Silizium bereitgestellt wird.9. The method according to any one of claims 1 to 6, wherein a carrier plate made of glass or silicon is provided.
10. Trägerplatte zur Durchführung eines Verfahren nach einem der Ansprüche 1 bis 3 bestehend aus einem im Temperaturbereich von 20 °C bis 200 °C formstabilem Material mit einem niedrigen thermischen Ausdehnungskoeffizienten, welche auf ihrer Oberseite mit einem thermosensitiven Klebstoff ver- sehen ist.10. Carrier plate for carrying out a method according to one of claims 1 to 3 consisting of a dimensionally stable material in the temperature range from 20 ° C to 200 ° C with a low thermal expansion coefficient, which is provided on its top with a thermosensitive adhesive.
11. Trägerplatte nach Anspruch 10, dadurch gekennzeichnet, dass das formstabile Material einen thermischen Ausdehnungskoeffizienten < 10 • 10~6/K bei Raumtemperatur auf- weist.11. Carrier plate according to claim 10, characterized in that the dimensionally stable material has a thermal expansion coefficient <10 • 10 ~ 6 / K at room temperature.
12. Trägerplatte nach Anspruch 10 oder 11, dadurch gekennzeichnet, dass das formstabile Material eine Wärmeleitfähigkeit σ > 100 W/mK bei Raumtemperatur aufweist.12. Carrier plate according to claim 10 or 11, characterized in that the dimensionally stable material has a thermal conductivity σ> 100 W / mK at room temperature.
13. Trägerplatte nach einem der Ansprüche 10 bis 12, dadurch gekennzeichnet, dass die Trägerplatte (8) auf ihrer Oberseite (9) mit einer Klebefolie (12) laminiert ist, die auf ihrer der Trägerplatte (8) abgewandten Seite mit einem thermosensitiven Klebstoff versehen ist und auf ihrer der Trägerplatte zugewandten Seite mit einem dauerhaftenden Klebstoff versehen ist. 13. Carrier plate according to one of claims 10 to 12, characterized in that the carrier plate (8) on its upper side (9) is laminated with an adhesive film (12) which on its side facing away from the carrier plate (8) is provided with a thermosensitive adhesive is and is provided on its side facing the carrier plate with a permanent adhesive.
14. Trägerplatte nach einem der Ansprüche 10 bis 12, dadurch gekennzeichnet, dass die Trägerplatte auf ihrer Oberseite mit einer Klebefolie laminiert ist, die auf ihrer der Trä- gerplatte abgewandten Seite mit einem dauerhaftenden Klebstoff versehen ist und auf ihrer der Trägerplatte zugewandten Seite mit einem thermosensitiven Klebstoff versehen ist.14. Carrier plate according to one of claims 10 to 12, characterized in that the carrier plate is laminated on its upper side with an adhesive film which is provided on its side facing away from the carrier plate with a permanent adhesive and on its side facing the carrier plate with a thermosensitive adhesive is provided.
15. Trägerplatte nach einem der Ansprüche 10 bis 12, dadurch gekennzeichnet, dass die Trägerplatte auf ihrer Oberseite direkt mit einem thermosensitiven Klebstoff versehen ist.15. Carrier plate according to one of claims 10 to 12, characterized in that the carrier plate is provided on its upper side directly with a thermosensitive adhesive.
16. Trägerplatte nach einem der Ansprüche 10 bis 15, dadurch gekennzeichnet, dass als formstabiles Material eine Keramik vorgesehen ist.16. Support plate according to one of claims 10 to 15, characterized in that a ceramic is provided as the dimensionally stable material.
17. Trägerplatte nach einem der Ansprüche 10 bis 15, dadurch gekennzeichnet, dass als formstabiles Material ein Metall oder eine Legierung vorgesehen ist.17. Support plate according to one of claims 10 to 15, characterized in that a metal or an alloy is provided as the dimensionally stable material.
18. Trägerplatte nach einem der Ansprüche 10 bis 15, dadurch gekennzeichnet, dass als formstabiles Material Glas oder Silizium vorgesehen ist. 18. Support plate according to one of claims 10 to 15, characterized in that glass or silicon is provided as the dimensionally stable material.
PCT/DE2004/001667 2003-07-28 2004-07-27 Method for the production of a semiconductor element with a plastic housing and support plate for carrying out said method WO2005013352A2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585701B2 (en) 2005-05-24 2009-09-08 Infineon Technologies Ag Carrier sheet with adhesive film and method for producing semiconductor devices using the carrier sheet with adhesive film

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US8268449B2 (en) 2006-02-06 2012-09-18 Brewer Science Inc. Thermal- and chemical-resistant acid protection coating material and spin-on thermoplastic adhesive
US8561371B2 (en) 2006-03-14 2013-10-22 Mute Wall Systems, Inc. Barrier wall and method of forming wall panels between vertical wall stiffeners with support members extending partially through the wall panels
FI20060256L (en) * 2006-03-17 2006-03-20 Imbera Electronics Oy Circuit board manufacturing and the circuit board containing the component
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
DE102006027283A1 (en) * 2006-06-09 2007-12-13 Infineon Technologies Ag Semiconductor component producing method, involves applying wiring structure with conductive strips and contact connection surfaces on upper side of carrier wafer, and applying semiconductor chips on upper side of carrier wafer
DE102006030581B3 (en) * 2006-07-03 2008-02-21 Infineon Technologies Ag Method for producing a component
US7713835B2 (en) * 2006-10-06 2010-05-11 Brewer Science Inc. Thermally decomposable spin-on bonding compositions for temporary wafer bonding
US20080200011A1 (en) * 2006-10-06 2008-08-21 Pillalamarri Sunil K High-temperature, spin-on, bonding compositions for temporary wafer bonding using sliding approach
FR2917234B1 (en) * 2007-06-07 2009-11-06 Commissariat Energie Atomique MULTI-COMPONENT DEVICE INTEGRATED IN A SEMICONDUCTOR MATRIX
JP5788173B2 (en) * 2007-06-25 2015-09-30 ブルーワー サイエンス アイ エヌシー． High temperature spin-on temporary bonding composition
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
US8102045B2 (en) * 2007-08-08 2012-01-24 Infineon Technologies Ag Integrated circuit with galvanically bonded heat sink
US8258624B2 (en) 2007-08-10 2012-09-04 Intel Mobile Communications GmbH Method for fabricating a semiconductor and semiconductor package
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI364801B (en) * 2007-12-20 2012-05-21 Chipmos Technologies Inc Dice rearrangement package structure using layout process to form a compliant configuration
PT2238618E (en) * 2008-01-24 2015-09-03 Brewer Science Inc Method for reversibly mounting a device wafer to a carrier substrate
US8030770B1 (en) 2008-09-09 2011-10-04 Triquint Semiconductor, Inc. Substrateless package
US8487435B2 (en) 2008-09-09 2013-07-16 Triquint Semiconductor, Inc. Sheet-molded chip-scale package
US8092628B2 (en) * 2008-10-31 2012-01-10 Brewer Science Inc. Cyclic olefin compositions for temporary wafer bonding
KR101015651B1 (en) * 2008-12-05 2011-02-22 삼성전기주식회사 Chip embedded printed circuit board and manufacturing method thereof
JP5188426B2 (en) * 2009-03-13 2013-04-24 新光電気工業株式会社 Semiconductor device, manufacturing method thereof, and electronic device
US8771927B2 (en) * 2009-04-15 2014-07-08 Brewer Science Inc. Acid-etch resistant, protective coatings
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
TWI456715B (en) 2009-06-19 2014-10-11 Advanced Semiconductor Eng Chip package structure and manufacturing method thereof
FR2947948B1 (en) * 2009-07-09 2012-03-09 Commissariat Energie Atomique HANDLE PLATE HAVING VISUALIZATION WINDOWS
TWI466259B (en) 2009-07-21 2014-12-21 Advanced Semiconductor Eng Semiconductor package, manufacturing method thereof and manufacturing method for chip-redistribution encapsulant
TWI405306B (en) 2009-07-23 2013-08-11 Advanced Semiconductor Eng Semiconductor package, manufacturing method thereof and chip-redistribution encapsulant
JP5296636B2 (en) * 2009-08-21 2013-09-25 新光電気工業株式会社 Manufacturing method of semiconductor package
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
KR101739606B1 (en) * 2009-11-17 2017-05-24 에바텍 어드벤스드 테크놀로지스 아크티엔게젤샤프트 Apparatus and method for processing a substrate
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
JP5042297B2 (en) * 2009-12-10 2012-10-03 日東電工株式会社 Manufacturing method of semiconductor device
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8409926B2 (en) * 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
TWI411075B (en) 2010-03-22 2013-10-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8852391B2 (en) 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US8337657B1 (en) 2010-10-27 2012-12-25 Amkor Technology, Inc. Mechanical tape separation package and method
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8680683B1 (en) 2010-11-30 2014-03-25 Triquint Semiconductor, Inc. Wafer level package with embedded passive components and method of manufacturing
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
TWI426584B (en) * 2010-12-22 2014-02-11 矽品精密工業股份有限公司 Semiconductor package and method of forming same
US10204879B2 (en) 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
US8492203B2 (en) 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
JP2013074184A (en) 2011-09-28 2013-04-22 Nitto Denko Corp Semiconductor device manufacturing method
US8980696B2 (en) 2011-11-09 2015-03-17 Freescale Semiconductor, Inc. Method of packaging semiconductor die
JP5729290B2 (en) 2011-12-16 2015-06-03 富士通株式会社 Semiconductor device manufacturing method, electronic device manufacturing method, and substrate
US8815651B2 (en) 2011-12-30 2014-08-26 Infineon Technologies Ag Method for manufacturing an electronic device by reducing thickness of electronic members attached to a carrier
TWI446501B (en) 2012-01-20 2014-07-21 矽品精密工業股份有限公司 Carrier board, semiconductor package and method of forming same
JP5903920B2 (en) * 2012-02-16 2016-04-13 富士通株式会社 Semiconductor device manufacturing method and electronic device manufacturing method
JP5810957B2 (en) 2012-02-17 2015-11-11 富士通株式会社 Semiconductor device manufacturing method and electronic device manufacturing method
JP5810958B2 (en) * 2012-02-17 2015-11-11 富士通株式会社 Semiconductor device manufacturing method and electronic device manufacturing method
TWI476841B (en) 2012-03-03 2015-03-11 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof
TWI517274B (en) 2012-03-21 2016-01-11 矽品精密工業股份有限公司 Fabrication method of wafer-scaled semiconductor package and fabrication method of wafer-scaled package substrate thereof
CN102664170B (en) * 2012-04-19 2015-06-17 日月光半导体制造股份有限公司 Semiconductor package structure and manufacturing method thereof
US8786111B2 (en) * 2012-05-14 2014-07-22 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
KR101429344B1 (en) 2012-08-08 2014-08-12 앰코 테크놀로지 코리아 주식회사 Semiconductor Package and Manufacturing Methode thereof
JP5521130B1 (en) * 2012-08-30 2014-06-11 パナソニック株式会社 Electronic component package and manufacturing method thereof
JP5651807B2 (en) 2012-09-05 2015-01-14 パナソニックＩｐマネジメント株式会社 Semiconductor device and manufacturing method thereof
KR20140038116A (en) 2012-09-20 2014-03-28 제이앤제이 패밀리 주식회사 Led lamp
JP2014099526A (en) * 2012-11-15 2014-05-29 Fujitsu Ltd Semiconductor device, semiconductor device manufacturing method, electronic apparatus and electronic apparatus manufacturing method
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (en) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US9825209B2 (en) 2012-12-21 2017-11-21 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
CN104603932A (en) 2012-12-21 2015-05-06 松下知识产权经营株式会社 Electronic component package and method for producing same
US9449944B2 (en) 2012-12-21 2016-09-20 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
WO2014097643A1 (en) 2012-12-21 2014-06-26 パナソニック株式会社 Electronic component package and method for manufacturing same
KR101488590B1 (en) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US8828807B1 (en) * 2013-07-17 2014-09-09 Infineon Technologies Ag Method of packaging integrated circuits and a molded substrate with non-functional placeholders embedded in a molding compound
JP2015032646A (en) * 2013-08-01 2015-02-16 パナソニックＩｐマネジメント株式会社 Production method of molding
TWI512853B (en) * 2013-09-04 2015-12-11 矽品精密工業股份有限公司 Method for manufacturing semiconductor packaging
US9275878B2 (en) 2013-10-01 2016-03-01 Infineon Technologies Ag Metal redistribution layer for molded substrates
KR101607981B1 (en) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 Interposer and method for manufacturing the same, and semiconductor package using the same
US9380697B2 (en) 2014-01-28 2016-06-28 Panasonic Intellectual Property Management Co., Ltd. Electronic device and manufacturing method for same
WO2015164245A1 (en) * 2014-04-22 2015-10-29 Cirrus Logic, Inc. Systems and methods for carrying singulated device packages
US9373762B2 (en) 2014-06-17 2016-06-21 Panasonic Intellectual Property Management Co., Ltd. Electronic part package
US20160118353A1 (en) 2014-10-22 2016-04-28 Infineon Techologies Ag Systems and Methods Using an RF Circuit on Isolating Material
US20160131702A1 (en) * 2014-11-10 2016-05-12 Teradyne, Inc. Assembling devices for probe card testing
US9324697B1 (en) 2015-03-16 2016-04-26 Toshiba Corporation Chip-on-heatsink light emitting diode package and fabrication method
JP6620989B2 (en) 2015-05-25 2019-12-18 パナソニックＩｐマネジメント株式会社 Electronic component package
US10504850B2 (en) 2015-08-14 2019-12-10 Pep Innovation Pte Ltd Semiconductor processing method
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
JP6610498B2 (en) * 2016-10-21 2019-11-27 株式会社村田製作所 Method for manufacturing composite electronic component
JPWO2018221379A1 (en) 2017-05-30 2020-02-06 京セラ株式会社 Support substrate
JP6780675B2 (en) 2017-07-24 2020-11-04 株式会社デンソー Semiconductor devices and methods for manufacturing semiconductor devices
US10221529B1 (en) 2018-03-13 2019-03-05 Mute Wall Systems, Inc. Wall panels, barrier wall constructed from same, and methods of making both
US10400402B1 (en) 2018-03-13 2019-09-03 Mute Wall Systems, Inc. Wall panels, barrier wall constructed from same, and methods of making both
CN112435965A (en) * 2020-11-18 2021-03-02 深圳宏芯宇电子股份有限公司 Memory card and packaging method thereof
DE102021103369A1 (en) 2021-02-12 2022-08-18 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung SEMICONDUCTOR DEVICE AND METHOD OF PRODUCTION THEREOF
KR102406694B1 (en) 2021-07-15 2022-06-10 (주)인랩 Temperature-sensitive type heat expansion release tape and method for separating electronic components using the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020025607A1 (en) * 2000-08-30 2002-02-28 Tadatoshi Danno Semiconductor device and a method of manufacturing the same
DE10051938A1 (en) * 2000-10-19 2002-02-28 Infineon Technologies Ag Arrangement comprises substrate attached to carrier element by means of adhesive layer which incorporates additional elements containing gas
US6528354B1 (en) * 2000-03-22 2003-03-04 Seiko Instruments Inc. Method of manufacturing a semiconductor device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4395451A (en) * 1980-07-14 1983-07-26 Althouse Victor E Semiconductor wafer and die handling method and means
KR100437437B1 (en) * 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 Semiconductor package manufacturing method and semiconductor package
JP3726985B2 (en) * 1996-12-09 2005-12-14 ソニー株式会社 Manufacturing method of electronic parts
DE19932269A1 (en) * 1998-07-06 2000-01-20 Fraunhofer Ges Forschung Method and device for producing a composite between a carrier body and at least one component contained therein
JP4540150B2 (en) * 1998-09-30 2010-09-08 日東電工株式会社 Thermally peelable adhesive sheet
DE19845847A1 (en) * 1998-10-05 2000-04-13 Konrad Kristen Label with an information carrier
US6784541B2 (en) * 2000-01-27 2004-08-31 Hitachi, Ltd. Semiconductor module and mounting method for same
WO2000059036A1 (en) * 1999-03-26 2000-10-05 Hitachi, Ltd. Semiconductor module and method of mounting
WO2001006558A1 (en) * 1999-07-16 2001-01-25 Matsushita Electric Industrial Co., Ltd. Package of semiconductor device and method of manufacture thereof
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
TW569424B (en) * 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
KR100347706B1 (en) * 2000-08-09 2002-08-09 주식회사 코스타트반도체 New molded package having a implantable circuits and manufacturing method thereof
DE10040450B4 (en) * 2000-08-18 2008-07-10 Osram Opto Semiconductors Gmbh Semiconductor laser device with a cooling element
DE10065686C2 (en) 2000-12-29 2002-11-14 Infineon Technologies Ag Process for handling a thin semiconductor wafer or substrate
DE10117880B4 (en) * 2001-04-10 2009-01-29 Mühlbauer Ag Method for separating electronic components from a composite
US6534338B1 (en) * 2001-06-29 2003-03-18 Amkor Technology, Inc. Method for molding semiconductor package having a ceramic substrate
DE10137184B4 (en) * 2001-07-31 2007-09-06 Infineon Technologies Ag Method for producing an electronic component with a plastic housing and electronic component
DE10156386B4 (en) * 2001-11-16 2007-08-09 Infineon Technologies Ag Method for producing a semiconductor chip
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6794273B2 (en) * 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
US7339276B2 (en) * 2002-11-04 2008-03-04 Intel Corporation Underfilling process in a molded matrix array package using flow front modifying solder resist
DE10333841B4 (en) * 2003-07-24 2007-05-10 Infineon Technologies Ag A method of producing a benefit having semiconductor device locations arranged in rows and columns and methods of making a semiconductor device
US7153725B2 (en) * 2004-01-27 2006-12-26 St Assembly Test Services Ltd. Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528354B1 (en) * 2000-03-22 2003-03-04 Seiko Instruments Inc. Method of manufacturing a semiconductor device
US20020025607A1 (en) * 2000-08-30 2002-02-28 Tadatoshi Danno Semiconductor device and a method of manufacturing the same
DE10051938A1 (en) * 2000-10-19 2002-02-28 Infineon Technologies Ag Arrangement comprises substrate attached to carrier element by means of adhesive layer which incorporates additional elements containing gas

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585701B2 (en) 2005-05-24 2009-09-08 Infineon Technologies Ag Carrier sheet with adhesive film and method for producing semiconductor devices using the carrier sheet with adhesive film

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US20060183269A1 (en) 2006-08-17
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