WO2003010820A1

WO2003010820A1 - Analog/digital hybrid integrated circuit

Info

Publication number: WO2003010820A1
Application number: PCT/JP2002/006974
Authority: WO
Inventors: Munehiro Karasudani
Original assignee: Niigata Seimitsu Co., Ltd.
Priority date: 2001-07-23
Filing date: 2002-07-10
Publication date: 2003-02-06
Also published as: JP2003037173A

Abstract

Digital circuits such as an A/D converter (7) and a D/A converter (9) are disposed nearly at the center of an IC chip (20) to prevent much coupling noise on wirings or much loss on the wirings from occurring even if the wirings elongate from pads (23) provided in the periphery of the IC chip (20) to the digital circuits provided nearly at the center. Analog circuits such as an RF circuit (21) and an IF circuit (22) are disposed in a periphery of the IC chip (20) to suppress the coupling noise on the wiring or loss on the wiring by shortening the wirings from the pads (23) to the analog circuits. A power source can be supplied at a low noise and low loss with the impedance reduced for connection to the power source line and a ground line (24).

Description

Description Analog / digital hybrid integrated circuit technology

The present invention relates to an analog / digital hybrid integrated circuit in which an analog circuit and a digital circuit are integrated on one semiconductor chip. Background art

In recent years, in addition to mobile phone devices and PDAs (Personal Digital Assistants), entertainment devices such as radio receivers, digital cameras, game devices, home appliances such as air conditioners and refrigerators, vending machines, manufacturing equipment in factories, and measuring devices Many electronic devices, such as in-vehicle devices such as car navigation systems and office equipment, have built-in communication means and are being used as network terminals.

In such a network environment, wireless communication enables "anytime, anywhere, anybody" communication. Means for wireless communication include mobile phone devices and PDAs, as well as short-range wireless data communication technology bluetooth and wireless LAN using the 5 GHz band.

Of course, these wireless communication terminals are assumed to be easily portable. Therefore, small size, light weight and low power consumption are strongly required. Generally, wireless communication terminals tend to be multifunctional and highly functional. Nevertheless, the equipment as a whole is required to be small, lightweight and low power consumption. Therefore, the wireless communication function built into the device needs to be even smaller, lighter, thinner and lower power consumption.

Against this background, semiconductor integrated circuits have become multifunctional, highly integrated, Densification is rapidly progressing. Attempts have also been made to integrate wireless circuits, including passive components such as capacitors, into one chip or one module. Recently, analog LSIs and digital LSIs, which had been independent from each other, have been developed as integrated analog / digital LSIs.

For example, a radio circuit (analog circuit) for transmitting and receiving analog signals, a PLL (Phase Lock Lock Loop) synthesizer circuit (digital circuit), and a baseband for processing signals to be transmitted and received digitally Many attempts have been made to integrate the signal processing circuit (digital circuit) into one chip or one module.

In highly integrated and high-density semiconductor integrated circuits, parasitic capacitances and parasitic inductances are generated between wiring and components, and this causes coupling noise. Wireless communication terminals such as radio receivers, mobile phone devices, bluetooth, and wireless LANs use very high frequency bands. As the frequency increases, any parasitic capacitance components begin to form a path for coupling noise. High-frequency current flowing through the wiring generates a magnetic field. As a result, dielectric coupling noise becomes apparent.

Also, as the frequency increases, the effective impedance increases, making it easier to ride noise. The loss on the transmission path is also very large. For example, in a high-frequency signal receiving unit, if there is a loss in the high-frequency circuit near the radio wave entrance, the receiving sensitivity will decrease, and it will not be possible to recover even if the gain is increased in subsequent circuits. Also, if there is a loss in the high-frequency circuit near the exit of the radio wave that handles high power in the high-frequency signal transmitter, the high-frequency power is not only converted to heat and wasted, but also increases in temperature. In some cases, this can lead to component failure.

In the case of analog / digital mixed integrated circuits, analog circuits and digital This means that the circuits are arranged closer to each other as compared to a case where the circuit is configured on a separate chip. Therefore, large noise of the digital circuit often enters the highly sensitive analog circuit. In this case, the characteristics of the analog signal are greatly deteriorated. Therefore, it is very important how to reduce the coupling noise between the analog circuit and the digital circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has been made to be able to suppress noise generated in an analog circuit, particularly a high-frequency circuit portion, and to reduce loss on a transmission line. The purpose is to do. It is another object of the present invention to suppress the inconvenience that an analog circuit receives digital noise from a digital circuit and the quality of an analog signal is degraded. Disclosure of the invention

An analog / digital hybrid integrated circuit according to the present invention is an analog / digital hybrid integrated circuit in which an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip. A circuit that operates in accordance with a clock is arranged at approximately the center of the.

In another aspect of the present invention, the circuit that operates according to the clock is a circuit that operates intermittently according to the clock. In another embodiment of the present invention, the circuit operating according to the clock is any one of a D / A converter, an A / D converter, a PLL circuit, and a baseband signal processing circuit or a combination thereof. I do.

According to another aspect of the present invention, an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip. A digital / digital hybrid integrated circuit, in which a circuit which operates according to a clock having a period long enough to operate the analog circuit between edges is arranged substantially at the center of the semiconductor chip. It is characterized by the following.

In another aspect of the present invention, the analog circuit is arranged in a peripheral portion of the semiconductor chip.

According to another aspect of the present invention, there is provided an analog / digital hybrid integrated circuit in which an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip, The above-mentioned analog circuit is arranged in the section.

According to another aspect of the present invention, the analog circuit disposed in the peripheral portion of the semiconductor chip is a high-frequency circuit that performs processing on a high-frequency signal in a desired frequency band.

Since the present invention comprises the above technical means, the wiring length is long from the pad provided at the peripheral portion of the semiconductor chip to the circuit provided at the substantially central portion of the semiconductor chip, but the circuit disposed at the substantially central portion is Since is a digital circuit, it is possible to reduce the problem of coupling noise generated on the wiring and the loss on the wiring, as compared with the case where the wiring length to the analog circuit, particularly to the high-frequency circuit becomes long.

According to another feature of the present invention, the circuit arranged substantially at the center of the semiconductor chip is a circuit that operates intermittently according to a clock, so that, for example, the analog circuit operates when the circuit is not operating. And the coupling noise between the analog circuit and the circuit can be reduced. According to another aspect of the present invention, since the circuit disposed substantially at the center of the semiconductor chip is a circuit that operates according to a clock having a long cycle, a transient state change occurs at the edge of the clock. While the mouth is The analog circuit can be operated in a state where the clock is stable without operating the switching circuit, and it is possible to suppress the inconvenience that switching noise due to the clock is superimposed on a signal in the analog circuit.

According to another feature of the present invention, since an analog circuit, particularly a high-frequency circuit, is arranged in the periphery of the semiconductor chip, the wiring length from the pad provided in the periphery of the semiconductor chip to the analog circuit is shortened. Therefore, it is possible to reduce the coupling noise generated on the wiring and the loss on the wiring. In addition, the connection to the power supply line and the ground line can be reduced in impedance, and power supply with low noise and low loss can be performed. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating a configuration example of a wireless communication device.

FIG. 2 is a diagram showing a layout configuration example of each block in an analog / digital hybrid IC chip in which the wireless communication device shown in FIG. 1 is integrated. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

The wireless communication device shown in Fig. 1 has an antenna 1, an antenna switch 2, a high-frequency amplifier 3, a mixer (mixer) 4, a local oscillator (OSC) 5, an intermediate-frequency amplifier 6, an AZD converter 7, It comprises a baseband signal processing circuit 8, a D / A converter 9, an intermediate frequency amplifier circuit 10, a mixing circuit 11, a power amplifier 12, and an audio signal processing circuit 13.

The high-frequency amplifier circuit 3 inputs radio waves received by the antenna 1 via the antenna switch 2 and selectively amplifies a high-frequency signal in a specific frequency band. . The mixing circuit 4 and the local oscillation circuit 5 constitute a frequency converter, and the carrier signal of the frequency f _e output from the high-frequency amplification circuit 3 and the local oscillation signal of the frequency f _t output from the local oscillation circuit 5 preparative mixed, and generates and outputs an intermediate frequency signal ft one f _c by performing frequency conversion, without changing the modulation content. The intermediate frequency increasing circuit 6 amplifies the intermediate frequency signal that has passed through the mixing circuit 4. The AZD converter 7 converts the analog intermediate frequency signal output from the intermediate frequency increase circuit 6 into digital data, and outputs the result to the baseband signal processing circuit 8. The baseband signal processing circuit 8 includes a voice CODEC (Corder-Decoder), a DSP (Digital Signal Processor), a memory, and the like, and performs digital data processing such as baseband modulation and error correction. The audio signal processing circuit 13 performs various processes related to the audio signal.

The DZA converter 9 performs DZA conversion on the digital data generated by the baseband signal processing circuit 8. The intermediate frequency increase circuit 10 amplifies the analog intermediate frequency signal output from the D / A converter 9. The mixing circuit 11 and the local oscillation circuit 5 constitute a frequency converter, and perform frequency conversion on the intermediate frequency signal output from the intermediate frequency circuit 10 without changing the modulation content to generate a high frequency signal. And output.

The power amplifier 12 amplifies a high-frequency signal in a specific frequency band that has passed through the mixing circuit 11. The amplified high-frequency signal is transmitted from the antenna 1 via the antenna switch 2.

In the above wireless communication device, a high frequency circuit (Radio Frequency: RF circuit) is configured by the high frequency amplifier circuit 3, the mixing circuit 4, the local oscillation circuit 5, the mixing circuit 11, and the power amplifier 12. An intermediate frequency circuit (Intermediate Frequency: IF circuit) is constituted by the intermediate frequency amplifier circuits 6 and 10. FIG. 2 is a diagram showing a layout configuration example of each block in an analog / digital hybrid IC chip in which the wireless communication device shown in FIG. 1 is integrated. As shown in FIG. 2, a plurality of pads 23 are provided around the IC chip 20 for data input / output and a power supply.

Inside the plurality of pads 23, there is a core unit on which analog circuits and digital circuits are integrated. An RF circuit 21, an IF circuit 22, an A / D converter 7, a baseband signal processing circuit 8, a D / A converter 9, and an audio signal processing circuit 13 are integrated in the core unit. Around the core portion (between the core portion and the pad region), a power supply line and a ground line 24 are arranged so as to go around the core portion.

The RF circuit 21 includes the high-frequency amplifier circuit 3, the mixing circuit 4, the local oscillation circuit 5, the mixing circuit 11, the power amplifier 12, and the like shown in FIG. Further, the IF circuit 22 includes the intermediate frequency amplifier circuits 6 and 10 shown in FIG. Note that the RF circuit 21 does not necessarily need to have all the above-described configurations. For example, the high-frequency amplifier circuit 3, the local oscillator circuit 5, the power amplifier 12, and the like may be provided as separate chips.

In the present embodiment, the A / D converter 7, the baseband signal processing circuit 8, and the D / A converter 9 are arranged at substantially the center of the IC chip 20. The A / D converter 7, the baseband signal processing circuit 8, and the DZA converter 9 are digital circuits that do not always operate according to a high-speed clock, that is, operate intermittently.

By arranging such a digital circuit at a substantially central portion of the IC chip 20, it is possible to connect the pad 23 provided around the IC chip 20 to the digital circuit via a power supply line and a ground line 24. Wiring lengths for power supplies and grounding can be long. However, since these circuits are digital circuits that operate in the relatively low-frequency region of the baseband, wiring 8

Even if the length is slightly longer, the coupling noise generated on the wiring ゃ the loss on the wiring is not so large.

In the present embodiment, the digital circuit having less problems of noise and loss is arranged substantially at the center of the IC chip 20, and the analog circuits such as the RF circuit 21 and the IF circuit 22 are mounted on the IC chip 20. It is located at the periphery of. As a result, the wiring length from the pad 23 provided around the IC chip 20 to the analog circuit can be shortened, and the coupling noise generated on the wiring and the loss on the wiring can be reduced. it can. Also, since the wiring length from the power supply line and the ground line 24 to the analog circuit can be shortened, the connection between the power supply line and the ground line 24 can be reduced in impedance, and low noise Low-loss power supply can be realized.

Further, as described above, the A / D converter 7, the baseband signal processing circuit 8, and the D / A converter 9, which are arranged in the approximate center of the IC chip 20, operate intermittently according to the clock. It is a digital circuit. Therefore, by operating analog circuits such as the RF circuit 21 and the IF circuit 22 when these digital circuits are not operating, the large digital noise generated in the digital circuits is applied to the signals in the analog circuits. The inconvenience of overlapping can be suppressed.

Further, as shown in FIG. 2, the baseband signal processing circuit 8 is disposed on the opposite side of the RF circuit 21 and the IF circuit 22 with the A / D converter 7 and the DZA converter 9 interposed therebetween. Although the baseband signal processing circuit 8 is a digital circuit, if the operation speed is high, it is conceivable that the high-speed digital signal leaks to the outside as radio waves and interferes with communication.

However, the baseband signal processing circuit 8 is arranged as far as possible from analog circuits such as the RF circuit 21 and the IF circuit 22. Therefore, the electromagnetic wave generated by the baseband signal processing circuit 8 is the square of the distance Attenuation is sufficient to reach the RF circuit 21 and the IF circuit 22 at a ratio of 1. Therefore, it is possible to prevent large digital noise from the baseband signal processing circuit 8 from being superimposed on the analog signals handled by the RF circuit 21 and the IF circuit 22. The baseband signal processing circuit 8 and the RF circuit 21 And the coupling noise with the IF circuit 22 can also be reduced.

In the above embodiment, the A / D converter 7, the baseband signal processing circuit 8, and the DZA converter 9 have been described as examples of the circuits arranged at the substantially central portion of the IC chip 20, but all of them are substantially omitted. It is not always necessary to place it in the center. In addition to these, any digital circuit that operates according to a clock can be arranged at a substantially central portion of the IC chip 20. For example, the PLL circuit may be arranged substantially at the center. Further, in the above-described embodiment, an example has been described in which the baseband signal processing circuit 8 is also arranged at a substantially central portion of the IC chip 20. However, the baseband signal processing circuit 8 may be arranged at a peripheral portion of the IC chip 20.

Further, in the baseband signal processing circuit 8, there is a logic part that does not need to operate at the highest clock speed. If there are many analog circuits to be placed around the IC chip 20 and it is not possible to place all of the baseband signal processing circuit 8 around the periphery, the above logic section is cut out and the IC chip 20 is cut out. May be arranged substantially at the center.

In the case of a digital circuit that does not operate at such a high speed, the operation clock is a long-period clock having a sufficient length between edges. On the other hand, the main cause of noise in an analog / digital hybrid circuit is a switch caused by a transient state change of a transistor that occurs when switching is performed in synchronization with a clock edge in a digital circuit such as a CM〇S inverter. This is tuning noise.

The digital circuit located at the approximate center of the IC chip 20 has a long cycle If the digital circuit operates according to the clock, do not operate the analog circuit while the transistor has a transient state change at the edge of the clock, and operate the analog circuit while the clock is stable. be able to. By doing so, it is possible to suppress the inconvenience that switching noise in a digital circuit is superimposed on a signal in an analog circuit.

In the above embodiment, the circuit that performs the audio signal processing is described. However, the present invention can be applied to a circuit that performs the video signal processing.

In the above embodiment, the analog / digital hybrid integrated circuit having both the transmitting function and the receiving function has been described. However, the present invention is also applied to the analog / digital hybrid integrated circuit having only one of the transmitting function and the receiving function. It is possible to

In addition, the embodiments described above are merely examples of embodying the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. It is. That is, the present invention can be embodied in various forms without departing from its spirit or its main features.

As described above, according to the present invention, the wiring length from the peripheral portion of the semiconductor chip to the circuit provided in the substantially central portion is long, but since the circuit disposed in the substantially central portion is a digital circuit, As compared with the case where the wiring length to the circuit becomes longer, the problem of coupling noise generated on the wiring and the loss on the wiring can be reduced.

Further, according to another aspect of the present invention, since the circuit arranged substantially at the center of the semiconductor chip is a digital circuit that operates intermittently according to a clock, for example, when the digital circuit is not operating, The circuit can operate, and the coupling noise between analog and digital circuits is also reduced. I can do it.

According to another aspect of the present invention, since the circuit arranged substantially in the center of the semiconductor chip operates according to a long-period clock, a transient state change occurs in the transistor at the edge of the clock. The analog circuit can be operated while the clock is stable while the analog circuit is not operating during the occurrence, and the switching noise due to the clock is prevented from being superimposed on the signal in the analog circuit. Can be.

According to another feature of the present invention, since an analog circuit, particularly a high-frequency circuit, is arranged in the periphery of the semiconductor chip, the wiring length from the periphery of the semiconductor chip to the analog circuit can be shortened. The coupling noise generated above, and the loss on the wiring can be reduced. In addition, the connection with the power supply line and the ground line can be reduced in impedance, and power supply with low noise and low loss can be performed. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention is useful for suppressing a noise generated in a high-frequency circuit portion and reducing a loss on a transmission line.

Claims

The scope of the claims

1. An analog / digital hybrid integrated circuit in which an analog circuit for processing a signal of a desired frequency band and a digital circuit are mounted on the same semiconductor chip.

A mixed analog / digital integrated circuit, wherein a circuit that operates according to a clock is disposed substantially at the center of the semiconductor chip.

2. The integrated analog / digital integrated circuit according to claim 1, wherein the circuit that operates according to the clock is a circuit that operates intermittently according to the clock.

3. The integrated analog / digital integrated circuit according to claim 1, wherein the circuit operating according to the clock is a D / A converter.

4. The integrated analog / digital integrated circuit according to claim 1, wherein the circuit operating according to the clock is an AZD converter.

5. The integrated analog / digital integrated circuit according to claim 1, wherein the circuit that operates according to the clock is a PLL circuit.

6. The mixed analog / digital integrated circuit according to claim 1, wherein the circuit that operates according to the clock is a baseband signal processing circuit.

7. An analog / digital hybrid integrated circuit in which an analog circuit for processing a signal of a desired frequency band and a digital circuit are mounted on the same semiconductor chip.

Operates at a substantially central part of the semiconductor chip according to a clock having a period long enough to operate the analog circuit between edges. Analog / digital hybrid integrated circuit characterized by arranging circuits to perform

8. The integrated analog / digital integrated circuit according to claim 1, wherein said analog circuit is arranged in a peripheral portion of said semiconductor chip.

9. The mixed analog / digital integrated circuit according to claim 7, wherein said analog circuit is arranged in a peripheral portion of said semiconductor chip.

10. An analog / digital hybrid integrated circuit in which an analog circuit that processes signals in a desired frequency band and a digital circuit are mounted on the same semiconductor chip.

An analog / digital hybrid integrated circuit, wherein the analog circuit is arranged in a peripheral portion of the semiconductor chip.

11. The mixed analog / digital circuit according to claim 8, wherein the analog circuit arranged in the peripheral part of the semiconductor chip is a high frequency circuit for performing processing relating to a high frequency signal in a desired frequency band. Integrated circuit.

12. The mixed analog / digital circuit according to claim 9, wherein the analog circuit arranged in the peripheral portion of the semiconductor chip is a high frequency circuit for performing processing relating to a high frequency signal in a desired frequency band. Integrated circuit.

13. The analog circuit according to claim 10, wherein the analog circuit disposed in a peripheral portion of the upper ffi semiconductor chip is a high-frequency circuit that performs processing relating to a high-frequency signal in a desired frequency band. Digital embedded integrated circuit.