WO1996031038A1 - Data transmitting method and transmission/reception circuit used therefor, and signal processor - Google Patents

Abstract

The purpose of this invention is to realize high-speed data transmission by reducing the waveform distortion which occurs when binary digital data signals are transmitted through a transmission line. A sinusoidal reference clock signal (Ck1) is transmitted together with data signal (D1) synchronously modulated in amplitude. The modulated signals are received and demodulated according to the received clock signal to obtain the original data (Dr2). In the synchronous amplitude modulation, a sine wave (Vddq) having the same period and phase as those of the reference clock signal (Ck1) is modulated to have an amplitude larger or smaller than that of the signal (Ck1) depending upon the information (1,0) of the digital data. This data transmitting method can be used for data transmission between the microprocessor and storage device of a computer.

Description

 Details

[Title of Invention]

 Data transmission method, transmission / reception circuit device used therefor, and signal processing device

[Technical field〕

 The present invention relates to a data transmission method, a transmission / reception circuit device and a signal processing device used for the same, and more specifically, to a central processing unit (CPU) and a main memory. The present invention relates to a configuration of an input / output circuit unit and a configuration of a signal transmission unit of a circuit device in a signal processing device in which the circuit device is connected by a transmission line such as a bus.

(Background technology)

 In recent years, with the advancement of large-scale integrated circuit (hereinafter abbreviated as LSI) technology, the operating frequency of microprocessors (MPUs) has exceeded 100 MHz. You. As for memory, Synchronous Random Access Memory (DRAM) that operates at 100 MHz or higher has been reported.

However, even if the speed can be increased at the LSI chip level of the circuit device, the signal processing device such as a work station or a personal computer using the LSI may not be able to operate at high speed. It is difficult to increase the speed of an LSI chip level to the speed of an LSI chip level with the following reasons.

 For signal transmission between the LSI chips constituting the circuit device of the signal processing device as described above, a pulse signal based on a non-return, zero (NRZ) code is used. If the wavelength of the harmonic component contained in this pulse signal becomes as short as the wiring on the board, the above wiring will behave as a distributed constant line, and the signal will be sent to the wiring end, branch, or LSI package. Parasitic inductance ゃ Remarkable reflections occur due to parasitic canon capacitance, and ringing and other waveform distortions occur in the pulse waveform. This waveform distortion causes difficulty in increasing the speed.

 For example, when transmitting signals between LSI chips 1-2 and 173 on board 170 as shown in Fig. 17 (a), the equivalent circuit is as shown in Fig. 17 (b). Can be expressed as The LSI 172 has an internal circuit 178, which is the original functional circuit, and an output circuit 176, which converts the output of the internal circuit into a signal suitable for the transmission line 171. It has an input circuit 177 that converts the signal received from the line into a signal suitable for the processing of the internal circuit 179.

In addition, there are a package read frame and a bonding wire between the LSI and the transmission line, and these are parasitic elements 1 of the parasitic capacitance C and the parasitic inductance L. 7 4 and 1 7 5. Although the case where the input and output terminals are independent is shown here, when the input and output are common, the parasitic capacitance of the terminals is further increased, so that the waveform disturbance is further increased.This is conventionally used in pulse transmission. Figure 18 shows the transmitting (output) circuit used. The transmission circuit 180 has an output stage 181, driving circuits 182 and 183 each including a pMOS transistor and an nMOS transistor, and an output control circuit 1884. In the figure, IV 11 to IV 15 indicate an inverter circuit, NAND 2 indicates a NAND circuit, and NOR indicates a NOR circuit. The output control circuit 184 puts the output Out into a high impedance state regardless of the value of the input signal In when the signal D0e has a low level. When the signal Doe is at a high level, the same signal as the input signal In is output. In general, the size of the transistor of the internal circuit 178 in the preceding stage that generates the input signal In is small, and the size of the transistor in the output stage 181 is large. Inverter trains with progressively larger transistor sizes are used.

Figure 19 shows a simulated transmission waveform when using the transmission circuit shown in Fig. 18. In this simulation, the following conditions were used: The power supply voltage is V dd power, '1.5 V, V ss power,' 0 V. The transmission line has a characteristic impedance of 50 Ω and a length of 2 cm. At the end, the voltage V tt is 0.75 V and the resistance R tt is 50 Ω. The inductance L of the knockout was 10 nH and the capacitance C was 5 pF. The output resistance of the output circuit is about 22 Ω, and a plus / minus 0.4 V amplitude is obtained for a load of 25 Ω.

 Waveforms I029 and〗 030 at the transmitting end and the receiving end when a rectangular wave having a period of 1 Ons was transmitted from the output circuit are shown. This means that data "0, 1, 0, 1" is transferred at a period of 5 ns. The reflection at the transmitting end and receiving end is large, and large ringing is occurring. The margin for the voltage V tt at the minimum point of the waveform due to the ringing at the rise of the signal is 0.22 V, which is 55% of the amplitude of 0.4 V on one side. . If this minimum falls below the voltage V tt, the receiver will incorrectly determine that it has received two pulses. Therefore, if the margin is small, the reliability in transmitting a high-speed signal decreases.

In addition, waveform disturbance due to multiple reflection is more remarkable when a plurality of receiving circuits transmit to a single transmitting circuit via a bus. In a work station or a personal computer, a memory LSI is often used in the module configuration shown in FIG. 20 (a. A main memory 201 on which a plurality of DRAM memory modules 202 are arranged, and a cache 2 comprising a plurality of SRAMs 204 0 5 is located. In this case, the memories are connected by a common memory bus 207. The equivalent circuit of Fig. 20 (a) is shown in Fig. 20 (b). One memory 2 0

For 4, a plurality of memory elements 201-1 to 210-7 are connected via one bus 207. Memory elements 201-1 to 210-7, and 204 are LSI chips.

Connected to the bus at 2 cm intervals. The end of the bus 207 is connected to the terminal power supply (voltage V tt) by the terminal resistor R tt. Let 204 be the transmission LSI, and let the memory elements 201-1-1 to 201-1 be the reception LSI. Although the internal configuration of the memory elements 201 to 211 is the same, only the internal configuration of the memory elements 201 to 7 is shown for simplicity. Here, the case where the input and output terminals are independent is shown, but when the input and output terminals are common, the parasitic capacitance of the terminals becomes large, and the waveform disturbance becomes larger.

 Next, as the transmission circuit 208 of the LSI 204 in FIG. 20, the received waveform of the simulation result when pulse transmission is performed using the circuit 180 in FIG. Figure 21 shows this. A rectangular wave with a period of 10 ns is transmitted from LSI 208 and the transmission end of LSI208, LSI210-1 — 1, 20

The waveforms at the receiving end of 1 1 4 and 2 0 1-7 are

031, 103, 102, 104 and 103 are shown. Significant ringing has occurred in the received waveform. There is no margin for the voltage V tt at the minimum point of the ringing waveform. Or 0.09 V. This is 22% of 0.4 V on one side. This is because multiple reflections occur due to parasitic components of the LSI connected in the middle of the node and branching of the bus.

 Another problem with high-speed data transmission is the increase in power supply noise. In data transmission using the NRZ code between LSI, the output terminal voltage changes rapidly during data transitions, so the output circuit needs to charge the load capacitance of the transmission line in a short time. As a result, the change in the current flowing through the power supply per unit time increases, and this causes noise such as ringing due to the parasitic inductance of the LSI power supply pin.

In addition, skew between the clock and data is also a problem in high-speed data transmission. As shown in Fig. 22 (a), clock and data transmission in conventional data transmission are performed without terminating the data transmission line 221, and the voltage on the line is from V dd to V ss. Can swing up. In this case, the clock and data supplied to each of S 1 2 2 3 — 1, 2 2 3 — 2 ··· 2 2 3 — 8 are transmitted in the same direction. Skew due to the propagation delay on the transmission line, because the data on the data transmission line 222 and the clock on the clock transmission line 222 are transmitted in opposite directions. As the data transmission speed generated by the clock increases and the clock cycle decreases, the relative ratio of the skew to the clock cycle increases. Because of the increase, the timing margin when latching data is reduced. 2 2 4 — 1… 2 2 4 — 8 is a transmission latch, 2 2 5 — 1… 2 2 5 — 8 is a reception latch, 2 2 6 — 1… 2 2 Reference numeral 6-8 denotes a CMOS inverter type transmission circuit, and reference numeral 227-7-1 ... 22 7-8 denotes a CMOS inverter type reception circuit.

 In order to solve this problem, one solution

A technique using a ramba interface shown in 23 is known. The Lannos interface is described in detail in Published Patent Publication No. 5-507734. 2 3 3 — 1,… 2 3 3 — 8 is an LSI, 2 3 4 1 1… 2 3 4 — 8 is a transmission latch, 2 3 5 — 1… 2 3 5 — 8 is a reception latch , 2 3 6 — 1 ··· 2 3 5 — 8 are NMOS open drain type transmission circuits, 2 3 7 — 1 •• 2 3 7 — 8 are differential type reception circuits, and 2 3 8 are Indicates the clock source. In this interface, the clock line 2332 is folded back and distributed, and one is used as a transmission clock, and the other is used as a reception clock. Also, data transmission is performed between the master 2 3 3-1 and a plurality of slaves 2 3 3-2… 2 3 3-8, and no data transmission is performed between the slaves. Slave 2 3 3 — 8 to Master 2

When transmitting data to 3 3 — 1, slave 2 3 3 _ 8 transmits data in synchronization with the transmission clock, and master 2 3 3-1 transmits data in synchronization with the transmission clock. Data in synchronization with Upon receipt, the data and clock will be transmitted to the left. Conversely, when data is transmitted from the master 233-1 to the slaves 23-3-8, the data and clock are transmitted to the right. Therefore, the clock and data are always transmitted in the same direction, and the skew is reduced. However, this solution has the problem of increasing the number of clock terminals.

 Also, in order to realize high-speed data transmission, this interface terminates the data transmission line and uses an active-low type small-amplitude interface using an open drain for the transmission circuit. Interface is used. For this reason, the high level of the signal becomes a constant value at the termination voltage V tt, but the low level depends on the device characteristics of the pull-down nMOS (2 3 3-1 2 3 3-8). You will be affected by fluctuations and changes. In order to suppress this effect, the driving power of the pull-down nMOS is controlled by feeding a low level voltage to the node, but the control circuit becomes complicated and the chip There is a problem that the area increases.

 [Disclosure of the Invention]

A main object of the present invention is to provide a data transmission method capable of performing high-speed and high-accuracy data transmission between circuit devices constituting a signal processing device, and a transmission / reception circuit device for implementing the method. That is. In particular, for signal processing devices such as work stations and personal computers. In data transmission between LSIs constituting a circuit device, a data transmission method that suppresses the ratio of harmonic components contained in a data transmission waveform, converts the transmission waveform into a signal that is less likely to be disturbed, and transmits the signal. The purpose of the present invention is to provide a transmitting circuit and a receiving circuit device used for the above.

 A second object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit for performing data transmission with low noise by reducing a change in power supply current per unit time with low bias. It is.

 A third object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit for reducing a skew between a clock signal and a data signal, which is a problem in high-speed data transmission. And.

 A fourth object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit capable of transmitting with a large margin with respect to an output level in a small-amplitude interface.

 A fifth object of the present invention is to provide a signal processing device capable of efficiently transmitting input / output signals of a circuit device for processing a plurality of data having different data transmission speeds through a single transmission line. The equipment is to be provided.

In order to achieve the above object, a data transmission method according to the present invention is characterized in that a signal level of one or a plurality of digital data (hereinafter simply referred to as data) signals to be transmitted is fixed in a transmission unit The data signal has the same cycle as the reference clock signal, and the amplitude is determined by the information of the data signal. The reference clock signal and the modulation data signal are converted to a signal (hereinafter referred to as “modulation data”) representing a value smaller or larger than the amplitude of the signal, and transmitted to a receiving unit via a transmission line. Hereinafter, the conversion of the data signal is abbreviated as synchronous amplitude modulation.

 The receiving unit detects the difference between the amplitude of the modulation data received from the transmission line and the amplitude of the reference clock, and demodulates the signal into the original binary data signal.

 Further, as a device used in the above data transmission method, the transmission circuit device according to the present invention is a reference clock signal generating means for generating a reference clock signal that is a sine wave having a constant period. And a data signal source for inputting the data signal to be transmitted, and the data signal to be transmitted having the same phase and period as the reference clock signal, and having the same amplitude as the information of the data signal to be transmitted. Accordingly, a synchronous amplitude modulation circuit for converting the amplitude into a sine wave or a signal approximating a sine wave having a smaller or larger amplitude than the sine wave amplitude of the reference clock signal and the synchronous amplitude modulation circuit A transmission circuit is provided which has an output terminal for outputting the modulated data which is the output of the reference signal and the reference port to the transmission line.

Further, the receiving circuit device according to the present invention provides the modulated data A receiving terminal that receives the reference clock and a reference clock; a comparator (detector) that compares the modulation data from the receiving terminal with the amplitude of the reference clock to determine the magnitude of the reference clock; And a demodulator that converts the output of the device into the original digital data signal.

 Further, a signal processing device according to the present invention is configured by connecting the above-mentioned plurality of receiving circuit devices and transmitting circuit devices via a transmission line. Note that the receiving circuit device and the transmitting circuit device include a case where the transmitting circuit and the receiving circuit are both provided.

According to a preferred embodiment of the present invention, when the data signal to be transmitted is a plurality of sequences, a reference clock signal of a different frequency is used for each sequence, and synchronous amplitude modulation is performed for each sequence. And frequency multiplexing for transmission. Further, the transmission circuit device and the reception circuit device are each configured by a single LSI together with an internal circuit that processes binary data. Further, according to another preferred embodiment, the modulation circuit outputs a sine wave synchronized with the data to be transmitted and the level of the clock signal external to the SI as described above. According to this information, the signal is converted into a sine wave having a level larger or smaller than the level of the reference signal. In the configuration of the present invention, the sine wave is not limited to a strict sine wave, but is a waveform having a high similarity to the sine wave, for example, a waveform having a small harmonic component. Including The transmission / reception circuit device is not particularly limited, but includes a circuit element configured by an LSI, for example, a memory, a micro processor, a control circuit, and the like.

 According to the data transmission method and the transmission / reception circuit device of the present invention, the waveform of the transmitted data signal becomes a waveform approximating a sine wave with few harmonics, so that the transmission line branches from the transmission waveform. As compared with a square wave that causes multiple reflections at the power supply pin and parasitic elements, and the change in power supply current is small, and the noise in the parasitic inductance of the power supply pin is reduced. Is done. For these reasons, the use of the data transmission method, transmission and reception circuit device according to the present invention enables highly reliable and high-speed data transmission, especially in high-speed data transmission.

 The above and other objects, configurations and features of the present invention will become more apparent from the following description of embodiments in conjunction with the drawings.

[Easy sharp drawing]

 FIGS. 1 (a) and 1 (b) are waveform diagrams for explaining the configuration and operation principle of a transmitting and receiving apparatus for implementing an embodiment of a data transmission method according to the present invention, respectively.

 FIG. 2 is a circuit diagram of the transmission circuit device of FIG.

FIGS. 3 (a) and 3 (b) are plots each showing a configuration of a sinusoidal clock generating means used in the above embodiment. FIG. 5 is a diagram and a waveform diagram for explaining the operation thereof.

 FIG. 4 is a circuit diagram of the receiving circuit of FIG.

 FIG. 5 is a timing chart showing the operation of one embodiment of the transmitting and receiving circuit device according to the present invention.

 FIG. 6 is a block diagram showing a transmission circuit model for explaining the effect of the transmitting and receiving circuit device according to the present invention.

 FIG. 7 is a diagram showing transmission / reception waveforms of one-to-one transmission showing simulation results using the circuit model of FIG.

 FIG. 8 is a block diagram showing a transmission circuit model for explaining the effect of the transmitting and receiving circuit device according to the present invention.

 FIG. 9 is a diagram showing transmission / reception waveforms of one-to-many transmission showing a simulation result based on the circuit model of FIG.

 FIGS. 10 (a) and 10 (b) are a circuit diagram of another embodiment of the transmission circuit device according to the present invention and a truth table for explaining the same, respectively.

 FIG. 11 is a block diagram showing a transmission system for explaining another embodiment of the data transmission method according to the present invention.

 FIG. 12 is a block diagram showing a configuration of a computer which is an embodiment of the signal processing device according to the present invention.

 FIG. 13 is a block diagram showing a configuration of a computer which is another embodiment of the signal processing device according to the present invention.

FIG. 14 is a diagram illustrating a waveform of a signal used in the signal processing device of FIG. 13 and a diagram illustrating a frequency domain of the signal. FIG. 15 is a circuit diagram of a filter used in the signal processing device of FIG.

 FIG. 16 is a waveform diagram for explaining the operation of the signal processing device of FIG.

 FIG. 17 is a block diagram showing the configuration of a conventional pulse data transmission device.

 FIG. 18 is a circuit diagram of a transmission circuit in a conventional pulse data transmission device.

 FIG. 19 is a waveform diagram showing transmission and reception waveforms of a conventional pulse data transmission device.

 FIGS. 20 (a) and (b) are a perspective view showing a main memory and a bus wiring model of a general signal processing device, respectively, and an equivalent circuit diagram thereof.

 FIG. 21 is a waveform diagram showing transmission / reception waveforms of a conventional pulse data transmission device.

 FIG. 22 is a block diagram showing the configuration of a conventional data transmission device.

 FIG. 23 is a block diagram showing the configuration of another conventional data transmission device.

 [Best mode for carrying out the invention]

 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

 Example 1>

FIGS. 1 (a) and (b) show the data according to the present invention, respectively. FIG. 2 is a waveform diagram for explaining the configuration and operation principle of an embodiment of a transmitting and receiving circuit device for implementing a data transmission method.

 In the present embodiment, the transmission circuit device 1 composed of an LSI is transferred from the transmission circuit device 1 composed of a plurality of LSIs to the modulated data D 1 synchronously modulated to 2 -1... 2-8 and the reference clock. C k 1 is transmitted via transmission lines 3-1 and 3-2, respectively. Since the plurality of receiving circuit devices 2-1-2-8 perform the same operation, the data transmission (one-to-one transmission) between the transmitting circuit device 1 and the receiving circuit device 2-1 will be described below. In the figure, only one transmission line 3-1 is shown, but multiple transmission lines may be used in parallel. The transmission lines 3-1 and 3-2 have substantially the same electrical characteristics, wiring patterns, and loads.

The clock transmitting terminal 5 of the transmitting circuit device 1 and the clock receiving terminal 6 of the receiving circuit device 2-1 are connected to each other by a transmission line 3-2. Similarly, the data transmission terminal 7 of the transmission circuit device 1 and the data reception terminal 8 of the reception circuit device 2-1 are connected by the transmission line 3-1. Both ends of the transmission lines 31 and 3-2 are connected to a fixed terminal potential V tt by a resistor R tt. The transmission lines 3-1 and 3-2 are composed of micro strip planes with a multilayer substrate to control the characteristic impedance, and are configured with the same wiring pattern. . For this reason, transmission lines 3-1 and 3-2 are almost equally affected by noise and signal delay. Therefore, the relative magnitude relationship between the reference clock C kl and the modulation data D 1 can be transmitted without being affected.

 The transmission circuit device 1 has a transmission circuit 9. The transmission circuit 9 receives the sine-wave clock V ddq and the norm-wave clock C kt via the transmission lines 3-3 and 3-4, respectively, and receives an internal circuit (not shown). The data D t1 to be transmitted is converted into modulated data D 1 by the synchronous amplitude modulation. The clock C kt is a system clock added from an external clock source that is also provided outside the LSI chip of the transmission circuit device 1, and is an internal circuit in the transmission circuit device 1. In addition, it controls the operation timing of the internal circuit. The clock Vddq has almost the same phase as the clock Ckt.

 The operation of the transmission circuit 9, that is, the principle of synchronous amplitude modulation will be described with reference to FIG. 1 (b).

 The clock Vddq is applied to the clock transmission terminal 5 via the fixed resistor 10 (resistance value Rc1). Therefore, the clock C k1 is obtained by dividing the voltage V ddq of the sine wave clock by the parallel connection resistance R tt, 2 of the termination resistance and the fixed resistance 11 (resistance value R c 1). It is a wave signal. This signal is used as the reference clock Ct1.

On the other hand, a clock V ddq is applied to the data transmission terminal 7 via a variable resistor 10 (resistance value R dl). Obedience Thus, the signal D1 at the data transmission terminal 7 is a sine wave signal obtained by dividing the voltage of the clock Vddq by Rtt / 2 and the resistance 10 (resistance Rd1). The resistance value R dl of the variable resistor 10 is varied by the control circuit 12 according to the data D t1 which is the output of the internal circuit. In particular, the amplitude of the sine wave data D 1 can be changed in magnitude compared to the amplitude of the reference clock C kt. As described above, the amplitude is modulated to be larger or smaller than the amplitude of the reference clock in accordance with the information of the data Dt1, that is, the two values of "1" and "0". Is defined as synchronous amplitude modulation. FIG. 1B shows an example in which the data D t 1 has the information power ヽ ″ 0, 1, 1, 0, ′. The modulation data D 1 transmitted from the transmission circuit 9 is shown. Has the same period and phase as the reference clock C kl, but its amplitude depends on the content of the data to be transmitted, and the amplitude of the reference clock C k1 for each half cycle. It changes to be smaller or larger.

The receiving circuit device 2-1 has the receiving circuit 13-2. The receiving circuit 13-2 receives the modulated data D2 and the reference clock Ck2 subjected to the synchronous amplitude modulation from the terminals 8 and 6 via the transmission lines 3-1 and 3-2, respectively. These are compared by the comparators 14 and 11, and the comparison result is latched by the latch circuit 15-1 to demodulate the original data Dt1. If necessary, these are converted to NRZ signals. FIG. 2 is a circuit diagram of the transmission circuit device 1 of FIG. In the present embodiment, the transmission circuit device 1 is configured by a single LSI chip. The LSI chip has an internal circuit 20 and a transmission circuit 9 to which NRZ code data D t1 output from the internal circuit 20 is input. Further, the DC power supplies V dd and V ss, the sine wave clock V ddq, and the clock C kt having a rectangular pulse waveform are supplied to the LSI chip 1.

 A clock C kt and DC power supplies V dd and V ss are applied to the internal circuit 20. Since the clock C kt determines the timing of the circuit operation, it is sufficient if the timing can be determined using the sine-wave shaped clock C kt, When specifying timing at both the rising edge and the falling edge of the clock, it is more efficient to use a pulse-shaped clock. It becomes.

 The data Dt1 processed by the internal circuit 20 is an NRZ code synchronized with the clock Ckt.

The transmitting circuit 9 has an analog switch in which an nMOS transistor (Mnl, Mn2, Mn3) and a pMOS transistor (Mp1, p2, M3) are connected in parallel. H 2 1 2 2 and 2 3 are provided. The analog switch functions as the resistors 10 and 11 in FIG. 1, and modulates the data Dtl into the synchronous amplitude-modulated data D1. To elaborate further, analog switch 21 is based on reference clock C In order to obtain k 1, a clock V ddq is received at its source (drain) terminal, and a reference clock C k1 is output from its drain (source) terminal. It is composed of a transistor Mn1 and a pMOS transistor Mp1. A voltage V dd is applied to the gate electrode of the nMOS transistor Mnl, and a fixed potential such as an installation potential is applied to the gate electrode of the pMOS transistor Mp1. Therefore, the transistors Mnl and p1 of the analog switch 21 function as a kind of resistance element having a predetermined on-resistance determined by the gate width, the gate length, and the like. And outputs a reference clock C k1 having an amplitude smaller than the clock V dd.

 It is not necessary to set the reference clock C kl to have a small amplitude with respect to the clock V ddq, but it is necessary to form the synchronous amplitude-modulated modulation data D 1 and compare the two signals. In consideration of the above, it is convenient to form a reference clock C k1 having a small amplitude from the clock V ddq.

The analog switches 22 and 23, together with the EXNOR circuit 24, convert the output signal D t 1 of the internal circuit 20 into a modulated data signal D 1 subjected to synchronous amplitude modulation. The EXNOR circuit 24 receives the clock Ckt of the pulse wave and the output signal Dt1 of the internal circuit 20, and outputs the exclusive output G2 of the exclusive OR of the signal clocks Ckt and Dt. Out. Analog switches 22 and 23 are analog switches 21. Similarly, the nMOS transistor (Mn2, 3) and the pMOS transistor (Mp2, 3) are connected in parallel, and the source (drain) of each transistor is connected. Clock V ddq is input to the electrodes, and synchronously modulated data D1 is output from the drain (source) electrode of each transistor. The output of the circuit 1 24 is applied to the gate electrode of the transistor M n 2, and the output of the EXNOR circuit 24 is applied to the gate electrode of the transistor M p 2. The inverted signal is applied from the inverter IV 1, a fixed potential voltage V dd is applied to the gate electrode of the transistor Mn 3, and the gate of the transistor M p 3 is applied. The fixed electrode is applied with a fixed ground voltage V ss.

 The MOS transistors (Μ η 1 ··· Μ η 3, p 1 ·· ρ ρ 3) constituting the analog switches 21, 22 and 23 are connected to external LSIs. Since this is a part of the transmission circuit affected by manufacturing variations in the circuit, the gate length is made longer than that of the MOS transistor used in the internal circuit 20 to improve the characteristics. The effect of variation can be reduced.

 FIGS. 3 (a) and 3 (b) are a block diagram showing a configuration of a clock generator for generating the clocks Ckt and Vddq, respectively, and a waveform diagram for explaining the operation thereof. is there.

The devices that generate the clocks C kt and V ddq are It is mounted on the same board 30 together with the LSI of the transmission circuit device 1. The device for generating the clock C kt comprises a crystal oscillator 31, and the device for generating the clock V ddq adds the output of the crystal oscillator 31 to the low-pass filter 32. The output of the mouth filter 32 is defined as a clock V ddq. By setting the cutoff frequency of the robust filter 32 near the fundamental frequency of the cut-off C kt, as shown in Fig. 3 (b), A sine-wave clock V ddq substantially synchronized with the phase of C kt is obtained.

 FIG. 4 is a circuit diagram of one embodiment of the receiving circuit device according to the present invention.

 In the present embodiment, a single LSI chip, a receiving circuit 13 having a differential amplifier 41 and latches 42-1, 42-2, and an output D of the receiving circuit 13 are provided. It has an internal circuit 4 3 that processes r 2.

The differential amplifier 41 detects the potential difference between the received reference clock C k 2 and the data signal D 2 subjected to the synchronous amplitude modulation, and detects the subsequent latch circuits 42 1 and 4 2 — In this embodiment, the differential amplifier 41 supplies an nMOS transistor Mn4 receiving a sine-wave reference clock Ck2 to its gate electrode and a data signal D2. N MOS transistor M n5 received at the gate electrode and n MOS transistor! Load MOS transistors connected to Vln 4 and 5 And the nMOS transistors Mn6 connected in common to the source electrodes of the nMOS transistors Mn4 and Mn5. Further, the differential amplifier 1 is connected between the power supply voltage V dd and the fixed potential V ss, and is connected to the reference clock C k from the drain electrode of the transistor Mn5. Outputs an output signal corresponding to the potential difference between D2 and data signal D2.

The latch circuits 42-1 and 42-2 are composed of an nMOS transistor (Mn7 power, Mnl 2) and a pMOS transistor (Mp7 ka to Mpl It consists of a CMOS transistor gate circuit composed of 2) and an inverter circuit (IV4 ... IV6). The gate electrode of the transistor Mp7, Mn8, Mn9, Mnl0, Mp11, Mp12 receives the signal of the reference clock Ck2. The signal is supplied via an amplification circuit 44 for amplification and shaping and a delay circuit 45. The gate electrodes of transistors Mn7, p8, Mp9, p10, Mn11, and Mn12 have a signal obtained by inverting the output of delay circuit 45 by inverter IV7. Is supplied. The output signal Dm of the differential amplifier circuit 41 is supplied to the source and drain electrodes of the transistors Mn7, Mp7, Mn10, and p10, and is supplied to the transistor. Sources of the transistors Mp9, Mn9, Mp12, and Mn12. The data Dr2 demodulated to the NRZ code from the drain electrode is supplied to the internal circuit 43. ing. FIG. 5 is a waveform diagram for explaining the operation of the transmitting circuit and the receiving circuit of the first embodiment. The reference numerals used in FIGS. 1, 2 and 4 are used for the description.

 First, the operation of the transmission circuit will be described. The sine wave clock Vddq is a sine wave of amplitude Vpa oscillating around a fixed voltage Vtt. The sine wave clock Vddq is applied to the reference clock terminal 5 of the transmission circuit 9 through the analog switch 21. The gates of the transistors Mnl and Mp1 are biased to the voltages Vddq and Vss, respectively, and the analog switch 22 is always on. Accordingly, reference clocks C kl and C k2 of sine waves appear at the clock transmission terminals 5 and 6, and the amplitude V ck of the reference clocks C kl and C k2 changes the amplitude V pa of the analog switch 21. The voltage is divided by the on resistance R 1 and the parallel connection of the terminating resistance R tt.

 Vck = Vpa- (Rtt / 2) / (Rl + Rtt / 2)

The data terminal 7 is connected to the analog switch 23 which is always on and the analog switch 22 which is connected in parallel to the gate and the signal is applied to the gate. ddq is supplied. Accordingly, a sine wave appears at the data transmission terminals 5 and 6, and its amplitude changes as follows depending on whether the analog switch 22 is off or on. The amplitude V off when the analog switch 22 is off is determined by the on-resistance R 3 of the analog switch 23. Vof f = Vpa- (Rtt / 2) / (R3 + Rtt / 2)

The amplitude V on when the analog switch 22 is on is determined by the on-resistance R 2 of the analog switch 22 and the resistance R 23 of the parallel connection of R 3.

 Von = Vpa- (Rtt / 2) / (R23 + Rtt / 2)

However, R 2 3 = R 2R 3 / (R 2 + R 3)

Here, the on-resistance of the analog switch is set to R3> R1> R23 in order to satisfy Von> Vck> Voff. As described above, the amplitude of the sine wave of the data D1 can be made larger or smaller than the clock Ck1 by turning on / off the analog switch 22. .

Next, the control of the analog switch 22 will be described. As described above, the data Dt to be transmitted by the NRZ code and the modulation are determined by using the voltage difference between the clock Ck1 and the data D1. The following control is performed to correspond the data D 1. Hereinafter, in the NRZ code, “1” represents V dd and “0” represents V ss. First, when the clock C kt is "1", the clock C kl, and the data D 1 sway to the positive side, the magnitude of the amplitude of the two sine waves matches the magnitude of the voltage Therefore, in order to represent data "1" and "0", the amplitude of data D1 may be Von and Voff, respectively. On the other hand, when the clock C k1 and the data D 1 swing to the negative side with the clock C kt force ヽ * "0", the magnitude of the amplitude and the magnitude of the voltage are reversed. Data "1" and "0" are displayed. For this purpose, the amplitude of the data D 1 is V off and V on, respectively, contrary to the above-mentioned state.

An EXNOR circuit 24 is used to perform the above control. The circuit 24 outputs "1" when the two inputs Ckt and Dt1 match, and outputs "0" when they differ. EXNOR of clock C kt and data D t1 is added to gate G 2 of switch 22. Since the gate of the nMOS of the switch 22 is directly connected to G2, and the gate of the pMOS is connected to G2 via the inverter IV1, the switch 22 Turns on when G 2 is “1” and turns off when G 2 is “0.” Therefore, when the clock C kt power is '1', G 2 = D t1 and the data D t 1 Force switch “1” turns on switch 22 and “0,” turns it off. When the clock Ckt is "0", G2 = Dt1 (Dt1 indicates the negation signal of Dt1), and the data Dt1 output, "" 1 " Switch 22 is off, "0" turns on. Therefore, the above-described amplitude control is realized. In this way, by using the EXNOR circuit 24 and the switches 22 and 23 acting as variable resistors, the signal subjected to synchronous amplitude modulation by assigning the NRZ code to the potential difference is used. Can be output as By allocating a digital signal to the magnitude relationship of the potential difference, the receiving side can demodulate the signal subjected to the synchronous amplitude modulation by a conventionally known simple differential amplifier circuit or the like. You. The receiving circuit 2 compares and amplifies the reference clock Ck2 (same as clock Ckl) and data D2 (same as data D1) received by the differential amplifier 41. An output signal Dm corresponding to the potential difference supplied to the transistors Mn4 and Mn5 is output. This output signal D m is a rectangular NRZ code as shown in FIG. As shown in FIG. 5, the output signal D m is demodulated into an NRZ code according to the definition (assignment) of the correspondence between the synchronous amplitude modulation wave and the NRZ code. The receiving clock Ckr for latching the demodulated signal amplifies the reference clock Ck2 by the amplifier circuit 44 and delays the reference clock Ck2 by the delay circuit 45. This is the signal that was sent. The reference clock Ck2 is amplified and shaped by the amplifier circuit 44, and is formed into a rectangular pulse wave as shown by a clock Ckr in FIG. As described above, the reception clock C kr that determines the timing of the latch circuit 42 is formed by using a rectangular signal obtained by shaping a sine wave into the reception circuit C kr. The timing of 2 can be determined accurately. The receiving clock Ckr is 90 degrees (1 degree) with respect to the output signal Dm to form the latch timing of the subsequent latch circuit by the delay circuit 45. 4 cycles) The signals are out of phase. Using the receiving clock C kr, the output signal D m is latched by the latches 42-1 and 42-2 and output as a demodulated signal Dr 2. The latch circuits 4 2-1 are connected to the inverter circuits IV 3, IV 4 and the The output signal D m is latched by a positive feedback path composed of the transistors M n8 and M p8. Similarly, the latch circuits 42 and 22 output the output signal D m by a positive feedback circuit composed of inverter circuits IV 5 and IV 6 and the transistors M n 11 and p 11. Latch. In this embodiment, each latch circuit is connected to the first-stage switch (Mn7, Mp7, n10, Mp10), the positive feedback switch (Mn8, Mp8, n 11, p 11) and switches (n 9, M p 9, M nl 2, p 12) of the output stage, and a latch circuit 4 2 — at each timing. The switch 1 and the latch circuits 4 2-2 are configured so that the switches in each stage operate alternately. With the configuration described above, the latch circuits 42-1 and 42-2 are configured to perform the latch operation and the output operation alternately, and perform high-speed operation. Note that the demodulated output signal Dr 2 is supplied to the internal circuit 43 of the LSI 40, and the internal circuit 43 performs predetermined processing. The power supply voltage V dd and the ground potential V ss are applied to the internal circuit 43, and a pulse clock signal C kt (not shown) is supplied to the internal circuit 43 to determine the operation timing of the internal circuit 43.

In addition, MOS transistors (Mn4—Mn6, Mp4, Mp5) that make up the analog switch are affected by manufacturing variations between external LSIs. MOS transistor used for internal circuit 40 because it is a part of the receiving circuit By making the gate length longer than that of a resistor, it is possible to make it less susceptible to characteristic variations.

 Next, the effects of the present embodiment will be described. Fig. 6 shows a model for one-to-one transmission by the data transmission device of this embodiment. The clock transmitting terminal 62 of the transmitting circuit device 61 and the clock receiving terminal 64 of the receiving circuit device 62 are connected by a transmission line 66. There is a package parasitic element between the terminals 62, 64 and the transmission line 66. Similarly, the data transmission terminal 63 of the transmission circuit device 61 and the data reception terminal 6 of the reception circuit device 62 are similar. 4 is connected by a transmission line 67. The transmission lines 66 and 67 are terminated at Vtt by the terminating resistor Rtt. Block 9 is the transmitting circuit shown in FIG. 2, and block 13 has the same configuration as receiving circuit 13 shown in FIG.

FIG. 7 shows a simulation waveform of the signal transmission device model of FIG. The simulation conditions are the same as in Fig. 19 of the conventional example. At the transmission terminals 62 and 63, a reference clock Ck9 and modulation data D9 are obtained, respectively. Even in the reception reference clock Ck10 and the reception modulation data D10, the waveform is not disturbed, and the magnitude relation of the voltage between the clock Ck10 and the data D10 is determined. It is kept. From the waveform Dr10 of the received data Dr10, it can be seen that the transmitted data is correctly demodulated. FIG. 8 shows a model when one-to-many transmission is performed by the data transmission device of another embodiment. Here, 81 indicates the LSI chip of the transmitting circuit device, 82-1, ..., 82-7 indicates the LSI chip of the receiving circuit device, and the clock terminal and the data terminal are They are connected to independent transmission lines 86 and 87, respectively. The ends of the transmission lines 86 and 87 are connected to a terminating power supply V tt by terminating resistors R tt. Although all of the plurality of receiving circuit devices are the same, only the receiving circuit devices 82-2 are shown in the figure. The configurations of the transmission circuit device 81 and the reception circuit device 82 are the same as the configurations of the transmission circuit device 81 and the reception circuit device 82 in FIG.

 FIG. 9 shows a simulated waveform of the signal based on the transmission device model of FIG. The simulation conditions are the same as in FIG. 20 of the conventional example. In the figure, C kl 1, C k 12, C kl 5, C kl 8 and D ll, D 12, D 15 D 18 are circuit devices 8 1, 8 2 — 1, 8 2 -48, respectively. The simulation clock waveform of reference clock and modulation data of 2-7 is shown. At each receiving end, the transmission waveform is not disturbed, and the magnitude relationship between the clock and the data voltage is maintained. The demodulated data of the receiving circuit device is also demodulated like the transmitted data.

According to the first embodiment, the following effects can be obtained. First, since the re-data transmission is performed using a sine wave or a waveform close to the sine wave, the received waveform has less disturbance. Since the sine wave remains the sine wave even if it is shifted in phase, even if multiple reflections occur at the branch of the transmission line, the parasitic element, or the like, the waveform is not disturbed. The amplitude-modulated signal changes with time and contains some harmonics because it is not a perfect sine wave, but its proportion is small compared to a pulse wave. As described in the conventional example, since the disturbance of the received waveform is caused by the difference between the reflection of the fundamental wave and the subharmonic wave or the difference in the phase shift, the synchronous amplitude modulated wave is compared with the pulse wave. As a result, the disturbance of the waveform is reduced. Also, since the data information "1" and "0" are represented by the difference between the reference clock and the modulation data, the transmission of the reference clock and the modulation data even if multiple reflections occur on the transmission line. If the line is set to the same conditions, the reference clock and the modulation data are reflected in the same manner, and the voltage difference is transmitted while being preserved, so that accurate data transmission can be achieved. Wear.

 Second, the current change per unit time is small. This is because there are few harmonics with respect to the pulse wave and the voltage changes slowly. Therefore, the current change for driving the external load is small, and the noise due to the current change generated by the inductance of the power supply terminal is reduced.

Third, it is easy to synchronize data with the reference clock in the receiving circuit. That is, in this embodiment, In the signal circuit, the sine wave V ddq is divided to generate the reference clock C k1 and the data D 1 so that the phases match.

 Fourth, when the transmission circuit is composed of elements arranged in the same LSI chip, the characteristics of the elements are not affected by variations between the LSI elements, and the characteristics of the elements are not affected. Data transmission can be performed without being performed. Since the reference clock Ck1 and the data D1 are generated in the transmission circuit 9 in the same LSI, the amplitude difference between the reference clock Ckl and the data D1 depends on the element characteristics in the same LSI. It is determined . Therefore, even if the device characteristics differ among the LSIs due to manufacturing variations and temperature changes during operation, the magnitude difference between the amplitude of the reference clock Ck1 and the amplitude of the data D1 is not significant. Gives no gag. On the other hand, in general, the variation of the device characteristics in the same LSI is very small as compared with the variation between the same LSIs. Data transmission that is difficult to receive is possible.

 Example 2>

FIGS. 10 (a) and 10 (b) show a circuit diagram of another embodiment of the transmission circuit device according to the present invention and a truth table for explaining the operation of the circuit, respectively. In this embodiment, a transmission circuit for transmitting data using a synchronous amplitude modulation signal and a transmission circuit for transmitting data using an NRZ code are provided, and both circuits are switched and used as necessary. . For example, fast data When transmission is required, the transmission line is terminated, a synchronous amplitude modulation signal is transmitted, and the disturbance of the transmission waveform is suppressed to improve reliability.If low-speed data transmission is sufficient, Can transmit the NRZ code without terminating the transmission line, and can reduce the power consumed by the terminating resistor.

 In FIG. 10 (a), the LSI chip 100 of the transmission circuit device includes, in addition to the internal circuit 101 receiving the power supply voltage V dd and the ground potential V ss and operating with the NRZ code, a transmission circuit 1 0 2, and the transmission circuit 102 has analog switches 21, 22, 23 and a switching control circuit 103 for switching between synchronous amplitude modulation and NRZ code. The same components as those in the circuit of FIG. 2 such as the analog switch are denoted by the same reference numerals, and detailed description is omitted.

 Sources of the transistors M n 21, M p 21, M n 22, M p 22 Mn 23, and M p 23 constituting the respective analog switches 21 22 23 The drain) electrode is supplied with a sine wave clock V ddq and an analog switch 21, and a sine wave reference clock C k 21. From the analog switches 22 and 23, a modulated data signal subjected to synchronous amplitude modulation or an output signal D21 based on an NRZ code is selectively output.

The switching control circuit 103 receives a clock signal Ckt from the outside of the LSI 100 and data output from the internal circuit 101. A logic gate EXNOR 2 receiving the data signal D t 21 1, an AND circuit AND 1 receiving the control signals A me and D oe 1, an OR circuit OR receiving the data signal D t 21 1 and the control signal A me AND a circuit AND AND circuit AND 2 that receives the output signals of EXNOR 1 and EXNOR 2, AND circuit AND 3 that receives the control signal D oe 1 and the output signal of the OR circuit, and receives the inverted signal of the control signal D oe 1 and the output of the OR circuit It is composed of NOR circuit NOR1.

 Further, the output signal G 21 of the AND circuit AND 1 is supplied to the gate electrode of the transistor Mn 21, and the inverted signal is supplied to the transistor Mp 21. Further, the output signal G22 of the AND circuit AND2 is supplied to the gate electrode of the transistor n22, and its inverted signal is supplied to the gate electrode of the transistor Mp22. The output signal G 23 of the AND circuit AND 3 is supplied to the gate senile pole of the transistor Mn 23, and its inverted signal is supplied to the gate electrode of the transistor Mp 23. Is The output signal G 24 of the NOR circuit NOR 1 is an nMOS transistor M n having its source / drain path connected between the data transmission terminal 104 and the ground potential V ss. Connected to 24 gate electrodes.

The switching control circuit 103 switches the operation mode using the control signal D 0 e 1 and the control signal A me signal. Switching control circuit based on the truth table shown in Fig. 10 (b) Will be described.

 First, when the output enable signal D oel is “0 (oral level)”, all the gate output signals G 21 and G 24 become “0”, and the analog switch is turned on. 2 1… 23 n MO transistor Mn 24 is turned off, so that the reference clock Ck 21 and the transmission data D 21 have high impedance.

 When the output enable signal D0e1 is "1" (high level), the signal A me is used to switch between the synchronous amplitude modulation signal and the NRZ code. When the signal A me is "1" At this time, the data G 21 becomes “1” and the switch 21 is always turned on, and the clock C kt is added to the data G 22 because the AND circuit AND 2 is opened. In addition, the output using the EXNOR of Dt21 and Dt21 is transmitted, and the output G24 is set to "0", and the transistor Mn24 is always off, so that the synchronous amplitude modulation circuit is activated. The operation of the circuit is the same as the operation of the circuit of FIG. 2 of the first embodiment, except that a sine wave synchronized with the clock C kt is added to the sine wave clock V ddq. This enables transmission of a signal subjected to synchronous amplitude modulation. An analog switch included in the output stage of the synchronous amplitude modulation circuit has an on-resistance set as in the first embodiment.

Next, when the signal A me is “0”, the signal G 2 122 becomes “0”, and the analog switches 21 and 22 become It turns off. The data D t 21 is the signal G 23

Data 'D t 21 is transmitted to 24. Accordingly, the reference clock C k 21 becomes a noise impedance, the NRZ output circuit is activated, and a DC voltage is applied to the sine wave clock V ddq. As a result, the data D t 21 is output as it is to the signal D 21, and normal NRZ code transmission becomes possible. When the circuit of the present embodiment is used for the transmission circuit of FIG. 1, when transmitting in the NRZ mode, the clock transmission terminal 5 is in a high-impedance state. k 2 — C k 8 voltage becomes constant at V tt, and this can be used as it is as reference voltage. In this case, the terminating resistors at both ends of the transmission lines 3-2 and 3-1 need not be connected.

The control signal A me of this embodiment is an enable signal for controlling the activation and deactivation of the transmission circuit 102, and is used when the transmission circuit 102 is applied to a dynamic RAM. Can be formed based on the write enable signal and CAS signal, and also can be formed from a signal that enables output to the outside of the LSI 100. . Further, the control signal A me has a function as a mode signal for selecting whether to transmit the output signal D 21 as an amplitude-modulated signal or as an NRZ code. Therefore, it is configured to receive a signal from the outside of the LSI 100 and switch the mode as necessary, and It is also possible to adopt a configuration in which the mode is determined in advance before mounting on a board or the like, and a constant potential is applied as the control signal Ame.

 Further, since the transmission circuit 102 of the present embodiment has a function of making the transmission end impedance, the transmission circuit 102 is connected to the transmission line 110 as shown in FIG. Each LSI (circuit device) 1 1 1… 1 1 8 has both a receiving circuit 1 19 and a transmitting circuit 1 20, and the clock and data transmitting and receiving terminals can be shared. Wear . One of the LSIs connected to the transmission line 110 performs transmission, and the other LSI sets the signal D0e1 to "0" and sets the transmission circuit 120 to a high impedance state. To receive. Further, even in this case, it is possible to perform transmission using the NRZ code. Since the transmission circuit 120 is configured to have a high impedance in this way, the transmission terminal and the reception terminal can be shared, and the number of LSI bins can be reduced. High-density mounting is possible.

The MOS transistors Mn21-Mn23, Mp21-Mp23, and Mn24 that constitute the analog switch are related to external LSIs. Since the variation in device characteristics affects the performance, the gate length is made larger than that of the M0N transistor used in the internal circuit 101, so that the device is less affected by the device variation. A highly reliable output circuit can be constructed. <Example 3>

 FIG. 12 is a block diagram showing the configuration of an embodiment of the signal processing device according to the present invention. In this embodiment, the transmission / reception circuit device of the present invention is applied to signal transmission of a bus in a computer which is a signal processing device.

 The computer 120 has an SRAM (statistic) for temporarily storing data such as a micro processor (MPU) 121 and a processor 121 on a node. DRAM (Dynamic Random Access Memory) that plays the role of the main memory for storing data 1 2 2 3. External storage devices such as disk 124 and display 125 are connected. The components described above, that is, the circuit devices, are connected by a node 126, a memory node 127, and an I bus 128, respectively.

High-speed data transmission is performed between the processor 122 and the cache 122, but since the cache 122 is composed of a small number of SRAMs, the data transmission form is the processor. In many cases, one-to-one transmission is performed by directly connecting the satellites 122 and the SRAMs 122 via the nodes 126. Therefore, even at the time of high-speed data transmission, the disturbance of the transmission waveform is smaller than that of the bus, so that data transmission by the normal NRZ code can be used. However, high-speed data transmission between processor 122 and SRAM 122 is required. Therefore, the sweater transmission method according to the present invention is used. When the synchronous amplitude modulation according to the present invention is used, a steady quiescent current flows through the terminating resistor R tt as shown in FIG. 1, so that the present invention can be applied from the viewpoint of consuming power. It is also possible to adopt signal transmission based on normal NRZ signals without using data transmission. In addition, when the NRZ code is used for high-speed data transmission and a terminating resistor is used, there is little difference from the synchronous amplitude modulation according to the present embodiment from the viewpoint of power consumption. Therefore, the data transmission method according to the present invention is performed.o

 On the other hand, for data transmission between the cache 122 and the main memory 123, the memory bus 127 is used to configure the main memory with a large number of DRAMs. It becomes a bus transmission via. In addition, since high-speed data transmission is required between the cache 122 and the main memory 123, the data transmission method of the present invention is used to improve the reliability of data transmission. .

The memory bus 127 is connected to the IZO bus 128 via a bus adapter 127, and is connected to the device (disk 122) on the bus 120. , Display 125, etc.) operate at a relatively low speed, so data transmission using normal NRZ code is used. A part of the computer system shown in Fig. 12 can be composed of the mounting board (motherboard) shown in Fig. 20. In this case, the noise in FIG. 20 corresponds to the memory cell 127 shown in FIG.

 Example 4>

 FIG. 13 is a block diagram showing the configuration of another embodiment of the signal processing device according to the present invention. In this embodiment, data of a plurality of systems having different transmission speeds are frequency-multiplexed and transmitted to a bus in a computer which is a signal processing device, and the synchronous amplitude modulation of the present invention is applied to the transmission. As shown in the figure, the computer includes a processor 131, a main memory controller 132, a disk device 1333, a display device 134, and a And a bus 135 for transmitting data between the circuit devices. The input / output unit of each circuit device is provided with a transmission circuit and a reception circuit that perform synchronous amplitude modulation and demodulation according to the present invention.

The main controller 1311 which is the internal circuit of the processor 1311 inputs and outputs multiple (three in the figure) pulse data of different processing speeds. The transmission / reception circuits 1311 and 12 received the data from the bus 1335 and the modulation section 1311 to 13, respectively, which synchronously amplitude-modulates and multiplexes the output data of the above three systems and outputs them to the path 135. It has demodulation units 13 1-4 that receive, separate, and convert three modulated data with different transmission speeds to digital data. 1 3 1 — a, 1 3 1 _ b, 1 3 1 — c are all synchronous amplitude modulators, 1 3 1 — d, 1 3 1 — e, 1 3 1 — f are non-synchronous modulators The filters, 1 3 1 — 6 are decoders.

 The memory control unit 132 has an internal circuit, a main memory 132-1, and a transmission / reception circuit 132-2. The transmission / reception circuit 1 3 2 — 2 includes a modulator section 13 2-a for synchronizing and amplitude-modulating a series of output data and outputting the result to the bus 13 5, and a modulation section for the driver 13 2 7. It has band-pass filters 13 2 -d and demodulators 13 2 -6 which receive the received modulation data and convert it to digital data.

 The disk unit 13 3 has a disk controller 13 3-1 as an internal circuit and a transmitting and receiving circuit 13 3-2 having a transmitting and receiving circuit 13 3-2. Modulators 13 3-b and 13 3-7, which perform synchronous amplitude modulation and output to bus 13 5, respectively, receive the received modulated data, and convert it to digital data. Bandwidth filter 1 3 3-e and decoder 1 3 3-6 are provided.

The display device 134 has a transmission / reception circuit 134-4 as an input / output circuit. The transmitter / receiver circuits 1 3 4-2 are modulator sections 1 3 4-b and 1 3 4-7, which modulate a series of output data with synchronous amplitude and output them to the bus 13 5. And a band-pass filter 134-f for receiving the received modulated data and converting the data into data, and a demodulator for a decoder 134-16. Transmission lines 135 are parallel lines, each having a reference clock transmission line and a data transmission line. Although not shown, a reference clock generation circuit is provided in each of the circuit devices S 13 1,.

 Fig. 14 (a) shows the sine wave of the reference clock used for data transmission at three transmission speeds of the signal processing device of Fig. 13. The order in which the operation speed of each circuit device is slow is the order of the disk device (FD) 133, the display control device (DCR) 134, the main memory (MM) 132, and the reference clock. The frequency of the shock is assigned. Figure (b) shows the frequency range assigned above. For example, a disk device (FD) 133 may have about 20 MHz to 30 MHz, and a display controller (DCR) 134 may have about 50 MHz to 100 MHz. Approximately 150 Hz to 300 Hz is divided by the memory (MM) 13 32.

 FIG. 15 is a circuit diagram showing the configuration of the above bandpass filter. The non-linear filter is configured by combining a low-nos filter 150 L and a high-no filter 150 H. The mouth filter 150 L and the noise filter 150 H are respectively composed of two capacitors (C, C 1, C 2) 15 1 a to 15 1 c and 2 It is composed of two resistance elements (R, Rl, R2) 152a to 152c and an op-amp (OP) 1553a to 1553b.

For low-pass filter 150 L, input terminal 154 a The received data signal is input to two resistors 15 2 a and an op-amp 15 3 a connected in series from the output terminal 0 (OUT) 15 5 a and an op-amp 15 3 a Negative feedback is applied to the input of a. It is also connected to the middle point between the two resistors 152a via the capacitor 151a. The cut-off frequency f 0 of this Lonos filter 140 L is

 1

 2 π C 1 C 2 R

And The Q value Q is

1 C 1

 Q =-——

 2 C 2.

 In the noise filter 150 H, the operational amplifier 1 is connected from the input terminal 154 b via two equal capacitors 15 1 c connected in series. A signal is input to 53b, and a part is negatively fed back from the output terminal 1555b to the input of the op-amp 1553b. It is also connected to the middle of two capacitors 15 1 c via a resistor 15 2 b.

The cut-off frequency f ₀ of the noise filter 150 H is 2 κ C \-C 2 R

And The Q value Q is

1 R 1

 Q = —— — ——

 2 R 2

And Thus, the cut-off frequency of the low-pass filter 15 OL and the low-pass filter 150 H is determined by the capacitors 15 1 a to l 51 c and the resistor 1. It can be set by the values of 52a to 152c. FIG. 16 is a timing chart showing an operation example of the CPU transmitting circuit in FIG. 13. In the transmitter / receiver circuit 13 1 3 in FIG. 13, the modulator 1 3 1 — a, b, and c have NRZ code data S 1, S 2, and 髙 ぃ in order of frequency.

The signal of S3 is subjected to synchronous amplitude modulation using the sine waves of frequencies f1, f2, and f3 in Fig. 14, respectively.

16 Modulation data f ml, f m2 and f m 3 are obtained. These modulation data f ml, f m2, and f m3 are frequency-multiplexed by a multiplexing circuit 135 and transmitted as a signal to a bus 135. Conversely, circuit device 1 3 2

When the modulated data fml, fm 2 and fm 3 are output to the path 13 5 from 13 3 and 13 4 respectively, The circuit 1 3 1 — 3 demodulation unit 1 3 1 — 4 band pass filter 1 3 1 — d, f, and c separate these components and use the NRZ code according to the decoda 1 3 1 — 6. To S l, S 2 and S 3.

 As described above with reference to FIGS. 13 to 16, the signal processing device (computer) according to the fourth embodiment includes a multiplexing device, and a plurality of circuit devices and CPUs having different operation speeds. Since signals are multiplexed and transferred between devices, a signal of a device with a low operating speed and a signal of a device with a high operating speed can exist on the same bus at the same time. Therefore, a plurality of devices having different operation speeds can use the same bus without the bus being occupied by a device having a low operation speed and the operation of another device being prevented. Yes The system can be sped up. In particular, when synchronous amplitude modulation using a sine wave is performed, the multiplexing circuit can be realized by a wire-OR circuit, and the frequency separation is configured by a simple filter as shown in Fig. 15. Therefore, it can be easily formed on LSI.

 Also, only a single system bus 135 is sufficient, and the mounting area can be reduced as compared with the conventional technology in which a dedicated bus is provided for each operation speed. It is also easy to apply.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and the gist of the present invention is as follows. Various changes can be made without departing from the scope. In the embodiment, an example has been described in which one bit of data is transmitted every half cycle of the reference clock. However, one bit of data is transmitted every one cycle. May be used.

 As the reference clock, a sine wave or a pulse waveform other than a waveform approximating it can be used. In this case, although some problems remain in the high-frequency distortion, the reference clock Ck1 and the modulation data D1 are obtained from the external clock Vddq, so that the reference clock Ck1 and the modulation data Dk1 are obtained. It is easier to synchronize D 1. Furthermore, since the external clock V ddq force, the reference clock C k1, and the modulation data D 1 are formed by using circuit elements arranged in the same LSI, the characteristics of the LSI are reduced. It is less susceptible to variations and allows accurate data transmission without being affected by variations in the characteristics of circuit elements.

 Furthermore, in the case of multiplexing and transmitting data of a plurality of systems shown in Fig. I3, an example of three systems has been described, but the number is not limited.

Claims

Range of W

 1. In a data transmission method in which a binary digital data signal to be transmitted by a transmitting section is modulated, transmitted via a transmission line, and demodulated by a receiving section, the digital data signal is transmitted by the transmitting section. Is compared with the level of the reference clock signal having a constant period, and the amplitude is higher than the level of the reference clock signal according to the binary information of the digital data signal. Synchronous amplitude modulation for converting to a large or small voltage waveform modulated data signal is performed, and the above-mentioned reference clock signal and the above-mentioned modulated data signal are simultaneously transmitted on the transmission line, and received by the receiving section. A data transmission method characterized by demodulating the modulated data into the binary digital data signal using the reference clock signal.

 2. The reference clock signal has a sine waveform having the same phase and the same period as the data signal, and the modulation data signal has a sine waveform signal representing the amplitude of the sine signal. The data transmission method according to claim 1, wherein the signal is controlled by a binary digital data signal of the signal.

3. The binary digital data signal is data of a plurality of systems having different transmission speeds, and a plurality of modulated signals modulated by the transmission unit are frequency-multiplexed and transmitted to the transmission line. The data transmission method according to claim 2, characterized in that:

4. A signal source for generating a binary digital data signal to be transmitted, a reference clock signal generating circuit for generating a reference clock signal having a predetermined amplitude, and the digital data described above. A synchronous amplitude modulation circuit for converting the signal into a signal having a magnitude corresponding to the level of the reference clock signal to generate a modulation data signal, and a transmission line for transmitting the reference clock signal and the modulation data signal. A transmission circuit device characterized by having a transmission circuit having a terminal for outputting a signal to the transmission circuit.

 5. The reference clock signal is a signal having a sinusoidal waveform, and the modulation data signal varies the amplitude of the sinusoidal waveform according to information of a binary digital data signal. 4. The transmission circuit device according to claim 3, wherein the transmission circuit device is a signal.

 6. The signal source is an internal circuit for processing a data signal, and the internal circuit, the reference clock signal generation circuit, and the synchronous amplitude modulation circuit are formed on the same LSI chip. 6. The transmission circuit device according to claim 5, wherein:

7. The reference clock signal generation circuit generates the reference clock signal based on a first external clock signal applied from outside the LSI chip. The synchronous amplitude modulation circuit comprises a voltage-dividing resistance element for reducing the amplitude of the first external clock signal. The synchronous amplitude modulation circuit responds to the information of the digital data signal. H signal 7. The transmitting circuit device according to claim 6, wherein the transmitting circuit device is configured by a circuit that changes the amplitude.

 8. The transmission circuit further includes a first output circuit that outputs the binary digital data signal as a pulse signal to the transmission line, the synchronous amplitude modulation circuit or the first circuit. The transmission circuit device according to any one of claims 5 to 7, further comprising a switching control circuit that selectively drives one of the two.

 9. The binary digital data signal includes a plurality of data sequences having different transmission speeds, and the synchronous amplitude modulation circuit and the reference clock signal generation circuit correspond to the plurality of data sequences. 8. The transmission circuit device according to claim 5, wherein a plurality of circuits are provided, and a circuit for multiplexing the outputs of the plurality of synchronous amplitude modulation circuits is further added. .

10. Synchronized with the reference clock signal and the reference clock signal, the information of the binary digital data signal is represented by the magnitude of the amplitude of the reference clock signal. A terminal for receiving a modulation data signal; a detection circuit for detecting the magnitude of the amplitude of the reference clock signal from the modulation data signal using the reference clock signal; A receiving circuit device comprising a converting circuit for converting an output of a detecting circuit into a binary digital data signal, and a receiving circuit including the converting circuit.

11. The feature is that the detection circuit is constituted by a differential amplifier to which the reference clock signal and the modulation data signal are inputted, and the conversion circuit is constituted by a latch circuit. The receiving circuit device according to claim 10, wherein:

 12. The filter according to claim 10, wherein a filter is provided on an input side of the detection circuit so as to pass frequency components of the reference clock signal and the modulation data signal. The receiving circuit device according to claim 1.

 13. The method according to claim 10, wherein the receiving circuit and an internal circuit for processing an output of the receiving circuit are configured by a single LSI chip. Receiving circuit device.

 14.2 A transmission circuit having a first internal circuit that outputs a binary digital data signal and a transmission circuit that converts the binary digital data signal into a signal suitable for transmission A transmission / reception device comprising: a device; a reception circuit device; and a transmission line connecting the transmission circuit device and the reception circuit device.

The transmission line has first and second transmission lines, the transmission circuit modulates the binary digital data signal, and outputs the modulated signal to the first transmission line; And a reference clock generation circuit for transmitting a reference clock signal having a predetermined amplitude in synchronization with the data signal to the second transmission line. The digital data signal is configured to be converted into a modulated data signal representing the magnitude of the amplitude with respect to the reference clock signal, and

 The reception circuit device includes: a reception circuit connected to the first transmission line and the second transmission line; and a second internal circuit receiving an output signal of the reception circuit. A circuit configured to convert the modulated data signal into a binary digital data signal corresponding to the magnitude of the amplitude with respect to the reference clock signal. The transmitting and receiving device that is the feature.

 15. The signal transmitting and receiving device further includes an external clock generation circuit for generating a first external clock signal having a sine wave shape, and the external clock generation circuit. A third transmission line connecting the circuit and the transmission circuit device and supplying an external clock signal to the transmission circuit device;

 The reference clock generation circuit is configured to divide the first external clock signal to generate the reference clock signal,

 The modulation circuit modulates the digital data signal by changing the amplitude of the first external clock signal in accordance with the information of the binary digital data signal. 15. The transmission / reception device according to claim 14, wherein the transmission / reception device is configured to be configured as follows.

1 6. The above transmitting and receiving device further has a fourth transmission path. The external clock generation circuit has an oscillation circuit that oscillates at a predetermined frequency and a filter circuit that filters the oscillation output of the oscillation circuit. The output of the oscillation circuit is The signal is supplied to the first internal circuit and the modulation circuit via the fourth transmission path, and the output of the filter circuit is supplied to the reference clock via the third transmission path. The transmission / reception device according to claim 15, characterized in that the transmission / reception device is configured to be supplied to a hook generation circuit.

 17. The reference clock generation circuit has a resistance element for receiving a signal corresponding to the first external clock, and the modulation circuit includes the first external clock. A variable resistance element that receives a signal corresponding to the signal and changes the resistance value according to the information of the digital data signal, and the first and second transmission lines each have a terminating resistance. The reference clock generation circuit outputs a signal obtained by dividing a signal corresponding to the first external clock by the resistance element and the termination resistor, and outputs the signal obtained by dividing the signal corresponding to the first external clock by the resistance element and the termination resistor. The modulation circuit is configured to output a signal obtained by dividing a signal corresponding to the first external clock by the variable resistance element and the termination resistor. The transmission / reception device according to claim 16.

18. The modulation circuit is configured to convert the digital data signal into a voltage having a magnitude larger than that of the reference clock signal and to output the converted voltage, and the reception circuit is configured to convert the digital clock signal into the reference clock signal. 15. The transmission / reception apparatus according to claim 14, further comprising: a differential amplifier circuit that compares a voltage between the transmission signal and an output signal of the transmission circuit. .

 19. A microprocessor, a first storage device for storing data used for processing of the microprocessor, the first storage device, and first and second memories. In the signal processing device, which is connected via the transmission line of the first storage device and stores the data to be transferred to the first storage device, the first pathological device is And a transmitting circuit for outputting data via the second transmission line.

 The transmission circuit is configured to output a reference clock signal having a predetermined amplitude to the second transmission line based on an external clock signal supplied from the outside, A signal processing device characterized by being configured to change the amplitude of the external clock signal and output the data as data to the second transmission line.

 20. The first storage device is constituted by a static random access memory, and the second storage device is constituted by a dynamic random access memory. 22. The signal processing apparatus according to claim 20, wherein the signal processing apparatus is configured by:

21. The microprocessor and the first storage device are connected via a third transmission line, and the first storage device is connected to the third transmission line. Is configured to transmit the digital data signal desired through the 21. The signal processing device according to claim 19, wherein the digital data signal is output as a signal corresponding to the magnitude of a voltage with respect to a DC level. 22. The microprocessor and the first storage device are connected via third and fourth transmission paths, and the first storage device is supplied from outside. A reference clock signal having a predetermined amplitude is formed based on the external clock signal to be generated, and the amplitude of the external clock signal is controlled. The first storage device is configured to form a digital signal stored in the first storage device.

 The reference clock signal is configured to be supplied to the microphone port processor via the transmission line (4), and the digital data signal is 21. The signal processing apparatus according to claim 19, wherein the signal processing apparatus is configured to be supplied to the microprocessor via the transmission line according to claim 3. .

23. The signal processing device further includes an oscillation circuit for forming a clock signal having a predetermined frequency, and filtering of the external clock signal. And a filter circuit for forming an external clock signal having less high-frequency components than the clock signal. The clock signal and the external clock signal are The signal according to claim 19 or claim 20, wherein the signal is configured to be supplied to the first storage device and the second storage device. Processing equipment.

 24. Perform signal processing and convert a plurality of digital data signals of different transmission speeds to a plurality of signal processing devices connected by the bus via a single transmission line to the digital processing device. In a signal processing device having a micro processor for transmitting and receiving a total data signal,

The above-mentioned micro processor modulates the above-mentioned plural kinds of digital data and multiplexes the frequency-multiplexed modulated data to the above-mentioned transmission line. A first transmitting circuit having a transmitting section, a separating section that separates a plurality of types of frequency-multiplexed data input from the transmission line, and a demodulating section of the modulated data. A first receiving circuit having a demodulating unit and a first receiving circuit;

Each of the plurality of signal processing devices separates a digital data signal of a specific transmission speed from among a plurality of types of data output from the microphone processor. A second receiving circuit having a filter to be demodulated, a demodulation unit for demodulating data from the output of the filter, and modulating and outputting data to be transmitted to the transmission line. A signal processing device having a _second transmission circuit.