WO1996024944B1 - Methods of mechanical and electrical substrate connection - Google Patents
Methods of mechanical and electrical substrate connectionInfo
- Publication number
- WO1996024944B1 WO1996024944B1 PCT/US1996/001657 US9601657W WO9624944B1 WO 1996024944 B1 WO1996024944 B1 WO 1996024944B1 US 9601657 W US9601657 W US 9601657W WO 9624944 B1 WO9624944 B1 WO 9624944B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrates
- bond
- recited
- wire
- tail
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract 46
- 239000004065 semiconductor Substances 0.000 claims 9
- 239000000853 adhesive Substances 0.000 claims 3
- 230000001070 adhesive Effects 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 3
- 239000011800 void material Substances 0.000 claims 3
- 210000001138 Tears Anatomy 0.000 abstract 2
Abstract
The disclosure describes a method of attaching and electrically connecting first and second planar substrates, wherein the first and second substrates have inwardly-facing surfaces with matching patterns of bond pads (72). The method includes adjusting a wire bonder's tear length to a setting which leaves a projecting tail (80) of severed bond wire at a terminating wedge bond connection. Further steps include making a wedge bond to an individual bond pad of the first planar substrate with bond wire from the wire bonder, and then severing the bond wire adjacent said wedge bond. The adjusted tear length of the wire bonder results in a tail of severed bond wire which projects from said wedge bond and said individual bond pad. Subsequent steps include positioning the first and second planar substrates with their inwardly-facing surfaces facing each other, aligning the matching bond pad patterns of the first and second planar substrates, and pressing the first and second planar substrates against each other. The bond wire tail (80) deforms between the bond pads of the first and second planar substrates to conductively bond therebetween.
Claims
1. A method of attaching and electrically connecting first and second substrates, the first and second substrates having inwardly-facing surfaces with at least one pair of opposing first and second electrically conductive bonding areas, the method comprising:
providing a wire wedge bond onto at least one of the opposing first and second bonding areas, the wire wedge bond having a tail of severed bond wire projecting from said wedge bond and said at least one bonding area;
positioning the first and second substrates with their inwardly-facing surfaces facing each other;
aligning the first and second bonding areas of the first and second substrates, the bond wire tail being interposed between the first and second bonding areas; and
pressing the first and second substrates against each other, the bond wire tail deforming between the first and second bonding areas of the first and second substrates to conductively bond therebetween.
2. A method as recited in claim 1 wherein at least one of the substrates is a semiconductor die.
3. A method as recited in claim 1 wherein the first substrate is a semiconductor die .
4. A method as recited in claim 1 wherein the second substrate is a semiconductor die.
5. A method as recited in claim 1 and further comprising applying heat during the pressing step to bond between the first and second substrates.
6. A method as recited in claim 1 and further comprising applying vibration during the pressing step to bond between the first and second substrates.
7. A method as recited in claim 1 and being void of any separate adhesive interconnect between the bonding areas of the first and second substrates.
8. A method of attaching and electrically connecting first and second substrates, the first and second substrates having inwardly-facing surfaces, the method comprising:
providing a wire wedge bond onto at least one of the inwardly-facing surfaces of the first and second substrates, the wire wedge bond having a tail of severed bond wire projecting from said wedge bond and said at least one surface;
positioning the first and second substrates with their inwardly-facing surfaces facing each other, the bond wire tail being interposed between the first and second substrates; and
pressing the first and second substrates against each other, the bond wire tail deforming between the first and second substrates to conductively bond therebetween.
9. A method as recited in claim 8 wherein at least one of the substrates is a semiconductor die.
10. A method as recited in claim 8 wherein the first substrate is a semiconductor die.
11. A method as recited in claim 8 wherein the second substrate is a semiconductor die .
12. A method as recited in claim 8 and further comprising applying heat during the pressing step to bond between the first and second substrates.
13. A method as recited in claim 8 and further comprising applying vibration during the pressing step to bond between the first and second substrates.
14. A method as recited in claim 8 and being void of any separate adhesive interconnect on the bond wire tail.
15. A method of attaching and electrically connecting first and second substrates, the first and second substrates having inwardly-facing surfaces with at least one pair of opposing first and second electrically conductive bonding areas, the method comprising:
providing a projecting tail of a conductor from at least one of the opposing first and second bonding areas;
positioning the first and second substrates with their inwardly-facing surfaces facing each other;
aligning the first and second bonding areas of the first and second substrates, the projecting conductor tail being interposed between the first and second bonding areas; and
pressing the first and second substrates against each other, the projecting conductor tail deforming between the first and second bonding areas of the first and second substrates to conductively bond therebetween.
16. A method as recited in claim 15 wherein at least one of the substrates is a semiconductor die.
17. A method as recited in claim 15 wherein the first substrate is a semiconductor die.
18. A method as recited in claim 15 wherein the second substrate is a semiconductor die.
19. A method as recited in claim 15 and further comprising applying heat during the pressing step to bond between the first and second substrates.
20. A method as recited in claim 15 and further comprising applying vibration during the pressing step to bond between the first and second substrates.
21. A method as recited in claim 15 and being void of any separate adhesive interconnect between the bonding areas of the first and second substrates.
22. A method of attaching and electrically connecting first and second substrates, the first and second substrates having inwardly-facing surfaces, the method comprising: 
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP19960906318 EP0808508B1 (en) | 1995-02-10 | 1996-02-08 | Methods of mechanical and electrical substrate connection |
| DE69618177T DE69618177T2 (en) | 1995-02-10 | 1996-02-08 | METHOD FOR MECHANICAL AND ELECTRICAL CONNECTION OF A SUBSTRATE |
| AT96906318T ATE211301T1 (en) | 1995-02-10 | 1996-02-08 | METHOD FOR MECHANICALLY AND ELECTRICALLY CONNECTING A SUBSTRATE |
| JP52440596A JP3619254B2 (en) | 1995-02-10 | 1996-02-08 | Method for connecting mechanical and electrical substrates |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/386,646 US5537738A (en) | 1995-02-10 | 1995-02-10 | Methods of mechanical and electrical substrate connection |
| US08/386,646 | 1995-02-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1996024944A1 WO1996024944A1 (en) | 1996-08-15 |
| WO1996024944B1 true WO1996024944B1 (en) | 1996-09-19 |
Family
ID=23526465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1996/001657 WO1996024944A1 (en) | 1995-02-10 | 1996-02-08 | Methods of mechanical and electrical substrate connection |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US5537738A (en) |
| EP (1) | EP0808508B1 (en) |
| JP (1) | JP3619254B2 (en) |
| KR (1) | KR100384990B1 (en) |
| AT (1) | ATE211301T1 (en) |
| DE (1) | DE69618177T2 (en) |
| WO (1) | WO1996024944A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100437437B1 (en) * | 1994-03-18 | 2004-06-25 | 히다치 가세고교 가부시끼가이샤 | Semiconductor package manufacturing method and semiconductor package |
| US5766053A (en) * | 1995-02-10 | 1998-06-16 | Micron Technology, Inc. | Internal plate flat-panel field emission display |
| US5763998A (en) * | 1995-09-14 | 1998-06-09 | Chorus Corporation | Field emission display arrangement with improved vacuum control |
| US6089442A (en) * | 1996-04-10 | 2000-07-18 | Canon Kabushiki Kaisha | Electrode connection method |
| US5688708A (en) * | 1996-06-24 | 1997-11-18 | Motorola | Method of making an ultra-high vacuum field emission display |
| US6045711A (en) * | 1997-12-29 | 2000-04-04 | Industrial Technology Research Institute | Vacuum seal for field emission arrays |
| US6255769B1 (en) | 1997-12-29 | 2001-07-03 | Micron Technology, Inc. | Field emission displays with raised conductive features at bonding locations and methods of forming the raised conductive features |
| US6765652B1 (en) | 1998-01-12 | 2004-07-20 | Micron Technology, Inc. | Forming thermally curable materials on a support structure in an electronic device |
| US6392304B1 (en) | 1998-11-12 | 2002-05-21 | United Memories, Inc. | Multi-chip memory apparatus and associated method |
| US6537400B1 (en) | 2000-03-06 | 2003-03-25 | Micron Technology, Inc. | Automated method of attaching flip chip devices to a substrate |
| EP1228540B1 (en) * | 2000-06-29 | 2010-09-29 | Koninklijke Philips Electronics N.V. | Optoelectric element |
| US6439115B1 (en) * | 2000-08-30 | 2002-08-27 | Micron Technology, Inc. | Uphill screen printing in the manufacturing of microelectronic components |
| GB2575038B (en) * | 2018-06-25 | 2023-04-19 | Lumentum Tech Uk Limited | A Semiconductor Separation Device |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387283A (en) * | 1981-08-03 | 1983-06-07 | Texas Instruments Incorporated | Apparatus and method of forming aluminum balls for ball bonding |
| FR2593953B1 (en) * | 1986-01-24 | 1988-04-29 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A DEVICE FOR VIEWING BY CATHODOLUMINESCENCE EXCITED BY FIELD EMISSION |
| US5015912A (en) * | 1986-07-30 | 1991-05-14 | Sri International | Matrix-addressed flat panel display |
| US4857799A (en) * | 1986-07-30 | 1989-08-15 | Sri International | Matrix-addressed flat panel display |
| US4764848A (en) * | 1986-11-24 | 1988-08-16 | International Business Machines Corporation | Surface mounted array strain relief device |
| US5014111A (en) * | 1987-12-08 | 1991-05-07 | Matsushita Electric Industrial Co., Ltd. | Electrical contact bump and a package provided with the same |
| US5063327A (en) * | 1988-07-06 | 1991-11-05 | Coloray Display Corporation | Field emission cathode based flat panel display having polyimide spacers |
| US4923421A (en) * | 1988-07-06 | 1990-05-08 | Innovative Display Development Partners | Method for providing polyimide spacers in a field emission panel display |
| US4948030A (en) * | 1989-01-30 | 1990-08-14 | Motorola, Inc. | Bond connection for components |
| US5246159A (en) * | 1989-07-19 | 1993-09-21 | Nec Corporation | Method for forming a bump by bonding a ball on an electrode of an electronic device and apparatus for forming the same |
| US5075591A (en) * | 1990-07-13 | 1991-12-24 | Coloray Display Corporation | Matrix addressing arrangement for a flat panel display with field emission cathodes |
| US5157304A (en) * | 1990-12-17 | 1992-10-20 | Motorola, Inc. | Field emission device display with vacuum seal |
| JP2852134B2 (en) * | 1991-02-20 | 1999-01-27 | 日本電気株式会社 | Bump forming method |
| US5140219A (en) * | 1991-02-28 | 1992-08-18 | Motorola, Inc. | Field emission display device employing an integral planar field emission control device |
| US5151061A (en) * | 1992-02-21 | 1992-09-29 | Micron Technology, Inc. | Method to form self-aligned tips for flat panel displays |
| JPH06244231A (en) * | 1993-02-01 | 1994-09-02 | Motorola Inc | Airtight semiconductor device and manufacture thereof |
| US5249732A (en) * | 1993-02-09 | 1993-10-05 | National Semiconductor Corp. | Method of bonding semiconductor chips to a substrate |
-
1995
- 1995-02-10 US US08/386,646 patent/US5537738A/en not_active Expired - Lifetime
-
1996
- 1996-02-08 WO PCT/US1996/001657 patent/WO1996024944A1/en active IP Right Grant
- 1996-02-08 DE DE69618177T patent/DE69618177T2/en not_active Expired - Lifetime
- 1996-02-08 EP EP19960906318 patent/EP0808508B1/en not_active Expired - Lifetime
- 1996-02-08 KR KR1019970705517A patent/KR100384990B1/en not_active IP Right Cessation
- 1996-02-08 AT AT96906318T patent/ATE211301T1/en not_active IP Right Cessation
- 1996-02-08 JP JP52440596A patent/JP3619254B2/en not_active Expired - Fee Related
- 1996-05-03 US US08/642,581 patent/US5653017A/en not_active Expired - Lifetime
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