WO1983004141A1 - Three dimensional integrated circuit structure - Google Patents

Abstract

A number of techniques are disclosed to enable the manufacture of ultra high capacity three dimensionally arranged integrated circuits. For one embodiment these techniques may include: 1) Layer to layer power clocking. 2) Multilayering by the total vertical parallel connection of identical sections. 3) Reliable lamination of integrated circuit sections by including a "hydraulic" cushion between each section 4) with thermally resilient vertical interconection via the intermediary of a stackable semiconductor bonding tape. 5) Handling individually fragile sections by gravity control. 6) Yield enhancement by multilayering ready fabricated sections which have already passed functional test. 7) Mass vertical interconnection of semiconductor carriers by capillary action soldering from the outer segmented faces of the stack of sections and, 8) for some versions, cooling the product during use by enclosing a long string of stacked sections in a tube through which coolant fluid is pumped cyclically.

Description

THREE DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE

Background art relevant for the understanding of the invention

Silicone gel and RTV silicone rubber have already been used successfully for the encapsulation of separate chips either singly or in two dimensional arrays.

The use of fluorinated hydrocarbons for liquid cooling is also known. See, for example, UK patent 1 462 748 Semiconductor bonding tapes are also in use for bonding chips single or in strips and for bonding chips to printed circuit boards in two dimensional arrays. (eg. patents 4,048, 438 (USA) 4,109,096 (USA)

The background information required for an understanding of gravity control can be traced back to the discovery that all material bodies (unless held back) will behave identically in earth's gravitational field irrespective of shape, size, composition or mass and the interpretation of this discovery in Einstein's formulation of the General Relativity.

Earlier descriptions for stacking chips can be found in patents: 1,212,279 (UK) 1,326,758 (UK)

3,370,203 (USA) 3,746,934 (USA) and the PCT application publication no.WO 81/00949 but some of these are quite impractical.

Patents for earlier techniques for stacking of whole wafers include the two IBM patents

1 , 465 , 424 (UK ) and 1 , 462 , 748 (UK ) Introduction

The theoretical advantages of greater convenience, higher speed, lower weight, lower volume and lower material costs of three dimensionally arranged integrated circuits have not been realised in practice for substantial commercial manufacture to date because of a variety of problems encountered in stacking chips or in producing a multitude of circuit layers on a single wafer substrate. It now seems likely that a combination of new techniques will enable such structures to be manufactured cost effectively by a process of subassembly which is described in this patent specification.

The various drawings given are all stylised to a greater or lesser extent and dimensional accuracy is not necessarily implied. Since many of the drawings are included only to elucidate a particular aspect of one embodiment of the invention, intermediate forms between examples, and versions combining features found in the various examples are generally implied as are versions combining these features with the known art not specifically described here. Various permutations with IC up, IC down, beam leads above tape substrate and beam leads below tape substrate are also possible and many examples can also be rotated about any axis without detracting from the principles of the invention. The number of input and output leads have been kept low in number in most drawings along with the number of sections depicted in any particular stack in order to keep the drawings both simple and clear. Many of the drawings are shown in either a 2D cross sectional slice or a 3D perspective of a sliced section.

Since it would mask detail, cross sectional hatching of the drawings is omitted except in fig 13. Cross sections. are usually obvious when the drawings are considered in relationship to each other.

Description of 1st Embodiment

When wired to a suitable power supply, the device of fig 16 is the cheapest, simplest, and above all, fastest memory building block which we have used to date for artificial intelligence machinery since it is a large, reliable, non volatile RAM. There is no memory loss during power cuts or when disconnected froε the mains. For 'one-off production it is also easily the fastest to construct and with the lowest cost of additional parts (considered in terms of PCB area, board to board connectors and board to board structural supports).

A number of state-of-the-art static CMOS RAMS are stacked and almost totally parallel interconnected without any additional parts except for interconnection solder on the vertically aligned output leads. The individual

pins having been bent outwards or cut, and then connected to a

decoder by flying leads. Since these low power chips dissipate substantially less power when deselected than when selected and since at most one chip in the stack will be selected at any particular time, no thermal dissipation problems occur unlike in earlier chip stacking attempts in the prior art. There are many advantages in taking this approach. A much smaller PCB area is required. The memory can often be expanded without adding any extra PCB and may also be repaired in most cases without the need for desoldering and extricating an integrated circuit. (The

of the offending chip is tied to V+ and an extra chip placed on the top of the stack). The vertical connection tracks are at more than double the spacing than the spacing needed to interconnect the packages in an efficient planar array so that the possibility of short circuits between these tracks is greatly reduced as is any potential tendency to crosstalk and capacitive loading. Since these conductor tracks are also shorter than they would be in a planar array, the magnitude of these benefits is amplified.

For volume manufacture it would be preferable to incorporate decoding of higher order address lines on each chip to effect the

signal for each layer so that all layers may be totally parallel interconnected, and since it is vastly more economical to produce a stack of identical sections, it is preferable if the selection of layers is achieved by an identical device on each layer. One such device could be a programmable comparator comprising inputs A connected to higher order address lines (layer address lines) and inputs B connected to a number of program once programmable bits.

It is envisaged that the simplest method for programming the program once side of the programmable comparator for each section could be to automatically program each section immediately prior to positioning on the stack such that layers l to N could be programmed with numbers 0 to N-l.

While the probability that a fault in one or more of these programmable cells in a given stack can be calculated to be low even for a stack 256 layers deep

(8 bit comparator) it is instructive to consider the consequences if an error of this type does occur. If there is an error on the programmed side of the comparator for one layer, when access to that layer is attempted, nothing will be accessed. When access to one other layer is attempted, that layer and the faulty layer will turn on simultaneously. However, since it is already known that all the normally accessible memory cells ofboth these layers function correctly, the observable result will be a doubling of the output drive capability during read since the same data will have been written into both layers during write. Therefore the stack could be repaired by adding one extra layer to the stack.

Even if each layer is to be retested after layer position programming and prior to its incorporation in the stack, this test will be much quicker than a test of all the memory cells in the layer since one only needs to test for correct layer turn on and this can be a virtually simultaneous process of program and validate. Program and validate programming of the layer address comparator could be done electrically utilising, for example, any of the known techniques for producing PEQMs or EEPROMs.Alternatively, it can also be achieved with the normal static RAM cells if, for example, a large enough capacitor is included under the chip lead frame interconnecting the two power supply rails, with the program once pin connected via an on chip resistor to one power supply rail to prevent an indeterminate state, provided that the completed stack is connected to a suitable power supply soon after the position programming and stack creation (ie. before the capacitor discharges).

Since CMOS gates only dissipate significant power during logic level transitions, if the layer address lines are connected to the highest order address lines of a central processor, the toggle rate of these information lines will usually be minimised thereby minimising the power dissipated in each comparator.

For lower pin counts and therefore lower cost and size, these highest order address bits are held in an on chip segment latch as in fig 24. This enables a single extra bond out pad on each chip (to be parallel connected chip to chip) 'to completely map or encode up to an NxN word array of cubic RAMs where N words is the largest viable memory capacity which can be manufactured commercially for a 2D chip. The same technique is used for the 'program during stacking' or 'program once' side of the comparator. This enables a single chip design to be targeted for an extremely wide range of future computer memory size requirements thus eventually further reducing costs due to higher sales volume.

A more efficient method of stacking chips can be achieved via the intermediary of a stackable bonding tape rather than by stacking packaged chips. This will mean that, although currently more expensive, it is possible to contain all the information normally held in Winchester disks in a compact robust non volatile

RAM with no risk of information loss during power cuts, no risk of failure of mechanical parts, and very much faster access to information, coupled with much faster and more reliable machine learning.

The additional overhead in terms of chip area required for the new features in figure 24 is considerably less than for the self-test circuitry already suggested in the industry.

The optional inclusion of a capacitor between the two supply rails on a leadframe is also already known in the art, but is used for transient suppression.

TAPE STRUCTURE Figs 1,4,7,8,10,12,15give a variety of possible implementations of a stackable bonding tape structure which comprises conductor tracks, and an insulator of sufficient thickness that a central chip cavity is large enough to accommodate a chip's thickness as well as length and breadth, and where conductor tracks on one side of the insulating substrate are continuous with conductor points on the opposite side of the substrate,or where the conductor tracks extend beyond the insulating substrate on the outer periphery such that they can be bent down to connect with a neighbouring section (Fig 2).

The inner conductor leads to the chip may be manufactured curved or bent in the horizontal plane and they can also be mechanically deformed to be curved or bent in the vertical plane as is already practiced in the known art. One or more of these leads may also be bonded to a metal backing plate bonded to the back surface of the chip to provide a low ohmic contact to the substrate and, if two or more of the leads are used for this purpose it is also possible to make these leads stronger than the bond out leads in order to effect a cradle for the chip (Figs 4, 5). An insulating membrane on the underside of the backing plate can be included to guarantee that adjacent sections do not accidentally interconnect and can also be incorporated between eaαh. chip even if no backing plate is used. It is desirable to add a cushioning substance such as silicone gel or RTV silicone rubber to each chip of a stack before the next chip is place on top in order to achieve a resiliently supported finished structure. While an elastomer such as polyimide has advantages for use as the insulating substrate of the tape, the cost of the substrate can be reduced while retaining these advantages by using a lower cost substrate such as the substances commonly used in PCB manufacture, and this can be coated with an elastomer. Under such schemes, it is also possible to have the thin elastomer extending further into the cavity than the bulk substrate in order to help hold the bond out leads in the correct relative positions prior to chip bonding (Figs 8 A to H, Fig 1 and Fig 15). It will be appreciated that with an appropriate choice of geometries it is possible to produce a section with any desired degree of freedom from thermally induced strain. However as the degree of thermal reliability is increased, the risk of failure due to excessive deformation during handling rises. Because of this, detailed handling considerations are described later and a device is also revealed which enables each section to effectively float in gravity-free conditions when not fully supported. While a totally parallel connected stack of identical

CMOS memory chips with programmable layer address comparators is envisaged as the ideal candidate for high volume 3D manufacture, it is within the scope of this invention that other chips exhibiting a high but incomplete level of parallelism may be stacked to advantage. In order to accommodate information lines which cannot be totally wired in parallel a number of variants on the standard lead termination are diagrammed in fig 6. Lead (A) enables a chip connected to a higher tape section to be connected to the outside world bypassing all lower chips.

Lead (B) enables a chip bonded to that tape section to be connected to the outside world bypassing all lower chips.

Lead (G) is the standard lead termination which enables a chip connected to that section to connect with a lower section. Lead (D) enables a lead connected to a chip on that section to connect only to higher sections (all of the previous and succeeding examples can also connect to higher sections if the leads on those higher sections are appropriately positioned). Lead (E) enables a higher section to connect to a lower section bypassing the chip connected to that section.

Lead (F) enables a chip to chip daisy chain to be accomplished.

(A daisy chain can also be accomplished by alternating CD, DC, CD, DC, between layers.)

When, as in figures 1 and 8 a layer of an elastomer such as polyimide extends further into the chip cavity than a thickened portion of the tape substrate, a means for providing additional stress relief during chip bonding and/or a means for facilitating the vertical curvature of the beam leads, such as a starburst of radiating slits in the substrate may be included as shown in figure 15

While the thickening portion of the substrate has been depicted as a single square rim, it can be more desirable for this thickened portion to be made from a number of separate strips as shown in the dotted outline of figure 15. Provided gaps are left between these strips, this technique not only facilitates the manufacture of the tape, but also enables a higher degree of thermal stress relief.

Figures 4 and 7 show some of the options available for providing vertically curved beam leads which avoid the risk of these leads contacting the rough sawn edge of the chip. Their curvature also allows further freedom for differential thermal expansion and contraction.

Figure 18 shows in detail a cross sectional view one optional facet of the construction of a multilayer structure in which the constituent integrated circuits are 'hydraulically' cushioned layer to layer during stacking by a substance applied in semifluid or gelatinous form. A ready formed insulating membrane A possibly composed of polyimide or possibly composed of RTV silicone rubber attached to the back surface of a chip or to the back surface of a chip backing plate is slightly larger than the diameter (2xR) of the chip cavity defined by the tape substrate thickener C. A small burr B running along the edge of the substrate thickener is produced when the substrate thickener is sliced into strips during the manufacture of the bonding tape. Since this burr is weaker than the supported metallic conductor track D, when the two sections are brought together the portion of the burr overlying the radial track D is flattened out or the portion of the insulating membrane A is compressed or both. The portions of the burr over the spacings between successive conductor tracks D of one section then help to fill the fine gap which could otherwise occur. Therefore each succeeding hydraulic cushion in the stack is independent, and a negligible or zero quantity of gel can escape from any cushion before the completed stack is sealed or packaged. Any small gap between vertically successive wrap around conductors D is filled as described later by capillary action soldering from the outer segmented faces of the completed stack. The stack can include a base and a lid of a form similar to the example shown in figure 13. If these, or final more robust stack terminators are made with a larger diameter than the other stack sections, this can simplify the sealing or final encapsulation of the complete stack as diagrammed in cross section in figure 19. The final sealant or encap sulant is preferably brought up approximately flush with the final stack terminators.

When a wafer is sawn up into chips, the glass passivation layer sometimes cracks or flakes off around the chip periphery exposing a rough substrate edge. The vertical curvature of beam leads D of figure 18 (or the examples of figures 4 and 7) removes the risk of these leads contacting the substrate. However when whole wafers are stacked or if a sufficiently deep metallisation is built up on the chip bond out pads it is possible to supply these leads curved or zigzagged only in the horizontal plane. If these beam leads are connected to the bond out pads by soldering it is then also possible to connect a face to face pair ofchips to each tape section. The direct face to face soldering of a pair of integrated circuits to form a 2 layer structure is already known. When face to face pairs are stacked via the intermediary of a stackable bonding tape, succeeding pairs of chips or wafers may butt against each other in the stack without causing problems (see for example figure 20). This technique is particularly useful when producing the device of figure 11 where coolant is required to percolate through the structure which is enclosed in a tube through which said coolant is pumped. INTERCONNECTION OF SECTIONS Stackable sections may be interconnected and/or connected to a leadframe or direct to a printed circuit board by soldering. The techniques used could closely parallel those currently in use for soldering leadless chip carriers eg. vapour phase reflow or jet wave soldering, and the self alignment phenomenon which occurs when the carrier is floating on molten solder is also useful.

The versions of the bonding tape which include metallic straps around the outer periphery of the section have advantages in this respect since these straps provide good heat conduction routes to transmit heat from the outside of the stack to appropriately positioned solder paste or solder preforms between each section. It is even possible to apply solder only to the outer metal faces of these 3D structures. When heated, this solder will tend to flow along the conductor/conductor interfaces between sections by capillary action thus ensuring good electrical and mechanical interconnection. This capillary phenomenon has already been used very widely in the past for producing fast reliable and economical copper/solder/ copper joints in, for example, plumbing fittings but it also works well for finer geometry joints.

Faster and more reliable joints are usually obtained by using a relatively high temperature heat source applied for a relatively short time, the speed of the operation preventing substantial heat flow well into the body of the device. It is also evident that the area on the bonding tape available for soldered interconnection is very much greater than the bond out area available on the chip so that high reliability vertical interconnection is easily achieved. Structural consideraτions for complete Device

Hodern CMCS, RAMS, RCMS and EEROMs generally dissipate less power than their NMOS or bipolar counterparts but they have the additional important advantage that when deselected, their power dissipation falls to a very low level.(CMOS RAMS also have the advantage over other RAMS that they become non volatile when wired with a suitable battery backup circuit) As all these devices are commonly manufactured in a bytewide configuration, it is a relatively straightforward matter to stack such chips with data and address lines paralleled and with successive chips occupying successive address blocks such that, during operation, only one chip in the block is selected at any one time, with a single area of significant power dissipation moving through the 3D structure when the total address space is scanned. The electrical interconnection of such a stack can be simplified by including layer address decoding on each chip to effect chip selection, and the manufacturing process can be further streamlined by using a device such as a programmable comparator for this layer address decoding to enable a common chip and a common tape design to be used for all layers of the stack and for all layers to be totally parallel connected. The layer address programming normally being accomplished prior to stacking and after the batch of chips has been screened for functional operation. Electrical or laser programming can be used. When incorporating the cushioning material between chips sufficient material can, of course, be included to completely fill each central cavity to provide a well cushioned finished product with the constituent chips still retaining a degree of freedom of independent movement caused by differential thermal expansion.

The soldered vertical interconnection of the surrounding tape sections provides a more rigid intermediate or outer casing and laminated structures face to face soldered along at least two opposing sides exhibit a much higher strength than a conventional flat P.C.B. When stacking other types, of memory, multiple microcomputers or other devices, many chips in the stack may be dissipating significant power simultaneously and it could then be desirable to immerse the structure in a liquid coolant such as the fluorinated hydrocarbons already used in the industry. The efficiency of heat transfer can be substantially increased by enclosing a long string of stacked sections in a tube of appropriate dimensions and pumping the coolant through the tube in a cyclic process (Fig 11). The metallic tracks of the constituent sections act as heat transference vanes as well as providing structural support and electrical interconnection of sections.

In general, the rate of flow of coolant along the outer surface of the structure (arrows a) will be much greater than the rate of flow within the structure (arrows b) and this will be especially so if the ends of the stack are closed off. However, because the faces of the constituent tape sections only touch along the copper/solder/copper interconnection points, the coolant can percolate upwards through the gaps between the insulating substrates of the various sections.

The rate of flow of coolant in this direction being maximised by orienting the structure in the total gravitational vector G as shown in fig 11. The substrate can also be contoured to increase the size of these percolation cavities. The complete structure for such a computer can be maintained in the correct orientation by a cradle like structure as depicted in fig 22 which will perform in exactly the same manner as a plumbline. Such a cradled structure also provides protection against impact during transportation if in a large enough housing. Tape Manufacture

There are a variety of known additive, semiadditive and subtractive methods for producing conductor tracks on one or both sides of an insulating substrate which are well documented elsewhere. However, there are at least five possible techniques relating to the bonding tape structures elucidated here which are not generally encountered. These are:

1) Wrapping overhanging conductor tracks around an insulating substrate

2) Wrapping conductor tracks on a thin elastomer substrate around another substrate used for thickening and/or strengthening

3) A hybridisation of a chemical method of plating such as is used in through hole plating with a prior mechanical lamination which can achieve metal over hole 4) Pressing metal squares into holes in a substrate prior to subsequent conventional chemical processing 5) Extending the normal photographic exposure processes to 3 dimensions in one of two ways a) for contact photoexposure by using a mask with raised sections which fit into the appropriate cavities and and with the desired mask tracks running continuously from normal to raised sections, and where the illumination is supplied from a sufficient number of angles to guarantee adequate exposure. b) for focused image photoexposure by using two (or more) appropriate image masks which are focused onto the object from two (or more) appropriate planes as in figure 3. In this example the ideal projection angles are 45º from the plane of the tape and along a cavity diagonal. A focal depth of the image of approxmately 1cm. is sufficient for producing sharp track edges. The example shown is for the shortest possible wire delay with inside as opposed to outside conductor wrap, copper being continuous from top surface to bottom surface through elastomer holes (corresponds to figs 8F or G). The photoexposure of the other side of the tape is not shown since it can be the normal 2D exposure in this case.

The use of two substrates, an elastomer such as polyimide and a lower cost bulk substrate such as fibreglass for thickening maintains a low cost while preserving a resilience to thermally induced strains. It is then possible to extend the elastomer further into the chip cavity than the bulk substrate to maintain accurate spatial positioning of the conductor tracks relative to the chip bond out pads. The inclusion of a thin elastomer layer between a bulk substrate and metal conductor tracks has already been used successfully for P.C.B.s for leadless ceramic chip carriers to accommodate thermal expansion differentials. (Electronics, July 141982 p135-141).

Handling and stacking of sections

While the description supplied already contains sufficient new information for three dimensionally arranged integrated circuits to be manufactured, it has already been mentioned that if a semiconductor bonding tape is designed to provide maximum freedom from thermally induced stress, then there is a distinct possibility that any particular section may be deformed or damaged during handling either before or after an integrated circuit has been attached thereto, and before said section has been incorporated into a resiliently supported stack.

It is also a fact that during normal wafer manufacture, substantially less than 1% of the thickness of the wafer is utilised for the manufacture of active components.

Therefore if more reliable handling techniques are adopted, a more reliable finished product will result and it should also be possible to make the constituent sections thinner thereby further increasing component density.

The following considerations could therefore be considered as design guidelines for the optimised manufacture of the finished product.

For an optimised process these design guidelines would be expressed within the control program and hardware of a fully automated assembly process. It is perhaps obvious that a fragile horizontally oriented section can be handled more reliably by supporting it from below over the whole of its area and that if the support is lipped at suitable points, this will prevent the section from sliding off its support. Such a horizontally oriented section is unconditionally stable when moved horizontally or vertically by providing it with accelerations and decelerations less than 1 G where G is the acceleration due to gravity. If the section has to be rotated vertically, or decelerated vertically at rates greater than 1 G, it is normally necessary to provide a second support plane similar to the first which is positioned above the section in order that deceleration forces can be suitably distributed over the section.

Figure 12 represents a bonding tape section with a chip attached which exhibits one direction of rigidity against a gravitational field provided by at least one straight conductor track (A) bonded either to the chip or to a chip backing plate. Freedom from thermally induced stress is provided in part by the tape substrate and in part by a curvature of the other conductor tracks. Any differential thermal expansion or contraction along the straight conductor track can be accommodated by the centre of the chip moving slightly from the centre of the cavity in the plane of the section once the tape section is rigidly fixed as part of the outer skeleton of the stack. Providing this section is maintained orientated as shown in the total gravitational vector shown on Fig 11 it is unconditionally stable against acceleration and deceleration. However, it is important that the orientation is here specified in the total gravitational vector since in general this vector is the vector product of the gravitational field experienced by the body due to the proximity of a massive body (the earth) and the gravitational field experienced by the body due to its acceleration relative to any inertial co-ordinate framework (usually taken unrigorously to be an earth co-ordinate framework). In general, this vector product can be either calculated or, if the gravitational vector is not fluctuating, its direction can be determined by a plumbline arrangement.

It can, then, be seen that fragile sections can usually be handled more reliably by the appropriate use of adequate supports and further improved by arranging for them to be moved in smoothly accelerating and decelerating trajectories, and that some use can also be made of a. single direction of rigidity exhibited by a section. However, there are certain points in the manu facturing process when it is inappropriate for a section to be supported from underneath and this is particularly so at the point of stacking.

Although the vertically oriented section of figure 12 could be stacked horizontally to produce a device such as the device of figure 11, in general an incomplete stack of sections is most stable when the constituent sections are oriented horizontally and with the gravitational field, if any, pulling the sections together, this being particularly relevant when a cushioning substance is being included between each integrated circuit section in a semifluid condition (eg. silicone gel).

It is then preferable for each succeeding section to be positioned on the stack in conditions which can be best understood as gravity free or accurately controlled gravity conditions. Each succeeding layer could be supported from above using suction pads but this technique precludes stacking in vacuo and would also make optical registration more difficult. The quality control achievable by this method is also less reliable than by gravity control.

Figure 14 demonstrates in principle and figure 17 demonstrates in practice how this design goal is achieved.

In accordance with the general principle of relativity, for a contained system, gravitational fields experienced within that system due to massive external bodies can be identical to gravitational fields experienced within that system due to acceleration of that system relative to an inertial co-ordinate framework. Since gravitational nullification is only required for a finite period of time it can be achieved by accelerating an automated stacking environment earthwards during one time period then skywards during another time period which then achieves a period of higher than earth normal gravity. The stacking environment may be maintained in a state of vertical oscillation by the application of alternating skyward and earthward accelerating forces of appropriate magnitude thereby multiplexing the environment between these two gravitational states. Referring to figure 14, if the closed box is cycled through a fixed acceleration of G alternately thrusting skywards and earthwards within the earth's gravitational field, the resultant total gravitational field experienced by the elements within the box alternate between zero and 2G. The accelerating forces required to maintain these (or other) gravitational fields could be accurately controlled via a feedback loop using light or wires from the box, to the circuitry generating the accelerating forces on the earth co-ordinate framework.

A driving force (other than earth gravity) during the period of earthward directed acceleration is desirable since this can counteract the undesirable effects of friction and air resistance which are velocity dependent and/or to produce a small and accurately controlled gravitational field while the section is manoeuvred. This is achieved in the simplified device of figure 17 by an electric current flowing through a long vertical magnetic linear accelerator coil A acting on a permanent magnet B within the coil and providing bi-directional thrust to the stacking environment C. The period of high gravity is arranged to correspond with the bedding of each integrated circuit on its appropriate cushion after it has been positioned on the stack and there is no need for the gravitational field during this period to be constant. Because of this, long springs D are provided to supply the skyward directed thrust during the bottom portion of the environment's trajectory and these springs go slack once the environment has reached an appropriate height (and skyward velocity). Suitable bearings or lubri cated collars E prevent the system from falling out of vertical alignment.

The vertically mobile environment C will, for stacking, generally include a positioning arm for performing certain manipulations and sensors for information feedback to the control processor(s) which may be within the environment C or on earth co-ordinate framework or both.

To recap certain of the points already made in the priority document, Firstly, temporary support structures may be attached to the carrying tapes to support the integrated circuits during transportation and testing or a continuous strip support run under the tape and cavities.

Secondly, suitably shaped multiple aperture vacuum suction pads can be used for handling chips or loaded tapes.

Thirdly, any automated movement of chips and support structures can be programmed to take place in a smoothly accelerating and decelerating trajectory. However, simply by arranging the orientations, directions of movement and accelerations of wafers, chips and carrier tapes suitably during all stages of processing and handling when the sections are not adequately supported over the whole of their surface area, it is possible to virtually eliminate the potentially destructive effects of gravitation, air resistance and impulsive movement while the individual sections of the final structure are at their most vulnerable.

The main points are that loaded tape sections can be handled without deformation if support plates are used or if the sections are oriented suitably in the gravitational field, and the sections can also be stacked without deformation by the simple expedient of removing the gravitational field entirely at the appropriate time. When zero G stacking is used, referring to diagram 14, at point A, the co-ordinate framework of the controlled environment is identical to that of the wider environment in all respects except that gravity free conditions obtain. This is, therefore, a convenient point for passing horizontally oriented sections on support plates into the gravity free environment from above. The support plate is now redundant and can now be removed leaving the section floating over the stack. The application of a small positive gravity or the existence of a small relative velocity of the section to the stack will result in the section dropping into position on the stack without the risk of vertical deformation of the section. Similarly, at point B, the co-ordinate framework of the controlled environment is identical to that of the wider environment in all respects except that the stack is held together by a higher than earth normal gravity and so this is a convenient point for passing the completed stack out of the bottom of the controlled environment.

It is also possible to arrange for the mobile environment C of figure 17 to stop at points A or B of figure 14 in order to insert or extract materials. but then the sequence of gravitational states and the diagrams of figures 14 and 17 become more complex and it is probably preferable for the whole process to be orchestrated as a totally dynamic set of events as in the embodiment given.

If sections on support plates are inserted at point A in figure 14 and support plates discarded at point B, then the energy required to lift each support plate from point B to point A in the earth's gravitational field is donated to the oscillating system every cycle.

The energy jump in the oscillating system is much larger when the complete stack is discarded at the bottom of the nth trajectory so that, if frictional losses are small it could be necessary for the bidirectional accelerator coil A of figure 17 to extract energy from the system (damping) instead of to supply energy to overcome the natural frictional damping inherent in the machine in order to maintain the correct vertical excursions during successive cycles.

Preferably, the actual fine tuning of the up and down driving fields is adjusted in coarse outline by machine learning of the average forces required to maintain perfect trajectories over many sets of n cycles plus ideally finer fine tuning on each cycle to adjust for deviations from ideal trajectory which is signalled by sensors and caused by production tolerances in the mass of each section.

Depending on the time taken for the αontrol processor, positioning arm and possible optical sensors to achieve reasonably accurate registration of sections, the vertical excursions of the system need not be great. The closure of the box C except at or near points A and B of figure 14 is necessary for adequate shielding from air turbulence.

[To check that gravity free conditions do apply in the machine described, this situation could be compared to that of an astronaut in free fall in orbit around the earth. In both cases a classical physicist could define the motion (relative to his inertial framework) of each environment as an acceleration towards earth caused by earth gravity, but in both cases said environments occupy null geodesies over the time span of interest and, consequently experience gravity free conditions.]

Optionally, additional bearings or lubricated collars

F and extension G may be added if the system is not properly balanced, but this doubles the height of the required housing. Streamlining may also be included on the roof and floor of C.

A device which is more tolerant of process variations and less demanding on the level of real time control required can be provided by a suitably positioned electromagnet which is switched on to clamp from the sides a ferrous portion of the oscillating machine when the point of zero velocity is reached. If materials are then both inserted and extracted at the point B of fig 14, and free running through point A, the usable period of low or zero gravity is doubled.

If thinner wafers are to be fabricated in ti.e future the possibility of producing holes in the silicon substrate either by laser boring or by preferential etching could become more attractive. Whereas, in the past, the inter connection of sections via this method usually involves the use of soldering, it should also be possible to effect vertical electrical interconnection of a totally parallel connected stack by sucking electrolyte through the aligned metallised holes of the constituent sections fig 21. The inclusion of a cushioning layer between each integrated circuit layer improves the strength of the laminated structure and also prevents electrolyte from flowing horizontally between sections during the plating of the vertical interconnection pillars. For optimisation, in zero G environments when a uniformly flat backing plate is accelerated away from a uniformly flat section atmospheric pressure tends to force the section to follow the plate.

Because of this, backing plates should include adequate channels or holes for air circulation, or separation should be performed in vacuo or since practical vacuums are not hard vacuums, both.

Since a yield in the region of 50% is fairly common for LSI chips, obviously, a high yield for a finished stack is much easier to achieve by stacking a number of sections which have passed functional testing than by incorporating extremely sophisticated redundancy techniques for deselecting non functional layers from a stack in which a statistical distribution around a mean of 50% of the layers are faulty. Ultimately, if laser annealing of silicon sections is adopted and if gravity control in the widest sense

(ie. including smoothly accelerating and decelerating trajectories during automated and supported handling through the normal processing steps) is refined sufficiently to enable wafer thicknesses to shrink at anything like the rate that lithography dimensions have with the (2D) integrated circuit, then it will ultimately be possible to multilayer sections as in fig 23 by successively depositing metallisations over through holes in overlying substrates to connect with the immediately underlying substrate.

The information supplied after the first embodiment encapsulates at least two very different (but linked) further embodiments which could be narrowed down to: 2nd embodiment. A rugged high capacity cubic RAM protected with a sealed hydraulic cushion for each layer (figs 18, 19 and 24).

3rd embodiment. A more generalised array of stacked processing power utilising pumped and percolated cooling (fig 11) unidirectionally rigid tape sections (fig 12) face to face pairs of slices (fig 20) and the whole structure slung in a plumbline effect cradle (fig 22) to maintain correct gravitational orientation and to protect from shock during transportation.

The slices used in the third embodiment could be fabricated using superconductor quantum devices such as Josephεon junctions with a coolant such as liquid helium. Both of these embodiments utilise stackable bonding tape.

Figure 25 depicts important aspects of the invention in boxes and important relationships in interconnecting rods. The diagram is best understood as a multidimensional structure of largely independent aspects with, nevertheless, a number of important axes of relationship. The time axis will be considerably longer than the duration of the patent, since there are no more dimensions which could usefully be integrated in silicon device technology (space, time and automation).

According to one aspect oi the invention, a stacked arrangement of integrated circuits in a multilayer configuration containing one integrated circuit per layer is characterised in that the constituent ICs are designed so as to dissipate substantially less power when deselected than when selected and in that the stack is arranged such that a proportion of the constituent sections are always deselected at any particular time. More specifically, according to one aspect of the invention comprising a high capacity memory, the constituent chips or wafers are so arranged that, normally, at most one memory layer in the stack will be selected at any particular time such that a single area of significant power dissipation can be considered as moving through the 3D structure when the total address space is scanned.

According to one aspect of the invention, in the specific example of a high capacity memory comprising a number of stacked integrated circuits, the structure is characterised in that a number of identical integrated circuits are stacked and totally parallel interconnected in the direction of stacking and where circuitry on each secticn selects a particular layer in the stack according to the status of layer address bits.

According to one aspect of the invention, a stack of integrated circuits is characterised in that the constituent integrated circuits are cushioned layer to layer by a substance such as silicone gel or RTV silicone rubber, such substance between each layer preferably being applied for each layer before the following integrated circuit layer is positioned on the stack.

According to one aspect of the invention, the invention is characterised as a stackable semiconductor bonding tape including metallic conductor tracks on an insulating substrate with a central cavity in each section and characterised in that a portion or all of said metallic conductor tracks on each section extend from one side of the substrate to the other or extend beyond the outer periphery of the substrate for each section such that they may be bent to connect with a similar or identical section positioned above or below said section and further characterised in that the central cavity is sufficiently deep and large to accommodate the volume of a semiconductor chip bonded to metallic conductor tracks of said section or of an adjacent section positioned above or below said section, the tape being further characterised in various alternate forαs as in the associated drawings and preceding description.

According to one aspect of the invention, electrical and mechanical interconnection of a set of stacked semiconductor carriers with wrap round conductors and with one or more integrated circuits bonded to each is achieved by capillary action soldering from the outer segmented faces of the stack of carriers.

According to one aspect of the invention, the invention is characterised as a device for controlling or nullifying the local gravitational field for at least one step in an assembly process and further characterised as in the associated descriptions and drawings which facilitates the reliable fabrication of a resiliently supported stack of sections from a number of individually fragile or easily deformed sections. According to one aspect of the invention, a high yield of finished stacked semiconductors is achieved by providing burn in and/or functional test of each section prior to multilayering of good sections, with the cost of manufacture preferably being minimised by the utilisation of identical sections.

While the invention can, therefore, be well understood in terms of this interlinked set of seven orthogonal concepts, it will be appreciated that substantially the same product could be manufactured by omitting one or several of these concepts or by substituting one or several other techniques described here of known in the art.

Thus, for example, the stack could be electrically interconnected by including solder paste or solder prefores between each section followed by vapour phase reflow soldering of the complete stack instead of utilising capillary action soldering from the outside of the stack, and a reasonable yield of finished devices could be achieved without utilising gravity control during positioning of sections, particularly if each chip is effectively cradled by a set of stronger leads connecting an attached backing plate to the bonding tape section (Fig 4, 5 ) and/or if a suction cup is used to position the chip.

It will, therefore, be appreciated that no single aspect of the invention can justifiably be given absolute significance over and above all the other aspects of the invention and that the significance of each is, to a degree, dependent on the specific product being produced.

Therefore, according to one further aspect of the invention the stack may be immersed in a tube of liquid coolant which is pumped round in a cyclic process, substantial heat being extracted from the coolant fluid possibly at a distance from the stack of integrated circuits.

According to one alternative aspect of the invention, interconnection of integrated circuits in the direction of stacking is achieved by sucking electrolyte through aligned holes in the constituent chips to form metallic interconnection pillars.

According to one aspect of the invention the constituent integrated circuits can be stacked as face to face pairs.

While the semiconductor bonding tape was designed to facilitate the stacking of LSI & VLSI chips, such a tape could also be useful for connecting such chips onto conventional planar circuit boards.

Whereas the specific examples given have generally related to the stacking of chips, it is envisaged that similar techniques may also be used in the stacking of wafers. In all respects, the examples are intended to be illustrative rather restrictive, and the invention may be understood in terms of a number of independent aspects or in terms of the use of any number of these aspects in conjunction for the manufacture of very high density integrated circuits.

Claims

What is claimed is:

(1) A multilayer integrated circuit configuration of at least two layers comprising or containing one monolithic essentially two dimensional array of circuit components per layer and characterised in that: the circuitry associated with a proportion or all of the constituent layers dissipates substantially less power when deselected than when selected and where said Layers are so interconnected that at least one of said layers is in effect deselected at any particular time.

(2) The item of the first claim further characterised in that: a proportion or all of the constituent layers are produced of identical sections which may be partially or totally parallel connected layer to layer and which include discrimination circuitry which can be used to determine which section or sections will be selected at any particular time.

(3) The items of claim 1 further characterised in that: at least one pair of integrated circuits or at least one integrated circuit and a lid or base are cushioned layer to layer by a suitable substance.

(4) A stackable semiconductor bonding tape section exhibiting any or all of the normal characteristics of a semiconductor bonding tape section including metallic conductor tracks centring on a central cavity and bonded to an insulating substrate, but characterised in that: a proportion or all of the conductor tracks extend beyond the outer periphery of the substrate of the section so that they may be bent up or down to connect with a further section positioned above or below said section, or where a proportion or all of the conductor tracks extend from one side of the substrate to the other, and where the central chip cavity is sufficiently deep and large to accommodate the volume of a chip bonded to the inner conductor leads of that or an adjacent section, such that a number of such sections with integrated circuits attached may be stacked to produce the device of claims 1 or 2 or 3.

(5) The item of claim 4 further characterised in that: the integrated circuit connected to the bonding tape section is effectively cradled in its appropriate cavity by further conductor leads bonded to a metal backing plate bonded to the back surface of the integrated circuit.

(6) A stack of sections according to claims 1, 2 or 4 further characterised in that: interconnection of sections is achieved in part or totally by capillary action soldering from the outer segmented faces of the stack.

(7) A manufacturing facility for the assembly or packaging of integrated circuits according to the preceding claims further characterised in that: during at least one stage in the manufacturing process, an automated handling process is provided which enables at least one section to be handled in gravity free or controlled gravity conditions for a period of time by providing the immediate automated handling environment with at least one period of earthward directed acceleration of a magnitude of the order of the acceleration due to gravity and at least one period of skyward directed acceleration at another time such that the environment is maintained in substantially the same position relative to the rest of the manufacturing facility when viewed over a longer period of time.

(8) The items of claims 1, 2 or 3 further characterised in that: a proportion or all of the constituent sections are electrically interconnected partially or totally by metal plating achieved by sucking an electrolyte through aligned holes in the constituent sections.

(9) A multilayer circuit according to claims 1, 2 or 4 but further characterised in that: the complete device is positioned in a tube through which coolant fluid is pumped in a cyclic process.

(10) A memory component which includes two additional memory sections each with a connection point for activation and with common data input lines, their output lines being compared by further circuitry which maintains the rest of the component in a passive state when there is no match between these two input words.