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US5196913A - Input protection device for improving of delay time on input stage in semi-conductor devices - Google Patents

Input protection device for improving of delay time on input stage in semi-conductor devices Download PDF

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Publication number
US5196913A
US5196913A US07/634,797 US63479790A US5196913A US 5196913 A US5196913 A US 5196913A US 63479790 A US63479790 A US 63479790A US 5196913 A US5196913 A US 5196913A
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region
input
substrate
layer
protection device
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US07/634,797
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Chang-Hyun Kim
Hyun-Soon Jang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1019880008604A external-priority patent/KR910007374B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment

Definitions

  • This invention relates to an input protection device for static electricity discharges at the input stages of semiconductor integrated circuits, and particularly to such protection devices for improving the signal delay time at the input stage of the integrated circuits.
  • protection devices against discharge of static electricity charges are provided at the input stage of the ICs.
  • Most semiconductor ICs, such as semiconductor memories have such protection devices in order to protect them from destruction resulting from instantaneous static charges coming from the human body or other sources.
  • FIG. 1 shows one example of such conventional device.
  • FIG. 1(A) is a plan view of a layout of the input stage of a conventional integrated circuit and shows the charge collection area 2 connected with Vss and the input path area 3 connected with the input pad.
  • FIG. 1(B) is a cross-sectional view along the line a--a' of FIG. 1(A) and shows an n+ diffusion layer of the input path area 3 and an n+ diffusion layer of the charge collection area 2 on a p type Si-substrate.
  • FIG. 1(C) is an equivalent circuit diagram of the device of FIGS. 1A and 1B.
  • FIG. 1(C) shows an input pad 4 which is connected to the input path area 3.
  • the input signal is applied to the pad 4 and is conveyed to the first or input stage of the integrated circuit (not shown) via the area 3.
  • Static charges which come through the input pad 4 are collected in the charge area 2 via the transistor 1.
  • the path of the input circuit 3 should be long in order to increase the effective charge collection area, which causes an increase of the diffusion resistance.
  • the input area 3 provides a long delay time. This, in turn, causes a decrease in the performance of the overall integrated circuit.
  • the present invention has been made in consideration of this and has its object to provide an input protection device for improving the delay time at the input stage in semiconductor devices, according to which invention, shortening the delay time for signal propagation is achieved without reducing the static charge collecting capacity of the device.
  • an input protection device for improving the delay time at the input stage of semiconductor devices which includes a low resistance layer on the input path area connected with the input pad on the Si-substrate.
  • FIG. 1(A) is a plan view of a layout of a conventional protection device for static discharge at an input stage
  • FIG. 1(B) is a cross-sectional view along the line a--a' of FIG. 1(A);
  • FIG. 1(C) is an equivalent circuit diagram of the conventional protection device shown in FIGS. 1(A) and 1(B);
  • FIG. 2(A) is a plan view of a layout of a protection device for static discharge at an input stage in accordance with the present invention
  • FIG. 2(B) is a cross-sectional view along the line a--a' of FIG. 2(A);
  • FIG. 3(B) is a cross-sectional view along the line A--A' of FIG. 3(A);
  • FIG. 3(C) is a cross-sectional view along the line B--B' of FIG. 3(B);
  • FIG. 3(D) is an equivalent circuit diagram of the protection device shown in FIGS. 3(A)-3(C).
  • an n+ diffusion region or layer of the charge collection area 2 and an n+diffusion region or layer of the path area 3 of the input circuit are formed on the p-type substrate 1, respectively.
  • a low resistance layer 5 is formed on the path area 3 of the input circuit.
  • An equivalent circuit is shown in FIG. 2(C).
  • the static charges coming through the input pad 4 are collected in the charge collection area 2 and the input signal coming through the input pad 4 is propagated through the diffusion resistance R3 and the low resistance R5. Therefore, shortening of the propagating time of the input signal is attained without reducing the static charge collecting capacity of the device.
  • the propagating time of the input signal is shortened by means of the reduced path resistance provided by the parallel circuit of the resistance R3 and R5. This, in turn, enhances the speed characteristics of integrated circuits using the inventive protection device.
  • an N+ diffusion region 10 is formed within a p-type substrate 11, the region 10 comprising a conductive path R 10 '--R 10 " (FIG. 3(D) for an input signal applied to a metal pad 12 to an internal circuit (not shown) connected to the path R 10 '--R 10 " via a metal strip 14 (FIG. 3(B)).
  • the surface of the substrate is covered by an insulating layer 16, and the metal pad 12 and the metal strip 14 are ohmically connected to the region 10 through openings through the insulating layer 16.
  • metal strip 18 Overlying the insulating layer 16 is another metal strip 18 ohmically connected to spaced apart portions of the region 10 through contact openings through the layer 16. The purpose of the metal strip 18 is to provide a low resistance path for the incoming signal in parallel to the path provided by the region 10.
  • FIG. 3(D) An equivalent circuit for the protection device is shown in FIG. 3(D).
  • the path for the input signal comprises the metal pad 12, a first portion R 10 ' of the region 10, the parallel paths comprising the portion R 10 " of the region 10 and the metal strip R 18 overlying the region 10, and the metal strip 14.
  • FIG. 3(D) also shows a transistor T 1 for discharging high frequency static charges to the substrate to prevent harm to the internal circuits of the semiconductor chip.
  • the transistor T 1 is formed from an additional n+ diffusion region 22 within the substrate (FIGS. 3(A) and 3(C)) which extends within the substrate 11 parallel to the n+ diffusion region 10 and spaced therefrom by the p-type material of the substrate.
  • the n+ region is connected to a metal strip 24 by means of which the region 22 can be connected to ground potential (VSS).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

This invention provides an input protection device having, within a body of semiconductor material, parallel, doped regions providing an input circuit and a charge collection area for protecting against static electricity charges at the input stage of semiconductor devices, the device including a low resistance layer formed on the body overlying the input circuit which is connected to an input pad on the body. Shortening the input signal delay time is thus attained.

Description

This is a continuation-in-part of copending application Ser. No. 07/333,432 filed on Apr. 4, 1989, abandoned.
BACKGROUND OF THE INVENTION
This invention relates to an input protection device for static electricity discharges at the input stages of semiconductor integrated circuits, and particularly to such protection devices for improving the signal delay time at the input stage of the integrated circuits.
In IC design, protection devices against discharge of static electricity charges are provided at the input stage of the ICs. Most semiconductor ICs, such as semiconductor memories have such protection devices in order to protect them from destruction resulting from instantaneous static charges coming from the human body or other sources.
A conventional protection device against static charge at an input stage will now be described with reference to FIG. 1 which shows one example of such conventional device.
FIG. 1(A) is a plan view of a layout of the input stage of a conventional integrated circuit and shows the charge collection area 2 connected with Vss and the input path area 3 connected with the input pad.
FIG. 1(B) is a cross-sectional view along the line a--a' of FIG. 1(A) and shows an n+ diffusion layer of the input path area 3 and an n+ diffusion layer of the charge collection area 2 on a p type Si-substrate.
FIG. 1(C) is an equivalent circuit diagram of the device of FIGS. 1A and 1B.
FIG. 1(C) shows an input pad 4 which is connected to the input path area 3. The input signal is applied to the pad 4 and is conveyed to the first or input stage of the integrated circuit (not shown) via the area 3. There is some delay of the signal coming through the input pad 4 by the diffusion layer resistance R3 of the input path area 3. Static charges which come through the input pad 4 are collected in the charge area 2 via the transistor 1. As a result, the IC is protected from destruction by the static charges. But, the path of the input circuit 3 should be long in order to increase the effective charge collection area, which causes an increase of the diffusion resistance. Thus, the input area 3 provides a long delay time. This, in turn, causes a decrease in the performance of the overall integrated circuit.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of this and has its object to provide an input protection device for improving the delay time at the input stage in semiconductor devices, according to which invention, shortening the delay time for signal propagation is achieved without reducing the static charge collecting capacity of the device.
According to the present invention, there is provided an input protection device for improving the delay time at the input stage of semiconductor devices which includes a low resistance layer on the input path area connected with the input pad on the Si-substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1(A) is a plan view of a layout of a conventional protection device for static discharge at an input stage;
FIG. 1(B) is a cross-sectional view along the line a--a' of FIG. 1(A);
FIG. 1(C) is an equivalent circuit diagram of the conventional protection device shown in FIGS. 1(A) and 1(B);
FIG. 2(A) is a plan view of a layout of a protection device for static discharge at an input stage in accordance with the present invention;
FIG. 2(B) is a cross-sectional view along the line a--a' of FIG. 2(A);
FIG. 2(C) is a equivalent circuit diagram of the protection device shown in FIGS. 2(A) and 2(B);
FIG. 3(A) is a plan view similar to that of FIG. 2(A) but showing a different embodiment of the invention;
FIG. 3(B) is a cross-sectional view along the line A--A' of FIG. 3(A);
FIG. 3(C) is a cross-sectional view along the line B--B' of FIG. 3(B); and
FIG. 3(D) is an equivalent circuit diagram of the protection device shown in FIGS. 3(A)-3(C).
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
The protection device of the present invention will now be described in more detail with reference to the accompanying drawings.
As shown in FIG. 2(A) and FIG. 2(B) an n+ diffusion region or layer of the charge collection area 2 and an n+diffusion region or layer of the path area 3 of the input circuit are formed on the p-type substrate 1, respectively.
A low resistance layer 5 is formed on the path area 3 of the input circuit. An equivalent circuit is shown in FIG. 2(C).
The static charges coming through the input pad 4 are collected in the charge collection area 2 and the input signal coming through the input pad 4 is propagated through the diffusion resistance R3 and the low resistance R5. Therefore, shortening of the propagating time of the input signal is attained without reducing the static charge collecting capacity of the device. The propagating time of the input signal is shortened by means of the reduced path resistance provided by the parallel circuit of the resistance R3 and R5. This, in turn, enhances the speed characteristics of integrated circuits using the inventive protection device.
Another embodiment of the invention is shown in FIGS. 3(A)-(3D).
As shown in FIGS. 3(A) and 3(B), an N+ diffusion region 10 is formed within a p-type substrate 11, the region 10 comprising a conductive path R10 '--R10 " (FIG. 3(D) for an input signal applied to a metal pad 12 to an internal circuit (not shown) connected to the path R10 '--R10 " via a metal strip 14 (FIG. 3(B)).
As shown in FIG. 3(B), the surface of the substrate is covered by an insulating layer 16, and the metal pad 12 and the metal strip 14 are ohmically connected to the region 10 through openings through the insulating layer 16.
Overlying the insulating layer 16 is another metal strip 18 ohmically connected to spaced apart portions of the region 10 through contact openings through the layer 16. The purpose of the metal strip 18 is to provide a low resistance path for the incoming signal in parallel to the path provided by the region 10.
An equivalent circuit for the protection device is shown in FIG. 3(D). The path for the input signal comprises the metal pad 12, a first portion R10 ' of the region 10, the parallel paths comprising the portion R10 " of the region 10 and the metal strip R18 overlying the region 10, and the metal strip 14.
FIG. 3(D) also shows a transistor T1 for discharging high frequency static charges to the substrate to prevent harm to the internal circuits of the semiconductor chip. The transistor T1 is formed from an additional n+ diffusion region 22 within the substrate (FIGS. 3(A) and 3(C)) which extends within the substrate 11 parallel to the n+ diffusion region 10 and spaced therefrom by the p-type material of the substrate. As shown in FIG. 3(C), the n+ region is connected to a metal strip 24 by means of which the region 22 can be connected to ground potential (VSS).

Claims (4)

We claim:
1. An input protection device for a semiconductor device including a substrate of semiconductor material of a first conductivity type, a signal input pad on a surface of said substrate, a first region, having first and second ends, of a second conductivity type within said substrate, said first end being connected to said input pad, said first region providing an electrical path between said ends thereof for an electrical signal, and a signal conductor connected to said second end for extending said electrical path beyond said first region, a second region of said second conductivity type within said substrate spaced from said first region and providing means for collecting static charges arriving along said first region, and a layer of low resistance material disposed on the surface of said substrate overlying and in direct contact with said first region for reducing the electrical resistance of said electrical path between said ends.
2. A device according to claim 1 wherein said signal conductor is directly connected to said second end and only indirectly connected to said layer of low resistance material via said first region.
3. An input protection device for a semiconductor device including a substrate of semiconductor material of a first conductivity type, a signal input pad on a surface of said substrate, a first region having spaced apart portions, of a second conductivity type within said substrate connected to said input pad and providing an electrical path between said portions thereof for an electrical signal, a second region of said second conductivity type within said substrate spaced from said first region and providing means for collecting static charges arriving along said first region, a layer of insulating material on the surface of said substrate overlying said first region, and a layer of low resistance material disposed on said layer of insulating material, said layer of insulating material having openings therethrough, and said low resistance layer extending through said openings into direct ohmic contact with said spaced apart portions of said first region.
4. A device according to claim 3 including a signal conductor connected to said first region for extending the path for an electrical signal, said signal conductor being spaced from direct contact with said layer of low resistance material by said layer of insulating material.
US07/634,797 1988-07-11 1990-12-28 Input protection device for improving of delay time on input stage in semi-conductor devices Expired - Lifetime US5196913A (en)

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US07/634,797 US5196913A (en) 1988-07-11 1990-12-28 Input protection device for improving of delay time on input stage in semi-conductor devices

Applications Claiming Priority (4)

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KR1019880008604A KR910007374B1 (en) 1988-07-11 1988-07-11 Protect of semiconductor device
KR88-8604 1988-07-11
US33343289A 1989-04-04 1989-04-04
US07/634,797 US5196913A (en) 1988-07-11 1990-12-28 Input protection device for improving of delay time on input stage in semi-conductor devices

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818088A (en) * 1995-09-11 1998-10-06 Analog Devices, Inc. Electrostatic discharge protection network and method
US6388851B1 (en) 1999-02-09 2002-05-14 Telefonaktiebolaget Lm Ericsson (Publ) Electronic discharge protection of integrated circuits
US20040164355A1 (en) * 2001-09-06 2004-08-26 Andrej Litwin Arrangement for ESD protection of an integrated circuit
US20050047037A1 (en) * 2003-08-27 2005-03-03 Andrej Litwin Device for ESD protection of an integrated circuit
US20060018066A1 (en) * 2004-05-28 2006-01-26 Infineon Technologies Ag Device for ESD protection of an integrated circuit

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JPS57211273A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor integrated circuit device
JPS58161375A (en) * 1982-03-19 1983-09-24 Toshiba Corp Input protection circuit of insulation gate type field effect semiconductor integrated circuit
US4481521A (en) * 1978-11-06 1984-11-06 Nippon Electric Co., Ltd. Insulated gate field effect transistor provided with a protective device for a gate insulating film
JPS59224164A (en) * 1983-06-03 1984-12-17 Hitachi Ltd Electrostatic-breakdown preventing circuit
US4617482A (en) * 1983-10-12 1986-10-14 Nec Corporation Complementary type MOS field-effect transistor circuit provided with a gate protection structure of small time constant
US4692781A (en) * 1984-06-06 1987-09-08 Texas Instruments Incorporated Semiconductor device with electrostatic discharge protection
US4710791A (en) * 1984-08-09 1987-12-01 Fujitsu Limited Protection device in an integrated circuit
US4724471A (en) * 1985-04-08 1988-02-09 Sgs Semiconductor Corporation Electrostatic discharge input protection network
US4730208A (en) * 1982-08-09 1988-03-08 Tokyo Sahbaura Denki Kabushiki Kaisha Semiconductor device
US4739438A (en) * 1984-05-22 1988-04-19 Nec Corporation Integrated circuit with an improved input protective device
US4777518A (en) * 1982-01-11 1988-10-11 Nissan Motor Company, Limited Semiconductor device including gate protection circuit with capacitor under input pad
US4802054A (en) * 1987-03-13 1989-01-31 Motorola, Inc. Input protection for an integrated circuit
US4821096A (en) * 1985-12-23 1989-04-11 Intel Corporation Excess energy protection device
US4876584A (en) * 1986-09-10 1989-10-24 British Aerospace Plc Electrostatic discharge protection circuit
US4881113A (en) * 1985-10-31 1989-11-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuits with a protection device
US5019888A (en) * 1987-07-23 1991-05-28 Texas Instruments Incorporated Circuit to improve electrostatic discharge protection

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481521A (en) * 1978-11-06 1984-11-06 Nippon Electric Co., Ltd. Insulated gate field effect transistor provided with a protective device for a gate insulating film
JPS57211273A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor integrated circuit device
US4777518A (en) * 1982-01-11 1988-10-11 Nissan Motor Company, Limited Semiconductor device including gate protection circuit with capacitor under input pad
JPS58161375A (en) * 1982-03-19 1983-09-24 Toshiba Corp Input protection circuit of insulation gate type field effect semiconductor integrated circuit
US4730208A (en) * 1982-08-09 1988-03-08 Tokyo Sahbaura Denki Kabushiki Kaisha Semiconductor device
JPS59224164A (en) * 1983-06-03 1984-12-17 Hitachi Ltd Electrostatic-breakdown preventing circuit
US4617482A (en) * 1983-10-12 1986-10-14 Nec Corporation Complementary type MOS field-effect transistor circuit provided with a gate protection structure of small time constant
US4739438A (en) * 1984-05-22 1988-04-19 Nec Corporation Integrated circuit with an improved input protective device
US4692781A (en) * 1984-06-06 1987-09-08 Texas Instruments Incorporated Semiconductor device with electrostatic discharge protection
US4692781B1 (en) * 1984-06-06 1995-05-30 Texas Instruments Inc Semiconductor device with electrostatic discharge protection.
US4692781B2 (en) * 1984-06-06 1998-01-20 Texas Instruments Inc Semiconductor device with electrostatic discharge protection
US4710791A (en) * 1984-08-09 1987-12-01 Fujitsu Limited Protection device in an integrated circuit
US4724471A (en) * 1985-04-08 1988-02-09 Sgs Semiconductor Corporation Electrostatic discharge input protection network
US4881113A (en) * 1985-10-31 1989-11-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuits with a protection device
US4821096A (en) * 1985-12-23 1989-04-11 Intel Corporation Excess energy protection device
US4876584A (en) * 1986-09-10 1989-10-24 British Aerospace Plc Electrostatic discharge protection circuit
US4802054A (en) * 1987-03-13 1989-01-31 Motorola, Inc. Input protection for an integrated circuit
US5019888A (en) * 1987-07-23 1991-05-28 Texas Instruments Incorporated Circuit to improve electrostatic discharge protection

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818088A (en) * 1995-09-11 1998-10-06 Analog Devices, Inc. Electrostatic discharge protection network and method
US6388851B1 (en) 1999-02-09 2002-05-14 Telefonaktiebolaget Lm Ericsson (Publ) Electronic discharge protection of integrated circuits
US20040164355A1 (en) * 2001-09-06 2004-08-26 Andrej Litwin Arrangement for ESD protection of an integrated circuit
US7019382B2 (en) 2001-09-06 2006-03-28 Infineon Technologies Ag Arrangement for ESD protection of an integrated circuit
US20050047037A1 (en) * 2003-08-27 2005-03-03 Andrej Litwin Device for ESD protection of an integrated circuit
US7164567B2 (en) 2003-08-27 2007-01-16 Infineon Technologies Ag Device for ESD protection of an integrated circuit
US20060018066A1 (en) * 2004-05-28 2006-01-26 Infineon Technologies Ag Device for ESD protection of an integrated circuit
US7227730B2 (en) 2004-05-28 2007-06-05 Infineon Technolgoies Ag Device for ESD protection of an integrated circuit

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