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US3953924A - Process for making a multilayer interconnect system - Google Patents

Process for making a multilayer interconnect system Download PDF

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Publication number
US3953924A
US3953924A US05/591,591 US59159175A US3953924A US 3953924 A US3953924 A US 3953924A US 59159175 A US59159175 A US 59159175A US 3953924 A US3953924 A US 3953924A
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United States
Prior art keywords
conductive
sheets
interconnect system
areas
conductive material
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US05/591,591
Inventor
Clyde L. Zachry
Andrew J. Niedzwiecke
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Boeing North American Inc
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Rockwell International Corp
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Priority to US05/591,591 priority Critical patent/US3953924A/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4635Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0302Properties and characteristics in general
    • H05K2201/0305Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/063Lamination of preperforated insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases

Definitions

  • This invention relates to a process for making a compact multilayer circuit interconnect system.
  • One example of a conventional process for making a multilayer circuit interconnect system includes forming holes in a nonconductive substrate and then building up the holes by an electroless plating technique.
  • An alternative process includes filling the holes formed in the substrate with a swage tube. Electrical components received by the holes are electrically interconnected with conductive layers on opposite sides of the substrate through a plated hole or a swage tube.
  • Another conventional process includes filling the holes formed in the nonconductive substrate with "balls" of conductive material (e.g. solder) and heating or pressing the balls to interconnect conductive layers of the circuit pattern.
  • Yet another conventional multilayer circuit interconnect process includes physically jumping together conductive layers on opposite sides of the nonconductive substrate.
  • the process for making the multilayer circuit interconnect system of the instant invention includes the steps of forming a first layer of the interconnect system by applying a masking material in a predetermined pattern to a continuous sheet of electrically conductive material.
  • the masking material pattern includes predetermined unmasked areas, determined by the desired locations of the feed-throughs or vias of the circuit pattern.
  • the unmasked areas formed in the masking material are filled with an electrically conductive material.
  • the layer of masking material is removed from the conductive sheet, leaving only a pattern of raised conductors on the conductive sheet.
  • An electrically insulating base member is selectively cut or punched to include voids which generally correspond in configuration to that of the raised conductors.
  • the conductive sheet and the base member are aligned with one another so that the raised conductors on the conductive layer extend into the voids which have been selectively punched into the base member.
  • the conductive sheet is then affixed to the base member.
  • a second layer of the instant interconnect system is formed by repeating the steps herein described.
  • the first and second layers are aligned relative to one another so that the respective raised conductors on each conductive sheet extend through the selectively punched voids in the base member.
  • the second conductive sheet is then affixed to the base member.
  • the raised conductor portions of each layer are secured to one another by suitable metallurgical joining process thereby forming the vias or feed-throughs which interconnect conductive layers on opposite sides of the base member.
  • the desired circuit pattern to be formed on both sides of the insulating base member is defined by removing the excess of the continuous conductive sheets and the laminating material from the composite laminate formed by the first and second layers.
  • FIGS. 1-6 illustrate the steps of the instant process for making a multilayer circuit interconnect system.
  • FIG. 1 shows the initial step of the process for making the multilayer circuit interconnect system of the instant invention.
  • a first layer 1 of the interconnect system is formed by applying a masking material 4 in a predetermined pattern to a continuous sheet 2 of electrically conductive material.
  • a typical masking material 4 is that known in the art as RISTON.
  • An example of a suitable conductive material comprising continuous sheet 2 is copper.
  • suitable electricaly conductive materials e.g. such as aluminum
  • the prescribed pattern of the masking material 4 applied to conductor sheet 2 is determined by the desired locations of the feedthroughs or vias which interconnect conductive layers of the circuit.
  • the masking material pattern 4 selectively includes predetermined unmasked areas 6 which will subsequently contain the feedthroughs, as will be explained in greater detail hereinafter.
  • the unmasked areas 6, selectively included in the masking material pattern 4, are filled with an electrically conductive material 8 in a suitable manner.
  • an electrically conductive material 8 for example, electroforming, amalgam filling or other techniques may be used.
  • the unmasked areas 6 are filled with gold.
  • This or any other suitable electrically conductive material e.g. copper or solder
  • the material 8 is required to be easily joinable to itself or to another conductive material, the purpose of which will soon become apparent.
  • the masking material is removed from the conductive sheet 2 by any convenient process leaving only the predetermined pattern of raised conductors 8 on sheet 2.
  • the masking material were RISTON, then the RISTON may be removed by a suitable solvent.
  • the process for removing the masking material from the conductive sheet 2 is determined by the type of masking material employed to form the instant interconnect system.
  • the conductive sheet 2 is attached to an electrically insulating base member 12.
  • the base 12 typically a printed circuit board, a flexible film or the like, is selectively cut or punched so as to include voids 16 which generally correspond in configuration to that of the raised conductors 8.
  • the voids 16 punched into the base 12 define the locations for the feedthroughs of one layer 1 of the circuit interconnect system.
  • the base 12 is comprised of a material having a high electrical resistivity, which may be that known in the art as KAPTON.
  • the conductive sheet 2 and the base 12 are coated with a suitable laminating material 14 (e.g. such as an epoxy).
  • the conductive sheet 2 is aligned with the base 12 so that the raised conductors 8 extend into the voids 16, as shown.
  • FIG. 5 shows a composite multilayer laminate 25 including the feedthroughs 20 of the instant interconnect system formed by the process herein disclosed.
  • a second layer 10, identical to layer 1, is formed by repeating the steps as described while referring to FIGS. 1-4.
  • Electrically conductive sheet 2-1 of layer 10 is coated with the lamination material 14-1 and attached to the base 12, as shown. Layers 1 and 10 are aligned relative to one another so that the respective raised conductors 8 and 8-1 extend through the selectively punched voids 16 in base 12.
  • the raised conductors 8 and 8-1 of layers 1 and 10, respectively, are secured to one another at junction 18 by a suitable metallurgical joining process, depending upon the composition of the raised conductors 8 and 8-1.
  • a suitable metallurgical joining process depending upon the composition of the raised conductors 8 and 8-1.
  • the raised conductors are comprised of gold
  • a diffusion bond may be formed between raised conductor 8 and 8-1.
  • a fusion bond may be formed between conductors 8 and 8-1 with the addition of a third conductor material, such as that typically having a lead-tin composition (e.g. solder).
  • the desired circuit pattern to be formed on both sides of the insulating base 12 is defined by removing the excess of the continuous conductive sheets 2 and 2-1 and the laminated material 14 and 14-1 from layers 1 and 10 of the instant composite laminate 25. This is accomplished by a suitable process, which may typically consist of a conventional etching procedure.
  • a multilayer circuit interconnect system which has a continuous electrically conductive path formed on both sides of an insulating base.
  • the conductive feedthroughs or vias of the instant invention can be selectively made in widths reduced to as small as the width of a circuit line. Because of the relatively small through-hole area consumed by the instant feedthrough configuration, the instant process is ideally suited for closely meshed circuits having high density conductor lines. Moreover, since the feedthroughs of the instant invention may essentially consist of a fine conductive line protruding through a hole in the base member from one conductive layer to another, circuit noise is minimized, as compared with that of conventional multilayer interconnect systems.
  • the instant process herein disclosed is applicable to all flexible printed circuit systems including polyimide and polyamide-imide type printed circuit systems. Additionally, the instant process may be employed for matrixing circuitry in magnetic bubble domain memory systems or the like. It is also to be understood that the instant process may be utilized for providing an interconnect system for a circuit comprised of any suitable plurality of conductive layers. For example, additional conductor "buttons" (or 8-1) can be formed on the opposite surface of conductive sheet 2 (or 2-1). These additional raised conductors can then be joined with aligned conductors on similar devices. Thus, a multilayer arrangement is provided.
  • the continuous conductive sheet of each layer of the composite laminate may be plated with a suitable conductive material (e.g. gold or the like) thereby providing an oxidation and corrosion resistant surface for the conductive sheets.
  • a suitable conductive material e.g. gold or the like
  • raised conductors 8 may be provided on opposite sides of a conductive sheet 2. That is both sides of the sheet may be operated upon concurrently (or consecutively) to produce a conductive sheet with suitable conductor patterns on the opposite sides thereof.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.

Description

The invention described herein was made in the performance of work under NASA Contract No. NASA 1-12435 and is subject to the provision of Section 305 of the National Aeronautics and Space Act of 1958 (72 STA. 435;42 U.S.C. 2457).
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for making a compact multilayer circuit interconnect system.
2. Prior Art
One example of a conventional process for making a multilayer circuit interconnect system includes forming holes in a nonconductive substrate and then building up the holes by an electroless plating technique. An alternative process includes filling the holes formed in the substrate with a swage tube. Electrical components received by the holes are electrically interconnected with conductive layers on opposite sides of the substrate through a plated hole or a swage tube. Another conventional process includes filling the holes formed in the nonconductive substrate with "balls" of conductive material (e.g. solder) and heating or pressing the balls to interconnect conductive layers of the circuit pattern. Yet another conventional multilayer circuit interconnect process includes physically jumping together conductive layers on opposite sides of the nonconductive substrate.
However, these conventional processes for forming a multilayer interconnect system consume relatively large amounts of areas on a nonconductive substrae, such as a printed circuit board, a flexible film and the like. As a consequence of the relatively large areas consumed, an interconnect system formed in accordance with any of the conventional processes is unsuitable when employed with circuit patterns having closely meshed, high density conductor lines.
SUMMARY OF THE INVENTION
Briefly, and in general terms, the process for making the multilayer circuit interconnect system of the instant invention includes the steps of forming a first layer of the interconnect system by applying a masking material in a predetermined pattern to a continuous sheet of electrically conductive material. The masking material pattern includes predetermined unmasked areas, determined by the desired locations of the feed-throughs or vias of the circuit pattern. The unmasked areas formed in the masking material are filled with an electrically conductive material. The layer of masking material is removed from the conductive sheet, leaving only a pattern of raised conductors on the conductive sheet. An electrically insulating base member is selectively cut or punched to include voids which generally correspond in configuration to that of the raised conductors. The conductive sheet and the base member are aligned with one another so that the raised conductors on the conductive layer extend into the voids which have been selectively punched into the base member. The conductive sheet is then affixed to the base member.
A second layer of the instant interconnect system is formed by repeating the steps herein described. The first and second layers are aligned relative to one another so that the respective raised conductors on each conductive sheet extend through the selectively punched voids in the base member. The second conductive sheet is then affixed to the base member. The raised conductor portions of each layer are secured to one another by suitable metallurgical joining process thereby forming the vias or feed-throughs which interconnect conductive layers on opposite sides of the base member. The desired circuit pattern to be formed on both sides of the insulating base member is defined by removing the excess of the continuous conductive sheets and the laminating material from the composite laminate formed by the first and second layers. Thus, a multilayer circuit interconnect system which consumes minimal area is formed having a continuous electrically conductive path on both sides of the insulating base member.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-6 illustrate the steps of the instant process for making a multilayer circuit interconnect system.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows the initial step of the process for making the multilayer circuit interconnect system of the instant invention. A first layer 1 of the interconnect system is formed by applying a masking material 4 in a predetermined pattern to a continuous sheet 2 of electrically conductive material. In a preferred embodiment, one example of a typical masking material 4 is that known in the art as RISTON. An example of a suitable conductive material comprising continuous sheet 2 is copper. However, it is to be understood, that other suitable electricaly conductive materials (e.g. such as aluminum) and masking materials may also be employed. The prescribed pattern of the masking material 4 applied to conductor sheet 2 is determined by the desired locations of the feedthroughs or vias which interconnect conductive layers of the circuit. The masking material pattern 4 selectively includes predetermined unmasked areas 6 which will subsequently contain the feedthroughs, as will be explained in greater detail hereinafter.
Referring now to FIG. 2, the unmasked areas 6, selectively included in the masking material pattern 4, are filled with an electrically conductive material 8 in a suitable manner. For example, electroforming, amalgam filling or other techniques may be used. In a preferred embodiment of the invention, but not regarded as a limitation thereof, the unmasked areas 6 are filled with gold. This or any other suitable electrically conductive material (e.g. copper or solder) may be employed. However, the material 8 is required to be easily joinable to itself or to another conductive material, the purpose of which will soon become apparent.
In FIG. 3, the masking material is removed from the conductive sheet 2 by any convenient process leaving only the predetermined pattern of raised conductors 8 on sheet 2. For example, if the masking material were RISTON, then the RISTON may be removed by a suitable solvent. The process for removing the masking material from the conductive sheet 2 is determined by the type of masking material employed to form the instant interconnect system.
In FIG. 4, the conductive sheet 2 is attached to an electrically insulating base member 12. The base 12, typically a printed circuit board, a flexible film or the like, is selectively cut or punched so as to include voids 16 which generally correspond in configuration to that of the raised conductors 8. The voids 16 punched into the base 12 define the locations for the feedthroughs of one layer 1 of the circuit interconnect system. The base 12 is comprised of a material having a high electrical resistivity, which may be that known in the art as KAPTON. The conductive sheet 2 and the base 12 are coated with a suitable laminating material 14 (e.g. such as an epoxy). The conductive sheet 2 is aligned with the base 12 so that the raised conductors 8 extend into the voids 16, as shown.
FIG. 5 shows a composite multilayer laminate 25 including the feedthroughs 20 of the instant interconnect system formed by the process herein disclosed. A second layer 10, identical to layer 1, is formed by repeating the steps as described while referring to FIGS. 1-4. Electrically conductive sheet 2-1 of layer 10 is coated with the lamination material 14-1 and attached to the base 12, as shown. Layers 1 and 10 are aligned relative to one another so that the respective raised conductors 8 and 8-1 extend through the selectively punched voids 16 in base 12.
The raised conductors 8 and 8-1 of layers 1 and 10, respectively, are secured to one another at junction 18 by a suitable metallurgical joining process, depending upon the composition of the raised conductors 8 and 8-1. For example, if the raised conductors are comprised of gold, a diffusion bond may be formed between raised conductor 8 and 8-1. Alternatively, if the raised conductors are comprised of copper, a fusion bond may be formed between conductors 8 and 8-1 with the addition of a third conductor material, such as that typically having a lead-tin composition (e.g. solder). It is to be understood that the foregoing are only examples of typical metallurgical processes which may be employed for joining raised conductors 8 and 8-1 together for forming the electrically conducting feedthroughs 20 of the multilayer interconnect system of the instant invention. Other suitable conventional bonding techniques, such as thermal compression, resistance welding, ultrasonic bonding, etc., may also be utilized, depending upon the materials comprising raised conductors 8 and 8-1.
Referring to FIG. 6, the desired circuit pattern to be formed on both sides of the insulating base 12 is defined by removing the excess of the continuous conductive sheets 2 and 2-1 and the laminated material 14 and 14-1 from layers 1 and 10 of the instant composite laminate 25. This is accomplished by a suitable process, which may typically consist of a conventional etching procedure.
By virtue of the instant process, a multilayer circuit interconnect system is achieved which has a continuous electrically conductive path formed on both sides of an insulating base. The conductive feedthroughs or vias of the instant invention can be selectively made in widths reduced to as small as the width of a circuit line. Because of the relatively small through-hole area consumed by the instant feedthrough configuration, the instant process is ideally suited for closely meshed circuits having high density conductor lines. Moreover, since the feedthroughs of the instant invention may essentially consist of a fine conductive line protruding through a hole in the base member from one conductive layer to another, circuit noise is minimized, as compared with that of conventional multilayer interconnect systems.
The instant process herein disclosed is applicable to all flexible printed circuit systems including polyimide and polyamide-imide type printed circuit systems. Additionally, the instant process may be employed for matrixing circuitry in magnetic bubble domain memory systems or the like. It is also to be understood that the instant process may be utilized for providing an interconnect system for a circuit comprised of any suitable plurality of conductive layers. For example, additional conductor "buttons" (or 8-1) can be formed on the opposite surface of conductive sheet 2 (or 2-1). These additional raised conductors can then be joined with aligned conductors on similar devices. Thus, a multilayer arrangement is provided.
It will be apparent that while a preferred embodiment of the invention has been shown and described, various modifications and changes may be made without departing from the true spirit and scope of the invention. For example, the continuous conductive sheet of each layer of the composite laminate (i.e., as shown in FIG. 6) may be plated with a suitable conductive material (e.g. gold or the like) thereby providing an oxidation and corrosion resistant surface for the conductive sheets. Also, raised conductors 8 may be provided on opposite sides of a conductive sheet 2. That is both sides of the sheet may be operated upon concurrently (or consecutively) to produce a conductive sheet with suitable conductor patterns on the opposite sides thereof.

Claims (7)

Having thus set forth a preferred embodiment of the instant invention, what is claimed is:
1. A process for making an interconnect system for a multilayer circuit, which comprises:
applying a masking material in a prescribed pattern selectively including masked and unmasked areas to first and second electrically conductive sheets;
filling said selectively unmasked areas with an electrically conductive material;
removing the masking material from each of said first and second sheets, thereby leaving said prescribed pattern of conductive material on each of said respective sheets;
removing through-hole areas from an electrically insulating substrate, said areas substantially corresponding in configuration to that of said prescribed pattern of conductive material;
coating at least some of said first and second conductive sheets and said insulating substrate with a laminating material;
affixing said first and second conductive sheets to said substrate so that said respective conductive material on each of said sheets is substantially aligned with respect to one another in said throughhole areas of said substrate;
removing selected portions of said first and second conductive sheets to accordingly interconnect circuit lines of said multilayer circuit through said conductive material in said through-hole areas of said substrate; and
plating said interconnect system with a protective layer of material.
2. The process recited in claim 1, further comprising joining said respective conductive material on each of said first and second conductive sheets to one another in said through-hole areas.
3. The process recited in claim 1 wherein said masking material is applied to only one surface of each of said electrically conductive sheets.
4. The process recited in claim 1 wherein said filling step is performed using an electro-chemical technique.
5. The process recited in claim 1 wherein each of the steps is repeated in order to provide an interconnect system having multiple layers.
6. The process recited in claim 2 including adding an additional layer of conductive mateial to said pattern of conductive material.
7. The process recited in claim 1, wherein said insulating substrate is comprised of a flexible material.
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Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052787A (en) * 1975-12-18 1977-10-11 Rockwell International Corporation Method of fabricating a beam lead flexible circuit
WO1985002751A1 (en) * 1983-12-15 1985-06-20 Laserpath Corporation Partially aligned multi-layered circuitry
EP0184608A2 (en) * 1984-11-02 1986-06-18 Kernforschungszentrum Karlsruhe Gmbh Process for the manufacture of mechanically separable multiconnectors for the electrical connection of micro-electronic components, and multiconnectors manufactured by this process
US4700214A (en) * 1983-12-15 1987-10-13 Laserpath Corporation Electrical circuitry
US4703559A (en) * 1984-11-02 1987-11-03 Kernforschungszentrum Karlsruhe Gmbh Method for producing connecting elements for electrically joining microelectronic components
US4720470A (en) * 1983-12-15 1988-01-19 Laserpath Corporation Method of making electrical circuitry
US4763403A (en) * 1986-12-16 1988-08-16 Eastman Kodak Company Method of making an electronic component
US4857400A (en) * 1984-02-22 1989-08-15 Gila River Products, Inc. Stratiform press pads and methods for use thereof in laminating flexible printed circuits
US4861648A (en) * 1988-03-14 1989-08-29 Gila River Products, Inc. Materials for laminating flexible printed circuits
WO1990003100A1 (en) * 1988-09-02 1990-03-22 Westinghouse Electric Corporation Printed circuit boards and method for manufacturing printed circuit boards
US4912020A (en) * 1986-10-21 1990-03-27 Westinghouse Electric Corp. Printed circuit boards and method for manufacturing printed circuit boards
US5192835A (en) * 1990-10-09 1993-03-09 Eastman Kodak Company Bonding of solid state device to terminal board
EP0533198A2 (en) * 1991-09-19 1993-03-24 Nitto Denko Corporation Flexible printed substrate
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
US5274912A (en) * 1992-09-01 1994-01-04 Rogers Corporation Method of manufacturing a multilayer circuit board
US5276955A (en) * 1992-04-14 1994-01-11 Supercomputer Systems Limited Partnership Multilayer interconnect system for an area array interconnection using solid state diffusion
US5309629A (en) * 1992-09-01 1994-05-10 Rogers Corporation Method of manufacturing a multilayer circuit board
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
EP0608726A1 (en) * 1993-01-26 1994-08-03 Dyconex Patente Ag Process for plating through-connections between conducting foils
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US5435732A (en) * 1991-08-12 1995-07-25 International Business Machines Corporation Flexible circuit member
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US6381837B1 (en) * 1998-09-04 2002-05-07 Visteon Global Technologies, Inc. Method for making an electronic circuit assembly
EP1272019A1 (en) * 2000-02-14 2003-01-02 Ibiden Co., Ltd. Printed-circuit board, multilayer printed-circuit board and method of manufacture thereof
US20040154162A1 (en) * 2003-02-06 2004-08-12 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7982504B1 (en) 2010-01-29 2011-07-19 Hewlett Packard Development Company, L.P. Interconnection architecture for multilayer circuits
US9324718B2 (en) 2010-01-29 2016-04-26 Hewlett Packard Enterprise Development Lp Three dimensional multilayer circuit

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US3152938A (en) * 1957-06-12 1964-10-13 Osifchin Nicholas Method of making printed circuits
US3098951A (en) * 1959-10-29 1963-07-23 Sippican Corp Weldable circuit cards
US3324014A (en) * 1962-12-03 1967-06-06 United Carr Inc Method for making flush metallic patterns
US3835531A (en) * 1971-06-10 1974-09-17 Int Computers Ltd Methods of forming circuit interconnections

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052787A (en) * 1975-12-18 1977-10-11 Rockwell International Corporation Method of fabricating a beam lead flexible circuit
WO1985002751A1 (en) * 1983-12-15 1985-06-20 Laserpath Corporation Partially aligned multi-layered circuitry
US4700214A (en) * 1983-12-15 1987-10-13 Laserpath Corporation Electrical circuitry
US4720470A (en) * 1983-12-15 1988-01-19 Laserpath Corporation Method of making electrical circuitry
US4857400A (en) * 1984-02-22 1989-08-15 Gila River Products, Inc. Stratiform press pads and methods for use thereof in laminating flexible printed circuits
EP0184608A2 (en) * 1984-11-02 1986-06-18 Kernforschungszentrum Karlsruhe Gmbh Process for the manufacture of mechanically separable multiconnectors for the electrical connection of micro-electronic components, and multiconnectors manufactured by this process
US4703559A (en) * 1984-11-02 1987-11-03 Kernforschungszentrum Karlsruhe Gmbh Method for producing connecting elements for electrically joining microelectronic components
EP0184608A3 (en) * 1984-11-02 1989-01-04 Kernforschungszentrum Karlsruhe Gmbh Process for the manufacture of mechanically separable multiconnectors for the electrical connection of micro-electronic components, and multiconnectors manufactured by this process
US4912020A (en) * 1986-10-21 1990-03-27 Westinghouse Electric Corp. Printed circuit boards and method for manufacturing printed circuit boards
US4763403A (en) * 1986-12-16 1988-08-16 Eastman Kodak Company Method of making an electronic component
US4861648A (en) * 1988-03-14 1989-08-29 Gila River Products, Inc. Materials for laminating flexible printed circuits
WO1990003100A1 (en) * 1988-09-02 1990-03-22 Westinghouse Electric Corporation Printed circuit boards and method for manufacturing printed circuit boards
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5192835A (en) * 1990-10-09 1993-03-09 Eastman Kodak Company Bonding of solid state device to terminal board
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
US5435732A (en) * 1991-08-12 1995-07-25 International Business Machines Corporation Flexible circuit member
EP0533198A2 (en) * 1991-09-19 1993-03-24 Nitto Denko Corporation Flexible printed substrate
EP0533198A3 (en) * 1991-09-19 1995-11-02 Nitto Denko Corp Flexible printed substrate
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5276955A (en) * 1992-04-14 1994-01-11 Supercomputer Systems Limited Partnership Multilayer interconnect system for an area array interconnection using solid state diffusion
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
US5274912A (en) * 1992-09-01 1994-01-04 Rogers Corporation Method of manufacturing a multilayer circuit board
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
US5309629A (en) * 1992-09-01 1994-05-10 Rogers Corporation Method of manufacturing a multilayer circuit board
EP0608726A1 (en) * 1993-01-26 1994-08-03 Dyconex Patente Ag Process for plating through-connections between conducting foils
US5457881A (en) * 1993-01-26 1995-10-17 Dyconex Patente Ag Method for the through plating of conductor foils
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US6381837B1 (en) * 1998-09-04 2002-05-07 Visteon Global Technologies, Inc. Method for making an electronic circuit assembly
EP1272019A1 (en) * 2000-02-14 2003-01-02 Ibiden Co., Ltd. Printed-circuit board, multilayer printed-circuit board and method of manufacture thereof
EP1272019A4 (en) * 2000-02-14 2004-12-29 Ibiden Co Ltd Printed-circuit board, multilayer printed-circuit board and method of manufacture thereof
US20040154162A1 (en) * 2003-02-06 2004-08-12 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7320173B2 (en) * 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7982504B1 (en) 2010-01-29 2011-07-19 Hewlett Packard Development Company, L.P. Interconnection architecture for multilayer circuits
US9324718B2 (en) 2010-01-29 2016-04-26 Hewlett Packard Enterprise Development Lp Three dimensional multilayer circuit

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