Nothing Special   »   [go: up one dir, main page]

US20110163438A1 - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

Info

Publication number
US20110163438A1
US20110163438A1 US13/049,109 US201113049109A US2011163438A1 US 20110163438 A1 US20110163438 A1 US 20110163438A1 US 201113049109 A US201113049109 A US 201113049109A US 2011163438 A1 US2011163438 A1 US 2011163438A1
Authority
US
United States
Prior art keywords
wiring board
heat sink
semiconductor device
hole
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/049,109
Inventor
Noriyuki Takahashi
Mamoru SHISHIDO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US13/049,109 priority Critical patent/US20110163438A1/en
Publication of US20110163438A1 publication Critical patent/US20110163438A1/en
Priority to US13/299,666 priority patent/US8232634B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method of the same, and more particularly to a technique effectively applied to a semiconductor package having improved heat dissipation properties and a manufacturing method of the same.
  • a semiconductor device of a BGA package configuration is manufactured by mounting a semiconductor chip on a wiring board, electrically connecting electrodes of the semiconductor chip and connecting terminals of the wiring board by bonding wires, sealing the semiconductor chip and the bonding wires with resin, and connecting solder balls on a rear surface of the wiring board.
  • Japanese Patent Application Laid-Open Publication No. 2004-296565 discloses a technique relating to the manufacturing method of a semiconductor element housing package, in which openings for cavities are bored in a panel-shaped resin substrate having a plurality of resin boards and heat sinks are formed and bonded so as to close the openings in the cavity periphery of one surface of the resin board.
  • Japanese Patent Application Laid-Open Publication No. 2003-46027 discloses a technique, in which, in a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board having a notch space in its center part, the plastic circuit board and the heat sink are bonded by a fastening member and the plastic circuit board and at least an end part of the bonding surface of the heat sink are covered with adhesive resin.
  • Japanese Patent Application Laid-Open Publication No. 2004-63830 discloses a technique, in which, in a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board, the plastic circuit board and the heat sink are bonded by a fastening member and the plastic circuit board and the heat sink are bonded by a flanged pin, and moreover, the flanged pin is press-fitted and its top end is accommodated inside the heat sink so as to be pressure-welded and bonded to the heat sink.
  • Patent document 4 discloses a technique relating to a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board having a notch space in its center part, in which a fastening member for bonding the plastic circuit board and the heat sink is provided.
  • the calorific value of an incorporated semiconductor chip is also increased. This is because the driving power is also increased with the improvement in performance of a semiconductor chip (applied voltage value is also increased). Hence, it is desired to take heat dissipation measures for the heat generated in the semiconductor chip incorporated inside the semiconductor device.
  • various means such as disposing thermal balls, installing a heat dissipation fin on a sealing body or providing a plane for the wiring board are possible.
  • these means can dissipate only about 2.5 W at best.
  • the cause thereof is that, for example, in the case of the thermal ball, there is a distance between a semiconductor device and a mounting board by the height of the ball, and the path through which the heat can pass through is provided only in the path corresponding to the diameter of the ball.
  • An object of the present invention is to provide a technique capable of improving the heat dissipation properties of the semiconductor device.
  • Another object of the present invention is to provide a technique capable of improving the manufacturing yield of the semiconductor device.
  • a semiconductor device comprises: (a) a board having a first main surface and a second main surface opposite to the first main surface, the board including a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, a plurality of second electrodes formed around the through-hole on the second main surface, and a heat sink disposed inside the through-hole; (b) a semiconductor chip having a third main surface, on which a plurality of third electrodes are formed, and mounted on an upper surface of the heat sink; (c) a plurality of conductive wires electrically connecting the plurality of third electrodes of the semiconductor chip and the plurality of first electrodes of the board; (d) a sealing portion for sealing the semiconductor chip and the plurality of conductive wires; and (e) a plurality of external terminals formed on the plurality of second electrodes of the board, respectively.
  • a thickness of the heat sink is larger than a thickness of the board
  • the heat sink has a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of the upper surface of the heat sink, the protruded portion is located on the first main surface of the board outside the through-hole, and a lower surface of the protruded portion contacts to the first main surface of the board.
  • a manufacturing method of a semiconductor device comprises: (a) a step of preparing a heat sink having a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of an upper surface of the heat sink; (b) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, and a plurality of second electrodes formed around the through-hole on the second main surface; (c) a step of disposing the heat sink inside the through-hole of the board so that the protruded portion is located on the first main surface of the board outside the through-hole and a lower surface of the protruded portion contacts to the first main surface of the board; (d) a step of mounting, on the upper surface of the heat sink, the semiconductor chip having a third main surface on which a pluralit
  • a manufacturing method of a semiconductor device comprises: (a) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, a plurality of second electrodes formed around the through-hole on the second main surface, and a heat sink disposed inside the through-hole; (b) a step of mounting, on an upper surface of the heat sink, a semiconductor chip having a third main surface on which a plurality of third electrodes are formed; (c) a step of electrically connecting the plurality of third electrodes of the semiconductor chip and the plurality of first electrodes of the board through a plurality of conductive wires; (d) a step of sealing the semiconductor chip and the plurality of conductive wires by resin; and (e) a step of forming a plurality of external terminals on the plurality of second electrodes of the board,
  • a thickness of the heat sink is larger than a thickness of the board
  • the heat sink has a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of the upper surface of the heat sink, the protruded portion is located on the first main surface of the board outside the through-hole, and a lower surface of the protruded portion contacts to the first main surface of the board.
  • a manufacturing method of a semiconductor device comprises: (a) a step of preparing a frame in which a plurality of heat sinks are joined to a frame portion by a joining portion, respectively; (b) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a plurality of through-holes reaching the second main surface from the first main surface, a plurality of first electrodes formed around each through-hole on the first main surface, and a plurality of second electrodes formed around each through-hole on the second main surface; (c) a step of mounting, on upper surfaces of the plurality of heat sinks of the frame, a plurality of semiconductor chips each having a third main surface on which a plurality of third electrodes are formed, respectively; (d) a step of disposing the frame on the first main surface of the board and inserting each heat sink into each through-hole of the board; (e) a step of electrically connecting the plurality of third electrodes of the plurality
  • a manufacturing method of a semiconductor device comprises: (a) a step of preparing a frame in which a plurality of heat sinks are joined to a frame portion by a joining portion, respectively; (b) a step of preparing a plurality of boards each having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, and a plurality of second electrodes formed around the through-hole on the second main surface; (c) a step of mounting, on upper surfaces of the plurality of heat sinks of the frame, a plurality of semiconductor chips each having a third main surface on which a plurality of third electrodes are formed, respectively; (d) a step of fixing the frame and the plurality of boards from a first main surface side of each board so that each heat sink is inserted into the through-hole of each board; (e) a step of electrically connecting the pluralit
  • FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2 is a perspective plan view of the semiconductor device of FIG. 1 ;
  • FIG. 3 is a lower surface view of the semiconductor device of FIG. 1 ;
  • FIG. 4 is a cross-sectional view of a heat sink used in the semiconductor device of FIG. 1 ;
  • FIG. 5 is an upper surface view of the heat sink of FIG. 4 ;
  • FIG. 6 is a lower surface view of the heat sink of FIG. 4 ;
  • FIG. 7 is an upper surface view of a wiring board used in the semiconductor device of FIG. 1 ;
  • FIG. 8 is a process flowchart showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 9 is a plan view of the wiring board used in the manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of the wiring board of FIG. 9 ;
  • FIG. 11 is a plan view of a frame used in the manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the frame of FIG. 11 ;
  • FIG. 13 is a plan view showing the manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 13 ;
  • FIG. 15 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 13 ;
  • FIG. 16 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 15 ;
  • FIG. 17 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 15 ;
  • FIG. 18 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 17 ;
  • FIG. 19 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 17 ;
  • FIG. 20 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 19 ;
  • FIG. 21 is a cross-sectional view showing a process of disposing a heat sink inside a through-hole of a wiring board
  • FIG. 22 is a cross-sectional view showing the process of disposing the heat sink inside the through-hole of the wiring board subsequent to FIG. 21 ;
  • FIG. 23 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 19 ;
  • FIG. 24 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 23 ;
  • FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 24 ;
  • FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 25 ;
  • FIG. 27 is a cross-sectional view showing another manufacturing process of a semiconductor device according to one embodiment of the present invention.
  • FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 27 ;
  • FIG. 29 is a cross-sectional view showing the semiconductor device manufactured in the process of FIG. 27 and FIG. 28 ;
  • FIG. 30 is a process flowchart showing another manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 31 is a plan view showing another manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 32 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 31 ;
  • FIG. 33 is a cross-sectional view showing a process of disposing a heat sink inside a through-hole of a wiring board
  • FIG. 34 is a cross-sectional view showing the process of disposing the heat sink inside the through-hole of the wiring board
  • FIG. 35 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 31 ;
  • FIG. 36 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 35 ;
  • FIG. 37 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 35 ;
  • FIG. 38 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 37 ;
  • FIG. 39 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 40 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 41 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 42 is a cross-sectional view showing a modified example of the semiconductor device according to one embodiment of the present invention.
  • FIG. 43 is a cross-sectional view showing another modified example of the semiconductor device according to one embodiment of the present invention.
  • FIG. 44 is a perspective plan view of the semiconductor device of FIG. 43 ;
  • FIG. 45 is a lower surface view of the semiconductor device of FIG. 43 ;
  • FIG. 46 is a perspective plan view showing still another modified example of the semiconductor device according to one embodiment of the present invention.
  • FIG. 47 is a cross-sectional view showing still another modified example of the semiconductor device according to one embodiment of the present invention.
  • FIG. 48 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 49 is another cross-sectional view of the semiconductor device of FIG. 48 ;
  • FIG. 50 is a perspective plan view of the semiconductor device of FIG. 48 ;
  • FIG. 51 is a lower surface view of the semiconductor device of FIG. 48
  • FIG. 52 is a cross-sectional view of a heat sink used in the semiconductor device of FIG. 48 ;
  • FIG. 53 is another cross-sectional view of the heat sink of FIG. 52 ;
  • FIG. 54 is an upper surface view of the heat sink of FIG. 52 ;
  • FIG. 55 is a lower surface view of the heat sink of FIG. 52 ;
  • FIG. 56 is a cross-sectional view of a wiring board used in the semiconductor device of FIG. 48 ;
  • FIG. 57 is an upper surface view of the wiring board of FIG. 56 ;
  • FIG. 58 is a plan view of a frame used for manufacturing the semiconductor device of FIG. 48 ;
  • FIG. 59 is an explanatory drawing showing a process of disposing a heat sink inside a through-hole of a wiring board
  • FIG. 60 is an explanatory drawing showing the process of disposing the heat sink inside the through-hole of the wiring board
  • FIG. 61A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 61B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 62A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 62B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 63A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 63B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 64A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 64B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 65A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 65B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 66A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 66B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 67A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 67B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 68A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 68B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 69A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 69B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 70A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 70B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 71 is an upper surface view showing a modified example of the wiring board
  • FIG. 72 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 73 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 72 ;
  • FIG. 74 is an explanatory drawing of the process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 72 ;
  • FIG. 75 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board
  • FIG. 76 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board
  • FIG. 77 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 78 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board
  • FIG. 79 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 80 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board
  • FIG. 81 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 82 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 83 is a cross-sectional view showing a modified example of the semiconductor device according to another embodiment of the present invention.
  • FIG. 84 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 83 ;
  • FIG. 85 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 83 ;
  • FIG. 86 is a process flowchart showing a manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 87 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 88 is a lower surface view of the frame of FIG. 87 ;
  • FIG. 89 is a cross-sectional view of the frame of FIG. 87 ;
  • FIG. 90 is another cross-sectional view of the frame of FIG. 87 ;
  • FIG. 91 is a plan view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 92 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 91 ;
  • FIG. 93 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 94 is a cross-sectional view of the wiring board of FIG. 93 ;
  • FIG. 95 is another cross-sectional view of the wiring board of FIG. 93 ;
  • FIG. 96 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 91 ;
  • FIG. 97 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 96 ;
  • FIG. 98 is another cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 96 ;
  • FIG. 99 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 100 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 101 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 96 ;
  • FIG. 102 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 101 ;
  • FIG. 103 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 101 ;
  • FIG. 104 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 103 ;
  • FIG. 105 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 104 ;
  • FIG. 106 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 107 is another cross-sectional view of the semiconductor device of FIG. 106 ;
  • FIG. 108 is a perspective plan view of the semiconductor device of FIG. 106 ;
  • FIG. 109 is a lower surface view of the wiring board in the semiconductor device of FIG. 106 ;
  • FIG. 110 is an explanatory drawing showing a technique of fixing the frame to the wiring board by using a bonding agent
  • FIG. 111 is an explanatory drawing showing a technique of fixing the frame to the wiring board by using the boding agent
  • FIG. 112 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 113 is a lower surface view of the frame of FIG. 112 ;
  • FIG. 114 is a cross-sectional view of the frame of FIG. 112 ;
  • FIG. 115 is another cross-sectional view of the frame of FIG. 112 ;
  • FIG. 116 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 117 is a plan view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 118 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 117 ;
  • FIG. 119 is another cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 117 ;
  • FIG. 120 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 121 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 122 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 123 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 124 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 117 ;
  • FIG. 125 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 126 is a perspective plan view of the semiconductor device of FIG. 125 ;
  • FIG. 127 is a process flowchart showing a manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 128 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 129 is a lower surface view of the frame of FIG. 128 ;
  • FIG. 130 is a cross-sectional view of the frame of FIG. 128 ;
  • FIG. 131 is an upper surface view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 132 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 131 ;
  • FIG. 133 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 134 is an upper surface view showing the manufacturing process of the semiconductor device subsequent to FIG. 131 ;
  • FIG. 135 is a lower surface view showing the same manufacturing process of the semiconductor device as FIG. 134 ;
  • FIG. 136 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 134 ;
  • FIG. 137 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 138 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 139 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 140 is an explanatory drawing showing a technique of fixing the frame to the wiring board
  • FIG. 141 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 136 ;
  • FIG. 142 is an upper surface view showing the manufacturing process of the semiconductor device subsequent to FIG. 141 ;
  • FIG. 143 is a lower surface view showing the same manufacturing process of the semiconductor device as FIG. 142 ;
  • FIG. 144 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 142 ;
  • FIG. 145 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 144 ;
  • FIG. 146 is an explanatory drawing showing a process of cutting the frame
  • FIG. 147 is an explanatory drawing showing a process of cutting the frame
  • FIG. 148 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 149 is another cross-sectional view of the semiconductor device of FIG. 148 ;
  • FIG. 150 is a perspective plan view of the semiconductor device of FIG. 148 ;
  • FIG. 151 is a lower surface view of the wiring board in the semiconductor device of FIG. 148 ;
  • FIG. 152 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 153 is a cross-sectional view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 154 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 153 ;
  • FIG. 155 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 154 ;
  • FIG. 156 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 155 ;
  • FIG. 157 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 156 ;
  • FIG. 158 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 157 ;
  • FIG. 159 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 160 is a cross-sectional view showing a state in which a heat dissipation fin is mounted on the upper surface of the semiconductor device of FIG. 152 ;
  • FIG. 161 is a cross-sectional view showing a state in which a heat dissipation fin is mounted on the upper surface of the semiconductor device of FIG. 159 ;
  • FIG. 162 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 163 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 164 is a cross-sectional view showing a technique of caulking (fixing) the heat sink according to another embodiment of the present invention to the wiring board;
  • FIG. 165 is a cross-sectional view showing a technique of caulking (fixing) the heat sink to the wiring board subsequent to FIG. 164 .
  • the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable.
  • the components are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle.
  • the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it can be conceived that they are apparently excluded in principle. The same goes for the numerical value and the range described above.
  • hatching is omitted even in a cross-sectional view and is used even in a plan view so as to make the drawings easy to see.
  • FIG. 1 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 according to one embodiment of the present invention
  • FIG. 2 is a perspective plan view (upper surface view) of the semiconductor device 1 when seen through a sealing resin 7
  • FIG. 3 is a lower surface view (bottom view, rear view, plan view) of the semiconductor device 1 .
  • the cross-sections cut along the line A 1 -A 1 of FIGS. 2 and 3 almost correspond to FIG. 1 .
  • FIG. 4 is a cross-sectional view (side cross-sectional view) of a heat sink 4 used in the semiconductor device 1 of the present embodiment
  • FIG. 5 is an upper surface view (plan view) of the heat sink 4
  • FIG. 6 is a lower surface view (plan view) of the heat sink 4 .
  • the cross-sections cut along the line A 2 -A 2 of FIGS. 5 and 6 almost correspond to FIG. 4 , but FIGS. 4 and 1 show the same cross-sectional positions.
  • FIG. 7 is an upper surface view (plan view) of a wiring board 2 used in the semiconductor device 1 of the present embodiment.
  • FIG. 7 is a plan view, hatching is applied to the wiring board 2 and connecting terminals 17 of its upper surface 2 a so as to make a position and a shape of a through-hole 3 in the wiring board 2 easily understood.
  • FIG. 2 the position of the through-hole 3 of the wiring board 2 which is invisible and concealed by the heat sink 4 even when the sealing resin 7 is seen through is shown by a dotted line for easy understanding.
  • the semiconductor device 1 of the present embodiment shown in FIGS. 1 to 3 is the semiconductor device of a resin-sealed semiconductor package configuration.
  • the semiconductor device 1 of the present embodiment includes the wiring board 2 , the heat sink 4 disposed inside the through-hole 3 of the wiring board 2 , a semiconductor chip 5 mounted on the heat sink 4 , a plurality of bonding wires 6 electrically connecting a plurality of electrodes 5 a of the semiconductor chip 5 and a plurality of connecting terminals 17 of the wiring board 2 , a sealing resin 7 covering the upper surface 2 a of the wiring board 2 including the semiconductor chip 5 and the bonding wires 6 , and a plurality of solder balls 8 provided on the lower surface 2 b of the wiring board 2 .
  • the wiring board (board, package board, wiring board for package) 2 includes an upper surface (first main surface) 2 a which is one main surface and a lower surface (rear surface, second main surface) 2 b which is the main surface opposite to the upper surface 2 a .
  • the through-hole 3 reaching the lower surface 2 b from the upper surface 2 a of the wiring board 2 is provided in the vicinity of the center of the wiring board 2 , and the heat sink 4 is disposed and fixed inside this through-hole 3 .
  • the heat sink (Heat Spreader) 4 has an upper surface (front surface, main surface, chip supporting surface) 9 a which is one main surface and a lower surface 9 b which is a main surface opposite to the upper surface 9 a , and the semiconductor chip 5 is mounted on the upper surface 9 a of the heat sink 4 . Consequently, the upper surface 9 a of the heat sink 4 is a chip mounting surface (surface on which the semiconductor chip 5 is mounted). The chip mounting surface of the heat sink 4 is almost parallel to the upper surface 2 a of the wiring board 2 .
  • a thickness t 1 of the heat sink 4 is larger than a thickness t 2 of the wiring board 2 (that is, t 1 >t 2 ), and a lower part (including the lower surface 9 b ) of the heat sink 4 protrudes from the lower surface 2 b of the wiring board 2 .
  • the thickness t 1 of the heat sink 4 corresponds to a dimension (distance) from the upper surface 9 a (chip mounting surface) of the heat sink 4 to the lower surface 9 b of the heat sink 4
  • the thickness t 2 of the wiring board 2 corresponds to the dimension (distance) from the upper surface 2 a to the lower surface 2 b of the wiring board 2 .
  • the heat sink 4 can be taken also as a conductive portion (metal portion) for chip mounting.
  • the heat sink 4 thicker than the wiring board 2 is disposed inside the through-hole 3 of the wiring board 2 , and the semiconductor chip 5 is disposed on this heat sink 4 , thereby transmitting a heat generated in the semiconductor chip 5 at the time of using the semiconductor device 1 to the heat sink 4 , so that the heat can be dissipated to the outside of the semiconductor device 1 from an exposed portion (lower surface 9 b of the heat sink 4 ) of the heat sink 4 .
  • the thickness t 1 of the heat sink 4 it is effective to make the thickness t 1 of the heat sink 4 larger, and the heat dissipation properties of the semiconductor device 1 can be improved by making the thickness t 1 of the heat sink 4 larger than the thickness t 2 of the wiring board 2 (that is, t 1 >t 2 ).
  • the thickness t 1 of the heat sink 4 can be made about 0.6 mm, or when the thickness t 2 of the wiring board 2 is about 0.6 mm, the thickness t 1 of the heat sink 4 can be made about 1.2 mm.
  • the heat sink 4 is a member for dissipating the heat generated in the semiconductor chip 5 and preferably has high heat conductivity, and it is necessary that the heat conductivity (heat conductivity coefficient) of the heat sink 4 is higher than at least the heat conductivity (heat conductivity coefficient) of the wiring board 2 and the sealing resin 7 . Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat sink 4 is preferably made of a conductive material and is more preferably formed of a metal material. It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 4 because high heat conductivity of the heat sink 4 can be obtained and the processing (formation of the heat sink 4 ) is easy.
  • a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 4 because high heat conductivity of the heat sink 4 can be obtained and the processing (formation of the heat sink 4 ) is easy.
  • the trough-hole 3 of the wiring board 2 has, for example, a rectangular planar shape.
  • the cross-sectional shapes of a portion located inside the through hole 3 and a portion protruding downward from the lower surface 2 b of the wiring board 2 (lower part of the heat sink 4 ) parallel to the upper surface 2 a of the wiring board 2 are almost the same as the planar shape of the through-hole 3 of the wiring board 2 .
  • a side surface (side wall) 10 of the heat sink 4 contacts to (adheres to) an inner wall (side wall, side surface) of the through-hole 3 of the wiring board 2 .
  • the lower surface 9 b of the heat sink 4 also has almost the same planar shape as the planar shape of the through-hole 3 of the wiring board 2 .
  • the heat sink 4 has a protruded portion (projecting portion, overhang portion, hook portion) 11 protruding to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface 10 of the heat sink 4 (side surface 10 contacting to the inner wall of the through-hole 3 of the wiring board 2 ) in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 , and this protruded portion 11 is located on the upper surface 2 a of the wiring board 2 outside the through-hole 3 and the lower surface of the protruded portion 11 contacts to the upper surface 2 a of the wiring board 2 .
  • the heat sink 4 has the protruded portion 11 , which protrudes to the upper side of the upper surface 2 a of the wiring board 2 from above the through-hole 3 and extends on the upper surface 2 a of the wiring board 2 , on the peripheral edge portion of the upper surface 9 a of the heat sink 4 , and this protruded portion 11 projects (overhung) on the upper surface 2 a of the wiring board from the through-hole 3 .
  • This protruded portion 11 is integrally formed with the heat sink 4 and can be taken as a part of the heat sink 4 .
  • the portions other than the protruded portions 11 of the heat sink 4 are located at a planarly overlapped position with the through-hole 3 , and the protruded portions 11 only are located outside the through-hole 3 (at the position not planarly overlapped with the through-hole 3 , that is, at the position overlapped with the wiring board 2 ).
  • a planar position of the through-hole 3 when the heat sink 4 is disposed inside the through-hole 3 of the wiring board 2 is shown by a dotted line in FIG. 5 .
  • the heat sink 4 is inserted and fixed into the through-hole 3 from the upper surface 2 a side of the wiring board 2 before the sealing resin 7 is formed. If the heat sink 4 has no protruded portion 11 and the cross-sectional shape parallel to the upper surface 2 a of the wiring board 2 is the same as the planar shape of the through-hole 3 in any part of the heat sink 4 unlike the present embodiment, the heat sink 4 is likely to fall off from the through-hole 3 of the wiring board 2 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 2 a side of the wiring board 2 .
  • the heat sink 4 since the heat sink 4 is provided with the protruded portion 11 , the protruded portion 11 of the heat sink 4 is caught on the upper surface 2 a of the wiring board 2 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 2 a side of the wiring board 2 , and therefore, it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 2 , and the heat sink 4 can be retained inside the through-hole 3 of the wiring board 2 .
  • the protruded portion 11 of the heat sink 4 functions as a stopper for preventing the sink plate 4 from falling off from the through-hole 3 of the wiring board 2 , it is necessary to provide the protruded portion 11 at least in a part of the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 .
  • the protruded portion 11 is provided at least in a part of the peripheral edge portion of the upper surface 9 a of the heat sink 4 though not in the entire peripheral edge portion of the upper surface 9 a of the heat sink 4 , it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 2 .
  • the protruded portion 11 in a flange shape or in an overhang shape
  • the heat sink 4 can be stably disposed inside the through-hole 3 of the wiring board 2 . Therefore, in the present embodiment, in the heat sink 4 , the protruded portion 11 is provided at least in a part of the peripheral edge portion of the upper surface 9 a of the heat sink 4 , and more preferably provided in the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 .
  • the protruded portion 11 is provided in the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 , the protruded portion 11 is preferably formed in a flange shape or in an overhang shape in the heat sink 4 .
  • the side surface 10 of the heat sink 4 contacting to the inner wall of the through-hole 3 preferably has a tapered shape (is tapered).
  • the part of the heat sink 4 located inside the through-hole 3 has a tapered cross-sectional shape (shape in cross-section vertical to the chip mounting surface of the heat sink 4 ).
  • the dimension of the heat sink 4 of the portion except the protruded portion is slightly larger on the upper side than on the lower side. More specifically, a dimension L 2 of the upper part of the heat sink 4 (except the protruded portion 11 ) is slightly larger than a dimension L 1 of the lower part of the heat sink 4 (that is, L 2 >L 1 ).
  • this side surface 10 is not vertical to the chip mounting surface (upper surface 2 a ) of the heat sink 4 , but is inclined by an angle ⁇ with respect to the vertical direction (here, ⁇ >0). That is, a vertical line of the side surface 10 of the heat sink 4 (line vertical to the side surface 10 ) is not parallel to the chip mounting surface (upper surface 2 a ) of the heat sink 4 , but is inclined by an angle ⁇ with respect to the parallel direction.
  • the side surface 10 of the heat sink 4 contacting to the inner wall of the through-hole 3 is not vertical to the upper surface 2 a of the wiring board 2 , but is inclined by the angle ⁇ with respect to the vertical direction.
  • This inclined angle ⁇ of the side surface 10 of the heat sink 4 is preferably about 3 to 30°.
  • the inner wall of the through-hole 3 of the wiring board 2 before the heat sink 4 is inserted is almost vertical to the upper surface 2 a of the wiring board 2 .
  • a dimension L 3 of the through-hole 3 of the wiring board 2 before the heat sink 4 is inserted is made the same or slightly larger than the dimension L 1 of the lower part of the heat sink 4 (that is, L 1 ⁇ L 3 ), and is made smaller than the dimension L 2 of the upper portion of the heat sink 4 (except the protruded portion 11 ) (that is, L 3 ⁇ L 2 ).
  • the heat sink 4 when the heat sink 4 is inserted into the through-hole 3 from the upper surface 2 a side of the wiring board 2 at the time of manufacturing the semiconductor device 1 , the heat sink 4 is pushed into the through-hole 3 , and the heat sink 4 and the wiring board 2 can be caulked by the tapered shape of the side surface 10 of the heat sink 4 , and the heat sink 4 can be fixed to the wiring board 2 .
  • the heat sink 4 when the heat sink 4 is inserted into the through-hole 3 from the upper surface 2 a side of the wiring board 2 at the time of manufacturing the semiconductor device 1 , since the through-hole 3 of the wiring board is expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4 , a force for causing the inner wall of the through-hole 3 of the wiring board 2 to be adhered and pushed to the side surface 10 of the heat sink 4 is operated by its reaction, so that the heat sink 4 can be fixed to the wiring board 2 . Accordingly, since the heat sink 4 can be fixed to the wiring board 2 until the sealing resin 7 is formed, the manufacture of the semiconductor device 1 can be facilitated.
  • the semiconductor chip 5 has a rectangular (square) shape in a plane vertical to its thickness. For example, after various semiconductor elements or semiconductor integrated circuits and the like are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single-crystal silicon or the like, a rear surface grinding of the semiconductor substrate is performed as required, and then, the semiconductor substrate is separated into each semiconductor chip 5 by the dicing or the like.
  • a semiconductor substrate semiconductor wafer
  • a rear surface grinding of the semiconductor substrate is performed as required, and then, the semiconductor substrate is separated into each semiconductor chip 5 by the dicing or the like.
  • the semiconductor chip 5 has a front surface (main surface, upper surface, third main surface on the semiconductor element formation side) 5 b and a rear surface (main surface, lower surface opposite to the main surface on the semiconductor element formation side) 5 c which are opposed to each other, and it is mounted (disposed) on the upper surface 9 a of the heat sink 4 so that the front surface 5 b of the semiconductor chip 5 is directed upward, and the rear surface 5 c of the semiconductor chip 5 is bonded and fixed to the upper surface 9 a of the heat sink 4 through a bonding agent (die bond agent, bonding agent, adhesive) 14 .
  • a bonding agent die bond agent, bonding agent, adhesive
  • the planar dimensions of the through-hole 3 of the wiring board 2 and the heat sink 4 are larger than the planar dimensions of the semiconductor chip 5 , respectively, and the semiconductor chip 5 mounted on the heat sink 4 is disposed so as to be planarly enclosed in the through-hole 3 of the wiring board 2 and the heat sink 4 .
  • the bonding agent 14 the bonding agent having high heat conductivity is preferably used, and for example, solder or a conductive paste material (the paste material preferable as a conductive paste material is silver paste) can be used.
  • a plurality of electrodes (bonding pad, pad electrode, electrode pad, third electrode) 5 a are formed on the front surface of the semiconductor chip 5 , and the electrodes 5 a are electrically connected to the semiconductor element or the semiconductor integrated circuit formed inside the semiconductor chip 5 or on the surface layer portion.
  • the wiring board 2 includes an insulating base material layer (insulating board, core material) 16 and a conductor layer (conductor pattern, conductor film pattern, wiring layer) formed on the upper surface and the lower surface of the base material layer 16 .
  • a board in which the conductor layer is formed on the upper surface and the lower surface of one insulating layer (base material layer 16 ) or a multilayer wiring board (multilayer board) in which a plurality of insulating layers (base material layers) and a plurality of conductor layers (wiring layers) are alternately formed (integrated) over multiple layers may be used as the wiring board 2 , but the multilayer wiring board is more preferable.
  • the illustration of the wiring layer inside the wiring board 2 (interlayer of the base material layer 16 ) is omitted.
  • a resin material for example, a glass epoxy resin
  • the like can be used as the base material layer 16 of the wiring board 4 .
  • the conductor layers of the upper surface and the lower surface of the base material layer 16 are developed into certain patterns and can be formed by a conductive material such as a copper thin film formed by, for example, an electroplating method.
  • a plurality of the connecting terminals (electrodes, bonding leads, bonding pads, pad electrodes, first electrodes) 17 and wirings connected thereto for connecting the bonding wires 6 are formed on the upper surface 2 a of the wiring board 2 by the conductor layer of the upper surface of the base material layer 16
  • a plurality of conductive lands (electrodes, land electrodes, pads, terminals, second electrodes) 18 for connecting the solder balls 8 are formed on the lower surface 2 b of the wiring board 2 by the conductor layer of the lower surface of the base material layer 16 .
  • the plurality of connecting terminals 17 are disposed (formed) around the through-hole 3 on the upper surface 2 a of the wiring board 2
  • the plurality of lands 18 are disposed (formed) around the through-hole 3 on the lower surface 2 b of the wiring board 2
  • solder resist layers can be formed according to need on the upper surface 2 a and the lower surface 2 b of the wiring board 2 .
  • the connecting terminals 17 and the lands 18 are exposed from a solder resist layer, and other conductor layers are covered by the solder resist layer.
  • the wirings (wirings connected with the connecting terminals 17 ) of the upper surface 2 a of the wiring board 2 and the lands 18 of the lower surface 2 b are electrically connected through conductors and the like inside the unillustrated through-hole formed in (base material layer 16 of) the wiring board 2 .
  • the unillustrated through-holes for connecting the wirings and the lands 18 are sufficiently small in planar dimension (dimension in a planar surface parallel to the upper surface 2 a and the lower surface 2 b of the wiring board 2 ) as compared with the through-hole 3 .
  • the plurality of electrodes 5 a of the semiconductor chip 5 are electrically connected to the plurality of connecting terminals 17 of the wiring board 2 through a plurality of bonding wires 6 , and further electrically connected to the plurality of lands 18 of the lower surface 2 b of the wiring board 2 through the wirings of the wiring board 2 (wirings connected with the connecting terminals 17 ) and the conductors inside the through-holes (not shown) and the like.
  • the bonding wires (conductive wires) 6 are conductive wires (connecting members) and are made of, for example, thin metal wires such as gold wires.
  • the plurality of lands 18 are disposed in an array pattern in a region having no through-hole 3 (region having the base material layer 16 of the wiring board 2 ) on the lower surface 2 b of the wiring board 2 , and the solder ball (ball electrode, solder bump, bump electrode, protruded portion electrode) 8 is connected to each of the lands 18 .
  • the plurality of solder balls 8 are disposed in an array pattern as external terminals.
  • the lower surface 2 a of the wiring board 2 disposed with the solder balls 8 become the lower surface of the semiconductor device 1 , and this becomes a mounting surface of the semiconductor device 1 (main surface of the side mounted on the mounting board).
  • the semiconductor device 1 of the present embodiment is a semiconductor device of a BGA (Ball Grid Array Package) configuration.
  • the solder ball 8 is made of a solder material, and can function as a bump electrode (protruded portion electrode, solder bump) of the semiconductor device 1 and can function as the external terminal (terminal for external connection) of the semiconductor device 1 .
  • a plurality external terminals are formed on the plurality of lands 18 of the wiring board 2 , respectively.
  • the lower surface 9 b of the heat sink 4 protrudes from the lower surface 2 b of the wiring board 2 , but the lower surface 9 b of the heat sink 4 is located on the lower surface 2 b side of the wiring board 2 compared with the position of the lower end of the solder ball 8 (end part opposite to the side connected to the land 18 , that is, top end of the solder ball 18 ). More specifically, when the semiconductor device 1 is disposed on a flat surface, the lower end of the solder ball 8 contacts to the flat surface, but the lower surface 9 b of the heat sink 4 does not contact thereto. In this manner, when the semiconductor device 1 is mounted on the mounting board, the heat sink 4 can be prevented from becoming a hindrance.
  • the plurality of electrodes 5 a of the semiconductor chip 5 are electrically connected to the plurality of connecting terminals 17 of the wiring board 2 through the plurality of bonding wires 6 , and further electrically connected to the plurality of lands 18 of the wiring board 2 and the plurality of solder balls 8 connected to the plurality of lands 18 through the wirings of the wiring board 2 and the conductors inside the through-holes (not shown) and the like.
  • the sealing resin (sealing resin portion, resin sealing portion, sealing portion, sealing body) 7 is made of, for example, a resin material such as a thermosetting resin material and can contain the filler and the like.
  • a resin material such as a thermosetting resin material
  • the sealing resin 7 is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on the upper surface 2 a of the wiring board and the upper surface 9 a of the heat sink 4 , and the semiconductor chip 5 and the bonding wire 6 are sealed and protected by the sealing resin 7 .
  • the sealing resin 7 is adhered (bonded) to the wiring board 2 and the heat sink 4 , respectively, so that the wiring board 2 , the heat sink 4 and the sealing resin 7 are coupled, and further the protruded portion 11 of the heat sink 4 is sandwiched by the sealing resin 7 and the wiring board 2 , so that the coupling of the wiring board 2 , the heat sink 4 and the sealing resin 7 is strengthened.
  • the semiconductor device 1 of the present embodiment is a semiconductor device (semiconductor package) in which the semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2 .
  • the solder balls 8 are bonded on the lower surface 2 a below the wiring board 2 as external terminals, and the heat sink 4 is exposed from the lower surface 2 a of the wiring board 2 .
  • the heat generated in the semiconductor chip 5 is transmitted to the heat sink 4 through the bonding agent 14 , and can be dissipated to the outside of the semiconductor device 1 from the exposed portion of the heat sink 4 (lower portion of the heat sink 4 ) on the lower surface side (lower surface 2 a of the wiring board 2 ) of the semiconductor device 1 .
  • the semiconductor device 1 of the present embodiment is a high heat-dissipation semiconductor device (semiconductor package).
  • FIG. 8 is a process flowchart showing a manufacturing process of the semiconductor device 1 of the present invention.
  • FIGS. 9 to 26 are plan views or cross-sectional views in the manufacturing process of the semiconductor device 1 of the present embodiment.
  • FIGS. 9 , 11 , 13 , 15 , 17 , 19 and 23 are plan views (upper surface views)
  • FIGS. 10 , 12 , 14 , 16 , 18 , 20 to 22 and 24 to 26 are cross-sectional views.
  • FIG. 10 corresponds to the cross-sectional view cut along the line A 3 -A 3 of FIG. 9
  • FIG. 10 corresponds to the cross-sectional view cut along the line A 3 -A 3 of FIG. 9 , and FIG.
  • FIG. 12 corresponds to the cross-sectional view cut along the line A 4 -A 4 of FIG. 11 .
  • FIG. 14 shows a cross-section at the same position as FIG. 12 , but corresponds to the same process stage as FIG. 13 .
  • FIG. 16 shows the cross-section of the same position as FIG. 12 , but corresponds to the same process stage as FIG. 15 .
  • FIG. 18 shows the cross-section of the same position as FIG. 12 , but corresponds to the same process stage as FIG. 17 .
  • FIG. 20 shows the cross-section of the same position as FIG. 10 , but corresponds to the same process stage as FIG. 19 .
  • FIG. 24 shows the cross-section of the same position as FIG. 10 , but corresponds to the same process stage as FIG. 23 .
  • FIG. 25 shows the cross-section of the same position as FIG. 10 , but corresponds to the process stage later than FIG. 24 .
  • FIG. 26 shows the cross-section of the same position as FIG. 10 , but
  • the individual semiconductor devices 1 are manufactured by using a multi-cavity wiring board (wiring board base) 21 in which a plurality of wiring boards 2 are connected in a row or in an array pattern will be described.
  • a multi-cavity wiring board (wiring board base) 21 in which a plurality of wiring boards 2 are connected in a row or in an array pattern will be described.
  • a wiring board 21 is prepared (step S 1 ).
  • This wiring board 21 is a base of the wiring board 2 , and the wiring board 21 is cut by a cutting process to be described later, and is separated into each semiconductor device region (board region, unit board region) 22 , and this region corresponds to the wiring board 2 of the semiconductor device 1 .
  • the wiring board 21 has a structure in which a plurality of semiconductor device regions 22 from each of which one semiconductor device 1 is formed are disposed in a row or in a matrix pattern.
  • the through-hole 3 is formed in each of the semiconductor device regions 22 of the wiring board 21 , the plurality of connecting terminals 17 and the wires connected thereto are formed in each of the semiconductor device regions 22 on an upper surface 21 a of the wiring board 21 (surface to be the upper surface 2 a of the wiring board 2 later, first main surface), and the plurality of lands 18 are formed in each of the semiconductor device regions 22 on a lower surface 21 b of the wiring board 21 (surface to be the lower surface 2 b of the wiring board 2 later, second main surface).
  • FIG. 9 upper surface view of the wiring board 21
  • FIG. 10 cross-sectional view of the wiring board 21 ) show an example in which the plurality of semiconductor device regions 22 are disposed in a row to constitute the wiring board 21 .
  • the frame 31 for the heat sink 4 is prepared (step S 2 ).
  • the frame 31 has a structure in which the plurality of heat sinks 4 are integrally joined to frame portions 32 . More specifically, the plurality of heat sinks 4 are disposed at the predetermined intervals between the two frame portions 32 extending in the same direction, and the four corners of the upper part of each heat sink 4 are joined to the frame portion 32 through joining portions 33 .
  • the frame 31 can be formed by, for example, processing a copper plate and the like by a metal mold.
  • joining portions 34 for mutually joining the frame portions 32 are provided between the adjacent heat sinks 4 so as to reinforce the frame 31 . If not required, the joining portion 34 can be omitted.
  • the heat sink 4 , the frame portion 32 , the joining portion 33 , and the joining portion 34 are integrally formed from the same material.
  • FIG. 11 is a plan view, hatching is applied to the frame 31 so as to make the shape of the frame 31 easily understood. Also, although the heat sinks 4 appear to be separated from each other in FIG. 12 , as evident from FIG. 11 , the heat sinks 4 are coupled with each other through the coupling portions 33 and the frame portions 32 in reality.
  • step S 3 the semiconductor chip 5 is mounted and bonded on the upper surface 9 a of each heat sink 4 of the frame 31 through the bonding agent 14 (step S 3 ).
  • the bonding process of the semiconductor chip 5 in the step S 3 can be performed as follows.
  • solder (first solder) 14 a is coated on the upper surface 9 a of each heat sink 4 of the frame 31 . Then, the solder 14 a on each heat sink 4 of the frame 31 is agitated as needed, and thereafter, the semiconductor chip 5 is mounted on the upper surface 9 a of each heat sink 4 of the frame 31 through the solder 14 a as shown in FIGS. 15 and 16 .
  • High melting point solder is preferably used for the solder 14 a , and the solder (first solder) having a melting point higher than at least a melting point of the solder (second solder) used for the external terminal (solder ball 8 in this case) formed later on the land 18 is preferably used as the solder 14 a .
  • the solder 14 a that is, the bonding agent 14 made of the solder 14 a
  • the bonding reliability of the semiconductor chip 5 and the heat sink 4 can be enhanced, and the heat conductivity from the semiconductor chip 5 to the heat sink 4 can be improved, so that the heat dissipation of the semiconductor device 1 can be improved.
  • each heat sink 4 mounted with the semiconductor chip 5 is cut and separated from the frame portion 32 of the frame 31 (step S 4 ). More specifically, the joining portion 33 between the heat sink 4 and the frame portion 32 is cut, so that each heat sink 4 mounted with the semiconductor chip 5 is separated from the frame portion 32 of the frame 31 . As shown in FIGS. 17 and 18 , individual pieces of the heat sinks 4 each mounted with the semiconductor chip 5 are obtained.
  • step S 5 the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 , respectively (step S 5 ).
  • step S 5 it is necessary to prepare the wiring board 21 in the step S 1 .
  • the preparation of the wiring board 21 in the step S 1 can be also performed before step S 2 , simultaneously with the step S 2 , before the step S 3 and after the step S 2 , simultaneously with the step S 3 , before the step S 4 and after the step S 3 , simultaneously with the step S 4 or before the step S 5 and after the step S 4 .
  • FIGS. 21 and 22 show one semiconductor device region 22 of the wiring board 21 .
  • the heat sink 4 mounted with the semiconductor chip 5 is inserted (plugged) into the through-hole 3 of the wiring board 21 from the upper surface 21 a side (side corresponding to the upper surface 2 a of the wiring board 2 ) of the wiring board 21 . More specifically, the heat sink 4 mounted with the semiconductor chip 5 is inserted into the through-hole 3 of the wiring board 21 in a direction 35 shown by an arrow mark of FIG. 21 .
  • the heat sink 4 has the protruded portion 11 protruding to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface of the heat sink 4 in the peripheral edge portion of the upper surface 9 a of the heat sink 4 , and in the step S 5 , the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 so that the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 outside the through-hole 3 and the lower surface of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21 .
  • the heat sink 4 has no protruded portion 11 and any of the cross-section of the heat sink 4 (cross-section parallel to the upper surface 9 a and the lower surface 9 b of the heat sink 4 ) is the same as or smaller than the planar shape of the through-hole 3 of the wiring board 21 unlike the present embodiment, the heat sink 4 is likely to fall off from the through-hole 3 of the wiring board 21 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21 .
  • the heat sink 4 is provided with the protruded portion 11 . Therefore, when the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 as shown in FIG. 21 , the protruded portion 11 of the heat sink 4 is caught on the upper surface 21 a of the wiring board 21 as shown in FIG. 22 . Since the protruded portion 11 functions as a stopper, it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 21 in the direction 35 . Accordingly, the heat sink 4 can be retained inside the through-hole 3 of the wiring board 21 .
  • the side surface 10 of the heat sink 4 has a tapered shape.
  • the inner wall of the through-hole 3 of the wiring board 21 before the heat sink 4 is inserted does not have the tapered shape, and is formed to be vertical to the upper surface 21 a of the wiring board 21 .
  • the heat sink 4 when the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 in the step S 5 , since the side surface 10 of the heat sink 4 contacts to the inner wall of the through-hole 3 of the wiring board 21 and the inner wall of the through-hole 3 of the wiring board 21 is pushed and expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4 , the side surface 10 of the heat sink 4 is fastened up by the inner wall of the through-hole 3 of the wiring board 21 by its reaction. In this manner, the heat sink 4 is fixed to the wiring board 21 .
  • the side surface 10 of the heat sink 4 contacts and adheres to the inner wall of the through-hole 3 of the wiring board 21 , and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21 . This state is maintained in the manufactured semiconductor device 1 .
  • step S 6 a wire bonding process is performed, so that each of the electrodes 5 a of the semiconductor chip 5 and the connecting terminals 17 formed in the wiring board 21 corresponding to the electrodes are electrically connected through the bonding wires 6 (step S 6 ). More specifically, a plurality of connecting terminals 17 of each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 and a plurality of electrodes 5 a of the semiconductor chip 5 bonded on (mounted on) the heat sink 4 disposed inside the through-hole 3 of the semiconductor device region 22 are electrically connected through a plurality of bonding wires 6 , respectively.
  • a molding process for example, transfer molding process
  • resin sealing by a molding process is performed to form a sealing resin 7 a (sealing portion), and the semiconductor chip 5 and the bonding wire 6 are sealed (resin-sealed) by the sealing resin 7 a (step S 7 ).
  • a collective sealing for collectively sealing the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 a is performed in the molding process in the step S 7 . More specifically, the sealing resin 7 a is formed on the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 so as to cover the semiconductor chips 5 and the bonding wires 6 . In this case, the sealing resin 7 a is formed so as to cover the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 .
  • the sealing resin 7 a is made of, for example, a resin material such as the thermosetting resin material and can contain the filler and the like.
  • the sealing resin 7 a can be formed by injecting the sealing resin material into a cavity of the metal mold disposed on the wiring board 21 and then heating and hardening this sealing resin material by heating.
  • a state in which the upper surface 21 a of the wiring board 21 is directed upward without turning the wiring board 21 upside down is preferably maintained until the molding process in the step S 7 is performed. More specifically, after disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S 5 , the wiring board 21 has the upper surface 21 a directed upward so that the lower surface 21 b thereof is not directed upward until the molding process in the step S 7 is performed. As a result, the falling off of the heat sink 4 from the through-hole 3 of the wiring board 21 before the sealing resin 7 a is formed can be prevented more precisely.
  • the sealing resin 7 a By forming the sealing resin 7 a , the heat sink 4 and the wiring board 21 are solidly bonded by the sealing resin 7 a , and therefore, after forming the sealing resin 7 a , the wiring board 21 may be directed to any direction (lower surface 21 b of the wiring board 21 may be directed upward).
  • the heat sink 4 can stay inside the through-hole 3 of the wiring board 21 due to the presence of the protruded portion 11 if a state in which the wiring board 21 is not turned upside down and the upper surface 21 a of the wiring board 21 is directed upward is maintained after the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 in the step S 5 until the molding process in the step S 7 is performed.
  • the bonding power of the heat sink 4 and the wiring board 21 is weak, the heat sink 4 is likely to fall off from the wiring board 21 or to oscillate during the manufacturing process (steps S 5 to S 7 ) of the semiconductor device, and therefore, it is preferable to enhance the bonding power of the heat sink 4 and the wiring board 21 to some extent.
  • the side surface 10 of the heat sink 4 is inclined so as to have the tapered shape, thereby caulking the heat sink 4 and the wiring board 21 .
  • the bonding power (fixing power) of the heat sink 4 and the wiring board 21 can be enhanced, and thus, the heat sink 4 can be fixed and stabilized in the wiring board 21 .
  • the semiconductor device since it is possible to prevent the heat sink 4 from falling off from the wiring board 21 or oscillating during the manufacturing process of the semiconductor device (steps S 5 to S 7 ), the semiconductor device can be stably manufactured. Therefore, the manufacture of the semiconductor device is facilitated, and further, the manufacturing yield of the semiconductor device can be improved.
  • the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21 (step 8 ).
  • the plurality of solder balls 8 are disposed on the plurality of lands 18 of the lower surface 21 b of the wiring board 21 and are temporally fixed by a flux and the like, and then, a solder reflow process (reflow process, heat treatment) is performed to melt and solidify the solder again, so that the solder balls 8 and the lands 18 of the lower surface 21 b of the wiring board can bonded and electrically connected to each other.
  • a solder reflow process reflow process, heat treatment
  • step S 8 the solder balls 8 as the external terminals of the semiconductor device 1 are formed on the lands 18 of the lower surface 21 b of the wiring board 21 .
  • solder ball 8 bonded to the lower surface 21 b of the wiring board 21 can be taken as a bump electrode (solder bump).
  • a bump electrode (solder bump) as the external terminal of the semiconductor device 1 can be also formed on the land 18 by supplying the solder onto the land 18 by a printing method and the like in place of the solder ball 8 .
  • solder ball 8 any of lead-containing solder and lead-free solder not containing lead can be used, and the lead-free solder not containing lead is more preferably used.
  • a mark such as a product number and the like is applied onto the front surface of the sealing resin 7 a (step 9 ).
  • a laser mark for performing the marking by laser can be performed, and an ink mark for performing the marking by an ink can be also performed.
  • the connecting process of the solder ball 8 in the step S 8 and the marking process in the step 9 can be interchanged in their order, so that the connecting process of the solder ball 8 in the step S 8 is performed after performing the marking process in the step S 9 . If not required, the marking process in the step S 9 can be omitted.
  • the wiring board 21 and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22 (step S 10 ).
  • the semiconductor device 1 as shown in FIGS. 1 to 3 can be manufactured.
  • the wiring board 21 diced and separated (divided) into each semiconductor device region 22 corresponds to the wiring board 2
  • the sealing resin 7 a diced and separated (divided) into each semiconductor device region 22 corresponds to the sealing resin 7 .
  • the upper surface 21 a of the wiring board 21 becomes the upper surface 2 a of the wiring board 2
  • the lower surface 21 b of the wiring board 21 becomes the lower surface 2 b of the wiring board 2 .
  • FIGS. 25 and 26 show the case where a collective sealing is performed in the molding process in the step S 7
  • the case where the individual sealing is performed will be described with reference to FIGS. 27 to 29 .
  • FIGS. 27 and 28 are cross-sectional views in another manufacturing process of the semiconductor device 1 of the present embodiment, and they correspond to FIGS. 25 and 26 , respectively. While FIGS. 25 and 26 show the cases where the collective sealing is performed in the molding process in the step S 7 , FIGS. 27 and 28 correspond to the case where the individual sealing for sealing each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 is performed in the molding process in the step S 7 . Also, FIG. 29 is a cross-sectional view (side cross-sectional view) of the semiconductor device 1 manufactured in the case where the individual sealing is performed in the molding process in the step S 7 (case of FIGS. 27 and 28 ), and it corresponds to FIG. 1 .
  • the molding process (resin sealing process) in the step S 7 is performed, and the sealing resin 7 is formed so as to seal (resin-seal) the semiconductor chip 5 and the bonding wire 6 by the sealing resin 7 as shown in FIG. 27 .
  • the individual sealing (divided sealing) for individually sealing each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 is performed. More specifically, the sealing resin 7 is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 .
  • the sealing resin 7 is formed for each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 .
  • the sealing resin 7 is made of, for example, a resin material such as the thermosetting resin material and can contain the filler and the like.
  • a resin material such as the thermosetting resin material
  • the sealing resin 7 can be formed by injecting the sealing resin material into a cavity of the metal mold disposed on the wiring board 21 and then hardening this sealing resin material by heating.
  • step S 8 as shown in FIG. 28 , the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21 . Since the connecting process of the solder balls 8 in the step S 8 is the same as the case of performing the collective sealing (case of FIGS. 25 and 26 ), the description thereof will be omitted here.
  • the marking in the step 9 is performed as needed, and a mark such as the product number and the like is applied onto the sealing resin 7 . Since the marking process in the step S 9 is the same as the case of performing the collective sealing (case of FIGS. 25 and 26 ), the description thereof will be omitted here.
  • the cutting process in the step S 10 is performed, and the wiring board 21 is cut (diced) and separated (divided) into each semiconductor device region 22 .
  • the semiconductor device 1 as shown in FIG. 29 can be manufactured.
  • the wiring board 21 diced and separated (divided) into each semiconductor device region 22 corresponds to the wiring board 2 , and the upper surface 21 a of the wiring board 21 becomes the upper surface 2 a of the wiring board 2 and the lower surface 21 b of the wiring board 21 becomes the lower surface 2 b of the wiring board 2 . Note that, when the collective sealing is performed in the step S 7 (case of FIGS.
  • the wiring board 21 and the sealing resin 7 a thereon are cut in the cutting process in the step S 10 , but when the individual sealing is performed in the step S 7 (case of FIGS. 27 and 28 ), only the wiring board 21 is cut in the cutting process in the step S 10 and the sealing resin 7 is not cut. Hence, the sealing resin 7 formed by the molding process in the step 7 is not cut and becomes the sealing resin 7 of the semiconductor device 1 .
  • the semiconductor device 1 of FIG. 29 has almost the same structure as the semiconductor device 1 of FIG. 1 except that the sealing resin 7 is not formed on the peripheral edge portion of the upper surface 2 a of the wiring board 2 and the sealing resin 7 is formed on the region other than the peripheral edge portion of the upper surface 2 a of the wiring board 2 , the description thereof will be omitted.
  • the perspective plan view of the semiconductor device 1 of FIG. 29 is the same as that of FIG. 2
  • the lower surface view thereof is the same as that of FIG. 3 .
  • the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21 .
  • FIG. 30 is a process flowchart showing another manufacturing process of the semiconductor device 1 of the present embodiment.
  • FIGS. 31 to 38 are plan views or cross-sectional views in another manufacturing process of the semiconductor device 1 of the present embodiment.
  • FIGS. 31 , 35 and 37 are plan views
  • FIGS. 32 to 34 and FIGS. 36 and 38 are cross-sectional views.
  • FIG. 32 corresponds to the cross-sectional view cut along the line A 5 -A 5 of FIG. 31 .
  • the position of the line A 5 -A 5 of FIG. 31 is the same as the position of A 3 -A 3 of FIG. 9 .
  • FIG. 36 shows the cross-section of the same position as FIG. 32 , but corresponds to the same process stage as FIG. 35 .
  • FIG. 38 shows the cross-section of the same position as FIG. 32 , but corresponds to the same process stage as FIG. 37 .
  • the wiring board 21 and the frame 31 are prepared. It does not matter if the wiring board 21 is prepared first, the frame 31 is prepared first or the wiring board 21 and the frame 31 are prepared at the same time.
  • each heat sink 4 of the frame 31 is cut and separated from the frame portion 32 of the frame 31 , and then, as shown in FIGS. 31 and 32 , the heat sink 4 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in the step S 5 .
  • the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21
  • the heat sink 4 not mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in FIGS. 31 and 32 .
  • FIGS. 33 and 34 correspond to FIGS. 21 and 22 , respectively, in which one semiconductor region 22 of the wiring board 21 is shown.
  • the heat sink 4 heat sink 4 not mounted with the semiconductor chip 5
  • the heat sink 4 is inserted (plugged) into the through-hole 3 of wiring board 21 from the upper surface 21 a side of the wiring board 21 (side corresponding to the upper surface 2 a of the wiring board 2 ). More specifically, the heat sink 4 is inserted into the through-hole 3 of the wiring board 21 in the direction 35 shown by the arrow mark of FIG. 33 to achieve the state of FIG. 34 .
  • step S 3 a After the heat sink 4 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in the step S 4 , the semiconductor chip 5 is mounted and bonded on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 through the bonding agent 14 (step S 3 a ).
  • the bonding process of the semiconductor chip 5 in the step S 3 a can be performed as follows.
  • a conductive paste material preferably silver paste 14 b is coated on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 .
  • the semiconductor chip 5 is mounted on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 through the silver paste 14 b . Thereafter, heat treatment and the like are performed so as to harden the silver paste 14 b .
  • the silver past 14 b in a paste state at the time of mounting the semiconductor chip 5 is hardened, and the semiconductor chip 5 is boded and fixed to the heat sink 4 by the hardened silver paste 14 b .
  • This hardened silver paste 14 b serves as the bonding agent 14 .
  • the subsequent process is the same as the manufacturing process described with reference to FIGS. 23 to 28 . More specifically, the wire bonding process in the step S 6 is performed as shown in FIGS. 23 and 24 , the resin sealing process in the step S 7 is performed as shown in FIG. 25 or FIG. 27 , the connecting process of the solder balls 8 in the step S 9 is performed as shown in FIG. 26 or 28 , the marking process in the step S 9 is performed as needed, and the cutting process in the step S 10 is performed. In this manner, the semiconductor device 1 as shown in FIG. 1 or FIG. 29 is manufactured.
  • the wiring board 21 composed of a resin board is low in durability to high temperature heat treatment as compared with the frame 31 (heat sink 4 ) made of a metal material.
  • the semiconductor chip 5 is bonded on the heat sink 4 in the step S 3 before disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S 5 , and therefore, the wiring board 21 is not heated at the time of heat treatment of the bonding process of the semiconductor chip 5 in the step S 3 .
  • the high temperature heat treatment can be performed for the heat treatment of the bonding process of the semiconductor chip 5 in the step S 3 without regard to the heat resistance of the wiring board 21 .
  • the manufacturing process described with reference to FIG. 8 is applied because the wiring board 21 does not suffer from damages at the time of solder reflow in the bonding process of the semiconductor chip 5 in the step S 3 .
  • the solder reflow temperature at the time of mounting the semiconductor device 1 when using the lead-free solder for the solder ball 8 is, for example, about 220° C.
  • the solder reflow temperature at the time of mounting the semiconductor device 1 when using the lead-containing solder for the solder ball 8 is, for example, about 180° C.
  • the solder reflow temperature in the step S 3 in which the high melting point solder is used for the solder 14 a is preferably 350 to 400° C., but there is the possibility that the wiring board 21 cannot endure such a high temperature.
  • the semiconductor chip 5 is bonded on the heat sink 4 in the step S 3 before disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S 5 , and therefore, there arises no problem of the durability of the wiring board 21 at the time of solder reflow.
  • the heat conductivity of the bonding agent 14 is increased as compared with a case of using the silver paste, and therefore, the heat conductivity to the heat sink 4 from the semiconductor chip 5 is more increased, so that the heat dissipation of the semiconductor device 1 can be more improved.
  • the wiring board 21 is heated at the time of the heat treatment of the bonding process of the semiconductor chip 5 in the step S 3 a .
  • the heat treatment at a very high temperature is not performed for the heat treatment of the bonding process of the semiconductor chip 5 in the step S 3 a , and the semiconductor chip 5 is preferably bonded on the heat sink 4 by using the silver paste 14 b as described above because the wiring board 21 does not suffer from damages at the time of the heat treatment for hardening the bonding agent (silver paste 14 b ) in the bonding process of the semiconductor chip 5 in the step S 3 a.
  • step S 5 is performed on a board manufacturer side to prepare the wiring board 21 in a state where the heat sink 4 is already disposed inside the through-hole 3 , and the wiring board 21 in this state is received from the board manufacturer to perform the subsequent process on the semiconductor device manufacturer side.
  • the thickness of the heat sink 4 mounted with the semiconductor chip 5 is preferably increased.
  • the weight of the heat sink 4 becomes heavy as the thickness of the heat sink 4 is increased.
  • the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a (upper surface 2 a of the wiring board 2 ) side of the wiring board 21 , the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 , and the lower surface 12 of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21 , so that the protruded portion 11 supports the weight of the heat sink 4 .
  • the thickness of the heat sink 4 can be increased and preferably can be made larger than the thickness of the wiring board 21 (that is, thickness t 2 of the wiring board 2 ), and it is thus possible to improve the heat dissipation properties of the semiconductor device.
  • this state (that is, a state where the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 and the lower surface 12 of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21 ) is maintained even in the manufactured semiconductor device.
  • the weight of the heat sink 4 itself operates in the direction to fix the heat sink 4 to the wiring board 21 , even if the fixing power of the heat sink 4 and the wiring board 21 by the tapered shape of the side surface 10 of the heat sink 4 is not so strong, the heat sink 4 can be fixed to the wiring board 21 , and the process up to the resin sealing can be performed appropriately.
  • the heat sink 4 used in the present embodiment has a simple structure, the processing of the heat sink 4 (frame 31 connecting the heat sinks 4 ) is easy, and the manufacturing cost of the heat sink 4 (frame 31 ) can be reduced, so that the manufacturing cost of the semiconductor device can be reduced. Further, by inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21 , the heat sink 4 can be fixed to the wiring board 21 by the tapered shape of the heat sink 4 , and therefore, the heat sink 4 can be fixed to the wiring board 21 by a simple operation, and the manufacturing process of the semiconductor device is facilitated.
  • FIG. 39 is a cross-sectional view (side cross-sectional view) showing a state in which the semiconductor device 1 of the present embodiment is mounted on a wiring board 41 .
  • the wiring board (mounting board) 41 shown in FIG. 39 is a mounting board for mounting the semiconductor device 1 , and an upper surface (front surface, main surface) 41 a which is a mounting surface for mounting the semiconductor device 1 is provided with a plurality of board side terminals (terminals, electrodes, pad electrodes, conductive lands) 42 for connecting the plurality of solder balls 8 of the semiconductor device 1 , respectively.
  • FIG. 39 shows a cross-sectional structure of the wiring board 41 in a simplified manner
  • the wiring board 41 is preferably a multilayer wiring board 41 (multilayer board), in which a plurality of insulating layers (dielectric layers, insulating base material layers) and a plurality of wiring layers (conductive layers, conductive pattern layers) are stacked and integrated.
  • the board side terminal 42 is a terminal for connecting the solder ball 8 (bump electrode) which is the external terminal of the semiconductor device 1 , and the board side terminal 42 is disposed at the position opposite to (planarly overlapped with) the solder ball 8 when the semiconductor device 1 is mounted on the upper surface 41 a of the wiring board 41 .
  • solder paste this solder paste is integrated with the solder ball 8 by the solder reflow
  • the semiconductor device 1 is mounted (disposed) on the wiring board 41 so that the positions of the solder balls 8 of the semiconductor device 1 and the board side terminals 42 of the wiring board 41 are matched, and then, the solder reflow treatment is performed.
  • the semiconductor device 1 is mounted (solder-mounted) on the wiring board 41 and the semiconductor device 1 is fixed to the wiring board 41 , and at the same time, the plurality of solder balls 8 as the external terminals of the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41 , respectively.
  • a plurality of electrodes 5 a of the semiconductor chip 5 in the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41 through the plurality of bonding wires 6 , the plurality of connecting terminals 17 and wires of the wiring board 2 , the conductors and the lands 18 inside the through-holes (not shown) of the wiring board 2 , and the plurality of solder balls 8 .
  • electronic parts and the like other than the semiconductor device 1 can be also mounted as needed on the region other than mounting region of the semiconductor device 1 on the upper surface 41 a of the wiring board 41 .
  • the heat sink 4 of the semiconductor device 1 is not connected to the board side terminal of the wiring board 41 .
  • FIG. 40 is a cross-sectional view (side cross-sectional view) of the case where the heat sink 4 of the semiconductor device 1 is connected to the board side terminal of the wiring board 41 at the time of mounting the semiconductor device 1 on the wiring board 41 .
  • the wiring board 41 shown in FIG. 40 is further provided with a board side terminal (terminal, electrode) 42 a for connecting the heat sink 4 of the semiconductor device 1 on the upper surface 41 a .
  • the board side terminal 42 a is a terminal for connecting the heat sink 4 of the semiconductor device 1
  • the board side terminal 42 a is disposed at the position opposite to (planarly overlapped with) the heat sink 4 at the time of mounting the semiconductor device 1 on the upper surface 41 a of the wiring board 41 .
  • the planar dimension of the board side terminal 42 a for connecting the heat sink 4 is larger than the planar dimension of the board side terminal 42 for connecting the solder ball 8 .
  • the semiconductor device 1 For mounting the semiconductor device 1 on the wiring board 41 , after the solder paste is supplied on the plurality of board side terminals 42 and 42 a of the wiring board 41 by the printing method or the like, the semiconductor device 1 is mounted (disposed) on the wiring board 41 so that the positions of the solder balls 8 of the semiconductor device 1 and the board side terminals 42 of the wiring board 41 are matched, and then, the solder reflow treatment is performed.
  • the solder paste supplied on the board side terminal 42 is integrated with the solder ball 8 by the solder reflow, and the solder paste supplied on the board side terminal 42 a is molten and solidified by the solder reflow to become solder 43 .
  • the semiconductor device 1 is mounted (solder-mounted) on the wiring board 41 and the semiconductor device 1 is fixed to the wiring board 41 , and at the same time, the plurality of solder balls 8 as the external terminals of the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41 , respectively, and moreover, (lower surface 9 b of) the heat sink 4 of the semiconductor device 1 is bonded and electrically connected to the board side terminal 42 a of the wiring board 41 through the solder 43 .
  • the board side terminal 42 is preferably a ground terminal.
  • the heat sink 4 of the semiconductor device 1 When the heat sink 4 of the semiconductor device 1 is connected to the board side terminal 42 a of the wiring board 41 by the solder 43 as shown in FIG. 40 , the heat generated in the semiconductor chip 5 of the semiconductor device 1 is dissipated to the wiring board 41 through the heat sink 4 and the solder 43 .
  • the heat dissipation properties of the semiconductor device 1 can be more improved.
  • FIG. 41 is another cross-sectional view (side cross-sectional view) showing a state in which the semiconductor device 1 is mounted on the wiring board 41 .
  • the electrode 5 d (preferably, the electrode for ground potential) of the plurality of electrodes 5 a of the semiconductor chip 5 can be electrically connected to the heat sink 4 through the bonding wire 6 a (bonding wire 6 a of the bonding wires 6 ).
  • the electrode 5 d of the semiconductor chip 5 can be electrically connected to the board side terminal 42 a of the wiring board 41 through the bonding wire 6 a , the heat sink 4 and the solder 43 .
  • a ground terminal is used as the board side terminal 42 a of the wiring board 41 , the ground potential can be supplied to the heat sink 4 and the electrode 5 d of the semiconductor chip 5 from the board side terminal 42 a of the wiring board 41 by mounting the semiconductor device 1 on the wiring board 41 .
  • FIG. 42 is a cross-sectional view of another modified example of the semiconductor device 1 (semiconductor device of a modified example).
  • the chip mounting surface (surface mounted with the semiconductor chip 5 , upper surface 9 a ) of the heat sink 4 is located almost on the same plane as the upper surface 2 a of the wiring board 2 .
  • the upper surface 9 a of the heat sink 4 is recessed and the semiconductor chip 5 is mounted on the recessed surface, and thus, the chip mounting surface of the heat sink 4 (surface mounted with the semiconductor chip 5 ) is lower than the upper surface 2 a of the wiring board 2 .
  • a height position of the upper surface of the semiconductor chip 5 is lowered and a height position of the top of the bonding wire 6 is lowered in the semiconductor device of FIG. 42 (modified example of the semiconductor device 1 ), so that the thickness of the sealing resin 7 can be reduced, and the semiconductor device can be made more thinner.
  • This can be applied to the semiconductor devices of the following other modified examples and the semiconductor devices of the following second, fourth and fifth embodiments.
  • FIGS. 43 to 45 are a cross-sectional view (side cross-sectional view), a perspective plan view (upper surface view) and a lower surface view (bottom view, rear surface view, plan view) of still another modified example of the semiconductor device 1 (semiconductor device of modified example).
  • FIG. 44 shows a perspective plan view when the sealing resin 7 is seen through, and the cross-section cut along the line A 6 -A 6 of FIG. 44 almost corresponds to the cross-sectional view of FIG. 43 .
  • FIG. 45 is a lower surface view.
  • the semiconductor chip contained inside the semiconductor device 1 is only one, and the one semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2 .
  • a plurality of semiconductor chips are contained inside the semiconductor device, and one semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2 and a semiconductor chip 5 e other than the semiconductor chip 5 is mounted and bonded on the upper surface 2 a of the wiring board 2 through a bonding agent 14 c instead of on the heat sink 4 .
  • the semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2 , and the electrodes on the upper surface of this semiconductor chip 5 e are electrically connected to the connecting terminals 17 on the upper surface 2 a of the wiring board 2 through the bonding wires 6 , and the sealing resin 7 seals the semiconductor chips 5 and 5 e and the bonding wires 6 connected to the electrodes thereof.
  • FIG. 46 is a perspective plan view (upper surface view) of still another modified example of the semiconductor device 1 (semiconductor device of the modified example), and a perspective plan view when the sealing resin 7 is seen through is shown.
  • one semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2 .
  • still one more semiconductor chip 5 f is mounted and bonded through the bonding agent in addition to the semiconductor chip 5 e in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2 .
  • the electrodes on the upper surface of this semiconductor chip 5 f are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 6 , and the sealing resin 7 seals the semiconductor chips 5 , 5 e and 5 f and the bonding wires 6 connected to the electrodes thereof.
  • FIG. 47 is a cross-sectional view (side cross-sectional view) of still another modified example of the semiconductor device 1 (semiconductor device of the modified example).
  • the semiconductor chip 5 e and the semiconductor chip 5 f are disposed in the different regions on the upper surface 2 a of the wiring board 2 so as not to be overlapped with each other, whereas the semiconductor chip 5 f is stacked on the semiconductor chip 5 e in the semiconductor device of FIG. 47 . More specifically, in the semiconductor device of FIG.
  • the semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2
  • the semiconductor chip 5 f is mounted and bonded through the bonding agent 14 d on the upper surface of this semiconductor chip 5 e .
  • the electrodes of the upper surface of the semiconductor chip 5 e are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 6
  • the electrodes of the upper surface of the semiconductor chip 5 f are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 5
  • the sealing resin 7 seals the semiconductor chips 5 , 5 e and 5 f and the bonding wires 6 connected to the electrodes thereof.
  • the number of semiconductor chips disposed in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2 may be three or more, and the number of stacked semiconductor chips may also be three or more.
  • the number of semiconductor chips contained in the semiconductor device can be made plural. Since the heat generated in the semiconductor chip 5 mounted on the heat sink 4 can be dissipated by the heat sink 4 , a large effect can be achieved if the semiconductor chip having a high calorific value is applied. Hence, when the number of the semiconductor chips contained in the semiconductor device is plural, the semiconductor chip having the highest calorific value of the chips (here, the semiconductor chip 5 ) is preferably mounted on the heat sink 4 .
  • the semiconductor chips here, the semiconductor chips 5 e and 5 f ) having the calorific value lower than the semiconductor chip 5 mounted on the heat sink 4 (semiconductor chip having the highest calorific value) are disposed on the upper surface 2 a of the wiring board 2 (region not having the through-hole 3 ).
  • the heat generated in the semiconductor chip having a high calorific value can be dissipated to the outside of the semiconductor device 1 from the heat sink 4 , thereby being able to achieve both the reduction in the manufacturing cost of the semiconductor device and the improvement of the heat dissipation properties of the semiconductor device. This can be applied also to the semiconductor devices of the following embodiments.
  • the semiconductor chips 5 e and 5 f can be made to be a memory chip having a volatile memory (for example, DRAM) or a non-volatile memory (for example, a flash memory) formed therein, and the semiconductor chip 5 can be made to be a control chip (microcomputer) having a control circuit for controlling (the memories of) the semiconductor chips 5 e and 5 f formed therein.
  • SIP System in Package
  • semiconductor chips 5 and 5 e or semiconductor chips 5 , 5 e and 5 f provided with integrated circuits having different functions on the wiring board 2 including the heat sink 4 , respectively.
  • control chip Since the control chip has a high calorific value as compared with the memory chip, the control chip liable to generate heat (here, the semiconductor chip 5 ) is mounted on the heat sink 4 , thereby improving the heat dissipation properties, and the memory chips (here, the semiconductor chips 5 e and 5 f ) are disposed on the upper surface 2 a of the wiring board 2 (region not having the through-hole 3 ), thereby restraining the number of heat sinks 4 to the minimum and reducing the manufacturing cost of the semiconductor device.
  • the control chip Since the control chip has a high calorific value as compared with the memory chip, the control chip liable to generate heat (here, the semiconductor chip 5 ) is mounted on the heat sink 4 , thereby improving the heat dissipation properties, and the memory chips (here, the semiconductor chips 5 e and 5 f ) are disposed on the upper surface 2 a of the wiring board 2 (region not having the through-hole 3 ), thereby restraining the number of heat
  • FIGS. 48 and 49 are cross-sectional views (side cross-sectional views) of a semiconductor device la of the second embodiment
  • FIG. 50 is a perspective plan view (upper surface view) of the semiconductor device la when the sealing resin 7 is seen through
  • FIG. 51 is a lower surface view (bottom view, rear surface view, plan view) of the semiconductor device 1 a.
  • a cross-section cut along the line A 7 -A 7 of FIGS. 50 and 51 almost corresponds to FIG. 48
  • the cross-section cut along the line A 8 -A 8 of FIGS. 50 and 51 almost corresponds to FIG. 49
  • FIGS. 52 and 53 are cross-sectional views (side cross-sectional views) of a heat sink 4 a used in the semiconductor device 1 a
  • FIG. 54 is an upper surface view (plan view) of the heat sink 4 a used in the semiconductor device 1 a
  • FIG. 55 is a lower surface view (plan view) of the heat sink 4 a used in the semiconductor device 1 a.
  • the cross-section cut along the line A 9 -A 9 of FIGS. 54 and 55 corresponds to FIG. 52
  • the cross-section cut along the line A 10 -A 10 of FIGS. 54 and 55 corresponds to FIG. 53
  • FIGS. 52 and 48 show the same cross-sectional positions
  • FIGS. 53 and 49 show the same cross-sectional positions.
  • FIG. 56 is a cross-sectional view (side cross-sectional view) of the wiring board 2 used for the semiconductor device 1 a
  • FIG. 57 is an upper surface view (plan view) of the wiring board 2 used for the semiconductor device 1 a.
  • the cross-section cut along the line A 11 -A 11 of FIG. 57 corresponds to FIG. 56 , but FIG. 56 and FIG. 48 show the same cross-sectional positions.
  • FIG. 57 is a plan view, hatching is applied to the wiring board 2 and the connecting terminals 17 of its upper surface 2 a so as to make a position and a shape of the through-hole 3 in the wiring board 2 easily understood.
  • FIG. 50 the position of the through-hole 3 of the wiring board 2 which is invisible and concealed by the heat sink 4 a even when the sealing resin 7 is seen through is shown by a dotted line for easy understanding.
  • the semiconductor device 1 a of the present embodiment has almost the same structure as the semiconductor device 1 of the first embodiment except for the shape of the heat sink 4 a and the caulking method (fixing method) of the heat sink 4 a to the wiring board 2 , and therefore, the description thereof will be omitted, and the points different from the semiconductor device 1 of the first embodiment will be mainly described.
  • the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 2 and the semiconductor chip 5 is mounted (bonded) on the upper surface 9 a of the heat sink 4 a through the bonding agent 14 like in the semiconductor device 1 of the first embodiment.
  • the heat sink 4 a corresponds to the heat sink 4 of the first embodiment and is made of the same material as that of the heat sink 4 . While the side surface 10 of the heat sink 4 is tapered, the side surface 10 of the heat sink 4 a (side surface 10 of the heat sink 4 a contacting to the inner wall of the through-hole 3 ) of the present embodiment is not tapered.
  • the heat sink 4 a when the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 2 , the inner wall of the through-hole 3 of the wiring board 2 contacts to the side surface 10 of the heat sink 4 a , but the heat sink 4 a cannot be caulked to the wiring board 2 by utilizing the side wall 10 of the heat sink 4 a .
  • the heat sink 4 a is further provided with a protruded portion 11 a and a pin portion (caulking portion, caulking pin portion, caulking pin, protruded portion, convex portion) 13 integrally connected to a lower surface 12 a of the protruded portion 11 a and disposed inside a hole portion 15 of the wiring board 2 , and the heat sink 4 a is caulked (fixed) to the wiring board 2 by this pin portion 13 .
  • the structure of the heat sink 4 a is the same as the heat sink 4 of the first embodiment except that the protruded portion 11 a and the pin portion 13 are provided and the taper (inclination) of the side surface 10 is eliminated.
  • the protruded portions 11 and 11 a and the pin portion 13 are integrally formed with the heat sink 4 a and can be taken as a part of the heat sink 4 a.
  • a recess is formed on the upper surface of the protruded portion 11 a above the pin portion 13 , but this recess is formed as a result of the formation of the pin portion 13 , and the recess may not be formed on the upper surface of the protruded portion 11 a above the pin portion 13 depending on a forming method of the pin portion 13 .
  • the wiring board 2 of the semiconductor device la of the present embodiment has the same structure as the wiring board 2 of the semiconductor device 1 of the first embodiment except that a hole portion 15 is provided in the vicinity of the through-hole 3 .
  • the hole portion 15 is a through-hole reaching a lower surface 2 b from the upper surface 2 a of the wiring board 2 and has sufficiently smaller planar dimensions as compared with the through-hole 3 for inserting a main portion of the heat sink 4 a (portion except for the protruded portions 11 and 11 a and the pin portion 13 ).
  • the hole portion 15 is provided in the wiring board 2 in such a manner as to stay away from the connecting terminal 17 and the land 18 .
  • the pin portion 13 of the heat sink 4 a is fixed inside the hole portion 15 of the wiring board 2 .
  • the heat sink 4 a has the protruded portion (projecting portion, overhang portion, hook portion) 11 a protruding to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface 10 of the heat sink 4 a (side surface 10 contacting to the inner wall of the through-hole 3 of the wiring board 2 ) in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a , and this protruded portion 11 a is located on the upper surface 2 a of the wiring board 2 outside the through-hole 3 and the lower surface of the protruded portion 11 a contacts to the upper surface 2 a of the wiring board 2 .
  • this protruded portion 11 a is preferable to provide this protruded portion 11 a at the corner portions of the rectangular (rectangular planar shaped) upper surface 9 a of the heat sink 4 because the protruded portion 11 a does not interfere with the disposition of the connecting terminal 17 , and it is more preferable to provide the protruded portion 11 a at the four corners of the rectangular upper surface 9 a of the heat sink 4 because the coupling (caulking) of the heat sink 4 and the wiring board 2 is well-balanced.
  • the heat sink 4 a has the protruded portions 11 and 11 a protruding to the upper surface 2 a side of the wiring board 2 from above the through-hole 3 and extending on the upper surface 2 a of the wiring board 2 on a peripheral edge portion of the upper surface 9 a of the heat sink 4 .
  • the protruded portions 11 and 11 a overhang (project) on the upper surface 2 a of the wiring board 2 from above the through-hole 3 , and the protruded portions 11 a of the four corners of the upper surface 9 a extend on the upper surface 2 a of the wiring board 2 up to the position away from the through-hole 3 as compared with the protruded portions 11 other than the four corners of the upper surface 9 a .
  • the protruded portions 11 a are provided at the four corners of the peripheral edge portion of the upper surface 9 a of the heat sink 4 , and the protruded portions 11 are provided on the peripheral edge portion of the upper surface 9 a of the heat sink 4 other than the four corners thereof (except for the four corners having the protruded portions 11 a ) in a flange shape or in an overhang shape, and the protruded portion 11 a extends on the upper surface 2 a of the wiring board 2 up to the position away from the through-hole 3 as compared with the protruded portion 11 in order to be able to connect the pin portion 13 .
  • the protruded portions 11 and 11 a function as a stopper to prevent the heat sink 4 a from falling off from the through-hole 3 of the wiring board 2 .
  • the protruded portions 11 and 11 a are required to be provided at least on a part of the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a .
  • the protruded portions 11 are provided (in a flange shape or in an overhang shape) on the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a like in the protruded portion 11 of the heat sink 4 , and the heat sink 4 a can be stably disposed inside the through-hole 3 of the wiring board 2 .
  • the heat sink 4 a can be prevented from falling off from the through-hole 3 of the wiring board 2 if the protruded portions 11 a are present.
  • the cross-sectional shapes of a portion located inside the through hole 3 and a portion protruding downward from the lower surface 2 b of the wiring board 2 (lower part of the heat sink 4 a ) parallel to the upper surface 2 a of the wiring board 2 are almost the same as the planar shape of the through-hole 3 of the wiring board 2 , and a side surface (side wall) 10 of the heat sink 4 a contacts to a side surface (side wall) of the through-hole 3 of the wiring board 2 .
  • the lower surface 9 b of the heat sink 4 a also has almost the same planar shape as the planar shape of the through-hole 3 of the wiring board 2 .
  • the protruded portions 11 and 11 a of the heat sink 4 a are projected (overhung) on the upper surface 2 a of the wiring board 2 from the through-hole 3 , and the lower surface 12 of the protruded portion 11 and the lower surface 12 a of the protruded portion 11 a contact to the upper surface 2 a of the wiring board 2 .
  • the portions other than the protruded portions 11 and 11 a and the pin portions 13 of the heat sink 4 are located at a planarly overlapped position with the through-hole 3 , and the protruded portions 11 and 11 a and the pin portions 13 only are located outside the through-hole 3 (at the position not planarly overlapped with the through-hole 3 , that is, at the position overlapped with the wiring board 2 ).
  • a planar position of the through-hole 3 when the heat sink 4 is disposed inside the through-hole 3 of the wiring board 2 is shown by a dotted line in FIG. 54 .
  • the heat sink 4 a is inserted and fixed into the through-hole 3 from the upper surface 2 a (upper surface 21 a ) side of the wiring board 2 (wiring board 21 ) before the sealing resin 7 is formed like in the first embodiment.
  • the protruded portion 11 a (protruded portions 11 a and 11 when the protruded portion 11 is provided) of the heat sink 4 a is caught on the upper surface 2 a of the wiring board 2 (upper surface 21 a of the wiring board 21 ) at the time of inserting the heat sink 4 a into the through-hole 3 from the upper surface 2 a side of the wiring board 2 (upper surface 21 a side of the wiring board 21 ), and therefore, it is possible to prevent the heat sink 4 a from falling off from the through-hole 3 , and the heat sink 4 a can be retained inside the through-hole 3 of the wiring board 2 (wiring board 21 ).
  • FIG. 58 is a plan view (upper surface view) of a frame 31 used when the semiconductor device 1 a of the present embodiment is manufactured, and it corresponds to FIG. 11 of the first embodiment. Although FIG. 58 is a plan view, hatching is applied to the frame 31 so as to make a shape of the frame 31 easily understood.
  • a joining portion 33 for joining each heat sink 4 a and a frame portion 32 is provided between the frame portion 32 and the protruded portion 11 a of the heat sink 4 a so as to join the protruded portion 11 a of the heat sink 4 a with the frame portion 32 .
  • the manufacturing process of the semiconductor device la of the present embodiment is the same as the manufacturing process of the semiconductor device 1 of the first embodiment except that a caulking method (fixing method) of the heat sink 4 a to the wiring board 21 in the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S 5 is different.
  • a caulking method (fixing method) of the heat sink 4 a to the wiring board 21 in the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S 5 is different.
  • FIGS. 59 and 60 are explanatory drawings (cross-sectional views) of the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S 5 in the manufacturing process of the semiconductor device 1 a of the present embodiment, and they correspond to FIGS. 33 and 34 of the first embodiment. Note that, although the case where the heat sink 4 a not mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21 like in the process described with reference to FIGS.
  • the heat sink 4 a mounted with the semiconductor chip 5 can be disposed inside the through-hole 3 of the wiring board 21 after mounting (bonding) the semiconductor chip 5 on the heat sink 4 a like in the process described with reference to FIGS. 8 and 19 to 22 .
  • the wiring board 21 used for manufacturing the semiconductor device la of the present embodiment is provided with the hole portion 15 for inserting the pin portion 13 of the heat sink 4 a , and has almost the same structure as the wiring board 21 of the first embodiment other than that.
  • FIGS. 59 and 60 correspond to the cross-section cut along the line A 7 -A 7 of FIG. 50 , and the connecting terminal 17 does not appear in the figure, and the illustration of the land 18 is omitted for the simplification of the drawing.
  • the heat sink 4 a is inserted (plugged) into the through-hole 3 of the wiring board 21 from the upper surface 21 a side (side corresponding to the upper surface 2 a of the wiring board 2 ) of the wiring board 21 in the process of disposing the heat sink 4 a into the through-hole 3 of the wiring board 21 in the step S 5 as shown in FIG. 59 like in the first embodiment. More specifically, the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 in a direction 35 shown by an arrow mark of FIG. 59 . At this time, the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 .
  • the through-hole 3 and the hole portion 15 of the wiring board 21 are disposed at the position so that the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 when the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 .
  • the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13 ) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 , and at the same time, the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a can be inserted into the hole portion 15 of the wiring board 21 .
  • the heat sink 4 a is provided with the protruded portion 11 a (and protruded portion 11 when the protruded portion 11 is provided), when the heat sink 4 a is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 and the pin portion 13 is inserted into the hole portion 15 as shown in FIG. 59 , the protruded portion 11 a (and protruded portion 11 when the protruded portion 11 is provided) of the heat sink 4 a is caught on the upper surface 21 a of the wiring board 21 as shown in FIG. 60 .
  • This protruded portion 11 a (and protruded portion 11 when the protruded portion 11 provided) functions as a stopper, so that the heat sink 4 a can be prevented from falling off downward, that is, in the direction 35 from the through-hole 3 of the wiring board 21 . Consequently, the heat sink 4 a can be retained inside the through-hole 3 of the wiring board 21 .
  • the heat sink 4 a has the protruded portion 11 a protruding to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface of the heat sink 4 a in the peripheral edge portion of the upper surface 9 a of the heat sink 4 a , and in the step S 5 , the main body portion and the pin portion 13 of the heat sink 4 a are disposed inside the through-hole 3 and the hole 15 of the wiring board 21 so that this protruded portion 11 a is located on the upper surface 21 a of the wiring board 21 outside the through-hole 3 and the lower surface 12 a of the protruded portion 11 a contacts to the upper surface 21 a of the wiring board 21 .
  • the side surface 10 of the heat sink 4 is tapered, so that the portion of the heat sink 4 disposed inside the through-hole 3 is tightened up by the inner wall of the through-hole 3 of the wiring board 21 , thereby caulking (fixing) the heat sink 4 to the wiring board 21 .
  • the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a is used to caulk (fix) the heat sink 4 a to the wiring board 21 .
  • a technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a in the present embodiment will be described.
  • FIGS. 61 and 62 are explanatory drawings showing a first technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a .
  • FIGS. 63 to 66 are the explanatory drawings showing a second technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a .
  • FIGS. 67 to 70 are the explanatory drawings showing a third technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a .
  • FIGS. 61 and 62 are explanatory drawings showing a first technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a .
  • FIGS. 63 to 66 are the explanatory drawings showing a second technique for caulking (fixing) the heat sink 4 a to the wiring board
  • FIGS. 61 to 70 , A and B are cross-sectional views and plan views of the same stage, but the plan view of B corresponds to the plan view (lower surface view) of the region in the vicinity of the hole portion 15 when the wiring board 21 is seen from the lower surface 21 b side and the cross-section cut along the line A 12 -A 12 of the plan view of B corresponds to the cross-sectional view of A.
  • FIGS. 61B , 63 B and 67 B are plan views, hatching is applied to the wiring board 21 so as to make the figures easy to see.
  • FIGS. 62B , 64 B and 68 B are plan views, hatching is applied to the wiring board 21 and the pin portions 13 of the heat sink 4 a so as to make the figures easy to see.
  • FIG. 65B is a plan view
  • hatching is applied to a washer or ring-shaped member 25 so as to make the figure easy to see.
  • the position of the hole portion 15 concealed by the bottom 13 b of the crushed pin portion 13 is shown by a dotted line.
  • FIG. 69B is a plan view
  • hatching is applied to the wiring board 21 , the pin portion 13 of the heat sink 4 a and a sleeve 26 so as to make the figure easy to see.
  • the position of the hole portion 15 concealed by the bottom 13 b of the crushed pin portion 13 is shown by a dotted line.
  • FIG. 61 corresponds to a state of FIG. 59
  • FIG. 62 corresponds to a state of FIG. 60 .
  • the first technique is to form a side wall (side surface) 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape as shown in FIGS. 61 and 62 .
  • the cross-sectional shape of the pin portion 13 of the heat sink 4 a shape of the cross-section vertical to the upper surface 21 a of the wiring board 21 when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21
  • the dimension of the pin portion 13 is larger on the upper side (side near the lower surface 12 a of the protruded portion 11 a ) than on the lower side.
  • the dimension of the pin portion 13 becomes thinner (smaller) as approaching a top end portion 13 b and becomes thicker (larger) as approaching the protruded portion 11 a .
  • the pin portion 13 is tapered.
  • the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted has no tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21 .
  • the dimension of the hole portion 15 before the pin portion 13 is inserted is made the same as or slightly larger than the dimension of the top end portion 13 b (top end opposite to the side connected to the lower surface 12 a of the protruded portion 11 a ) of the pin portion 13 , and moreover, is made smaller than the dimension of the upper portion (portion close to the lower surface 12 a of the protruded portion 11 a ) of the pin portion 13 .
  • the planar shape (shape in a plane parallel to the upper surface 21 a of the wiring board 21 ) of the hole portion 15 of the wiring board 21 can be made, for example, circular, and the shape (cross-sectional shape) of the pin portion 13 in the cross-section parallel to the upper surface 21 a of the wiring board 21 when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 can be made the same shape as the through-hole 3 , for example, the circular shape.
  • step S 5 when the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13 ) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 as shown in FIGS. 59 and 60 , the pin portion 13 of the heat sink 4 a is inserted (plugged) into the hole portion 15 of the wiring board 21 as shown in FIGS. 61 and 62 , and the pin portion 13 and the wiring board 21 can be caulked (fixed) by the tapered shape of the side wall 13 a of the pin portion 13 . By this means, the heat sink 4 a can be fixed to the wiring board 21 .
  • the pin portion 13 of the heat sink 4 a when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 in the step S 5 , the side wall 13 a of the pin portion 13 contacts to the inner wall of the hole portion 15 of the wiring board 21 , and the inner wall of the hole portion 15 of the wiring board 21 is expanded in a lateral direction by the tapered shape of the side wall 13 a of the pin portion 13 , and the side wall 13 a of the pin portion 13 is tightened up by the inner wall of the hole portion 15 of the wiring board 21 by its reaction.
  • the pin portion 13 can be caulked (fixed) to the wiring board 21 , and the heat sink 4 a is fixed to the wiring board 21 .
  • the side wall 13 a of the pin portion 13 contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21 , and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21 , and this state is maintained even in the manufactured semiconductor device 1 a.
  • the heat sink 4 a By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the first technique described above, the heat sink 4 a can be fixed to the wiring board 21 , and in addition to this, the following advantages can be further obtained. That is, by inserting the pin portion 13 of the heat sink 4 a into the hole portion 15 of the wiring board 21 , the heat sink 4 a can be fixed to the wiring board 21 , and therefore, the process of disposing and fixing the heat sink 4 a inside the through-hole 3 of the wiring board 21 can be easily performed in the step S 5 . Therefore, the manufacturing process of the semiconductor device can be simplified, and also, the manufacturing time of the semiconductor device can be reduced.
  • the hole portion 15 into which the pin portion 13 of the heat sink 4 a is inserted can be made smaller than the through-hole 3 into which the main portion of the heat sink 4 a is inserted.
  • the dimension of the hole portion 15 is made small (smaller than the through-hole 3 ), so that a place in which the stress occurs in the wiring board 21 can be restricted to the vicinity of the hole portion 15 and a load to the wiring board 21 can be reduced.
  • FIG. 63 corresponds to a state of FIG. 59
  • FIG. 64 corresponds to a state of FIG. 60
  • the operations (processes) of FIGS. 65 and 66 are sequentially performed after FIG. 64 in the second technique.
  • the second technique does not form the side wall 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape.
  • the dimension of the pin portion 13 is the same on the upper surface side and on the lower side (side near the lower surface 12 a of the protruded portion 11 a ).
  • the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted has no tapered shape, and is kept almost vertical with respect to the upper surface 21 a of the wiring board 21 like in the first technique.
  • planar shape of the hole portion 15 of the wiring board 21 (shape in a plane parallel to the upper surface 21 a of the wiring board 21 ) can be made, for example, circular, and the pin portion 13 can be made, for example, columnar.
  • the dimension of the hole portion 15 before the pin portion 13 is inserted is made the same as or slightly larger than the dimension of the pin portion 13 .
  • the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 as shown in FIGS. 63 and 64 . Since the side wall 13 a of the pin portion 13 has no tapered shape, the side wall 13 a of the pin portion 13 is not tightened up by the inner wall of the hole portion 15 of the wiring board 21 at this stage.
  • the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the thickness of the wiring board 21 , so that the top end portion 13 b of the pin portion 13 protrudes from the lower surface 21 b of the wiring board 21 as shown in FIG. 64 at the stage when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 .
  • a washer or ring-shaped member (washer, ring, buffer) 25 is fitted (installed) to the portion of the pin portion 13 protruding from the lower surface 21 b of the wiring board 21 as shown in FIG. 65 . More specifically, the washer or ring-shaped member 25 is disposed on the lower surface 21 b of the wiring board 21 so that the top end portion 13 b of the pin portion 13 penetrates through it. By this means, the portion of the pin portion 13 protruding from the lower surface 21 b of the wiring board 21 is disposed inside the hole of the washer or ring-shaped member 25 .
  • the washer or ring-shaped member 25 is preferably made of a metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the washer or ring-shaped member 25 from the same material as the heat sink 4 a because the heat expansion coefficient of the pin portion 13 and that of the washer or ring-shaped member 25 become the same.
  • the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the total thickness of the wiring board 21 and the washer or ring-shaped member 25 , so that the top end portion 13 b of the pin portion 13 protrudes from the washer or ring-shaped member 25 as shown in FIG. 65 at the stage where the washer or ring-shaped member 25 is fitted to the pin portion 13 .
  • the portion of the pin portion 13 protruding from the lower surface 21 a of the wiring board 21 here, the portion of the pin portion 13 protruding from the washer or ring-shaped member 25 because the washer or ring-shaped member 25 is disposed is crushed by a tool (not shown) and the like. More specifically, the top end portion 13 b of the pin portion 13 is crushed by a tool (not shown) and the like.
  • the pin portion 13 of the heat sink 4 a and the wiring board 21 can be caulked (fixed), and the heat sink 4 a can be fixed to the wiring board 21 .
  • the pin portion 13 is expanded in the lateral direction inside the hole portion 15 of the wiring board 21 , and the side wall 13 a of the pin portion 13 contacts to (adheres to) the inner wall of the hole portion 15 of the wiring board 21 . Then, by the reaction of the expansion of the inner wall of the hole portion 15 of the wiring board 21 in the lateral direction due to the expansion of the pin portion 13 in the lateral direction, the side wall 13 a of the pin portion 13 is tightened up by the inner wall of the hole portion 15 of the wiring board 21 .
  • the pin portion 13 of the heat sink 4 a can be caulked (fixed) to the wiring board 21 , and the heat sink 4 a is fixed to the wiring board 21 .
  • the process up to here is performed by the step S 5 .
  • the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 21 , and the pin portion 13 of the heat sink 4 a is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21 .
  • the side wall 13 a of the pin portion 13 contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21 , and this state is maintained also in the manufactured semiconductor device 1 a.
  • the heat sink 4 a By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the second technique described above, the heat sink 4 a can be fixed to the wiring board 21 , and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 , the pin portion 13 is crushed so as to be able to fix the heat sink 4 a to the wiring board 21 , and therefore, the heat sink 4 a can be more firmly fixed to the wiring board 21 . Hence, it is possible to prevent the heat sink 4 a from falling off from the through-hole 3 of the wiring board 21 more precisely in the manufacturing process of the semiconductor device (until the sealing resin 7 is formed).
  • the hole portion 15 into which the pin portion 13 of the heat sink 4 a is inserted can be made smaller than the through-hole 3 into which the main portion of the heat sink 4 a is inserted.
  • a stress causes in the wiring board 21 by crushing the pin portion 13 inserted into the hole portion 15 of the wiring board 21
  • a place in which the stress occurs in the wiring board 21 can be restricted to the vicinity of the hole portion by making the dimension of the hole portion 15 small, and a load to the wiring board 21 can be reduced.
  • the washer or ring-shaped member 25 functions as a buffer, and therefore, a load applied to the wiring board 21 (region in the vicinity of the hole portion 15 of the lower surface 21 b ) can be reduced.
  • FIG. 67 corresponds to a state of FIG. 59
  • FIG. 68 corresponds to a state of FIG. 60 .
  • the operations (processes) of FIGS. 69 and 70 are sequentially performed after FIG. 68 in the third technique.
  • the third technique does not form the side wall 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape like in the second technique.
  • the dimension of the pin portion 13 is the same on the lower side and on the upper side (side near the lower surface 12 a of the protruded portion 11 a ).
  • the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted does not have the tapered shape, and is kept almost vertical with respect to the upper surface 21 a of the wiring board 21 like in the first and second techniques.
  • the planar shape (shape in a plane parallel to the upper surface 21 a of the wiring board 21 ) of the hole portion 15 of the wiring board 21 can be made, for example, circular, and the pin portion 13 can be made, for example, columnar.
  • the dimension of the hole portion 15 before the pin portion 13 is inserted is made larger than the dimension of the pin portion 13 so that the sleeve 26 to be described later can be inserted.
  • the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 as shown in FIGS. 67 and 68 . Since the side wall 13 a of the pin portion 13 has no tapered shape, the side wall 13 a of the pin portion 13 is not tightened up by the inner wall of the hole portion 15 of the wiring board 21 at this stage.
  • the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the thickness of the wiring board 21 , so that the top end portion 13 b of the pin portion 13 protrudes from the lower surface 21 b of the wiring board 21 as shown in FIG. 68 at the stage when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 .
  • the sleeve 26 is inserted from the lower surface 21 b side of the wiring board 21 into the hole portion 15 in which the pin portion 13 has been inserted.
  • the sleeve 26 is a tube-shaped or a cylindrical member. More specifically, while disposing (inserting) the pin portion 13 into the hole of the sleeve 26 , the sleeve 26 is disposed inside the hole portion 15 of the wiring board 21 . Therefore, the sleeve 26 is interposed between the inner wall of the hole portion 15 of the wiring board 21 and the side wall 13 a of the pin portion 13 .
  • the external dimension of the sleeve 26 is made almost the same as or slightly smaller than the hole portion 15 of the wiring board 21 , and the dimension of the hole of the sleeve 26 is made almost the same as or slightly larger than the pin portion 13 .
  • the sleeve 26 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the sleeve 26 from the same material as the heat sink 4 a because the heat expansion coefficient of the pin portion 13 and that of the sleeve 26 become the same.
  • the portion of the pin portion 13 protruding from the lower surface 21 a of the wiring board 21 that is, the top end portion 13 b of the pin portion 13 is crushed by a tool (not shown) and the like.
  • the pin portion 13 of the heat sink 4 a and the wiring board 21 can be caulked (fixed), and the heat sink 4 a can be fixed to the wiring board 21 .
  • the top end portion 13 b of the pin portion 13 is crushed, the top end portion 13 b of the pin portion 13 is expanded in the lateral direction outside the hole portion 15 of the wiring board 21 and the sleeve 26 , and the wiring board 21 and the sleeve 26 are sandwiched by the top end portion 13 b of the pin portion 13 expanded in the lateral direction and the protruded portion 11 a , so that the heat sink 4 a can be caulked (fixed) to the wiring board 21 and the heat sink 4 a is fixed to the wiring board 21 .
  • the process up to here is performed by the step S 5 .
  • the sleeve 26 is interposed between the side wall of the pin portion 13 and the inner wall of the hole portion 15 inside the hole portion 15 of the wiring board 21 , and the expansion of the pin portion 13 in the lateral direction is restricted by the sleeve 26 , and since this sleeve 26 functions as a buffer, the application of a load to the inner wall of the hole portion 15 of the wiring board 21 can be prevented.
  • the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 21 , and the pin portion 13 of the heat sink 4 a is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21 .
  • the sleeve 26 is interposed between the inner wall of the hole portion 15 and the side wall 13 a of the pin portion 13 inside the hole portion 15 of the wiring board 21 , and this state is maintained even in the manufactured semiconductor device 1 a.
  • the heat sink 4 a By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the third technique described above, the heat sink 4 a can be fixed to the wiring board 21 , and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 , the pin portion 13 is crushed so as to be able to fix the heat sink 4 a to the wiring board 21 , and therefore, the occurrence of the falling off of the heat sink 4 a from the through-hole 3 of the wiring board 21 can be reduced.
  • the second and third techniques require the operations (processes) for crushing the top end portion 13 b of the pin portion 13 after the disposition inside the through-hole 3 of the wiring board 21 , if the manufacturing process described with reference to FIGS. 30 to 38 is applied, the top end portion 13 b of the pin portion 13 can be crushed in a state in which the semiconductor chip 5 is not mounted on the heat sink 4 a , and therefore, the operation for crushing the pin portion 13 can be easily performed.
  • the side surface of the heat sink 4 a can be tapered like in the first embodiment.
  • the heat sink 4 a in addition to the fixing by the pin portion 13 , the heat sink 4 a can be fixed to the wiring board 21 by the tapered shape of the side surface 10 of the heat sink 4 a , and therefore, a fixing power between the heat sink 4 a and the wiring board 21 can be further strengthened and the stability of the manufacturing process can be further increased.
  • FIG. 71 is an upper surface view (plan view) showing a modified example of the wiring board 2 used for the semiconductor device 1 a , and it corresponds to FIG. 57 . In FIG. 71 , no hatching is applied.
  • FIG. 72 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 b of the third embodiment, and it corresponds to FIG. 1 of the first embodiment and FIG. 48 or FIG. 49 of the second embodiment.
  • a heat sink 4 b is attached to a lower surface 2 b side of the wiring board 2 , and the semiconductor chip 5 is mounted on an upper surface 9 c of the heat sink 4 b exposed at the bottom of the through-hole 3 of the wiring board 2 .
  • the heat sink 4 b is not provided with a portion corresponding to the protruded portions 11 and 11 a , and has a flat plate shape (flat plate shape whose planar shape is rectangular) having the upper surface 9 c and the lower surface 9 d , and a pin portion (caulking portion, pin portion for caulking, caulking pin, protruded portion, convex portion) 13 c is integrally provided with the heat sink 4 b in the vicinity of the peripheral edge portion of the upper surface 9 c of the heat sink 4 b .
  • the heat sink 4 b is disposed on a lower surface 2 b of the wiring board 2 so as to planarly enclose the through-hole 3 of the wiring board 2 and the pin portion 13 c of the heat sink 4 b is disposed inside the hole portion 15 of the wiring board 2 , and the heat sink 4 b is fixed to the wiring board 2 by this pin portion 13 c .
  • the structure of the semiconductor device 1 b other than this is almost the same as the semiconductor devices 1 and 1 a of the first and second embodiments, and therefore, the description thereof will be omitted here.
  • the material of the heat sink 4 b is the same as those of the heat sinks 4 and 4 a of the first and second embodiments.
  • the manufacturing process of the semiconductor device 1 b of the present embodiment is the same as the manufacturing processes of the semiconductor devices 1 and 1 a of the first and second embodiments except that the step S 5 is different.
  • the process performed in place of the step S 5 process of disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 ) in the present embodiment will be described below.
  • the process performed in place of the step S 5 process of disposing the heat sink 4 inside the through-hole 3 of the wiring board 21
  • step S 5 a or a process of fixing the heat sink 4 b to the wiring board 2 will be referred to as step S 5 a or a process of fixing the heat sink 4 b to the wiring board 2 .
  • FIGS. 73 and 74 are explanatory drawings (cross-sectional views) of the process of fixing the heat sink 4 b to the wiring board 21 in the step S 5 in the manufacturing process of the semiconductor device 1 b of the present embedment, and they correspond to FIGS. 59 and 60 of the second embodiment.
  • the case of fixing the heat sink 4 b not mounted with the semiconductor chip 5 to the wiring board 21 like in the process described with reference to FIG. 30 to FIG. 34 will be described.
  • the heat sink 4 b mounted with the semiconductor chip 5 can be fixed to the wiring board 21 like in the process described with reference to FIG. 8 and FIGS. 19 to 22 .
  • the heat sink 4 b is brought close to the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 b of the wiring board 2 ) of the wiring board 21 in the process of fixing the heat sink 4 b to the wiring board 21 in the step S 5 a performed as the step S 5 as shown in FIG. 73 . Then, as shown in FIG. 74 , the pin portion 13 c provided on the upper surface 9 c of the heat sink 4 b is inserted (plugged) into the hole portion 15 of the wiring board 21 .
  • the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 in a direction 35 a shown by arrow marks of FIGS. 73 and 74 . Then, by using a fourth technique shown in FIGS. 75 to 78 to be described later or a fifth technique shown in FIGS. 79 to 82 to be described later, the heat sink 4 b and the wiring board 21 are fixed.
  • the heat sink 4 b is attached and fixed to the lower surface 2 b side of the wiring board 2 , and the heat sink 4 b planarly encloses the through-hole 3 of the wiring board 21 , and the through-hole 3 of the wiring board 21 is blocked by the heat sink 4 b on the lower surface 2 b side of the wiring board 2 .
  • FIGS. 75 to 78 are explanatory drawings (cross-sectional views) showing the fourth technique for fixing (caulking) the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b .
  • FIGS. 79 to 82 are explanatory drawings (cross-sectional view) showing the fifth technique for fixing (caulking) the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b .
  • FIGS. 75 to 78 show the cross-section of the region in the vicinity of the hole portion 15 of the wiring board 21 , and they correspond to FIGS. 63A , 64 A, 65 A and 66 A of the second embodiment.
  • FIGS. 79 to 82 show the cross-section of the region in the vicinity of the hole portion 15 of the wiring board 21 , and they correspond to FIGS. 67A , 68 A, 69 A and 70 A of the second embodiment.
  • the fourth technique for fixing the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b will be described with reference to FIGS. 75 to 78 .
  • This fourth technique is the same as the second technique (technique shown in FIGS. 63 to 66 ) described in the second embodiment except that the inserting direction of the pin portion 13 c into the hole portion 15 of the wiring board 21 is opposite.
  • the fourth technique used in the present embodiment is the same as the second technique (technique shown in FIGS. 63 to 66 ) of the second embodiment in the shapes and the dimensions of the pin portion 13 c and the hole portion 15 , and therefore, the description thereof will be omitted here.
  • the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 from the lower surface 21 b side of the wiring board 21 , and the upper surface 9 c of the heat sink 4 b is made to contact to the lower surface 21 b (lower surface 21 b in the peripheral region of the through-hole 3 ) of the wiring board 21 .
  • the top end portion 13 d of the pin portion 13 c protrudes from the upper surface 21 a of the wiring board 21 .
  • a washer or ring-shaped member 25 similar to the second embodiment is fitted (installed) to the portion of the pin portion 13 c protruding from the upper surface 21 a of the wiring board 21 as shown in FIG. 77 . More specifically, the portion of the pin portion 13 c protruding from the upper surface 21 a of the wiring board 21 is disposed inside the hole of the washer or ring-shaped member 25 . Further, in the fourth technique, a length of the pin portion 13 c before being inserted into the hole portion 15 is made larger than the total thickness of the wiring board 21 and the washer or ring-shaped member 25 . By this means, as shown in FIG. 77 , at the stage in which the washer or ring-shaped member 25 is fitted into the pin portion 13 c , the top end portion 13 d of the pin portion 13 c protrudes from the washer or ring-shaped member 25 .
  • the washer or ring-shaped member 25 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is preferable to form the washer or ring-shaped member 25 from the same material as the heat sink 4 b because the heat expansion coefficient of the pin portion 13 c and that of the washer or ring-shaped member 25 become the same.
  • the top end portion 13 d of the pin portion 13 c is crushed by a tool (not shown) and the like.
  • the pin portion 13 c of the heat sink 4 b and the wiring board 21 can be caulked (fixed), and the heat sink 4 b can be fixed to the wiring board 21 .
  • the pin portion 13 c is expanded in the lateral direction inside the hole portion 15 of the wiring board 21 , and the side wall of the pin portion 13 c contacts to (adhered to) the inner wall of the hole portion 15 of the wiring board 21 . Then, by the reaction of the expansion of the inner wall of the hole portion 15 of the wiring board 21 in the lateral direction due to the expansion of the pin portion 13 c in the lateral direction, the side wall of the pin portion 13 c is tightened up by the inner wall of the hole portion 15 of the wiring board 21 .
  • the pin portion 13 c of the heat sink 4 b can be caulked (fixed) to the wiring board 21 , and the heat sink 4 b is fixed to the wiring board 21 .
  • the process up to here is performed by the step S 5 a corresponding to the step S 5 .
  • the pin portion 13 c of the heat sink 4 b is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21 .
  • the side wall of the pin portion 13 c contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21 , and this state is maintained even in the manufactured semiconductor device 1 b.
  • the heat sink 4 b By caulking (fixing) the heat sink 4 b to the wiring board 21 by using the fourth technique described above, the heat sink 4 b can be fixed to the wiring board 21 , and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 , the pin portion 13 c is crushed so as to be able to fix the heat sink 4 b to the wiring board 21 , and therefore, the heat sink 4 b can be firmly fixed to the wiring board 21 .
  • the fifth technique for fixing the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b will be described with reference to FIGS. 79 to 82 .
  • This fifth technique is the same as the third technique (technique shown in FIGS. 67 to 70 ) described in the second embodiment except that the inserting direction of the pin portion 13 c to the hole portion 15 of the wiring board 21 is opposite.
  • the fifth technique used in the present embodiment is the same as the third technique (technique shown in FIGS. 67 to 70 ) of the second embodiment in the shapes and the dimensions of the pin portion 13 c and the hole portion 15 , and therefore, the description thereof will be omitted here.
  • the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 from the lower surface 21 b side of the wiring board 21 , and the lower surface 21 b (lower surface 21 b in the peripheral region of the through-hole 3 ) of the wiring board 21 is made to contact to the upper surface 9 c of the heat sink 4 b .
  • the top end portion 13 d of the pin portion 13 c protrudes from the upper surface 21 a of the wiring board 21 .
  • the sleeve 26 similar to the second embodiment is inserted from the upper surface 21 a side of the wiring board 21 into the hole portion 15 in which the pin portion 13 c has been inserted. More specifically, while disposing (inserting) the pin portion 13 c into the hole of the sleeve 26 , the sleeve 26 is disposed inside the hole portion 15 of the wiring board 21 . Therefore, the sleeve 26 is interposed between the inner wall of the hole portion 15 of the wiring board 21 and the side wall 13 a of the pin portion 13 c.
  • the sleeve 26 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the sleeve 26 from the same material as the heat sink 4 b because the heat expansion coefficient of the pin portion 13 c and that of the sleeve 26 become the same.
  • the top end portion 13 d of the pin portion 13 c is crushed by a tool (not shown) and the like.
  • the pin portion 13 c of the heat sink 4 b and the wiring board 21 can be caulked (fixed), and the heat sink 4 b can be fixed to the wiring board 21 .
  • the top end portion 13 d of the pin portion 13 c is crushed, the top end portion 13 d of the pin portion 13 c is expanded in the lateral direction outside the hole portion 15 of the wiring board 21 and the sleeve 26 , and the wiring board 21 and the sleeve 26 are sandwiched by the top end portion 13 d of the pin portion 13 c expanded in the lateral direction and (the upper surface 9 c of) the heat sink 4 b , so that the heat sink 4 b can be caulked (fixed) to the wiring board 21 , and the heat sink 4 b is fixed to the wiring board 21 .
  • the process up to here is performed by the step S 5 a.
  • the pin portion 13 c of the heat sink 4 b is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21 .
  • the sleeve 26 is interposed between the inner wall of the hole portion 15 and the side wall of the pin portion 13 c inside the hole portion 15 of the wiring board 21 , and this state is maintained even in the manufactured semiconductor device 1 b.
  • the heat sink 4 b By caulking (fixing) the heat sink 4 b to the wiring board 21 by using the fifth technique described above, the heat sink 4 b can be fixed to the wiring board 21 , and in addition to this, the following advantages can be further obtained. That is, even if the top end portion 13 d of the pin portion 13 c is crushed, the expansion of the pin portion 13 c in the lateral direction is restricted by the sleeve 26 inside the hole portion 15 of the wiring board 21 , and since this sleeve 26 functions as a buffer, the application of a load to the inner wall of the hole portion 15 of the wiring board 21 can be prevented. Hence, the application of a load to the wiring board 21 can be prevented.
  • FIG. 83 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 b 1 of an modified example of the third embodiment and FIGS. 84 and 85 are explanatory drawings (cross-sectional views) of the process of fixing a heat sink 4 b 1 to the wiring board 21 in the step S 5 a in the manufacturing process of the semiconductor device of FIG. 83 , and they correspond to FIGS. 72 to 74 , respectively.
  • the heat sink 4 b 1 is fixed to the wiring board 21 from the lower surface 21 b side of the wiring board 21 like in the case of FIGS. 72 to 82 .
  • FIGS. 83 the case of FIGS.
  • a fixing technique uses the pin portion 13 c of the heat sink 4 b
  • the fixing technique uses the tapered shape of the side surface 10 of the heat sink 4 b 1 .
  • the heat sink 4 b 1 mounted with the semiconductor chip 5 can also be fixed to the wiring board 21 in the step S 5 a as shown in FIGS. 73 and 74 .
  • the process of fixing the heat sink 4 b 1 to the wiring board 21 in the step S 5 a is performed as shown in FIGS. 84 and 85 . More specifically, as shown in FIG. 84 , the heat sink 4 b 1 mounted with the semiconductor chip 5 is brought close to the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 b of the wiring board 2 ) of the wiring board 21 . Then, as shown in FIG.
  • the heat sink 4 b 1 mounted with the semiconductor chip 5 is inserted (plugged) into the through-hole 3 of the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 a of the wiring board 2 ) of the wiring board 21 . That is, the heat sink 4 b 1 mounted with the semiconductor chip 5 is inserted into the through-hole 3 of the wiring board 21 in a direction 35 a shown by the arrow marks of FIGS. 84 and 85 .
  • the heat sink 4 b 1 does not have a protruded portion like the protruded portions 11 and 11 a in the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1 , the heat sink 4 b 1 can be inserted into the through-hole 3 of the wiring board 21 from the lower surface 21 b side of the wiring board 21 .
  • the heat sink 4 b 1 is integrally provided with a protruded portion (projecting portion, overhang portion, hook portion) 11 b protruding to the outside further than the side surface 10 of the heat sink 4 b 1 in the peripheral edge portion of the lower surface 9 b of the heat sink 4 b 1 , and this protruded portion 11 b functions as a stopper when the heat sink 4 b 1 is inserted into the through-hole 3 of the wiring board 21 from the lower surface 21 b side of the wiring board 21 .
  • a protruded portion projecting portion, overhang portion, hook portion
  • the side surface 10 of the heat sink 4 b 1 has a tapered shape.
  • the tapered shape of the side surface 10 of the heat sink 4 b 1 is reversed in direction with respect to the tapered shape of the side surface 10 of the heat sink 4 of the first embodiment, and the dimension of the heat sink 4 b 1 (dimension of the cross-section parallel to the upper surface 2 a of the wiring board 2 ) is made slightly smaller on the upper side than on the lower side.
  • the inner wall of the through-hole 3 of the wiring board 21 before the heat sink 4 b 1 is inserted does not have the tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21 .
  • the heat sink 4 b 1 and the wiring board 21 can be caulked by the tapered shape of the side surface 10 of the heat sink 4 b 1 , and the heat sink 4 b 1 can be fixed to the wiring board 21 .
  • the side surface 10 of the heat sink 4 b 1 contacts to the inner wall of the through-hole 3 of the wiring board 21 , and the inner wall of the through-hole 3 of the wiring board 21 is expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4 b 1 , so that the side surface 10 of the heat sink 4 b 1 is tightened up by the inner wall of the through-hole 3 of the wiring board 21 by its reaction, and the heat sink 4 b 1 is fixed to the wiring board 21 .
  • the protruded portion like the above-described protruded portion 11 is not present in the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1 , a stopper effect to the lower side (in the direction 35 ) of the protruded portion 11 is eliminated as compared with the first embodiment and an effect of preventing the heat sink from falling off is reduced, but the heat sink 4 b 1 can be retained to the wiring board 21 by the tightening up by the tapered shape of the side surface 10 of the heat sink 4 b 1 .
  • the side surface 10 of the heat sink 4 b 1 contacts and adheres to the inner wall of the through-hole 3 of the wiring board 21 and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21 , and this state is maintained even in the manufactured semiconductor device 1 b 1 as shown in FIG. 83 .
  • the manufacturing process of the semiconductor device 1 b 1 of FIG. 83 is almost the same as the manufacturing process of the semiconductor device 1 of the first embodiment except that the step S 5 a as shown in FIGS. 84 and 85 is performed in place of the step S 5 of the first embodiment, the description thereof will be omitted here. Since the heat sink 4 b 1 and the wiring board 21 are caulked and fixed by the tapered shape of the side surface 10 of the heat sink 4 b 1 , the heat sink 4 b 1 can be retained (fixed) to the wiring board 21 until the resin sealing is performed in the step S 7 after the step S 5 a.
  • the heat sink 4 b 1 is disposed inside the through-hole 3 of the wiring board 2 .
  • the portions equivalent to the protruded portions 11 and 11 a are not present on the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1 , the heat sink 4 b 1 does not extend on the upper surface 2 a of the wiring board 2 .
  • the protruded portion 11 b is provided on the peripheral edge portion of the lower surface 9 b of the heat sink 4 b 1 , this protruded portion 11 b is located on the lower surface 2 b of the wiring board 2 outside the through-hole 3 , and the upper surface of the protruded portion 11 b contacts to the lower surface 2 b of the wiring board 2 .
  • the portion other than the protruded portion 11 b of the heat sink 4 b 1 when seen on the plane parallel to the upper surface 2 a of the wiring board 2 , the portion other than the protruded portion 11 b of the heat sink 4 b 1 is located at the position planarly overlapped with the through-hole 3 , and only the protruded portion 11 b is located outside the through-hole 3 (position not planarly overlapped with the through-hole 3 , that is, the position overlapped with the wiring board 2 ). Since the structure of the semiconductor device 1 b 1 other than this is almost the same as the semiconductor device 1 of the first embodiment, the description thereof will be omitted here. Also, the material of the heat sink 4 b 1 is the same as that of the heat sink 4 of the first embodiment.
  • the connecting terminal 17 can be disposed close to the through-hole 3 (that is, the semiconductor chip 5 on the heat sink 4 b 1 disposed inside the through-hole 3 ) in the wiring board 21 (wiring board 2 ) because the portions corresponding to the protruded portions 11 and 11 a are not present on the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1 .
  • this is advantageous for the miniaturization (reduction in area) of the semiconductor device.
  • the bonding wire 6 is less likely to contact to the heat sink 4 b 1 .
  • FIGS. 72 to 82 of the third embodiment are similar to the second and third techniques described in the second embodiment in that the washer or ring-shaped member 25 or the sleeve 26 is used, and FIGS. 83 to 85 of the third embodiment are similar to the first embodiment in that the tapered shape of the side surface of the heat sink is used.
  • the first and second embodiments and the following fourth and fifth embodiments have still other advantages as follows.
  • the first and second embodiments and the following fourth and fifth embodiments have a structure provided with the heat sinks 4 , 4 a and 4 c inside the through-hole 3 of the wiring board 21 , the thickness of the heat sinks 4 , 4 a and 4 c can be made large, and the heat dissipation properties of the semiconductor device can be more improved.
  • the weight of the heat sink 4 b and 4 b 1 operates so that the heat sink 4 b and 4 b 1 fall off from the wiring board 21 .
  • the heat sinks 4 b and 4 b 1 are likely to fall off (peel off) from the wiring board 21 in the manufacturing process of the semiconductor device, and this will lower the manufacturing yield of the semiconductor device.
  • the heat sinks 4 , 4 a and 4 c are disposed inside the through-hole 3 of the wiring board 21 from the upper surface 21 a side of the wiring board 21 , and the weight of the heat sinks 4 , 4 a and 4 c h (gravity working on the heat sinks 4 , 4 a and 4 c ) can be received by the protruded portions 11 and 11 a of the heat sinks 4 and 4 a or a joining portion 33 a to be described later.
  • the protruded portions 11 and 11 a or the joining portion 33 a to be described later are located on the upper surface 21 a of the wiring board 21 so that the lower surfaces of the protruded portions 11 and 11 a or the joining portion 33 a to be described later contact to the upper surface 21 a of the wiring board 21 in the first and second embodiments and the following fourth and fifth embodiments, the protruded portions 11 and 11 a or the joining portion 33 a to be described later support the weight of the heat sinks 4 , 4 a and 4 c.
  • those corresponding to the wiring board 21 are wiring boards 21 c , 21 d and 2 f.
  • the heat sinks 4 , 4 a , 4 b , 4 b 1 and 4 c are required to be surely fixed inside the through-hole 3 of the wiring board 2 .
  • the heat sinks 4 , 4 a and 4 c into the through-hole 3 from the upper surface 21 a side of the wiring board 21 like in the first and second embodiments and the fourth and fifth embodiments to be described later rather than fixing the heat sinks 4 b and 4 b 1 to the wiring board 21 from the lower surface 21 b side of the wiring board 21 like in the third embodiment.
  • that corresponding to the wiring board 2 is a wiring board 2 f.
  • the individually segmented heat sinks 4 and 4 a are disposed inside the through-hole 3 of the wiring board 21 to manufacture the semiconductor devices 1 and 1 a .
  • a resin sealing process is performed in a state in which a plurality of heat sinks 4 c are joined, and then, the sealing body is individually segmented, thereby manufacturing the semiconductor device 1 c.
  • FIG. 86 is a process flowchart showing the manufacturing process of a semiconductor device of the present embodiment.
  • FIG. 87 is an upper surface view (plan view) of a frame 31 a used for the manufacture of the semiconductor device of the present embodiment
  • FIG. 88 is a lower surface view (plan view) of the frame 31 a
  • FIGS. 89 and 90 are cross-sectional views of the frame 31 a.
  • the cross-section cut along the line A 13 -A 13 of FIGS. 87 and 88 corresponds to FIG. 89
  • the cross-section cut along the line A 14 -A 14 of FIGS. 87 and 88 corresponds to FIG. 90 .
  • FIG. 87 is a plan view, hatching is applied to the frame 31 a so that the shape of the frame 31 a is easily understood.
  • FIGS. 91 and 92 are a plan view (upper surface view) and a cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 91 shows a planar region corresponding to FIG. 87 and FIG. 92 shows the cross-section corresponding to FIG. 89 .
  • FIG. 93 is an upper surface view (plan view) of the wiring board 21 c used for the manufacturing process of the semiconductor device of the present embodiment, and FIGS. 94 and 95 are cross-sectional views of the wiring board 21 c .
  • the cross-section cut along the line A 15 -A 15 of FIG. 93 corresponds to FIG.
  • FIGS. 96 to 98 are a plan view (upper surface view) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 96 shows a planar region corresponding to FIGS. 87 and 93 , FIG. 97 shows the cross-section corresponding to FIGS. 89 and 94 , and FIG. 98 shows the cross-section corresponding to FIGS. 90 and 95 .
  • FIGS. 99 and 100 are explanatory drawings (cross-sectional views) showing a technique of fixing the frame 31 a to the wiring board 21 c by using a pin portion 13 e of the frame 31 a .
  • FIGS. 101 to 105 are plan views (upper surface views) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment.
  • FIGS. 101 and 102 show the same process stage, and FIG. 101 shows the planar region corresponding to FIG. 96 and FIG. 102 shows the cross-section corresponding to FIG. 97 .
  • FIGS. 103 and 104 show the same process stage, and FIG. 103 shows the planar region corresponding to FIG. 101 and FIG. 104 shows the cross-section corresponding to FIG. 102 .
  • FIG. 105 is a process stage subsequent to FIG. 104 , and shows the cross-section corresponding to FIG. 104 .
  • FIGS. 106 and 107 are cross-sectional views (side cross-sectional views) of the semiconductor device 1 c of the present embodiment
  • FIG. 108 is a perspective plan view (upper surface view) of the semiconductor device 1 c when the sealing resin 7 is seen through.
  • the cross-section cut along the line A 17 -A 17 of FIG. 108 almost corresponds to FIG. 106
  • the cross-section cut along the line A 18 -A 18 of FIG. 108 almost corresponds to FIG. 107
  • FIG. 109 is a lower surface view of the wiring board 2 in the semiconductor conductor device 1 c .
  • FIG. 109 is a plan view, hatching is applied to a solder resist layer 19 so that the planar shape (pattern) of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 is easily understood.
  • FIG. 103 is a plan view, hatching is applied to the sealing resin 7 a and the outer shape of the frame 31 a located below the sealing resin 7 a is shown by a dotted line for easy understanding.
  • FIG. 103 shows a cutting position (cutting line, dicing line) DL of the cutting process in the step S 10 b by a two-dot chain line.
  • the frame 31 a in which a plurality of heat sinks 4 c are joined as shown in FIGS. 87 to 90 is prepared (step S 2 b ).
  • the frame 31 a has a structure in which a plurality of heat sinks 4 c are integrally joined with the frame portion 32 . More specifically, a plurality of heat sink 4 c are disposed in a row at the predetermined intervals (preferably equal intervals) between the two frame portions 32 extending in parallel in the same direction at the predetermined interval, and each heat sink 4 c is joined with the frame portion 32 through a joining portion (suspension lead) 33 a .
  • the joining portion 33 a can be taken also as a suspension lead for suspending (retaining) the heat sink 4 c for mounting the semiconductor chip 5 later on the frame portion 32 .
  • the heat sink 4 c corresponds to the heat sinks 4 and 4 a of the first and second embodiments and is made of the same material as the heat sinks 4 and 4 a .
  • the heat sink 4 c has the same structure as the heat sinks 4 and 4 a of the first and second embodiments except that the protruded portions 11 and 11 a and the pin portion 13 are not formed, the taper (inclination) of the side surface 10 of the heat sink 4 c is eliminated, and the dimension of the heat sink 4 c is made slightly smaller than the dimension of the through-hole 3 of the wiring board 21 .
  • each joining portion 33 a is connected to the heat sink 4 c , and the other end portion is connected to the frame portion 32 .
  • the joining portion 33 a is connected to the upper portion of the heat sink 4 c , and the joining portion 33 a and the heat sink 4 c are integrally formed, and therefore, the joining portion 33 a extends until reaching the frame portion 32 in the peripheral edge portion of the upper surface 9 a of the heat sink 4 c so as to protrude outside from the side surface of the heat sink 4 c .
  • the one obtained by adding the protruded portion 11 a from which the pin portion 13 c is omitted and the joining portion 33 integrally connected to the protruded portion 11 a in the frame 31 of the second embodiment corresponds to the joining portion 33 a in the frame 31 a of the present embodiment. Further, it can be said that the one in which the protruded portion 11 a provided with no pin portion 13 c is extended until reaching the frame portion 32 in the second embodiment corresponds to the joining portion 33 a in the frame 31 a of the present embodiment.
  • the joining portion 33 a is connected to each of the four corners of the upper surface 9 a of the heat sink 4 c as shown in FIGS. 87 and 88 , and by this means, the heat sink 4 c can be stably joined (retained) to the frame portion 32 , and at the same time, when the frame 31 a is fixed to the wiring board 21 c later, the joining portion 33 a and the connecting terminal 17 b are less likely to overlap with each other.
  • the extending direction of the joining portion 33 a is preferably the diagonal direction of the upper surface 9 a of the heat sink 4 c.
  • the lower surface 32 a of the frame portion 32 has pin portions (caulking portions, pin portions for caulking, caulking pins, protruded portions, convex portions) 13 e integrally formed with the frame portion 32 .
  • the pin portion 13 e is used for fixing the frame portion 32 and the wiring board 21 .
  • the heat sink 4 c , the frame portion 32 , the joining portion 33 a , and the pin portion 13 e are integrally formed of the same material.
  • the frame 31 a can be formed by, for example, processing a copper plate and the like by a metal mold.
  • the heat sinks 4 c appear to be separated from each other in the cross-sectional view of FIG. 89 , as evident from FIGS. 87 and 88 , the heat sinks 4 c are mutually joined in reality through the joining portion 33 a and the frame portion 32 .
  • step S 3 b After the frame 31 a is prepared, as shown in FIGS. 91 and 92 , the semiconductor chip 5 is bonded on the upper surface 9 a of each heat sink 4 c of the frame 31 a through the bonding agent 14 (step S 3 b ).
  • the bonding process of the semiconductor chip 5 in the step S 3 b can be performed in the same manner as the bonding process of the semiconductor chip 5 in the step S 3 of the first embodiment, and therefore, the detailed description thereof will be omitted here.
  • the wiring board 21 c for the semiconductor device manufacture is prepared (step S 1 b ).
  • this wiring board 21 c corresponds to the wiring boards of the first and second embodiments
  • the wiring board 21 c has a structure in which a plurality of semiconductor device regions 22 from each of which one semiconductor device 1 is formed are disposed (joined) in a row.
  • the wiring board 21 c is cut by a cutting process to be described later, and the one separated into each semiconductor device region (board region, unit board region) 22 corresponds to the wiring board 2 of the semiconductor device 1 c to be described later.
  • each semiconductor device region 22 in the wiring board 21 c is almost the same as the structure of each semiconductor device region 22 of the wiring board 21 in the first embodiment, and the through-hole 3 is formed in each semiconductor device region 22 of the wiring board 21 c , a plurality of connecting terminals 17 and the wirings connected thereto are formed in each of the semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c , and a plurality of lands 18 are formed in each of the semiconductor device regions 22 of the lower surface 21 b of the wiring board 21 .
  • a plurality of hole portions 15 a similar to the hole portion 15 of the second embodiment are formed in the wiring board 21 c of the present embodiment, but the forming position of the hole portion 15 a is different from that of the hole portion 15 of the second embodiment. More specifically, in the wiring board 21 c of the present embodiment, the hole portion 15 a is formed at the position planarly overlapped with the pin portion 13 e provided on the lower surface 32 a of the frame portion 32 when the frame 31 a is fixed to the wiring board 21 c in the step S 5 b to be described later. Consequently, the hole portion 15 a is formed in the vicinity of the side end portion of the wiring board 21 c .
  • the hole portion 15 a is a through-hole reaching the lower surface 21 b from the upper surface 21 a of the wiring board 21 c , but the planar dimension of the hole portion 15 a is sufficiently smaller as compared with the through-hole 3 for inserting the heat sink 4 c.
  • step S 5 b the frame 31 a is fixed to the wiring board 21 c (step S 5 b ). It is necessary to prepare the wiring board 21 c in the step S 1 b before performing this step S 5 b . Hence, the preparation of the wiring board 21 c in the step S 1 b can be performed also before the step S 2 b , simultaneously with the step S 2 b , before the step S 3 b and after the step S 2 b , simultaneously with the step S 3 b or before the step S 5 b and after the step S 3 b.
  • each of the heat sinks 4 and 4 a is separated from the frame 31 into individual pieces, and then, the heat sinks 4 and 4 a are disposed inside each of the through-holes 3 of the wiring board 21 .
  • the frame 31 a in a state in which a plurality of heat sinks 4 c are joined is fixed to the wiring board 21 c.
  • the frame 31 a is positioned and disposed on the upper surface 21 a of the wiring board 21 c and each heat sink 4 c of the frame 31 a is inserted (plugged) into each through-hole 3 of the wiring board 21 c from the upper surface 21 a side of the wiring board 21 c , and at the same time, each pin portion 13 e of the frame 31 a is inserted (plugged) into each hole portion 15 a of the wiring board 21 c .
  • the through-hole 3 and the hole portion 15 a of the wiring board 21 c are disposed at the position in which each pin portion 13 e of the frame 31 a is inserted into each hole portion 15 a of the wiring board 21 c when each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c.
  • each heat sink 4 c is connected to the frame portion 32 through the joining portion 33 a .
  • the frame portion 32 and the joining portion 33 a are overlapped with the upper surface 21 a of the wiring board 21 c as shown in FIGS. 96 to 98 , and therefore, the heat sink 4 c does not fall off downward from the through-hole 3 of the wiring board 21 c .
  • each heat sink 4 c of the frame 31 a is disposed inside each through-hole 3 of the wiring board 21 c
  • the frame 31 a is fixed to the wiring board 21 c by the pin portion 13 e of the frame 31 a.
  • each heat sink 4 c in the frame 31 a has the joining portion 33 a which protrudes to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface of each heat sink 4 c on the peripheral edge portion of the upper surface 9 a of each heat sink 4 c , and in the step S 5 b , each heat sink 4 c is disposed inside the through-hole 3 of the wiring board 21 c so that this joining portion 33 a is located on the upper surface 21 a of the wiring board 21 c outside the through-hole 3 and the lower surface of the joining portion 33 a contacts to the upper surface 21 a of the wiring board 21 c.
  • the frame 31 a and the wiring board 21 c are fixed by the same technique as the first technique of the second embodiment. More specifically, for fixing the frame 31 a to the wiring board 21 c , the pin portion 13 e provided on the frame 31 a is used.
  • FIGS. 99 and 100 are explanatory drawings (cross-sectional views) showing a technique for fixing (caulking) the frame 31 a to the wiring board 21 c by using the pin portion 13 e of the frame 31 a , and they correspond to FIGS. 61 and 62A of the second embodiment.
  • FIGS. 99 and 100 show the cross-sectional views of the region in the vicinity of the hole portion 15 a of the wiring board 21 c.
  • the shape of the pin portion 13 e of the frame 31 a is the same as the shape of the pin portion 13 in the first technique of the second embodiment. More specifically, as shown in FIG. 99 , the side wall (side surface) 13 f of the pin portion 13 e of the frame 31 a is tapered.
  • the cross-sectional shape (shape of the cross-section vertical to the lower surface 32 a of the frame portion 32 ) of the pin portion 13 e of the frame 31 a has a tapered shape.
  • the dimension of the pin portion 13 e becomes thinner (smaller) as approaching a top end portion 13 g and becomes thicker (larger) as approaching the frame portion 32 .
  • the pin portion 13 e is tapered.
  • the inner wall of the hole portion 15 a of the wiring board 21 c before the pin portion 13 e of the frame 31 a is inserted has no tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21 c .
  • the dimension of the hole portion 15 a before the pin portion 13 e is inserted is made the same as or slightly larger than the dimension of the top end portion 13 g of the pin portion 13 e , and moreover, is made smaller than the dimension of a root portion (portion close to the frame 32 ) of the pin portion 13 e.
  • the pin portion 13 e of the frame 31 a is inserted (plugged) into the hole portion 15 a of the wiring board 21 c , and the pin portion 13 e of the frame 31 a and the wiring board 21 c can be caulked (fixed) by the tapered shape of the pin portion 13 e .
  • the frame 31 a can be fixed to the wiring board 21 c.
  • the pin portion 13 e of the frame 31 a when the pin portion 13 e of the frame 31 a is inserted into the hole portion 15 a of the wiring board 21 c in the step S 5 b , the side wall 13 f of the pin portion 13 e contacts and adheres to the inner wall of the hole portion 15 a of the wiring board 21 c , and the inner wall of the hole portion 15 a of the wiring board 21 c is expanded in the lateral direction by the tapered shape of the side wall 13 f of the pin portion 13 e , and the side wall 13 f of the pin portion 13 e is tightened up by the inner wall of the hole portion 15 a of the wiring board 21 c by its reaction.
  • the pin portion 13 e of the frame 31 a can be caulked (fixed) to the wiring board 21 c , and the frame 31 a can be fixed to the wiring board 21 c.
  • step S 3 b bonding process of the semiconductor chip 5
  • step S 6 b wire bonding process
  • step S 5 b process of fixing the frame 31 a to the wiring board 21 c
  • step S 6 b After the frame 31 a is fixed to the wiring board 21 c in the step S 5 b , as shown in FIGS. 101 and 102 , the wire bonding process is performed, and each electrode 5 d of the semiconductor chip 5 and the connecting terminal 17 formed in the wiring board 21 c corresponding thereto are electrically connected through the bonding wire 6 (step S 6 b ). More specifically, a plurality of connecting terminals 17 of each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 c and a plurality of electrodes 5 a of the semiconductor chip 5 bonded (mounted) on the heat sink 4 c disposed inside the through-hole 3 of the semiconductor device region 22 are electrically connected through a plurality of bonding wires 6 , respectively.
  • the resin sealing by a molding process is performed so as to form a sealing resin 7 a (sealing portion), thereby sealing (resin-sealing) the semiconductor chip 5 and the bonding wire 6 by the sealing resin 7 a (step S 7 b ).
  • the collective sealing for collectively sealing the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c by the sealing resin 7 a is performed in the molding process in the step S 7 b . More specifically, the sealing resin 7 a is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c .
  • the sealing resin 7 a is formed to cover the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c , and the frame 31 a disposed on the upper surface 21 a of the wiring board 21 c is also covered (sealed) with the sealing resin 7 a except for a part of the frame portion 32 .
  • a state in which the upper surface 21 a of the wiring board 21 c is directed upward without turning the wiring board 21 c upside down is preferably maintained until the molding process in the step S 7 b is performed. More specifically, after fixing the frame 31 a to the wiring board 21 c in the step S 5 b , the wiring board 21 c has the upper surface 21 a directed upward so that the lower surface 21 b thereof is not directed upward until the molding process in the step S 7 b is performed. As a result, the falling off of the frame 31 a from the wiring board 21 c before the sealing resin 7 a is formed can be prevented more precisely.
  • the sealing resin 7 a By forming the sealing resin 7 a, the frame 31 a and the wiring board 21 c are solidly bonded by the sealing resin 7 a , and therefore, after forming the sealing resin 7 a , the wiring board 21 c may be directed to any direction (lower surface 21 b of the wiring board 21 c may be directed upward).
  • step S 8 b the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21 c (step S 8 b ). Then, marking is performed as needed and a mark such as a product number and the like is applied on the surface of the sealing resin 7 a (step S 9 b ). Since the connecting process of the solder balls 8 in the step S 8 b and the marking process in the step S 9 b can be performed in the same manner as the connecting process of the solder balls 8 in the step S 8 and the marking process in the step S 9 of the first embodiment, the detailed description thereof will be omitted here.
  • the marking process in the step S 9 b may be performed after the connecting process of the solder balls 8 in the step S 8 b is performed, the connecting process of the solder balls 8 in the step S 8 b may be performed after the marking process in the step S 9 b is performed, or the marking process in the step S 9 b may be omitted if not required.
  • step S 10 b the wiring board 21 c and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22 (step S 10 b ).
  • step S 10 b the wiring board 21 c , the frame 31 a and the sealing resin 7 a are cut along a cutting position (cutting line, dicing line) DL shown by the two-dot chain line in FIG. 103 .
  • the cutting process in the step S 10 b is performed by dicing.
  • the semiconductor device 1 c as shown in FIGS. 106 to 109 is manufactured.
  • the wiring board 21 c cut and separated (divided) into each semiconductor device region corresponds to the wiring board 2 of the semiconductor device 1 c
  • the sealing resin 7 a cut and separated (divided) into each semiconductor device region 22 corresponds to the sealing resin 7 of the semiconductor device 1 c.
  • the sealing resin 7 a is formed in a state in which the frame 31 a is disposed (fixed) on the upper surface 21 a of the wiring board 21 c , when the wiring board 21 c and the sealing resin 7 a formed thereon are cut in the step S 10 b , the frame 31 a is also cut.
  • the wiring board 21 c , the frame 31 a and the sealing resin 7 a thereon are cut so that the frame portion 32 is not contained in the semiconductor device 1 c.
  • an excess region not contained in the semiconductor device region 22 is provided in advance at a side end portion of the wiring board 21 c , so that the frame portion 32 is positioned on this excess region when the frame 31 a is fixed to the wiring board 21 c in the step S 5 b . Then, in the step S 10 b , the excess region of the wiring board 21 c is cut and removed together with the frame portion 32 and the sealing resin 7 a thereon. In this manner, the frame portion 32 is not contained in the semiconductor device 1 c .
  • the pin portion 13 e of the frame 31 a is provided in the frame portion 32 and the hole portion 15 a of the wiring board 21 c is provided in the excess region, the pin portion 13 e and the hole portion 15 a are not contained in the manufactured semiconductor device 1 c.
  • the structure of the manufactured semiconductor device 1 c will be described in relation to the difference from the semiconductor device 1 a of the second embodiment.
  • the heat sink 4 c has almost the same structure as the heat sinks 4 and 4 a of the first and second embodiments except that the protruded portions 11 and 11 a and the pin portion 13 are not formed, the taper (inclination) of the side surface 10 of the heat sink 4 c is eliminated, and the dimension of the heat sink 4 c is made slightly smaller than the dimension of the through-hole 3 of the wiring board 21 (wiring board 2 ).
  • the side surface (side wall) 10 a of the heat sink 4 c disposed inside the through-hole 3 of the wiring board 2 and the inner wall of the through-hole 3 of the wiring board 2 are slightly spaced apart, and a resin material constituting the sealing resin 7 is interposed (for example, with the thickness of about 50 to 100 ⁇ m) between the inner wall of the through-hole 3 of the wiring board 2 and the side surface (side wall) 10 a of the heat sink 4 c .
  • the reason therefor is as follows.
  • the individually segmented heat sinks 4 and 4 a are inserted into each of the plurality of through-holes 3 of the wiring board 21 in the step S 5 .
  • the dimension of these heat sinks 4 and 4 a and the dimension of the through-hole 3 are matched, it is easy to dispose the heat sinks 4 and 4 a inside each through-hole 3 of the wiring board 21 .
  • the side surfaces 10 of the heat sinks 4 and 4 a contact to the inner wall of the through-hole 3 , and it is possible to prevent the resin material from flowing between the side surfaces 10 of the heat sinks 4 and 4 a and the inner wall of the through-hole 3 in the resin sealing process.
  • the heat sink 4 c is not segmented into individual pieces, and the heat sink 4 c is inserted into each of the plurality of through-holes 3 of the wiring board 21 c in a state in which the plurality of heat sinks 4 c are joined by the joining portion 33 a and the frame portion 32 in the step S 5 b .
  • the dimension of the heat sink 4 c and the dimension of the through-hole 3 are matched, it is difficult to insert each of the plurality of heat sinks 4 c joined to each other into the through-hole 3 of the wiring board 21 c .
  • the dimension (planar dimension of the portion inserted into the through-hole 3 ) of the heat sink 4 c is made slightly smaller than the dimension (planar dimension) of the through-hole 3 .
  • the resin material constituting the sealing resin 7 a flows between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c in the molding process in the step S 7 b .
  • the resin material constituting the sealing resin 7 is interposed between the inner wall of the through-hole 3 of the wiring board 21 c (wiring board 2 ) and the side surface (side wall) 10 a of the heat sink 4 c , and therefore, the heat sink 4 c is further firmly fixed. More specifically, in the molding process in the step S 7 b, a part of the sealing resin 7 a is formed between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c.
  • a gap between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c into which the resin material flows is a gap at most equivalent to an air vent of a resin sealing metal mold and is about 50 to 100 ⁇ m, and therefore, the filler of the resin material constituting the sealing resin 7 a does not flow in this gap, but the liquid resin flows therein.
  • the portion of the sealing resin 7 interposed between the inner wall of the though-hole 3 of the wiring board 2 and the side surface (side wall) 10 a of the heat sink 4 c does not contain the filler, but the other portion of the sealing resin 7 (portion on the upper surface 2 a of the wiring board 2 , on the upper surface of the heat sink 4 c and on the semiconductor chip 5 ) contains the filler.
  • a shape of the solder resist layer 19 formed on the lower surface 21 b (that is, the lower surface 2 b of the wiring board 2 ) of the wiring board 21 c is devised as follows.
  • the solder resist layer to expose the connecting terminal 17 and the land 18 is formed on the upper surface 2 a and the lower surface 2 b of the wiring board 2 .
  • the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 is illustrated. Note that, although the solder resist layer is formed also on the upper surface 2 a of the wiring board 2 , the illustration thereof is omitted. Further, in the first and second embodiments, the illustrations of both of the solder resist layer formed on the upper surface 2 a of the wiring board 2 and the solder resist layer formed on the lower surface 2 b are omitted.
  • the solder resist layer 19 is formed in the hatched region in FIG. 109 .
  • a region 20 is a region in which the solder resist layer 19 is not formed on the lower surface 2 b of the wiring board 2 and is a region in which the lower surface of the base material layer (base material layer 16 ) of the wiring board 2 is exposed.
  • the solder resist layer 19 of the lower surface 2 b of the wiring board 2 includes a first solder resist portion 19 a provided to surround the periphery of the through-hole 3 in the vicinity of the through-hole 3 and a second solder resist portion 19 b located on the periphery (outer periphery) of the first solder resist portion 19 a .
  • a region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16 ) of the wiring board 2 is exposed is present.
  • the first solder resist portion 19 a and the second solder resist portion 19 b are isolated with interposing the region 20 therebetween.
  • the plurality of lands 18 provided on the lower surface 2 b of the wiring board 2 are exposed from an opening formed in the second solder resist portion 19 b .
  • the second solder resist portion 19 b has an opening for exposing the land 18 , and a conductive pattern for the land 18 is exposed from this opening.
  • the opening of the solder resistor layer 19 for exposing the land 18 is formed in the second solder resist portion 19 b and is not formed in the first solder resist portion 19 a.
  • the pattern shape of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 has been illustrated and described, but since the wiring board 21 c cut in the step S 10 b becomes the wiring board 2 , the pattern shape of the solder resist layer on the lower surface 21 b of the wiring board 21 c is also the same as the pattern shape of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 .
  • the resin material (mold resin) which flows between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c is likely to overflow to the lower surface 21 b side of the wiring board 21 c .
  • the region (dam region) 20 in which the solder resist layer 19 is not present and the base material layer (base material layer 16 ) of the wiring board 21 is exposed is provided between the first solder resist portion 19 a and the second solder resist portion 19 b , the resin material (mold resin) overflowed to the lower surface 21 b side of the wiring board 21 c from the gap between the through-hole 3 and the heat sink 4 c can be prevented from spreading on the second solder resist portion 19 b over the region 20 .
  • a plurality of heat sinks 4 c are joined by the joining portion 33 a and the frame portion 32 until the cutting process in the step S 10 b is performed, and these heat sinks 4 c are segmented into individual pieces in the step S 10 b . Therefore, in the semiconductor device 1 c , the joining portion 33 a of the frame 31 a is left on the upper surface 2 a of the wiring board 2 and sealed by the sealing resin 7 while being connected to the heat sink 4 c , and a cut surface (end portion) of the joining portion 33 a is exposed on the cut surface (that is, the side surface of the semiconductor device 1 c ) in the step S 10 b .
  • the protruded portions 11 and 11 a of the heat sinks 4 and 4 a prevent the heat sinks 4 and 4 a from falling off from the through-hole 3 of the wiring board 21 , whereas the joining portion 33 a has this function in the present embodiment. Consequently, in the semiconductor device 1 c , the joining portion 33 a integrally connected to the heat sink 4 c has the same structure as the protruded portion 11 a of the second embodiment except that the pin portion 13 is not formed and the joining portion 33 a extends on the upper surface 2 a of the wiring board 2 until reaching the side surface of the semiconductor device 1 c .
  • the heat sink 4 c is integrally provided with the joining portion 33 a which is a protruded portion protruding to the outside (in the direction away from the center of the upper surface 9 a ) of the side surface 10 of the heat sink 4 c in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 c , and this joining portion 33 a is positioned (extended) on the upper surface 2 a of the wiring board 2 outside the through-hole 3 .
  • the heat sink 4 c is integrally provided with the joining portion 33 a , which protrudes to the upper surface 2 a side of the wiring board 2 from the through-hole 3 and extends on the upper surface 2 a of the wiring board 2 (extends until reaching the side surface of the wiring board 2 ), on the peripheral edge portion of the upper surface 9 a of the heat sink 4 c , and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 .
  • FIGS. 110 and 111 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 a to the wiring board 21 c by using the bonding agent, and they correspond to FIGS. 99 and 100 , respectively.
  • the pin portion 13 e is not provided in the frame 31 a
  • the hole portion 15 a is not provided in the wiring board 21 c .
  • a bonding agent 51 is coated (disposed) in advance on the upper surface 21 a of the wiring board 21 c , and then, the frame 31 a is disposed on the upper surface 21 a of the wiring board 21 c so that the frame portion 32 of the frame 31 a is positioned on the bonding agent.
  • each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c from the upper surface 21 a side of the wiring board 21 c .
  • the bonding agent 51 is coated at the position on the upper surface 21 a of the wiring board 21 c on which the frame portion 32 overlaps when each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c .
  • the lower surface 32 a of the frame portion 32 of the frame 31 a is bonded to the upper surface 21 a of the wiring board 21 c through the bonding agent 51 , so that the frame 31 a is fixed to the wiring board 21 c .
  • a film type bonding agent such as a DAF (die attach film) can be also used.
  • the pin portion 13 e and the hole portion 15 a are provided in the region not contained later in the semiconductor device 1 c .
  • the pin portion 13 e and the hole portion 15 a can be provided in the region contained later inside the semiconductor device 1 c , and the manufacturing process in this case will be described with reference to FIGS. 112 to 124 .
  • FIG. 112 is an upper surface view (plan view) of the frame 31 b used in another manufacturing process of the present embodiment
  • FIG. 113 is a lower surface view (plan view) of the frame 31 b of FIG. 112
  • FIGS. 114 and 115 are cross-sectional views of the frame 31 b of FIG. 112 .
  • the cross-section cut along the line A 19 -A 19 of FIG. 112 corresponds to FIG. 114
  • the cross-section cut along the line A 20 -A 20 of FIG. 112 corresponds to FIG. 115 .
  • FIG. 116 is an upper surface view (plan view) of the wiring board 21 d used in another manufacturing process of the present embodiment, and it corresponds to FIG. 93 .
  • FIGS. 120 and 121 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the pin portion 13 e of the frame 31 b
  • FIGS. 122 and 123 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the bonding agent 51 .
  • FIG. 124 is a plan view (upper surface view) showing a state in which the sealing resin 7 a is formed in another manufacturing process of the present embodiment, and it shows a planar region corresponding to FIG. 117 . Also, although FIG. 124 is a plan view, hatching is applied to the sealing resin 7 a for easy understanding, and an outer shape of the frame 31 b located below the sealing resin 7 a is shown by a dotted line. Further, a cutting position (cutting line, dicing line) DL of the cutting process in the step S 10 b is shown by the two-dot chain line in FIG. 124 .
  • the frame 31 b in which a plurality of heat sinks 4 c are joined as shown in FIGS. 112 to 115 is prepared in the step S 2 b .
  • the frame 31 b has the same structure as the frame 31 a used in the manufacturing process described with reference to FIGS. 86 to 105 except that a wide portion (island portion) 33 b is provided in the joining portion 33 a and the pin portion 13 e is provided on the lower surface of the wide portion 33 b instead of the lower surface of the frame portion 32 .
  • the material of the frame 31 b is the same as those of the frames 31 and 31 a.
  • the wide portion 33 b is provided in the midst of the joining portion 33 a and is a portion in which the width of the joining portion 33 a is locally widened. Consequently, the wide portion 33 b can be also taken as a part of the joining portion 33 a , and in the joining portion 33 a , the width of the wide portion 33 b is larger than the width of the region other than the wide portion 33 b , and the pin portion 13 e is integrally formed on the lower surface of this wide portion 33 b .
  • the wide portion 33 b and the pin portion 13 e may be provided for at least one of the plurality (four in this case) of the joining portions 33 a joined to each heat sink 4 c .
  • the frame 31 a and the frame 31 b are different in the position of the pin portion 13 e , since the shape of the pin portion 13 e is the same, the description thereof will be omitted here.
  • the wiring board 21 d for the manufacture of the semiconductor device is prepared.
  • the wiring board 21 d has the same structure as the wiring board 21 c used in the manufacturing process described with reference to FIGS. 86 to 105 except that the position of the hole portion 15 a is different. More specifically, as a result of the change of the position of the pin portion 13 e between the frame 31 a and the frame portion 31 b , the position of the hole portion 15 a is also changed between the wiring board 21 c and the wiring board 21 d .
  • the hole portion 15 a is formed in an excess region outside the semiconductor device region 22 (region not contained in the semiconductor device 1 c in the cutting process in the step S 10 b ) in the wiring board 21 c
  • the hole portion 15 a is formed inside each semiconductor device region 22 in the wiring board 21 d .
  • the wiring board 21 c and the wiring board 21 d are different in the position of the hole portion 15 a .
  • the shape of the hole portion 15 a is the same, the description thereof will be omitted here.
  • the semiconductor chip 5 is bonded on the upper surface 9 a of each heat sink 4 c of the frame 31 b through the bonding agent 14 in the step S 3 b .
  • This process is the same as the manufacturing process described with reference to FIGS. 86 to 105 .
  • FIGS. 117 to 119 show a state in which the frame 31 b is fixed to the wiring board 21 d.
  • the frame 31 b is fixed to the wiring board 21 d in the step S 5 b , but this process is the same as the manufacturing process described with reference to FIGS. 86 to 105 except for the positions of the pin portion 13 e and the hole portion 15 a for fixing the frame 31 b and the wiring board 21 d.
  • the frame 31 b is positioned and disposed on the upper surface 21 a of the wiring board 21 d and each heat sink 4 c of the frame 31 b is inserted (plugged) into each through-hole 3 of the wiring board 21 d from the upper surface 21 a side of the wiring board 21 d , and at the same time, each pin portion 13 e of the frame 31 b is inserted (plugged) into each hole portion 15 a of the wiring board 21 d . Since the frame portion 32 and the joining portion 33 a are overlapped with the upper surface 21 a of the wiring board 21 d , the heat sink 4 c does not fall off downward from the through-hole 3 of the wiring board 21 d .
  • the through-hole 3 and the hole portion 15 a of the wiring board 21 d are located at the position at which each pin portion 13 e of the frame 31 b is inserted into each hole portion 15 a of the wiring board 21 d when each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d.
  • a principle of fixing the frame 31 b to the wiring board 21 d is the same as the case where the frame 31 a is fixed to the wiring board 21 c . More specifically, as shown in FIG. 120 , the pin portion 13 e provided on the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 b is also tapered, and in the step S 5 b , as shown in FIGS. 120 and 121 , the pin portion 13 e of the frame 31 b is inserted (pushed) into the hole portion 15 a of the wiring board 21 d , and the pin portion 13 e of the frame 31 b and the wiring board 21 d can be caulked (fixed) by the tapered shape of the pin portion 13 e . By this means, the frame 31 b is fixed to the wiring board 21 d.
  • FIGS. 122 and 123 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the bonding agent.
  • the bonding agent 51 is coated (disposed) in advance on the upper surface 21 a of the wiring board 21 d , and then, the frame 31 b is disposed on the upper surface 21 a of the wiring board 21 d so that the wide portion 33 b of the joining portion 33 a of the frame 31 b is positioned on the bonding agent 51 .
  • each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d from the upper surface 21 a side of the wiring board 21 d .
  • the bonding agent 51 is coated at the position on the upper surface 21 a of the wiring board 21 d on which the wide portion 33 b of the joining portion 33 a of the frame 31 b overlaps when each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d .
  • the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 b is bonded to the upper surface 21 a of the wiring board 21 d through the bonding agent 51 , so that the frame 31 b is fixed to the wiring board 21 d.
  • the subsequent process is the same as the manufacturing process described with reference to FIGS. 86 to 105 . More specifically, the wire bonding process in the step S 6 b , the molding process in the step S 7 b , the solder ball 8 connecting process in the step S 8 b , the marking process in the step S 9 b , and the cutting process in the step S 10 b are performed.
  • the wiring board 21 d , the frame 31 b and the sealing resin 7 a are cut along the cutting position (cutting line, dicing line) DL shown by the two-dot chain line in FIG. 124 .
  • the pin portion 13 e and the hole portion 15 a are provided in the region (excess region) not contained later inside the semiconductor device 1 c in the frame 31 a and the wiring board 21 c , but in this case, the pin portion 13 e and the hole portion 15 a are provided in the region (semiconductor device region 22 ) contained later inside the semiconductor device 1 c in the frame 31 b and the wiring board 21 d . Therefore, as evident from FIG. 124 and FIGS. 125 and 126 to be described later, the wide portion 33 b , the pin portion 13 e and the hole portion 15 a are contained in the manufactured semiconductor device 1 c.
  • FIGS. 125 and 126 are a cross-sectional view and an upper surface perspective view (seen through the sealing resin 7 ) of the semiconductor device 1 c manufactured by the manufacturing process described with reference to FIGS. 112 to 124 , and they almost correspond to FIGS. 107 and 108 , respectively.
  • the semiconductor device 1 c of FIGS. 125 and 126 manufactured by the manufacturing process described with reference to FIGS. 112 to 124 is different from the semiconductor device 1 c of FIGS. 106 to 108 manufactured by the manufacturing process described with reference to FIGS. 86 to 105 in the following points. That is, in the semiconductor device of FIGS.
  • the hole portion 15 a is present in the wiring board 2
  • the wide portion 33 b is present in the joining portion 33 a
  • the pin portion 13 e integrally formed on the lower surface of the wide portion 33 b is inserted (disposed) inside the hole portion 15 a of the wiring board 2 .
  • the wide portion 33 b is present in the joining portion 33 a in the semiconductor device of FIGS.
  • the hole portion 15 a is not present in the wiring board 2 , and the wide portion 33 b and the upper surface 2 a of the wiring board 2 are bonded through the bonding agent 51 . Further, in the wiring board 2 (that is, the wiring board 21 d ) of the semiconductor device of FIGS. 125 and 126 , the hole portion 15 a is disposed in such a manner to stay away from the connecting terminal 17 and the land 18 .
  • the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted it is preferable to increase the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted, but the weight of the heat sink 4 c increases as the thickness increases.
  • the plurality of heat sinks 4 c mutually joined are inserted into the through-holes 3 from the upper surface 21 a side of the wiring boards 21 c and 21 d , respectively, and the joining portion 33 a is located on the upper surface 21 a of the wiring boards 21 c and 21 d and the lower surface of the joining portion 33 a contacts to the upper surface 21 a of the wiring boards 21 c and 21 d , so that the joining portion 33 a supports the weight of the heat sink 4 c .
  • the thickness of the heat sink 4 c (thickness t 1 ) can be increased and preferably made larger than the thickness of the wiring boards 21 c and 21 d (that is, the thickness t 2 of the wiring board 2 ), so that the heat dissipation properties of the semiconductor device can be improved.
  • the heat sink 4 c is not segmented into individual pieces, and the frames 31 a and 31 b and the wiring boards 21 c and 21 d are integrally resin-sealed in the step S 7 b , and then, the sealing body is segmented into individual pieces by the cutting process in the step S 10 b . Therefore, as compared with the first and second embodiments, the cutting process (process corresponding to step S 4 ) for the segmentation into individual pieces of the heat sink 4 c can be omitted, and the manufacturing process can be simplified.
  • a process conveyance form can be made into a frame 31 a (or frame 31 b ) support type. Therefore, regardless of the thickness of the wiring board 21 c (or the wiring board 21 d ), it can be adapted to the case where the groove of a process conveyance system is constant. Further, the frame 31 a (or frame 31 b ) retaining the heavy heat sink 4 c is made as a conveyance system support, thereby preventing the falling off of the heat sink 4 c more surely.
  • the bonding portion (bonding portion through the pin portion 13 e or the bonding agent 51 ) between the joining portion 33 a and the wiring board 21 d remains inside the manufactured semiconductor device 1 c , and therefore, also in the manufactured semiconductor device 1 c , the supporting (retaining, fixing) of the heavy heat sink 4 c can be strengthened without committing the bonding and supporting of the heat sink 4 c and the wiring board 2 to only the curing fixation of the sealing resin 7 .
  • the frame 31 b in which a plurality of heat sinks 4 c are joined and the multiply-connected wiring board are fixed to manufacture the semiconductor devices.
  • individually segmented wiring boards 2 f are fixed to a frame 31 c in which a plurality of heat sinks 4 c are joined, thereby manufacturing the semiconductor devices.
  • FIG. 127 is a process flowchart showing a manufacturing process of the semiconductor device of the present embodiment.
  • FIG. 128 is an upper surface view (plan view) of the frame 31 c used for the manufacture of the semiconductor device of the present embodiment
  • FIG. 129 is an lower surface view (plan view) of the frame 31 c
  • FIG. 130 is a cross-sectional view of the frame 31 c .
  • the cross-section cut along the line A 21 -A 21 of FIGS. 128 and 129 corresponds to FIG. 130 .
  • FIG. 128 is a plan view, hatching is applied to the frame 31 c so as to make a shape of the frame 31 c easily understood. Further, FIGS.
  • FIGS. 134 to 136 are plan views (upper surface view and lower surface view) and a cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 134 which is the upper surface view shows the planar region corresponding to FIGS. 128 and 131 , FIG.
  • FIGS. 137 to 140 are explanatory drawings (cross-sectional views) for explaining a technique for fixing the wiring board 2 f to the frame 31 c .
  • FIGS. 141 to 145 are plan views (upper surface view and lower surface view) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment.
  • FIG. 141 is a cross-sectional view and shows the cross-section corresponding to FIG. 136 .
  • FIG. 142 which is the upper surface view
  • FIG. 143 which is the lower surface view
  • FIG. 144 which is the cross-sectional view show the same process stage (process stage after FIG. 141 ), and FIG. 142 shows the same planar region as FIG. 134 , FIG. 143 shows the same planar region as FIG. 135 , and FIG. 144 shows the cross-section corresponding to FIGS. 136 and 141 .
  • FIG. 142 an outer shape of the frame 31 c located below the sealing resin 7 is shown by a dotted line for easy understanding.
  • FIG. 145 is a cross-sectional view of the process stage after FIG. 144 and shows the cross-section corresponding to FIG. 144 .
  • the frame 31 c in which a plurality of heat sinks 4 c are joined is prepared (step S 2 c ).
  • the structure of the frame 31 c is almost the same as the frame 31 b of the fourth embodiment expect the following points. That is, in the frame 31 c , a joining portion 34 for mutually joining the frame portions 32 is provided to reinforce the frame 31 c . Further, in the frame 31 c , the wide portion (island portion) 33 b similar to that of the frame 31 b is provided for each joining portion 33 a for joining the heat sink 4 c and the frame portion 32 . Further, in the frame 31 c , the pin portion 13 e is not provided on the lower surface of the wide portion 33 b . Except for these, the frame 31 c has the same structure as the frame 31 b of the fourth embodiment, and the material of the frame 31 c is also the same as the frames 31 , 31 a and 31 b.
  • the frame 31 c has a structure in which a plurality of unit regions (unit frame region, semiconductor region) 23 are disposed (joined) in a row.
  • This unit region 23 is a region used for manufacturing one semiconductor device (semiconductor device 1 e to be described later) and has one heat sink 4 c and four joining portions 33 a joined to the heat sink 4 c.
  • the wide portion 33 b may be provided for at least one of the plurality (four in this case) of the joining portions 33 a joined to each heat sink 4 c .
  • the wide portion 33 b may be provided for two joining portions located in a diagonal direction with interposing the heat sink 4 c therebetween of the four joining portions 33 a connected to each heat sink 4 c .
  • step S 3 c the bonding process of the semiconductor chip 5 in the step S 3 c can be performed in the same manner as the bonding process of the semiconductor chip 5 in the step S 3 , the detailed description thereof will be omitted here.
  • the wiring board 2 f is prepared (step S 1 c ). Although this wiring board 2 f almost corresponds to the one obtained by separating the wiring board 21 d used in the fourth embodiment into the semiconductor device region 22 , the hole portion 15 a is not formed in the wiring board 2 f . More specifically, this wiring board 2 f is not the multiply-connected wiring board, and one semiconductor device is manufactured from one wiring board 2 f .
  • the wiring board 2 f has the same structure as the wiring board 2 in the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment except for the shape of the solder resist layer 19 to be described later.
  • the through-hole 3 is formed in the wiring board 2 f , a plurality of connecting terminals 17 and the wirings connected thereto are formed on the upper surface 2 a of the wiring board 2 f , and a plurality of lands 18 are formed on the lower surface 2 b of the wiring board 2 f.
  • step S 5 c the wiring board 2 f is fixed to the frame 31 c (step S 5 c ).
  • step S 5 c it is necessary to prepare the wiring board 2 f in the step S 1 c . Therefore, the preparation of the wiring board 2 f in the step S 1 c can be performed before the step S 2 c , simultaneously with the step S 2 c, before the step S 3 c and after the step S 2 c , simultaneously with the step S 3 c or before the step S 5 c and after the step S 3 c.
  • the multiply-connected wiring boards 21 c and 21 d are fixed to the multiply-connected frames 31 a and 31 b in the fourth embodiment, but in the present embodiment, a plurality of wiring boards 2 f are fixed to the frame 31 c in which a plurality of heat sinks 4 c are joined in the step S 5 c .
  • the wiring board 2 f is fixed to each of the plurality of unit regions 23 of the frame 31 c.
  • the plurality of wiring boards 2 f are disposed side by side and the frame 31 c is positioned and disposed thereon, so that each heat sink 4 c of the frame 31 c is inserted (plugged) into each through-hole 3 of the wiring board 2 f from the upper surface 2 a side of the wiring board 2 f , and at the same time, the wiring board 2 f is fixed to the frame 31 c.
  • FIGS. 137 and 138 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 c to the wiring board 2 f by using the bonding agent.
  • step S 5 c before the heat sink 4 c of the frame 31 c is interested into the through-hole 3 of the wiring board 2 f , as shown in FIG. 137 , the bonding agent 51 is coated (disposed) in advance on the upper surface 2 a of the wiring board 2 f , and then, the frame 31 c is disposed on the upper surface 2 a of the wiring board 2 f so that the wide portion 33 b of the joining portion 33 a of the frame 31 c is positioned on the bonding agent 51 . At this time, each heat sink 4 c of the frame 31 c is inserted into each through-hole 3 of the plurality of wiring boards 2 f from the upper surface 2 a side of the wiring board 2 f .
  • the bonding agent 51 is coated at the position on the upper surface 2 a of each wiring board 21 f on which the wide portion 33 b of the joining portion 33 a of the frame 31 c overlaps when each heat sink 4 c of the frame 31 c is inserted into the through-hole 3 of each wiring board 21 f .
  • each heat sink 4 c of the frame 31 c is inserted into the through-hole 3 of each wiring board 2 f from the upper surface 2 a side of the wiring board 2 f , and at the same time, as shown in FIG.
  • the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 is bonded to the upper surface 2 a of the wiring board 2 f through the bonding agent 51 , so that the wiring board 2 f is fixed to the frame 31 c .
  • the bonding agent 51 a film type bonding agent such as a DAF (die attach film) can be also used.
  • each heat sink 4 c in the frame 31 c has the joining portion 33 a protruding to the outside (in the direction away from the center of the upper surface 9 a ) from the side surface of each heat sink 4 c in the peripheral edge portion of the upper surface 9 a of each heat sink 4 c , and in the step S 5 c , each heat sink 4 c is disposed inside the through-hole 3 of the wiring board 2 f so that this joining portion 33 a is located on the upper surface 2 a of the wiring board 2 f outside the through-hole 3 and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 f.
  • FIGS. 139 and 140 are the explanatory drawings thereof (cross-sectional views). This principle is the same as the technique described with reference to FIGS. 120 and 121 in the fourth embodiment.
  • the pin portion 13 e is formed in advance on the lower surface of the wide portion 33 b also in the frame 31 c , and the hole portion 15 a is formed in advance in the wiring board 2 f .
  • the pin portion 13 e pin portion 13 e having a tapered shape
  • the pin portion 13 e is inserted (pushed) into the hole portion 15 a of the wiring board 2 f as shown in FIG.
  • the frame 31 c and the wiring board 2 f can be caulked (fixed) by the tapered shape of the pin portion 13 e .
  • the frame 31 c and the wiring board 2 f are fixed.
  • step S 3 c bonding process of the semiconductor chip 5
  • step S 5 c process of fixing the frame 31 c and the wiring board 2 f
  • step S 6 c wire bonding process
  • step S 6 c After the plurality of wiring boards 2 f are fixed to the frame 31 c in the step S 5 c , as shown in FIG. 141 , a wire bonding process is performed, so that each electrode 5 a of the semiconductor chip 5 and the connecting terminal 17 formed on the wiring board 2 f corresponding to the electrode 5 a are electrically connected through the bonding wire 6 (step S 6 c ). More specifically, the plurality of connecting terminals 17 on the upper surface 21 a of each wiring board 2 f and the plurality of electrodes 5 a of the semiconductor chip 5 bonded (mounted) on the heat sink 4 c disposed inside the through-hole 3 of the wiring board 2 f are electrically connected through the plurality of bonding wires 6 , respectively.
  • the resin sealing by the molding process (for example, the transfer-molding process) is performed to form the sealing resin 7 (sealing portion), and the semiconductor chip 5 and the bonding wire 6 are sealed (resin-sealed) by the sealing resin 7 (step S 7 c ).
  • the individual sealing for individually sealing each unit region 23 of the frame 31 c by the sealing resin 7 is performed. More specifically, in each unit region 23 of the frame 31 c , the sealing resin 7 is formed on the upper surface 2 a of the wiring board 2 f so as to cover the semiconductor chip 5 and the bonding wire 6 . In this case, the sealing resin 7 is formed for each unit region 23 of the frame 31 c , and is not integrally formed for the adjacent unit regions 23 .
  • the sealing resin 7 is made of, for example, a resin material such as a thermosetting resin material and can contain the filler and the like.
  • the sealing resin 7 can be formed by using the epoxy resin and the like containing the filler.
  • the sealing resin material is injected into a cavity of the metal mold in which the frame 31 c to which the wiring board 2 f is fixed is disposed, and this sealing resin material is hardened by heating, so that the sealing resin 7 can be formed.
  • the sealing resin 7 is formed so as to cover not only the upper surface 2 a of the wiring board 2 f but also the side surface of the wiring board 2 f . Further, the sealing resin 7 is formed so that the frame portion 32 of the frame 31 is located outside the sealing resin 7 .
  • a state in which the upper surface 2 a of the wiring board 2 f is directed upward without turning the frame 31 c upside down is preferably maintained until the molding process in the step S 7 c is performed. More specifically, after fixing the frame 31 c to the plurality of wiring boards 2 f in the step S 5 c , the wiring board 2 f has the upper surface 2 a directed upward (that is, the upper surface of the frame 31 c is also directed upward) so that the lower surface 2 b thereof is not directed upward until the molding process in the step S 7 c is performed.
  • the falling off of the frame 31 c from the wiring board 2 f before the sealing resin 7 is formed can be prevented more precisely.
  • the frame 31 c and the wiring board 2 f are solidly bonded by the sealing resin 7 , and therefore, after forming the sealing resin 7 , the wiring board 2 f may be directed to any direction (lower surface 2 b of the wiring board 2 f may be directed upward).
  • step S 8 c the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 2 b of each wiring board 2 f (step S 8 c ). Then, marking is performed as needed, and a mark such as a product number and the like is applied onto the front surface of the sealing resin 7 (step S 9 c ). Since the connecting process of the solder ball 8 in the step S 8 c and the marking process in the step S 9 c can be performed in the same manner as the connecting process of the solder ball 8 in the step S 8 and the marking process in the step S 9 of the first embodiment, the detailed description thereof will be omitted here.
  • the marking process in the step S 9 c may be performed after the connecting process of the solder ball 8 in the step S 8 c is performed, or the connecting process of the solder ball 8 in the step S 8 c may be performed after the marking process in the step S 9 c is performed. Alternatively, if not needed, the marking process in the step S 9 c may be omitted.
  • step S 10 c the frame 31 c is cut. More specifically, the portion protruding from the side surface of the sealing resin 7 of the frame 31 c is cut and removed.
  • FIGS. 146 and 147 are explanatory drawings (cross-sectional views) of the cutting process of the frame 31 c
  • FIG. 146 is a cross-sectional view showing the state before the cutting process in the step S 10 c
  • FIG. 147 is a cross-sectional view showing the state after the cutting process in the step S 10 c, in which the cross-sections along the joining portion 33 a of the frame 31 c are illustrated.
  • the sealing bodies 24 structure sealing the wiring board 5 , the heat sink 4 and the semiconductor chip 5 by the sealing resin 7 ) of the adjacent unit regions 23 are joined by a part of the frame 31 c (joining portion 33 a and frame portion 32 ).
  • the frame 31 c outside the sealing body 24 portion of the joining portion 33 a not sealed by the sealing resin 7 , the frame portion 32 and the jointing portion 34 ) is cut and removed.
  • the individually segmented sealing body 24 as shown in FIG. 147 that is, the semiconductor device 1 e is obtained (manufactured).
  • the semiconductor device 1 e of the present embodiment is manufactured.
  • FIGS. 148 and 149 are cross-sectional views (side cross-sectional views) of the semiconductor device 1 e of the present embodiment
  • FIG. 150 is a perspective plan view (upper surface view) of the semiconductor device 1 e when the sealing resin 7 is seen through.
  • FIG. 151 is a lower surface view of the wiring board 2 f used in the semiconductor device 1 e of the present embodiment.
  • FIGS. 148 to 150 correspond to FIGS. 106 to 109 of the fourth embodiment, respectively.
  • the cross-section cut along the line A 22 -A 22 of FIG. 150 almost corresponds to FIG. 148
  • the cross-section cut along the line A 23 -A 23 of FIG. 150 almost corresponds to FIG. 149 .
  • FIG. 151 is plan view, hatching is applied to the solder resist layer 19 so that the planar shape (pattern) of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 f is easily understood.
  • a structure of the semiconductor device 1 e will be described in relation to the difference from the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment.
  • the wide portion 33 is present in the joining portion 33 a , and the lower surface of the wide portion 33 b is bonded to the upper surface 2 a of the wiring board 2 f through the bonding agent 51 (illustration thereof is omitted in FIG. 149 ). Further, the sealing resin 7 is formed so as to cover not only the upper surface 2 a of the wiring board 2 f but also a side surface 55 of the wiring board 2 f .
  • the side surface of the wiring board 2 and the side surface of the sealing resin 7 are flush with each other, and the joining portion 33 a connected to the heat sink 4 c extends on the upper surface 2 a of the wiring board 2 until reaching the side surface of the sealing resin 7 .
  • the joining portion 33 a connected to the heat sink 4 c extends on the upper surface 2 a of the wiring board 2 f , and further extends in the sealing resin 7 over an end portion of the upper surface 2 a of the wiring board 2 f until reaching the side surface of the sealing resin 7 .
  • the frame 31 c and the wiring board 2 f are fixed by a technique described with reference to FIGS. 139 and 140 , the hole portion 15 a is formed in the wiring board 2 f like in FIG.
  • a shape of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f is devised as follows. Except for this, the structure of the semiconductor device 1 e of the present embodiment is the same as the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment, and therefore, the description thereof will be omitted here.
  • solder resist layer 19 on the lower surface 2 b of the wiring board 2 f will be described with reference to FIG. 151 .
  • the solder resist layer exposing the connecting terminal 17 and the land 18 is formed on the upper surface 2 a and the lower surface 2 b of the wiring board 2 f , hereinafter, an illustration and a description of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f will be made, whereas an illustration and a description of the solder resist layer formed on the upper surface 2 a of the wiring board 2 f will be omitted.
  • the sealing resin 7 not only the upper surface 2 a of the wiring board 2 f but also the side surface 55 of the wiring board 2 f is covered by the sealing resin 7 , and therefore, a gap is present between the side surface 55 of the wiring board 2 f and a metal mold in the molding process in the step S 7 c .
  • the resin material invades between the metal mold and the lower surface 2 b of the wiring board 2 f , and a resin burr is formed on the lower surface 2 b of the wiring board 2 f , so that the resin is easily adhered to the land 18 . Therefore, the shape of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f is made as shown in FIG. 151 .
  • the solder resist layer 19 is formed in the hatched region in FIG. 151 .
  • the region 20 is a region in which the solder resist layer 19 is not formed on the lower surface 2 b of the wiring board 2 f , and is a region in which the lower surface of the base material layer (base material layer 16 ) of the wiring board 2 f is exposed.
  • the solder resist layer 19 is formed on the lower surface 2 b of the wiring board 2 f .
  • the solder resist layer 19 of the lower surface 2 b of the wiring board 2 f includes a first solder resist portion 19 a provided in the vicinity of the through-hole 3 so as to surround the periphery of the through-hole 3 , a second solder resist portion 19 b located in the periphery (outer periphery) of the first solder resist portion 19 a , and a third solder resist portion 19 c located further in the periphery (outer periphery) of the second solder resist portion 19 b .
  • the first solder resist portion 19 a is formed in the periphery of the through-hole 3
  • the third solder resist portion 19 c is formed in the peripheral edge portion of the lower surface 2 b of the wiring board 2 f
  • the second solder resist portion 19 b is formed between the first solder resist portion 19 a and the third solder resist portion 19 c.
  • first solder resist portion 19 a and the second solder resist portion 19 b there is the region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16 ) of the wiring board 2 f is exposed. Consequently, the first solder resist portion 19 a and the second solder resist portion 19 b are isolated with interposing the region 20 therebetween. Further, between the second solder resist portion 19 b and the third solder resist portion 19 c , there is the region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16 ) of the wiring board 2 f is exposed. Consequently, the second solder resist portion 19 b and the third solder resist portion 19 c are isolated with interposing the region 20 therebetween.
  • the plurality of lands 18 provided on the lower surface 2 b of the wiring board 2 f are exposed from the openings formed in the second solder resist portion 19 b .
  • the second solder resist portion 19 b has the openings for exposing the lands 18 , and a conductive pattern for the land 18 is exposed from the opening.
  • the opening of the solder resist layer 19 for exposing the land 18 is formed in the second solder resist portion 19 b , and is not formed in the first solder resist portion 19 a and the third solder resist portion 19 c.
  • the resin material (mold resin) flowing between the inner wall of the through-hole 3 of the wiring board 2 f and the side surface (side wall) 10 a of the heat sink 4 c is likely to overflow to the lower surface 2 b side of the wiring board 2 f .
  • the region (dam region) 20 in which no solder resist layer 19 is present and the base material layer (base material layer 16 ) of the wiring board 2 f is exposed is provided between the first solder resist portion 19 a and the second solder resist portion 19 b , so that the resin material (mold resin) overflowing to the lower surface 2 b side of the wiring board 2 f from the gap between the through-hole 3 and the heat sink 4 c can be prevented from spreading up to the second solder resist portion 19 b over the region 20 .
  • the resin material is likely to invade between the metal mold and the lower surface 2 b of the wiring 2 f in the molding process in the step S 7 c.
  • the region (dam region) 20 in which no solder resist layer 19 is present and the base material layer (base material layer 16 ) of the wiring board 2 f is exposed is provided between the third solder resist portion 19 c and the second solder resist portion 19 b .
  • the resin material intending to invade between the metal mold and the lower surface 2 b of the wiring board 2 f from an external end portion (lower end of the side surface 55 ) of the lower surface 2 b of the wiring board 2 f can be prevented from spreading up to the second solder resist portion 19 b over the region 20 between the third solder resist portion 19 c and the second solder resist portion 19 b.
  • the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted it is preferable to increase the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted, but the weight of the heat sink 4 c increases as the thickness increases.
  • the plurality of heat sinks 4 c mutually joined are inserted into the through-holes 3 of the wiring boards 2 f from the upper surface 2 a side of the wiring board 2 f , respectively, and the joining portion 33 a is located on the upper surface 2 a of each wiring board 2 f and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 f , so that the joining portion 33 a supports the weight of the heat sink 4 c .
  • the thickness of the heat sink 4 c (thickness t 1 ) can be increased and preferably made larger than the thickness of the wiring board 2 f (that is, the thickness t 2 of the wiring board 2 ), so that the heat dissipation properties of the semiconductor device can be improved.
  • the individually segmented (individualized) wiring board 2 f is used in the fifth embodiment, it is possible to use only the non-defective wiring board 2 f .
  • the plurality of unit board regions constituting the multiply-connected wiring board are not always constituted of only the non-defective products, and the case where the unit board region having a defect is present in the plurality of unit board regions constituting the multiply-connected wiring board occurs frequently.
  • the semiconductor device when the semiconductor device is manufactured by using the multiply-connected wiring board, a series of processing must be performed for the plurality of unit board regions including the unit board region having a defect, and the semiconductor device manufactured from the unit board region having a defect has to be eliminated after the manufacture of the semiconductor devices, so that the processing materials are wasted.
  • the wiring board having a defect is removed in advance and only the wiring board 2 f having no defect can be attached to the frame 31 c in which the plurality of heat sinks 4 c are joined, so that the processing material can be efficiently used.
  • the bonding portion (bonding portion through the pin portion 13 e or the bonding agent 51 ) between the joining portion 33 a and the wiring board 2 f remains inside the manufactured semiconductor device 1 e like in the manufacturing process and the structure shown in FIGS. 112 to 126 of the fourth embodiment.
  • the support (retaining, fixing) of the heavy heat sink 4 c can be strengthened without committing the bonding and supporting of the heat sink 4 c and the wiring board 2 f to only the curing fixation of the sealing resin 7 .
  • FIG. 152 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 f of the sixth embodiment, and it corresponds to FIG. 1 of the first embodiment.
  • the semiconductor device 1 f of the present embodiment has almost the same structure as the semiconductor device 1 of the first embodiment except that a heat sink (Heat Spreader) 61 is mounted on a front surface 5 b of the semiconductor chip 5 through a bonding agent 62 and an upper surface 61 a of the heat sink 61 is exposed from an upper surface 7 b of the sealing resin 7 , and therefore, the description thereof will be omitted and the difference from the semiconductor device 1 of the first embodiment will be mainly described.
  • a heat sink (Heat Spreader) 61 is mounted on a front surface 5 b of the semiconductor chip 5 through a bonding agent 62 and an upper surface 61 a of the heat sink 61 is exposed from an upper surface 7 b of the sealing resin 7 , and therefore, the description thereof will be omitted and the difference from the semiconductor device 1 of the first embodiment will be mainly described.
  • the heat sink 61 is mounted (disposed, bonded) on the front surface 5 b of the semiconductor chip 5 mounted (disposed) on the heat sink 4 through the bonding agent (adhering material) 62 .
  • the semiconductor chip 5 is vertically sandwiched between the heat sink 61 and the heat sink 4 .
  • the heat sink 61 is disposed on an inner region with respect to the electrode 5 a on the front surface 5 b of the semiconductor chip 5 so that the heat sink 61 does not contact to the electrode 5 a of the semiconductor chip 5 and the bonding wire 6 .
  • the planar shape of the heat sink 61 can be made into a rectangular shape smaller than the semiconductor chip 5 .
  • the bonding agent 62 a bonding agent having high heat conductivity is preferably used, and for example, solder and a conductive paste material (the paste material preferable as a conductive paste material is silver paste) and the like can be used.
  • the upper surface 61 a of the heat sink 61 is exposed from the upper surface 7 b of the sealing resin 7 , and this upper surface 61 a is a surface (main surface) opposite to the side opposing to the front surface 5 b of the semiconductor chip 5 .
  • the heat sink 61 is a member for dissipating the heat generated in the semiconductor chip 5 and preferably has high heat conductivity, and it is necessary that the heat conductivity (heat conductivity coefficient) of the heat sink is higher than at least the heat conductivity (heat conductivity coefficient) of the sealing resin 7 . Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat sink 61 is preferably made of a conductive material and is more preferably formed of a metal material. It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 61 because high heat conductivity of the heat sink 61 can be obtained and the processing thereof (formation of the heat sink 61 ) is easy.
  • a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 61 because high heat conductivity of the heat sink 61 can be obtained and the processing thereof (formation of the heat sink 61 ) is easy
  • the heat sink 61 is made of the same material as the heat sink 4 , and by this means, the heat sink 61 and the heat sink 4 sandwiching the semiconductor chip 5 come to have the same heat expansion coefficient. Thus, the heat stress acting on the semiconductor chip 5 can be reduced, so that the reliability of the semiconductor device can be more improved. Therefore, it is most preferable that both the heat sink 61 and the heat sink 4 are formed of copper (Cu) or copper (Cu) alloy.
  • the heat generated in the semiconductor chip 5 is transmitted to the heat sink 4 through the bonding agent 14 and dissipated to the outside of the semiconductor device 1 from the portion of the heat sink 4 (lower portion of the heat sink 4 ) exposed on the lower surface (lower surface 2 a of the wiring board 2 ) side of the semiconductor device 1 like in the semiconductor device 1 of the first embodiment.
  • the heat generated in the semiconductor chip 5 is transmitted also to the heat sink 61 through the bonding agent 62 , and the heat is dissipated to the outside of the semiconductor device 1 f from the portion of the heat sink 61 (upper surface 61 a of the heat sink 61 ) exposed from the upper surface 7 b of the sealing resin 7 .
  • the semiconductor device 1 f of the present embodiment can dissipate the heat from both below and above, and therefore, the heat dissipation properties can be further improved.
  • FIGS. 153 to 158 are cross-sectional views in the manufacturing process of the semiconductor device 1 f of the present embodiment.
  • FIG. 153 is a cross-sectional view of the same region as FIG. 16 , each of the heat sinks 4 is not segmented, but is integrated as the frame 31 at the stage of FIG. 153 .
  • solder (solder paste) 62 a is coated on the front surface 5 b of each semiconductor chip 5 mounted on each heat sink 4 of the frame 31 through a nozzle (not shown), and then, as shown in FIG. 154 , the heat sink 61 is mounted on the front surface 5 b of each semiconductor chip 5 through the solder 62 a .
  • a sheet-like solder may be supplied on the front surface 5 b of the semiconductor chip 5 by using the printing method and the transfer method.
  • the heat sink 61 can be bonded and fixed on the front surface 5 b of each semiconductor chip 5 through the solder 62 a (bonding agent 62 ).
  • the molten and solidified solder 62 a by this solder reflow becomes the bonding agent 62 .
  • the solder reflow not only the solder 62 a but also the solder 14 a can be melted and re-solidified.
  • High melting point solder similar to the solder 14 a is preferably used for the solder 62 a , and the solder having a melting point at least higher than the melting point of the solder used for an external terminal (in this case, solder ball 8 ) formed on the land 18 later is preferably used as the solder 62 a .
  • the solder 62 a that is, the bonding agent 62 made of the solder 62 a
  • the bonding reliability of the semiconductor chip 5 and the heat sink 62 can be improved, and the heat conductivity from the semiconductor chip 5 to the heat sink 62 is improved, so that the heat dissipation properties of the semiconductor device if can be improved.
  • step S 4 to S 10 The subsequent process is almost the same as the first embodiment (steps S 4 to S 10 ).
  • step S 5 is performed in the same manner as the first embodiment, and as shown in FIG. 155 , the heat sink 4 mounted with the semiconductor chip 5 having the heat sink 61 mounted thereon is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 . Since step S 5 has been described in detail in the first embodiment, the description thereof will be omitted here.
  • each electrode 5 a of the semiconductor chip 5 and the corresponding connecting terminal 17 formed on the wiring board 21 are electrically connected through the bonding wire 6 .
  • the molding process in the step S 7 is performed in the same manner as the first embodiment, and as shown in FIG. 157 , the sealing resin 7 a is formed and the semiconductor chip 5 , the bonding wire 6 and the heat sink 61 are sealed (resin-sealed) by the sealing resin 7 a .
  • the sealing resin 7 a is formed so that the upper surface 61 a of the heat sink 61 is exposed from the upper surface of the sealing resin 7 a , and this is the difference between the present embodiment and the first embodiment.
  • the connecting process of the solder ball in the step S 8 is performed in the same manner as the first embodiment, and as shown in FIG. 158 , the solder ball 8 is connected (bonded) to the land 18 of the lower surface 21 b of the wiring board 21 .
  • the marking process in the step S 9 and the cutting process in the step S 10 are performed in the same manner as the first embodiment, and the wiring board 21 and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22 .
  • the semiconductor device if as shown in FIG. 152 can be manufactured.
  • the high temperature heat treatment is performed as the heat treatment for bonding the semiconductor chip 5 to the heat sink 4 and for bonding the heat sink 61 to the semiconductor chip 5
  • the solders 14 a and 62 a having a melting point higher than that of the solder used for the external terminal (in this case, solder ball 8 ) formed on the land 18 are used, it is preferable to apply the manufacturing process described with reference to FIGS. 153 to 158 because the wiring board 21 is not damaged at the time of high temperature heat treatment (solder reflow).
  • the heat conductivity of the bonding agent 62 becomes high as compared with the case of using the silver paste, and therefore, the heat transmission from the semiconductor chip 5 to the heat sink 61 is more increased, so that the heat dissipation properties of the semiconductor device 1 f can be more improved.
  • the heat sink 61 can be bonded on the front surface 5 b of the semiconductor chip 5 after the process up to the wire bonding process in the step S 6 is performed in the same manner as the first embodiment. Then, after the molding process and the connecting process of the solder ball are performed in the same manner as the process of FIG. 157 and the process of FIG. 158 , the marking process in the step S 9 and the cutting process in the step S 10 may be performed.
  • the heat sink 61 does not hinder a capillary motion of the wire bonding apparatus even if the planar shape of the heat sink 61 is made larger. Hence, there is an advantage that the dimension (planar shape) of the heat sink 61 can be made large.
  • the heat sink 61 is bonded to the semiconductor chip 5 by using a conductive paste type bonding agent such as the silver paste because the temperature of thermosetting heat treatment of this conductive paste type bonding agent is not so high as the temperature by which the wiring board 21 is damaged.
  • FIG. 159 is a cross-sectional view (side cross-sectional view) of the semiconductor device if in the case when the individual sealing is performed.
  • the semiconductor device if of FIG. 159 has almost the same structure as the semiconductor device if of FIG. 152 except that the sealing resin 7 is not formed on the peripheral edge portion of the upper surface 2 a of the wiring board 2 and the sealing resin 7 is formed on the region other than the peripheral edge portion of the upper surface 2 a of the wiring board 2 , and therefore, the description thereof will be omitted.
  • FIG. 160 is a cross-sectional view (side cross-sectional view) showing a state in which a heat dissipation fin 63 is mounted further on the upper surface of the semiconductor device if of FIG. 152
  • FIG. 161 is a cross-sectional view (side cross-sectional view) showing a state in which the heat dissipation fin 63 is mounted further on the upper surface of the semiconductor device if of FIG. 159 .
  • the heat dissipation fin (heat sink) 63 is mounted (disposed) on the upper surface of the semiconductor device 1 f .
  • the upper surface of the semiconductor device 1 f is formed of the upper surface 7 b of the sealing resin 7 and the upper surface 61 a of the heat sink 61 .
  • the heat dissipation fin 63 is required to be overlapped at least with a part of the upper surface 61 a of the heat sink 61 when seen planarly, and it is more preferable if the heat dissipation fin 63 encloses the upper surface 61 a of the heat sink 61 when seen planarly.
  • the heat dissipation fin 63 is attached to the upper surface 61 a of the heat sink 61 exposed from the upper surface 7 b of the sealing resin 7 . Specifically, (the lower surface of) the heat dissipation fin 63 is bonded and fixed to the upper surface 61 a of the heat sink 61 through the bonding agent 64 made of, for example, solder. For dissipating the heat generated in the semiconductor chip 5 from the heat dissipation fin 63 through the heat sink 61 , it is not necessary to bond the upper surface 7 b of the sealing resin 7 to the heat dissipation fin 63 , but the upper surface 61 a of the heat sink 61 is required to be bonded to the heat dissipation fin 63 .
  • the bonding agent 64 for bonding the heat dissipation fin 63 and the heat sink 61 the bonding agent having high conductivity (conductive bonding agent) is preferably used, and the solder is preferable.
  • the heat dissipation fin 63 can be also bonded and fixed to the upper surface 61 a of the heat sink 61 through a heat conductive bonding sheet (not shown) and the like having high heat conductivity. In this case, the heat dissipation fin 63 can be bonded and fixed to both of the upper surface 61 a of the heat sink 61 and the upper surface 7 b of the sealing resin 7 through the heat conductive bonding sheet.
  • the heat dissipation fin 63 is a member for dissipating the heat of the semiconductor device 1 f (heat generated in the semiconductor chip 5 ) and preferably has high heat conductivity, and the heat conductivity (heat conductivity coefficient) of the heat dissipation fin 63 is required to be at least higher than the heat conductivity (heat conductivity coefficient) of the sealing resin 7 . Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat dissipation fin 63 is preferably made of a conductive material and is more preferably formed of a metal material.
  • the heat sink 61 It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 61 because high heat conductivity of the heat dissipation fin 63 can be obtained and the processing thereof is easy. Further, it is more preferable that the heat dissipation fin 63 is made of the same material as the heat sink 61 , and by this means, the heat dissipation fin 63 and the heat sink 61 come to have the same heat expansion coefficient, and thus, a heat stress can be reduced. Therefore, it is most preferable that the heat dissipation fin 63 , the heat sink 61 and the heat sink 4 are formed of copper (Cu) or copper (Cu) alloy.
  • the heat dissipation fin 63 When the heat dissipation fin 63 is further attached to the upper surface of the semiconductor device 1 f as shown in FIG. 160 or FIG. 161 , the heat transmitted also to the heat sink 61 from the semiconductor chip 5 through the bonding agent 62 can be dissipated from the heat dissipation fin 63 , and therefore, the heat dissipation properties can be further improved.
  • the present embodiment can be applied to any one of the first to fifth embodiments. More specifically, in any of the semiconductor devices (semiconductor devices 1 , 1 a , 1 b , 1 b 1 , 1 c and 1 e ) shown in the first to fifth embodiments, the heat sink 61 can be mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the upper surface 61 a of the heat sink 61 can be exposed from the upper surface 7 b of the sealing resin 7 by applying the present embodiment. Further, the heat dissipation fin 63 can be further attached to the upper surface of the semiconductor device.
  • the heat sink 61 can be mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the sealing resins 7 and 7 a can be formed so that the upper surface 61 a of the heat sink 61 is exposed by applying the present embodiment.
  • a heat dissipation path can be secured not only to the lower side but also to the upper side of the semiconductor chip 5 , and therefore, the heat dissipation properties of the semiconductor device can be further improved.
  • FIG. 162 the case where the present embodiment is applied to the semiconductor device 1 b of the third embodiment is shown in FIG. 162 .
  • the semiconductor device shown in FIG. 162 has almost the same structure as the semiconductor device 1 b of FIG. 72 of the third embodiment except that the heat sink 61 is mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the upper surface 61 a of the heat sink 61 is exposed from the upper surface 7 b of the sealing resin 7 .
  • the semiconductor device of FIG. 162 can secure the heat dissipation path not only to the lower side but also to the upper side of the semiconductor chip 5 by providing the heat sink 61 , and therefore, the heat dissipation properties can be further improved as compared with the semiconductor device 1 b of FIG. 72 of the third embodiment.
  • FIG. 163 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 g of the seventh embodiment.
  • the semiconductor device 1 g of the present embodiment is the same as the first embodiment in that a heat sink 4 d (corresponding to the heat sink 4 ) is caulked inside the through-hole 3 of the wiring board 2 and fixed to the wiring board 2 .
  • the side surface (surface between the upper surface 9 a and the lower surface 9 b ) 10 of the heat sink 4 d is not inclined and is a surface almost vertical to the upper surface 9 a (or the lower surface 9 b ).
  • a groove 71 is formed in a part (upper surface 9 a in the present embodiment) of the heat sink 4 d along each side of the heat sink 4 d whose planar shape is rectangular (square in the present embodiment).
  • This groove 71 is used in the following manner. That is, when the semiconductor device 1 g is manufactured, this groove 71 is hit (pressed, crushed) by a jig (jig 73 to be described later) so that a part of the heat sink 4 d is expanded in a horizontal direction inside the through-hole 3 of the wiring board 2 and the heat sink 4 d is fixed to the wiring board 2 . Since the adhesion of the side surface 10 of the heat sink 4 d and the inner wall surface of the through-hole 3 of the wiring board 2 is improved as described above, the heat sink 4 d can be fixed to the wiring board 2 .
  • the protruded portion 11 is formed in the peripheral edge portion of the upper surface 9 a of the heat sink 4 d like in the first embodiment, a trouble of the heat sink 4 d falling off from the wiring board 2 can be prevented even when the thickness of the heat sink 4 d is increased so as to improve the heat dissipation properties and the weight of the heat sink 4 d is increased.
  • FIGS. 164 and 165 are cross-sectional views (explanatory drawings) showing a technique of caulking (fixing) the heat sink 4 d in the present embodiment to the wiring board 2 .
  • the heat sink 4 d is disposed inside the through-hole 3 of the wiring board 2 .
  • the wiring board 2 is disposed on a stage 72 , and then, the heat sink 4 d individually segmented and obtained in advance is disposed inside the through-hole 3 of the wiring board 2 as shown in FIG. 164 in the same manner as the above-described embodiments.
  • the heat sink 4 d is made thicker than the wiring board 2 so that the heat sink 4 d can also be electrically connected to a mother board (specifically, the board side terminal 42 a of the wiring board 41 ) when the completed semiconductor device 1 g is mounted on the mother board (corresponding to the wiring board 41 ). Therefore, it is preferable to form a groove (recess) 72 a at a position corresponding to the heat sink 4 d in the stage 72 .
  • the external dimension of the heat sink 4 d is preferably smaller than a size of the internal dimension of the through-hole 3 of the wiring board 2 . This is for the purpose of suppressing the trouble that a part of the heat sink 4 d contacts to the wiring board 2 and a crack is formed in the wiring board 2 at the time of inserting the heat sink 4 d into the through-hole 3 .
  • the heat sink 4 d can be inserted into the through-hole 3 so that the heat sink 4 d does not contact to the wiring board 2 , the heat sink 4 d having the same size as the inner dimension of the through-hole 3 may be used.
  • the jig 73 having a top end portion larger than a width (opening area on the upper surface 9 a side of the heat sink 4 d ) W 1 of the groove 71 is caused to descend toward the groove 71 in the direction (that is, the direction toward the lower surface 9 b of the heat sink 4 d from the upper surface 9 a of the heat sink 4 d ) shown by an arrow mark 74 of FIG. 165 , thereby hitting this groove 71 .
  • a part of the heat sink 4 d is expanded in the horizontal direction by a cubic volume by which the groove 71 is crushed (pushed and expanded) by the jig 73 , and the side surface 10 of the heat sink 4 d can be adhered to the inner wall surface of the through-hole 3 of the wiring board 2 . Therefore, the heat sink 4 d and the wiring board 2 can be caulked, and the heat sink 4 d can be fixed to the wiring board 2 .
  • the thicknesses of the heat sinks 4 , 4 a , 4 b , 4 c and 4 d become smaller as compared with the first to seventh embodiments, and moreover, since the electrical connection between the entire surface of the heat sinks 4 , 4 a , 4 b , 4 c and 4 d exposed from the lower surface 2 b of the wiring board 2 and the mounting board (equivalent to the wiring board 41 ) becomes difficult, the heat dissipation effect is decreased as compared with the cases shown in the first to seventh embodiments.
  • the structure in which the heat sink 4 (or the heat sink 4 a or 4 b ) obtained by performing individual segmentation is disposed inside the through-hole 3 of the wiring board 21 has been described in the first to third embodiments, but a plurality of heat sinks 4 (or a plurality of heat sinks 4 a or 4 b ) in a state of being fixed to the lead frame may be disposed and fixed inside the plurality of through-holes 3 of the wiring board 21 , respectively, and then, the separation of the wiring board 21 and the lead frame may be performed at the same time.
  • the structure in which the groove 71 is formed on the upper surface 9 a of the heat sink 4 d and the inside of this groove 71 is hit by the jig has been described in the seventh embodiment, but the heat sink 4 d may be expanded in the horizontal direction by directly hitting the upper surface 9 a of the heat sink 4 d by the jig without forming the groove 71 .
  • the present invention is suitably applied to the semiconductor device of a semiconductor package configuration and the manufacturing method thereof.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This is a continuation application of U.S. application Ser. No. 12/481,078, filed Jun. 9, 2009, the contents of which are hereby incorporated by reference into this application.
  • The present application claims priority from Japanese Patent Application No. JP 2008-154497 filed on Jun. 12, 2008 and Japanese Patent Application No. JP 2009-6240 filed on Jan. 15, 2009, the contents of which are hereby incorporated by reference into this application.
    • TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device and a manufacturing method of the same, and more particularly to a technique effectively applied to a semiconductor package having improved heat dissipation properties and a manufacturing method of the same.
    • BACKGROUND OF THE INVENTION
  • A semiconductor device of a BGA package configuration is manufactured by mounting a semiconductor chip on a wiring board, electrically connecting electrodes of the semiconductor chip and connecting terminals of the wiring board by bonding wires, sealing the semiconductor chip and the bonding wires with resin, and connecting solder balls on a rear surface of the wiring board.
  • Japanese Patent Application Laid-Open Publication No. 2004-296565 (patent document 1) discloses a technique relating to the manufacturing method of a semiconductor element housing package, in which openings for cavities are bored in a panel-shaped resin substrate having a plurality of resin boards and heat sinks are formed and bonded so as to close the openings in the cavity periphery of one surface of the resin board.
  • Japanese Patent Application Laid-Open Publication No. 2003-46027 (patent document 2) discloses a technique, in which, in a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board having a notch space in its center part, the plastic circuit board and the heat sink are bonded by a fastening member and the plastic circuit board and at least an end part of the bonding surface of the heat sink are covered with adhesive resin.
  • Japanese Patent Application Laid-Open Publication No. 2004-63830 (patent document 3) discloses a technique, in which, in a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board, the plastic circuit board and the heat sink are bonded by a fastening member and the plastic circuit board and the heat sink are bonded by a flanged pin, and moreover, the flanged pin is press-fitted and its top end is accommodated inside the heat sink so as to be pressure-welded and bonded to the heat sink.
  • International Publication No. 2002/084733 (patent document 4) discloses a technique relating to a heat dissipation BGA package having a metal heat sink bonded on one surface of a plastic circuit board having a notch space in its center part, in which a fastening member for bonding the plastic circuit board and the heat sink is provided.
    • SUMMARY OF THE INVENTION
  • Studies by the inventors of the present invention have revealed the following facts.
  • With the improvement in performance of a semiconductor device, the calorific value of an incorporated semiconductor chip is also increased. This is because the driving power is also increased with the improvement in performance of a semiconductor chip (applied voltage value is also increased). Hence, it is desired to take heat dissipation measures for the heat generated in the semiconductor chip incorporated inside the semiconductor device.
  • As the heat dissipation measures, various means such as disposing thermal balls, installing a heat dissipation fin on a sealing body or providing a plane for the wiring board are possible. However, these means can dissipate only about 2.5 W at best. The cause thereof is that, for example, in the case of the thermal ball, there is a distance between a semiconductor device and a mounting board by the height of the ball, and the path through which the heat can pass through is provided only in the path corresponding to the diameter of the ball.
  • Hence, as disclosed in the patent document 1, it is considered to paste the heat sink to the wiring board so that the heat sink mounted with the semiconductor chip is exposed also from a mounting surface side of the wiring board (the surface opposite to the mounting board when the semiconductor device is mounted on the mounting board). However, it is found that, when the heat sink (0.5 mm) having a thickness larger than the board (0.2 mm) is pasted in consideration of heat dissipation properties, the heat sink falls off due to the weight of the heat sink itself. The falling off of the heat sink lowers the manufacturing yield of the semiconductor device.
  • Hence, as disclosed in the patent documents 2 to 4, it is possible to take measures for the falling off of the heat sink by inserting and caulking (interposing a dam-like member between an end part of the pin and the printed circuit board) a heat sink pin into the printed circuit board.
  • However, the studies conducted by the inventors have revealed that, if a metal member such as disclosed in the patent document 4 is interposed, the load in the pressing is directly transmitted to the wiring board, and therefore, a crack of the wiring board is not sufficiently suppressed.
  • An object of the present invention is to provide a technique capable of improving the heat dissipation properties of the semiconductor device.
  • Further, another object of the present invention is to provide a technique capable of improving the manufacturing yield of the semiconductor device.
  • The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.
  • The typical ones of the inventions disclosed in this application will be briefly described as follows.
  • A semiconductor device according to a representative embodiment comprises: (a) a board having a first main surface and a second main surface opposite to the first main surface, the board including a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, a plurality of second electrodes formed around the through-hole on the second main surface, and a heat sink disposed inside the through-hole; (b) a semiconductor chip having a third main surface, on which a plurality of third electrodes are formed, and mounted on an upper surface of the heat sink; (c) a plurality of conductive wires electrically connecting the plurality of third electrodes of the semiconductor chip and the plurality of first electrodes of the board; (d) a sealing portion for sealing the semiconductor chip and the plurality of conductive wires; and (e) a plurality of external terminals formed on the plurality of second electrodes of the board, respectively. Also, a thickness of the heat sink is larger than a thickness of the board, the heat sink has a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of the upper surface of the heat sink, the protruded portion is located on the first main surface of the board outside the through-hole, and a lower surface of the protruded portion contacts to the first main surface of the board.
  • Further, a manufacturing method of a semiconductor device according to a representative embodiment comprises: (a) a step of preparing a heat sink having a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of an upper surface of the heat sink; (b) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, and a plurality of second electrodes formed around the through-hole on the second main surface; (c) a step of disposing the heat sink inside the through-hole of the board so that the protruded portion is located on the first main surface of the board outside the through-hole and a lower surface of the protruded portion contacts to the first main surface of the board; (d) a step of mounting, on the upper surface of the heat sink, the semiconductor chip having a third main surface on which a plurality of third electrodes are formed; (e) a step of electrically connecting the plurality of third electrodes of the semiconductor chip and the plurality of first electrodes of the board through a plurality of conductive wires; (f) a step of sealing the semiconductor chip and the plurality of conductive wires by resin; and (g) a step of forming a plurality of external terminals on the plurality of second electrodes of the board, respectively. Also, the heat sink is inserted into the through-hole from a first main surface side of the board in the step (c).
  • Further, a manufacturing method of a semiconductor device according to another representative embodiment comprises: (a) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, a plurality of second electrodes formed around the through-hole on the second main surface, and a heat sink disposed inside the through-hole; (b) a step of mounting, on an upper surface of the heat sink, a semiconductor chip having a third main surface on which a plurality of third electrodes are formed; (c) a step of electrically connecting the plurality of third electrodes of the semiconductor chip and the plurality of first electrodes of the board through a plurality of conductive wires; (d) a step of sealing the semiconductor chip and the plurality of conductive wires by resin; and (e) a step of forming a plurality of external terminals on the plurality of second electrodes of the board, respectively. Also, in the board prepared in the step (a), a thickness of the heat sink is larger than a thickness of the board, the heat sink has a protruded portion protruding to outside from a side surface of the heat sink in a peripheral edge portion of the upper surface of the heat sink, the protruded portion is located on the first main surface of the board outside the through-hole, and a lower surface of the protruded portion contacts to the first main surface of the board.
  • Further, a manufacturing method of a semiconductor device according to another representative embodiment comprises: (a) a step of preparing a frame in which a plurality of heat sinks are joined to a frame portion by a joining portion, respectively; (b) a step of preparing a board having a first main surface, a second main surface opposite to the first main surface, a plurality of through-holes reaching the second main surface from the first main surface, a plurality of first electrodes formed around each through-hole on the first main surface, and a plurality of second electrodes formed around each through-hole on the second main surface; (c) a step of mounting, on upper surfaces of the plurality of heat sinks of the frame, a plurality of semiconductor chips each having a third main surface on which a plurality of third electrodes are formed, respectively; (d) a step of disposing the frame on the first main surface of the board and inserting each heat sink into each through-hole of the board; (e) a step of electrically connecting the plurality of third electrodes of the plurality of semiconductor chips and the plurality of first electrodes of the board through a plurality of conductive wires; (f) a step of forming a sealing resin portion for sealing the plurality of semiconductor chips and the plurality of conductive wires on the first main surface of the board; (g) a step of forming a plurality of external terminals on the plurality of second electrodes of the boards, respectively; and (h) a step of cutting the board, the frame and the sealing resin portion on the first main surface of the board.
  • Further, a manufacturing method of a semiconductor device according to another representative embodiment comprises: (a) a step of preparing a frame in which a plurality of heat sinks are joined to a frame portion by a joining portion, respectively; (b) a step of preparing a plurality of boards each having a first main surface, a second main surface opposite to the first main surface, a through-hole reaching the second main surface from the first main surface, a plurality of first electrodes formed around the through-hole on the first main surface, and a plurality of second electrodes formed around the through-hole on the second main surface; (c) a step of mounting, on upper surfaces of the plurality of heat sinks of the frame, a plurality of semiconductor chips each having a third main surface on which a plurality of third electrodes are formed, respectively; (d) a step of fixing the frame and the plurality of boards from a first main surface side of each board so that each heat sink is inserted into the through-hole of each board; (e) a step of electrically connecting the plurality of third electrodes of each semiconductor chip and the plurality of first electrodes of each board through a plurality of conductive wires; (f) a step of forming a sealing resin portion on the first main surface of each board so that the semiconductor chip and the plurality of conductive wires thereon are sealed; (g) a step of forming a plurality of external terminals on the plurality of second electrodes of each board, respectively; and (h) a step of cutting the frame protruding from the sealing resin portion.
  • The effects obtained by typical embodiments of the inventions disclosed in this application will be briefly described below.
  • According to the exemplary embodiment, it is possible to improve the heat dissipation properties of the semiconductor device.
  • Further, it is possible to improve the manufacturing yield of the semiconductor device.
    • BRIEF DESCRIPTIONS OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention;
  • FIG. 2 is a perspective plan view of the semiconductor device of FIG. 1;
  • FIG. 3 is a lower surface view of the semiconductor device of FIG. 1;
  • FIG. 4 is a cross-sectional view of a heat sink used in the semiconductor device of FIG. 1;
  • FIG. 5 is an upper surface view of the heat sink of FIG. 4;
  • FIG. 6 is a lower surface view of the heat sink of FIG. 4;
  • FIG. 7 is an upper surface view of a wiring board used in the semiconductor device of FIG. 1;
  • FIG. 8 is a process flowchart showing a manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 9 is a plan view of the wiring board used in the manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 10 is a cross-sectional view of the wiring board of FIG. 9;
  • FIG. 11 is a plan view of a frame used in the manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 12 is a cross-sectional view of the frame of FIG. 11;
  • FIG. 13 is a plan view showing the manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 14 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 13;
  • FIG. 15 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 13;
  • FIG. 16 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 15;
  • FIG. 17 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 15;
  • FIG. 18 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 17;
  • FIG. 19 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 17;
  • FIG. 20 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 19;
  • FIG. 21 is a cross-sectional view showing a process of disposing a heat sink inside a through-hole of a wiring board;
  • FIG. 22 is a cross-sectional view showing the process of disposing the heat sink inside the through-hole of the wiring board subsequent to FIG. 21;
  • FIG. 23 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 19;
  • FIG. 24 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 23;
  • FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 24;
  • FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 25;
  • FIG. 27 is a cross-sectional view showing another manufacturing process of a semiconductor device according to one embodiment of the present invention;
  • FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 27;
  • FIG. 29 is a cross-sectional view showing the semiconductor device manufactured in the process of FIG. 27 and FIG. 28;
  • FIG. 30 is a process flowchart showing another manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 31 is a plan view showing another manufacturing process of the semiconductor device according to one embodiment of the present invention;
  • FIG. 32 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 31;
  • FIG. 33 is a cross-sectional view showing a process of disposing a heat sink inside a through-hole of a wiring board;
  • FIG. 34 is a cross-sectional view showing the process of disposing the heat sink inside the through-hole of the wiring board;
  • FIG. 35 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 31;
  • FIG. 36 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 35;
  • FIG. 37 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 35;
  • FIG. 38 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 37;
  • FIG. 39 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 40 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 41 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on the wiring board;
  • FIG. 42 is a cross-sectional view showing a modified example of the semiconductor device according to one embodiment of the present invention;
  • FIG. 43 is a cross-sectional view showing another modified example of the semiconductor device according to one embodiment of the present invention;
  • FIG. 44 is a perspective plan view of the semiconductor device of FIG. 43;
  • FIG. 45 is a lower surface view of the semiconductor device of FIG. 43;
  • FIG. 46 is a perspective plan view showing still another modified example of the semiconductor device according to one embodiment of the present invention;
  • FIG. 47 is a cross-sectional view showing still another modified example of the semiconductor device according to one embodiment of the present invention;
  • FIG. 48 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 49 is another cross-sectional view of the semiconductor device of FIG. 48;
  • FIG. 50 is a perspective plan view of the semiconductor device of FIG. 48;
  • FIG. 51 is a lower surface view of the semiconductor device of FIG. 48
  • FIG. 52 is a cross-sectional view of a heat sink used in the semiconductor device of FIG. 48;
  • FIG. 53 is another cross-sectional view of the heat sink of FIG. 52;
  • FIG. 54 is an upper surface view of the heat sink of FIG. 52;
  • FIG. 55 is a lower surface view of the heat sink of FIG. 52;
  • FIG. 56 is a cross-sectional view of a wiring board used in the semiconductor device of FIG. 48;
  • FIG. 57 is an upper surface view of the wiring board of FIG. 56;
  • FIG. 58 is a plan view of a frame used for manufacturing the semiconductor device of FIG. 48;
  • FIG. 59 is an explanatory drawing showing a process of disposing a heat sink inside a through-hole of a wiring board;
  • FIG. 60 is an explanatory drawing showing the process of disposing the heat sink inside the through-hole of the wiring board;
  • FIG. 61A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 61B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 62A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 62B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 63A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 63B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 64A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 64B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 65A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 65B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 66A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 66B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 67A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 67B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 68A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 68B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 69A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 69B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 70A is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 70B is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 71 is an upper surface view showing a modified example of the wiring board;
  • FIG. 72 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 73 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 72;
  • FIG. 74 is an explanatory drawing of the process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 72;
  • FIG. 75 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 76 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 77 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 78 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 79 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 80 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 81 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 82 is an explanatory drawing showing a technique of caulking (fixing) the heat sink to the wiring board;
  • FIG. 83 is a cross-sectional view showing a modified example of the semiconductor device according to another embodiment of the present invention;
  • FIG. 84 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 83;
  • FIG. 85 is an explanatory drawing of a process of fixing the heat sink to the wiring board in the manufacturing process of the semiconductor device of FIG. 83;
  • FIG. 86 is a process flowchart showing a manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 87 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 88 is a lower surface view of the frame of FIG. 87;
  • FIG. 89 is a cross-sectional view of the frame of FIG. 87;
  • FIG. 90 is another cross-sectional view of the frame of FIG. 87;
  • FIG. 91 is a plan view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 92 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 91;
  • FIG. 93 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 94 is a cross-sectional view of the wiring board of FIG. 93;
  • FIG. 95 is another cross-sectional view of the wiring board of FIG. 93;
  • FIG. 96 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 91;
  • FIG. 97 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 96;
  • FIG. 98 is another cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 96;
  • FIG. 99 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 100 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 101 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 96;
  • FIG. 102 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 101;
  • FIG. 103 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 101;
  • FIG. 104 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 103;
  • FIG. 105 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 104;
  • FIG. 106 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 107 is another cross-sectional view of the semiconductor device of FIG. 106;
  • FIG. 108 is a perspective plan view of the semiconductor device of FIG. 106;
  • FIG. 109 is a lower surface view of the wiring board in the semiconductor device of FIG. 106;
  • FIG. 110 is an explanatory drawing showing a technique of fixing the frame to the wiring board by using a bonding agent;
  • FIG. 111 is an explanatory drawing showing a technique of fixing the frame to the wiring board by using the boding agent;
  • FIG. 112 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 113 is a lower surface view of the frame of FIG. 112;
  • FIG. 114 is a cross-sectional view of the frame of FIG. 112;
  • FIG. 115 is another cross-sectional view of the frame of FIG. 112;
  • FIG. 116 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 117 is a plan view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 118 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 117;
  • FIG. 119 is another cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 117;
  • FIG. 120 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 121 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 122 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 123 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 124 is a plan view showing the manufacturing process of the semiconductor device subsequent to FIG. 117;
  • FIG. 125 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 126 is a perspective plan view of the semiconductor device of FIG. 125;
  • FIG. 127 is a process flowchart showing a manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 128 is an upper surface view of a frame used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 129 is a lower surface view of the frame of FIG. 128;
  • FIG. 130 is a cross-sectional view of the frame of FIG. 128;
  • FIG. 131 is an upper surface view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 132 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 131;
  • FIG. 133 is an upper surface view of the wiring board used in the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 134 is an upper surface view showing the manufacturing process of the semiconductor device subsequent to FIG. 131;
  • FIG. 135 is a lower surface view showing the same manufacturing process of the semiconductor device as FIG. 134;
  • FIG. 136 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 134;
  • FIG. 137 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 138 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 139 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 140 is an explanatory drawing showing a technique of fixing the frame to the wiring board;
  • FIG. 141 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 136;
  • FIG. 142 is an upper surface view showing the manufacturing process of the semiconductor device subsequent to FIG. 141;
  • FIG. 143 is a lower surface view showing the same manufacturing process of the semiconductor device as FIG. 142;
  • FIG. 144 is a cross-sectional view showing the same manufacturing process of the semiconductor device as FIG. 142;
  • FIG. 145 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 144;
  • FIG. 146 is an explanatory drawing showing a process of cutting the frame;
  • FIG. 147 is an explanatory drawing showing a process of cutting the frame;
  • FIG. 148 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 149 is another cross-sectional view of the semiconductor device of FIG. 148;
  • FIG. 150 is a perspective plan view of the semiconductor device of FIG. 148;
  • FIG. 151 is a lower surface view of the wiring board in the semiconductor device of FIG. 148;
  • FIG. 152 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 153 is a cross-sectional view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention;
  • FIG. 154 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 153;
  • FIG. 155 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 154;
  • FIG. 156 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 155;
  • FIG. 157 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 156;
  • FIG. 158 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 157;
  • FIG. 159 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 160 is a cross-sectional view showing a state in which a heat dissipation fin is mounted on the upper surface of the semiconductor device of FIG. 152;
  • FIG. 161 is a cross-sectional view showing a state in which a heat dissipation fin is mounted on the upper surface of the semiconductor device of FIG. 159;
  • FIG. 162 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 163 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
  • FIG. 164 is a cross-sectional view showing a technique of caulking (fixing) the heat sink according to another embodiment of the present invention to the wiring board; and
  • FIG. 165 is a cross-sectional view showing a technique of caulking (fixing) the heat sink to the wiring board subsequent to FIG. 164.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable. Further, in the embodiments described below, it goes without saying that the components (including element steps) are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle. Similarly, in the embodiments described below, when the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it can be conceived that they are apparently excluded in principle. The same goes for the numerical value and the range described above.
  • Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference numbers throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the embodiments described below, descriptions of the same or similar components are not repeated in principle except the case where the descriptions are particularly necessary.
  • Also, in the drawings used in the embodiments, hatching is omitted even in a cross-sectional view and is used even in a plan view so as to make the drawings easy to see.
    • First Embodiment
  • A semiconductor device and a manufacturing method (manufacturing process) of the same according to one embodiment of the present invention will be described with reference to the drawings.
  • FIG. 1 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 according to one embodiment of the present invention, FIG. 2 is a perspective plan view (upper surface view) of the semiconductor device 1 when seen through a sealing resin 7, and FIG. 3 is a lower surface view (bottom view, rear view, plan view) of the semiconductor device 1. The cross-sections cut along the line A1-A1 of FIGS. 2 and 3 almost correspond to FIG. 1. Also, FIG. 4 is a cross-sectional view (side cross-sectional view) of a heat sink 4 used in the semiconductor device 1 of the present embodiment, FIG. 5 is an upper surface view (plan view) of the heat sink 4, and FIG. 6 is a lower surface view (plan view) of the heat sink 4. The cross-sections cut along the line A2-A2 of FIGS. 5 and 6 almost correspond to FIG. 4, but FIGS. 4 and 1 show the same cross-sectional positions. Further, FIG. 7 is an upper surface view (plan view) of a wiring board 2 used in the semiconductor device 1 of the present embodiment. Although FIG. 7 is a plan view, hatching is applied to the wiring board 2 and connecting terminals 17 of its upper surface 2 a so as to make a position and a shape of a through-hole 3 in the wiring board 2 easily understood. In FIG. 2, the position of the through-hole 3 of the wiring board 2 which is invisible and concealed by the heat sink 4 even when the sealing resin 7 is seen through is shown by a dotted line for easy understanding.
  • The semiconductor device 1 of the present embodiment shown in FIGS. 1 to 3 is the semiconductor device of a resin-sealed semiconductor package configuration.
  • The semiconductor device 1 of the present embodiment includes the wiring board 2, the heat sink 4 disposed inside the through-hole 3 of the wiring board 2, a semiconductor chip 5 mounted on the heat sink 4, a plurality of bonding wires 6 electrically connecting a plurality of electrodes 5 a of the semiconductor chip 5 and a plurality of connecting terminals 17 of the wiring board 2, a sealing resin 7 covering the upper surface 2 a of the wiring board 2 including the semiconductor chip 5 and the bonding wires 6, and a plurality of solder balls 8 provided on the lower surface 2 b of the wiring board 2.
  • The wiring board (board, package board, wiring board for package) 2 includes an upper surface (first main surface) 2 a which is one main surface and a lower surface (rear surface, second main surface) 2 b which is the main surface opposite to the upper surface 2 a. The through-hole 3 reaching the lower surface 2 b from the upper surface 2 a of the wiring board 2 is provided in the vicinity of the center of the wiring board 2, and the heat sink 4 is disposed and fixed inside this through-hole 3.
  • The heat sink (Heat Spreader) 4 has an upper surface (front surface, main surface, chip supporting surface) 9 a which is one main surface and a lower surface 9 b which is a main surface opposite to the upper surface 9 a, and the semiconductor chip 5 is mounted on the upper surface 9 a of the heat sink 4. Consequently, the upper surface 9 a of the heat sink 4 is a chip mounting surface (surface on which the semiconductor chip 5 is mounted). The chip mounting surface of the heat sink 4 is almost parallel to the upper surface 2 a of the wiring board 2. A thickness t1 of the heat sink 4 is larger than a thickness t2 of the wiring board 2 (that is, t1>t2), and a lower part (including the lower surface 9 b) of the heat sink 4 protrudes from the lower surface 2 b of the wiring board 2. Here, the thickness t1 of the heat sink 4 corresponds to a dimension (distance) from the upper surface 9 a (chip mounting surface) of the heat sink 4 to the lower surface 9 b of the heat sink 4, and the thickness t2 of the wiring board 2 corresponds to the dimension (distance) from the upper surface 2 a to the lower surface 2 b of the wiring board 2. Also, the heat sink 4 can be taken also as a conductive portion (metal portion) for chip mounting.
  • The heat sink 4 thicker than the wiring board 2 is disposed inside the through-hole 3 of the wiring board 2, and the semiconductor chip 5 is disposed on this heat sink 4, thereby transmitting a heat generated in the semiconductor chip 5 at the time of using the semiconductor device 1 to the heat sink 4, so that the heat can be dissipated to the outside of the semiconductor device 1 from an exposed portion (lower surface 9 b of the heat sink 4) of the heat sink 4. For the improvement of the heat dissipation properties, it is effective to make the thickness t1 of the heat sink 4 larger, and the heat dissipation properties of the semiconductor device 1 can be improved by making the thickness t1 of the heat sink 4 larger than the thickness t2 of the wiring board 2 (that is, t1>t2). For example, when the thickness t2 of the wiring board 2 is about 0.2 mm, the thickness t1 of the heat sink 4 can be made about 0.6 mm, or when the thickness t2 of the wiring board 2 is about 0.6 mm, the thickness t1 of the heat sink 4 can be made about 1.2 mm.
  • The heat sink 4 is a member for dissipating the heat generated in the semiconductor chip 5 and preferably has high heat conductivity, and it is necessary that the heat conductivity (heat conductivity coefficient) of the heat sink 4 is higher than at least the heat conductivity (heat conductivity coefficient) of the wiring board 2 and the sealing resin 7. Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat sink 4 is preferably made of a conductive material and is more preferably formed of a metal material. It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 4 because high heat conductivity of the heat sink 4 can be obtained and the processing (formation of the heat sink 4) is easy.
  • The trough-hole 3 of the wiring board 2 has, for example, a rectangular planar shape. In the heat sink 4, the cross-sectional shapes of a portion located inside the through hole 3 and a portion protruding downward from the lower surface 2 b of the wiring board 2 (lower part of the heat sink 4) parallel to the upper surface 2 a of the wiring board 2 are almost the same as the planar shape of the through-hole 3 of the wiring board 2. A side surface (side wall) 10 of the heat sink 4 contacts to (adheres to) an inner wall (side wall, side surface) of the through-hole 3 of the wiring board 2. Further, the lower surface 9 b of the heat sink 4 also has almost the same planar shape as the planar shape of the through-hole 3 of the wiring board 2.
  • The heat sink 4 has a protruded portion (projecting portion, overhang portion, hook portion) 11 protruding to the outside (in the direction away from the center of the upper surface 9 a) from the side surface 10 of the heat sink 4 (side surface 10 contacting to the inner wall of the through-hole 3 of the wiring board 2) in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4, and this protruded portion 11 is located on the upper surface 2 a of the wiring board 2 outside the through-hole 3 and the lower surface of the protruded portion 11 contacts to the upper surface 2 a of the wiring board 2. That is, the heat sink 4 has the protruded portion 11, which protrudes to the upper side of the upper surface 2 a of the wiring board 2 from above the through-hole 3 and extends on the upper surface 2 a of the wiring board 2, on the peripheral edge portion of the upper surface 9 a of the heat sink 4, and this protruded portion 11 projects (overhung) on the upper surface 2 a of the wiring board from the through-hole 3. This protruded portion 11 is integrally formed with the heat sink 4 and can be taken as a part of the heat sink 4.
  • Consequently, in the semiconductor device 1, when seen in a plane parallel to the upper surface 2 a of the wiring board 2, the portions other than the protruded portions 11 of the heat sink 4 are located at a planarly overlapped position with the through-hole 3, and the protruded portions 11 only are located outside the through-hole 3 (at the position not planarly overlapped with the through-hole 3, that is, at the position overlapped with the wiring board 2). For easy understanding, a planar position of the through-hole 3 when the heat sink 4 is disposed inside the through-hole 3 of the wiring board 2 is shown by a dotted line in FIG. 5.
  • Although the details will be described later, the heat sink 4 is inserted and fixed into the through-hole 3 from the upper surface 2 a side of the wiring board 2 before the sealing resin 7 is formed. If the heat sink 4 has no protruded portion 11 and the cross-sectional shape parallel to the upper surface 2 a of the wiring board 2 is the same as the planar shape of the through-hole 3 in any part of the heat sink 4 unlike the present embodiment, the heat sink 4 is likely to fall off from the through-hole 3 of the wiring board 2 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 2 a side of the wiring board 2. In contrast to this, in the present embodiment, since the heat sink 4 is provided with the protruded portion 11, the protruded portion 11 of the heat sink 4 is caught on the upper surface 2 a of the wiring board 2 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 2 a side of the wiring board 2, and therefore, it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 2, and the heat sink 4 can be retained inside the through-hole 3 of the wiring board 2.
  • Since the protruded portion 11 of the heat sink 4 functions as a stopper for preventing the sink plate 4 from falling off from the through-hole 3 of the wiring board 2, it is necessary to provide the protruded portion 11 at least in a part of the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4. Hence, if the protruded portion 11 is provided at least in a part of the peripheral edge portion of the upper surface 9 a of the heat sink 4 though not in the entire peripheral edge portion of the upper surface 9 a of the heat sink 4, it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 2. However, if the protruded portion 11 (in a flange shape or in an overhang shape) is provided in the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 as shown in FIG. 6, the heat sink 4 can be stably disposed inside the through-hole 3 of the wiring board 2. Therefore, in the present embodiment, in the heat sink 4, the protruded portion 11 is provided at least in a part of the peripheral edge portion of the upper surface 9 a of the heat sink 4, and more preferably provided in the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4. When the protruded portion 11 is provided in the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4, the protruded portion 11 is preferably formed in a flange shape or in an overhang shape in the heat sink 4.
  • Also, the side surface 10 of the heat sink 4 contacting to the inner wall of the through-hole 3 preferably has a tapered shape (is tapered). In other words, the part of the heat sink 4 located inside the through-hole 3 has a tapered cross-sectional shape (shape in cross-section vertical to the chip mounting surface of the heat sink 4). Hence, the dimension of the heat sink 4 of the portion except the protruded portion (dimension of the cross-section parallel to the upper surface 2 a of the wiring board 2) is slightly larger on the upper side than on the lower side. More specifically, a dimension L2 of the upper part of the heat sink 4 (except the protruded portion 11) is slightly larger than a dimension L1 of the lower part of the heat sink 4 (that is, L2>L1).
  • Since the side surface 10 of the heat sink 4 contacting to the inner wall of the through-hole 3 has a tapered shape, this side surface 10 is not vertical to the chip mounting surface (upper surface 2 a) of the heat sink 4, but is inclined by an angle α with respect to the vertical direction (here, α>0). That is, a vertical line of the side surface 10 of the heat sink 4 (line vertical to the side surface 10) is not parallel to the chip mounting surface (upper surface 2 a) of the heat sink 4, but is inclined by an angle α with respect to the parallel direction. Also, since the chip mounting surface (upper surface 9 a) of the heat sink 4 is almost parallel to the upper surface 2 of the wiring board 2, the side surface 10 of the heat sink 4 contacting to the inner wall of the through-hole 3 is not vertical to the upper surface 2 a of the wiring board 2, but is inclined by the angle α with respect to the vertical direction. This inclined angle α of the side surface 10 of the heat sink 4 is preferably about 3 to 30°.
  • On the other hand, the inner wall of the through-hole 3 of the wiring board 2 before the heat sink 4 is inserted is almost vertical to the upper surface 2 a of the wiring board 2. Further, a dimension L3 of the through-hole 3 of the wiring board 2 before the heat sink 4 is inserted is made the same or slightly larger than the dimension L1 of the lower part of the heat sink 4 (that is, L1≦L3), and is made smaller than the dimension L2 of the upper portion of the heat sink 4 (except the protruded portion 11) (that is, L3<L2). By this means, when the heat sink 4 is inserted into the through-hole 3 from the upper surface 2 a side of the wiring board 2 at the time of manufacturing the semiconductor device 1, the heat sink 4 is pushed into the through-hole 3, and the heat sink 4 and the wiring board 2 can be caulked by the tapered shape of the side surface 10 of the heat sink 4, and the heat sink 4 can be fixed to the wiring board 2. More specifically, when the heat sink 4 is inserted into the through-hole 3 from the upper surface 2 a side of the wiring board 2 at the time of manufacturing the semiconductor device 1, since the through-hole 3 of the wiring board is expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4, a force for causing the inner wall of the through-hole 3 of the wiring board 2 to be adhered and pushed to the side surface 10 of the heat sink 4 is operated by its reaction, so that the heat sink 4 can be fixed to the wiring board 2. Accordingly, since the heat sink 4 can be fixed to the wiring board 2 until the sealing resin 7 is formed, the manufacture of the semiconductor device 1 can be facilitated.
  • The semiconductor chip 5 has a rectangular (square) shape in a plane vertical to its thickness. For example, after various semiconductor elements or semiconductor integrated circuits and the like are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single-crystal silicon or the like, a rear surface grinding of the semiconductor substrate is performed as required, and then, the semiconductor substrate is separated into each semiconductor chip 5 by the dicing or the like. The semiconductor chip 5 has a front surface (main surface, upper surface, third main surface on the semiconductor element formation side) 5 b and a rear surface (main surface, lower surface opposite to the main surface on the semiconductor element formation side) 5 c which are opposed to each other, and it is mounted (disposed) on the upper surface 9 a of the heat sink 4 so that the front surface 5 b of the semiconductor chip 5 is directed upward, and the rear surface 5 c of the semiconductor chip 5 is bonded and fixed to the upper surface 9 a of the heat sink 4 through a bonding agent (die bond agent, bonding agent, adhesive) 14. The planar dimensions of the through-hole 3 of the wiring board 2 and the heat sink 4 are larger than the planar dimensions of the semiconductor chip 5, respectively, and the semiconductor chip 5 mounted on the heat sink 4 is disposed so as to be planarly enclosed in the through-hole 3 of the wiring board 2 and the heat sink 4. As the bonding agent 14, the bonding agent having high heat conductivity is preferably used, and for example, solder or a conductive paste material (the paste material preferable as a conductive paste material is silver paste) can be used. A plurality of electrodes (bonding pad, pad electrode, electrode pad, third electrode) 5 a are formed on the front surface of the semiconductor chip 5, and the electrodes 5 a are electrically connected to the semiconductor element or the semiconductor integrated circuit formed inside the semiconductor chip 5 or on the surface layer portion.
  • The wiring board 2 includes an insulating base material layer (insulating board, core material) 16 and a conductor layer (conductor pattern, conductor film pattern, wiring layer) formed on the upper surface and the lower surface of the base material layer 16. A board in which the conductor layer is formed on the upper surface and the lower surface of one insulating layer (base material layer 16) or a multilayer wiring board (multilayer board) in which a plurality of insulating layers (base material layers) and a plurality of conductor layers (wiring layers) are alternately formed (integrated) over multiple layers may be used as the wiring board 2, but the multilayer wiring board is more preferable. In FIG. 1, the illustration of the wiring layer inside the wiring board 2 (interlayer of the base material layer 16) is omitted. For example, a resin material (for example, a glass epoxy resin) and the like can be used as the base material layer 16 of the wiring board 4.
  • The conductor layers of the upper surface and the lower surface of the base material layer 16 are developed into certain patterns and can be formed by a conductive material such as a copper thin film formed by, for example, an electroplating method. A plurality of the connecting terminals (electrodes, bonding leads, bonding pads, pad electrodes, first electrodes) 17 and wirings connected thereto for connecting the bonding wires 6 are formed on the upper surface 2 a of the wiring board 2 by the conductor layer of the upper surface of the base material layer 16, and a plurality of conductive lands (electrodes, land electrodes, pads, terminals, second electrodes) 18 for connecting the solder balls 8 are formed on the lower surface 2 b of the wiring board 2 by the conductor layer of the lower surface of the base material layer 16. The plurality of connecting terminals 17 are disposed (formed) around the through-hole 3 on the upper surface 2 a of the wiring board 2, and the plurality of lands 18 are disposed (formed) around the through-hole 3 on the lower surface 2 b of the wiring board 2. Also, solder resist layers (not shown) can be formed according to need on the upper surface 2 a and the lower surface 2 b of the wiring board 2. In this case, on the upper surface 2 a and the lower surface 2 b of the wiring board 2, the connecting terminals 17 and the lands 18 are exposed from a solder resist layer, and other conductor layers are covered by the solder resist layer.
  • The wirings (wirings connected with the connecting terminals 17) of the upper surface 2 a of the wiring board 2 and the lands 18 of the lower surface 2 b are electrically connected through conductors and the like inside the unillustrated through-hole formed in (base material layer 16 of) the wiring board 2. The unillustrated through-holes for connecting the wirings and the lands 18 are sufficiently small in planar dimension (dimension in a planar surface parallel to the upper surface 2 a and the lower surface 2 b of the wiring board 2) as compared with the through-hole 3.
  • Consequently, the plurality of electrodes 5 a of the semiconductor chip 5 are electrically connected to the plurality of connecting terminals 17 of the wiring board 2 through a plurality of bonding wires 6, and further electrically connected to the plurality of lands 18 of the lower surface 2 b of the wiring board 2 through the wirings of the wiring board 2 (wirings connected with the connecting terminals 17) and the conductors inside the through-holes (not shown) and the like. The bonding wires (conductive wires) 6 are conductive wires (connecting members) and are made of, for example, thin metal wires such as gold wires.
  • The plurality of lands 18 are disposed in an array pattern in a region having no through-hole 3 (region having the base material layer 16 of the wiring board 2) on the lower surface 2 b of the wiring board 2, and the solder ball (ball electrode, solder bump, bump electrode, protruded portion electrode) 8 is connected to each of the lands 18. Hence, in the region having no through-hole 3 (region having the base material layer 16 of the wiring board 2) on the lower surface 2 b of the wiring board 2, the plurality of solder balls 8 are disposed in an array pattern as external terminals. The lower surface 2 a of the wiring board 2 disposed with the solder balls 8 become the lower surface of the semiconductor device 1, and this becomes a mounting surface of the semiconductor device 1 (main surface of the side mounted on the mounting board).
  • Consequently, the semiconductor device 1 of the present embodiment is a semiconductor device of a BGA (Ball Grid Array Package) configuration. The solder ball 8 is made of a solder material, and can function as a bump electrode (protruded portion electrode, solder bump) of the semiconductor device 1 and can function as the external terminal (terminal for external connection) of the semiconductor device 1. Hence, a plurality external terminals (solder balls 8 in this case) are formed on the plurality of lands 18 of the wiring board 2, respectively.
  • Since the thickness t1 of the heat sink 4 is thicker than the thickness t2 of the wiring board 2, the lower surface 9 b of the heat sink 4 protrudes from the lower surface 2 b of the wiring board 2, but the lower surface 9 b of the heat sink 4 is located on the lower surface 2 b side of the wiring board 2 compared with the position of the lower end of the solder ball 8 (end part opposite to the side connected to the land 18, that is, top end of the solder ball 18). More specifically, when the semiconductor device 1 is disposed on a flat surface, the lower end of the solder ball 8 contacts to the flat surface, but the lower surface 9 b of the heat sink 4 does not contact thereto. In this manner, when the semiconductor device 1 is mounted on the mounting board, the heat sink 4 can be prevented from becoming a hindrance.
  • The plurality of electrodes 5 a of the semiconductor chip 5 are electrically connected to the plurality of connecting terminals 17 of the wiring board 2 through the plurality of bonding wires 6, and further electrically connected to the plurality of lands 18 of the wiring board 2 and the plurality of solder balls 8 connected to the plurality of lands 18 through the wirings of the wiring board 2 and the conductors inside the through-holes (not shown) and the like.
  • The sealing resin (sealing resin portion, resin sealing portion, sealing portion, sealing body) 7 is made of, for example, a resin material such as a thermosetting resin material and can contain the filler and the like. For example, it is also possible to form the sealing resin 7 by using the epoxy resin containing the filler and the like. The sealing resin 7 is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on the upper surface 2 a of the wiring board and the upper surface 9 a of the heat sink 4, and the semiconductor chip 5 and the bonding wire 6 are sealed and protected by the sealing resin 7.
  • Also, the sealing resin 7 is adhered (bonded) to the wiring board 2 and the heat sink 4, respectively, so that the wiring board 2, the heat sink 4 and the sealing resin 7 are coupled, and further the protruded portion 11 of the heat sink 4 is sandwiched by the sealing resin 7 and the wiring board 2, so that the coupling of the wiring board 2, the heat sink 4 and the sealing resin 7 is strengthened.
  • In this manner, the semiconductor device 1 of the present embodiment is a semiconductor device (semiconductor package) in which the semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2. The solder balls 8 are bonded on the lower surface 2 a below the wiring board 2 as external terminals, and the heat sink 4 is exposed from the lower surface 2 a of the wiring board 2. The heat generated in the semiconductor chip 5 is transmitted to the heat sink 4 through the bonding agent 14, and can be dissipated to the outside of the semiconductor device 1 from the exposed portion of the heat sink 4 (lower portion of the heat sink 4) on the lower surface side (lower surface 2 a of the wiring board 2) of the semiconductor device 1. Hence, the semiconductor device 1 of the present embodiment is a high heat-dissipation semiconductor device (semiconductor package).
  • Next, the manufacturing method of the semiconductor device 1 of the present embodiment will be described with reference to the drawings. FIG. 8 is a process flowchart showing a manufacturing process of the semiconductor device 1 of the present invention. FIGS. 9 to 26 are plan views or cross-sectional views in the manufacturing process of the semiconductor device 1 of the present embodiment. Of FIGS. 9 to 26, FIGS. 9, 11, 13, 15, 17, 19 and 23 are plan views (upper surface views), and FIGS. 10, 12, 14, 16, 18, 20 to 22 and 24 to 26 are cross-sectional views. Note that FIG. 10 corresponds to the cross-sectional view cut along the line A3-A3 of FIG. 9, and FIG. 12 corresponds to the cross-sectional view cut along the line A4-A4 of FIG. 11. FIG. 14 shows a cross-section at the same position as FIG. 12, but corresponds to the same process stage as FIG. 13. FIG. 16 shows the cross-section of the same position as FIG. 12, but corresponds to the same process stage as FIG. 15. FIG. 18 shows the cross-section of the same position as FIG. 12, but corresponds to the same process stage as FIG. 17. FIG. 20 shows the cross-section of the same position as FIG. 10, but corresponds to the same process stage as FIG. 19. FIG. 24 shows the cross-section of the same position as FIG. 10, but corresponds to the same process stage as FIG. 23. FIG. 25 shows the cross-section of the same position as FIG. 10, but corresponds to the process stage later than FIG. 24. FIG. 26 shows the cross-section of the same position as FIG. 10, but corresponds to the process stage later than FIG. 25.
  • In the present embodiment, the case where the individual semiconductor devices 1 are manufactured by using a multi-cavity wiring board (wiring board base) 21 in which a plurality of wiring boards 2 are connected in a row or in an array pattern will be described.
  • First, as shown in FIGS. 9 and 10, a wiring board 21 is prepared (step S1). This wiring board 21 is a base of the wiring board 2, and the wiring board 21 is cut by a cutting process to be described later, and is separated into each semiconductor device region (board region, unit board region) 22, and this region corresponds to the wiring board 2 of the semiconductor device 1. The wiring board 21 has a structure in which a plurality of semiconductor device regions 22 from each of which one semiconductor device 1 is formed are disposed in a row or in a matrix pattern. Consequently, the through-hole 3 is formed in each of the semiconductor device regions 22 of the wiring board 21, the plurality of connecting terminals 17 and the wires connected thereto are formed in each of the semiconductor device regions 22 on an upper surface 21 a of the wiring board 21 (surface to be the upper surface 2 a of the wiring board 2 later, first main surface), and the plurality of lands 18 are formed in each of the semiconductor device regions 22 on a lower surface 21 b of the wiring board 21 (surface to be the lower surface 2 b of the wiring board 2 later, second main surface). Note that FIG. 9 (upper surface view of the wiring board 21) and FIG. 10 (cross-sectional view of the wiring board 21) show an example in which the plurality of semiconductor device regions 22 are disposed in a row to constitute the wiring board 21.
  • Also, as shown in FIG. 11 (upper surface view of a frame 31) and 12 (cross-sectional view of the frame 31), the frame 31 for the heat sink 4 is prepared (step S2). The frame 31 has a structure in which the plurality of heat sinks 4 are integrally joined to frame portions 32. More specifically, the plurality of heat sinks 4 are disposed at the predetermined intervals between the two frame portions 32 extending in the same direction, and the four corners of the upper part of each heat sink 4 are joined to the frame portion 32 through joining portions 33. The frame 31 can be formed by, for example, processing a copper plate and the like by a metal mold. In the frame 31, joining portions 34 for mutually joining the frame portions 32 are provided between the adjacent heat sinks 4 so as to reinforce the frame 31. If not required, the joining portion 34 can be omitted. In the frame 31, the heat sink 4, the frame portion 32, the joining portion 33, and the joining portion 34 are integrally formed from the same material.
  • Although FIG. 11 is a plan view, hatching is applied to the frame 31 so as to make the shape of the frame 31 easily understood. Also, although the heat sinks 4 appear to be separated from each other in FIG. 12, as evident from FIG. 11, the heat sinks 4 are coupled with each other through the coupling portions 33 and the frame portions 32 in reality.
  • Next, the semiconductor chip 5 is mounted and bonded on the upper surface 9 a of each heat sink 4 of the frame 31 through the bonding agent 14 (step S3). The bonding process of the semiconductor chip 5 in the step S3 can be performed as follows.
  • That is, as shown in FIGS. 13 and 14, solder (first solder) 14 a is coated on the upper surface 9 a of each heat sink 4 of the frame 31. Then, the solder 14 a on each heat sink 4 of the frame 31 is agitated as needed, and thereafter, the semiconductor chip 5 is mounted on the upper surface 9 a of each heat sink 4 of the frame 31 through the solder 14 a as shown in FIGS. 15 and 16. These processes, that is, the coating process of the solder 14 a on each heat sink 4 of the frame 31, the agitating process of the solder 14 a, and the mounting process of the semiconductor chip 5 onto the heat sink 4 are performed while heating the entire frame 31 including the heat sinks 4, and the frame 31 is cooled to the extent of the room temperature after the mounting process of the semiconductor chip 5 onto the heat sink 4. By this means, the solder 14 a which is in a molten state at the time of mounting the semiconductor chip 5 is solidified, and the semiconductor chip 5 is bonded and fixed to the heat sink 4 by the solidified solder 14 a. This solidified solder 14 a serves as the bonding agent 14.
  • High melting point solder is preferably used for the solder 14 a, and the solder (first solder) having a melting point higher than at least a melting point of the solder (second solder) used for the external terminal (solder ball 8 in this case) formed later on the land 18 is preferably used as the solder 14 a. By this means, even when the solder ball 8 is melted in a connecting process of the solder ball 8 in the step S8 to be described later and a mounting process of the completed semiconductor device 1 (process of mounting the semiconductor device 1 on the wiring board 41 to be described later), the solder 14 a (that is, the bonding agent 14 made of the solder 14 a) for bonding the semiconductor chip 5 and the heat sink 4 can be prevented from being melted. Accordingly, the bonding reliability of the semiconductor chip 5 and the heat sink 4 can be enhanced, and the heat conductivity from the semiconductor chip 5 to the heat sink 4 can be improved, so that the heat dissipation of the semiconductor device 1 can be improved.
  • Next, each heat sink 4 mounted with the semiconductor chip 5 is cut and separated from the frame portion 32 of the frame 31 (step S4). More specifically, the joining portion 33 between the heat sink 4 and the frame portion 32 is cut, so that each heat sink 4 mounted with the semiconductor chip 5 is separated from the frame portion 32 of the frame 31. As shown in FIGS. 17 and 18, individual pieces of the heat sinks 4 each mounted with the semiconductor chip 5 are obtained.
  • Next, as shown in FIGS. 19 and 20, the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21, respectively (step S5). Before performing this step S5, it is necessary to prepare the wiring board 21 in the step S1. Hence, the preparation of the wiring board 21 in the step S1 can be also performed before step S2, simultaneously with the step S2, before the step S3 and after the step S2, simultaneously with the step S3, before the step S4 and after the step S3, simultaneously with the step S4 or before the step S5 and after the step S4.
  • The process of disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5 will be described in detail with reference to FIGS. 21 and 22. The cross-sectional views of FIGS. 21 and 22 show one semiconductor device region 22 of the wiring board 21.
  • In the step S5, as shown in FIG. 21, the heat sink 4 mounted with the semiconductor chip 5 is inserted (plugged) into the through-hole 3 of the wiring board 21 from the upper surface 21 a side (side corresponding to the upper surface 2 a of the wiring board 2) of the wiring board 21. More specifically, the heat sink 4 mounted with the semiconductor chip 5 is inserted into the through-hole 3 of the wiring board 21 in a direction 35 shown by an arrow mark of FIG. 21.
  • As described above, the heat sink 4 has the protruded portion 11 protruding to the outside (in the direction away from the center of the upper surface 9 a) from the side surface of the heat sink 4 in the peripheral edge portion of the upper surface 9 a of the heat sink 4, and in the step S5, the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 so that the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 outside the through-hole 3 and the lower surface of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21.
  • If the heat sink 4 has no protruded portion 11 and any of the cross-section of the heat sink 4 (cross-section parallel to the upper surface 9 a and the lower surface 9 b of the heat sink 4) is the same as or smaller than the planar shape of the through-hole 3 of the wiring board 21 unlike the present embodiment, the heat sink 4 is likely to fall off from the through-hole 3 of the wiring board 21 at the time of inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21.
  • In contrast to this, in the present embodiment, the heat sink 4 is provided with the protruded portion 11. Therefore, when the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 as shown in FIG. 21, the protruded portion 11 of the heat sink 4 is caught on the upper surface 21 a of the wiring board 21 as shown in FIG. 22. Since the protruded portion 11 functions as a stopper, it is possible to prevent the heat sink 4 from falling off from the through-hole 3 of the wiring board 21 in the direction 35. Accordingly, the heat sink 4 can be retained inside the through-hole 3 of the wiring board 21.
  • As described above, the side surface 10 of the heat sink 4 has a tapered shape. On the other hand, the inner wall of the through-hole 3 of the wiring board 21 before the heat sink 4 is inserted does not have the tapered shape, and is formed to be vertical to the upper surface 21 a of the wiring board 21. By this means, by inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21 as shown in FIGS. 21 and 22, the heat sink 4 and the wiring board 21 can be caulked by the tapered shape of the side surface 10 of the heat sink 4, so that the heat sink 4 can be fixed to the wiring board 21.
  • More specifically, when the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 in the step S5, since the side surface 10 of the heat sink 4 contacts to the inner wall of the through-hole 3 of the wiring board 21 and the inner wall of the through-hole 3 of the wiring board 21 is pushed and expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4, the side surface 10 of the heat sink 4 is fastened up by the inner wall of the through-hole 3 of the wiring board 21 by its reaction. In this manner, the heat sink 4 is fixed to the wiring board 21.
  • Therefore, as shown in FIG. 22, in a state in which the heat sink 4 is disposed (inserted) inside the through-hole 3 of the wiring board 21 in the step S5, the side surface 10 of the heat sink 4 contacts and adheres to the inner wall of the through-hole 3 of the wiring board 21, and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21. This state is maintained in the manufactured semiconductor device 1.
  • Next, as shown in FIGS. 23 and 24, a wire bonding process is performed, so that each of the electrodes 5 a of the semiconductor chip 5 and the connecting terminals 17 formed in the wiring board 21 corresponding to the electrodes are electrically connected through the bonding wires 6 (step S6). More specifically, a plurality of connecting terminals 17 of each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 and a plurality of electrodes 5 a of the semiconductor chip 5 bonded on (mounted on) the heat sink 4 disposed inside the through-hole 3 of the semiconductor device region 22 are electrically connected through a plurality of bonding wires 6, respectively.
  • After the wire bonding process, as shown in FIG. 25, resin sealing by a molding process (for example, transfer molding process) is performed to form a sealing resin 7 a (sealing portion), and the semiconductor chip 5 and the bonding wire 6 are sealed (resin-sealed) by the sealing resin 7 a (step S7).
  • In FIG. 25, a collective sealing for collectively sealing the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 a is performed in the molding process in the step S7. More specifically, the sealing resin 7 a is formed on the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 so as to cover the semiconductor chips 5 and the bonding wires 6. In this case, the sealing resin 7 a is formed so as to cover the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21. The sealing resin 7 a is made of, for example, a resin material such as the thermosetting resin material and can contain the filler and the like. For example, it is also possible to form the sealing resin 7 a by using the epoxy resin containing the filler and the like. For example, the sealing resin 7 a can be formed by injecting the sealing resin material into a cavity of the metal mold disposed on the wiring board 21 and then heating and hardening this sealing resin material by heating.
  • After the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 in the step S5, a state in which the upper surface 21 a of the wiring board 21 is directed upward without turning the wiring board 21 upside down is preferably maintained until the molding process in the step S7 is performed. More specifically, after disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5, the wiring board 21 has the upper surface 21 a directed upward so that the lower surface 21 b thereof is not directed upward until the molding process in the step S7 is performed. As a result, the falling off of the heat sink 4 from the through-hole 3 of the wiring board 21 before the sealing resin 7 a is formed can be prevented more precisely. By forming the sealing resin 7 a, the heat sink 4 and the wiring board 21 are solidly bonded by the sealing resin 7 a, and therefore, after forming the sealing resin 7 a, the wiring board 21 may be directed to any direction (lower surface 21 b of the wiring board 21 may be directed upward).
  • Also, even when the side surface 10 of the heat sink 4 does not have the tapered shape (that is, when α=0), though the bonding power (fixing power) of the heat sink 4 and the wiring board 21 is weak, the heat sink 4 can stay inside the through-hole 3 of the wiring board 21 due to the presence of the protruded portion 11 if a state in which the wiring board 21 is not turned upside down and the upper surface 21 a of the wiring board 21 is directed upward is maintained after the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 in the step S5 until the molding process in the step S7 is performed. Hence, even when the side surface 10 of the heat sink 4 does not have the tapered shape (that is, when a=0), it is possible to manufacture the semiconductor device 1 by inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21. However, if the bonding power of the heat sink 4 and the wiring board 21 is weak, the heat sink 4 is likely to fall off from the wiring board 21 or to oscillate during the manufacturing process (steps S5 to S7) of the semiconductor device, and therefore, it is preferable to enhance the bonding power of the heat sink 4 and the wiring board 21 to some extent. Hence, in the present embodiment, as described above, the side surface 10 of the heat sink 4 is inclined so as to have the tapered shape, thereby caulking the heat sink 4 and the wiring board 21. By this means, the bonding power (fixing power) of the heat sink 4 and the wiring board 21 can be enhanced, and thus, the heat sink 4 can be fixed and stabilized in the wiring board 21. As a result, since it is possible to prevent the heat sink 4 from falling off from the wiring board 21 or oscillating during the manufacturing process of the semiconductor device (steps S5 to S7), the semiconductor device can be stably manufactured. Therefore, the manufacture of the semiconductor device is facilitated, and further, the manufacturing yield of the semiconductor device can be improved.
  • Next, as shown in FIG. 26, the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21 (step 8). For example, after the lower surface 21 b of the wiring board 21 is directed upward, the plurality of solder balls 8 are disposed on the plurality of lands 18 of the lower surface 21 b of the wiring board 21 and are temporally fixed by a flux and the like, and then, a solder reflow process (reflow process, heat treatment) is performed to melt and solidify the solder again, so that the solder balls 8 and the lands 18 of the lower surface 21 b of the wiring board can bonded and electrically connected to each other. Thereafter, a cleaning process is performed as needed, thereby removing the flux and the like adhered on the front surface of the solder balls 8. In this manner, in the step S8, the solder balls 8 as the external terminals of the semiconductor device 1 are formed on the lands 18 of the lower surface 21 b of the wiring board 21.
  • The solder ball 8 bonded to the lower surface 21 b of the wiring board 21 can be taken as a bump electrode (solder bump). Note that the case where the solder ball 8 as the external terminal of the semiconductor device 1 is bonded to the land 18 has been described in the present embodiment, but this is not restrictive, and for example, a bump electrode (solder bump) as the external terminal of the semiconductor device 1 can be also formed on the land 18 by supplying the solder onto the land 18 by a printing method and the like in place of the solder ball 8. For the material of the external terminal (here, solder ball 8) of the semiconductor device 1, any of lead-containing solder and lead-free solder not containing lead can be used, and the lead-free solder not containing lead is more preferably used.
  • Next, marking is performed as needed, and a mark such as a product number and the like is applied onto the front surface of the sealing resin 7 a (step 9). For example, a laser mark for performing the marking by laser can be performed, and an ink mark for performing the marking by an ink can be also performed. Also, the connecting process of the solder ball 8 in the step S8 and the marking process in the step 9 can be interchanged in their order, so that the connecting process of the solder ball 8 in the step S8 is performed after performing the marking process in the step S9. If not required, the marking process in the step S9 can be omitted.
  • Next, the wiring board 21 and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22 (step S10). By performing the dicing and segmentation into individual pieces in this manner, the semiconductor device 1 as shown in FIGS. 1 to 3 can be manufactured. The wiring board 21 diced and separated (divided) into each semiconductor device region 22 corresponds to the wiring board 2, and the sealing resin 7 a diced and separated (divided) into each semiconductor device region 22 corresponds to the sealing resin 7. Further, the upper surface 21 a of the wiring board 21 becomes the upper surface 2 a of the wiring board 2 and the lower surface 21 b of the wiring board 21 becomes the lower surface 2 b of the wiring board 2.
  • While FIGS. 25 and 26 show the case where a collective sealing is performed in the molding process in the step S7, it is also possible to perform an individual sealing (divided sealing) to seal each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 in the molding process in the step 7. The case where the individual sealing is performed will be described with reference to FIGS. 27 to 29.
  • FIGS. 27 and 28 are cross-sectional views in another manufacturing process of the semiconductor device 1 of the present embodiment, and they correspond to FIGS. 25 and 26, respectively. While FIGS. 25 and 26 show the cases where the collective sealing is performed in the molding process in the step S7, FIGS. 27 and 28 correspond to the case where the individual sealing for sealing each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 is performed in the molding process in the step S7. Also, FIG. 29 is a cross-sectional view (side cross-sectional view) of the semiconductor device 1 manufactured in the case where the individual sealing is performed in the molding process in the step S7 (case of FIGS. 27 and 28), and it corresponds to FIG. 1.
  • After the wire bonding process in the step S6, the molding process (resin sealing process) in the step S7 is performed, and the sealing resin 7 is formed so as to seal (resin-seal) the semiconductor chip 5 and the bonding wire 6 by the sealing resin 7 as shown in FIG. 27. At this time, as shown in FIG. 27, the individual sealing (divided sealing) for individually sealing each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 by the sealing resin 7 is performed. More specifically, the sealing resin 7 is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on each semiconductor device region 22 of the upper surface 21 a of the wiring board 21. In this case, the sealing resin 7 is formed for each semiconductor device region 22 of the upper surface 21 a of the wiring board 21. The sealing resin 7 is made of, for example, a resin material such as the thermosetting resin material and can contain the filler and the like. For example, it is also possible to form the sealing resin 7 by using the epoxy resin containing the filler and the like. For example, the sealing resin 7 can be formed by injecting the sealing resin material into a cavity of the metal mold disposed on the wiring board 21 and then hardening this sealing resin material by heating.
  • Next, in the step S8, as shown in FIG. 28, the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21. Since the connecting process of the solder balls 8 in the step S8 is the same as the case of performing the collective sealing (case of FIGS. 25 and 26), the description thereof will be omitted here.
  • Next, the marking in the step 9 is performed as needed, and a mark such as the product number and the like is applied onto the sealing resin 7. Since the marking process in the step S9 is the same as the case of performing the collective sealing (case of FIGS. 25 and 26), the description thereof will be omitted here.
  • Next, the cutting process in the step S10 is performed, and the wiring board 21 is cut (diced) and separated (divided) into each semiconductor device region 22. By performing the dicing and segmentation into individual pieces in this manner, the semiconductor device 1 as shown in FIG. 29 can be manufactured. The wiring board 21 diced and separated (divided) into each semiconductor device region 22 corresponds to the wiring board 2, and the upper surface 21 a of the wiring board 21 becomes the upper surface 2 a of the wiring board 2 and the lower surface 21 b of the wiring board 21 becomes the lower surface 2 b of the wiring board 2. Note that, when the collective sealing is performed in the step S7 (case of FIGS. 25 and 26), the wiring board 21 and the sealing resin 7 a thereon are cut in the cutting process in the step S10, but when the individual sealing is performed in the step S7 (case of FIGS. 27 and 28), only the wiring board 21 is cut in the cutting process in the step S10 and the sealing resin 7 is not cut. Hence, the sealing resin 7 formed by the molding process in the step 7 is not cut and becomes the sealing resin 7 of the semiconductor device 1.
  • Since the semiconductor device 1 of FIG. 29 has almost the same structure as the semiconductor device 1 of FIG. 1 except that the sealing resin 7 is not formed on the peripheral edge portion of the upper surface 2 a of the wiring board 2 and the sealing resin 7 is formed on the region other than the peripheral edge portion of the upper surface 2 a of the wiring board 2, the description thereof will be omitted. The perspective plan view of the semiconductor device 1 of FIG. 29 is the same as that of FIG. 2, and the lower surface view thereof is the same as that of FIG. 3.
  • In the manufacturing process described with reference to FIGS. 8 to 28, after mounting the semiconductor chip 5 on the heat sink 4, the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21. As another manufacturing process of the semiconductor device 1, it is also possible to dispose the heat sink 4 inside the through-hole 3 of the wiring board 21 before mounting the semiconductor chip 5 on the heat sink 4, and then, mount the semiconductor chip 5 on the heat sink 4 disposed inside the through-hole 3 of the wiring board 21. This case will be described with reference to FIGS. 30 to 38.
  • FIG. 30 is a process flowchart showing another manufacturing process of the semiconductor device 1 of the present embodiment. FIGS. 31 to 38 are plan views or cross-sectional views in another manufacturing process of the semiconductor device 1 of the present embodiment. Of FIGS. 31 to 38, FIGS. 31, 35 and 37 are plan views, and FIGS. 32 to 34 and FIGS. 36 and 38 are cross-sectional views. Note that FIG. 32 corresponds to the cross-sectional view cut along the line A5-A5 of FIG. 31. The position of the line A5-A5 of FIG. 31 is the same as the position of A3-A3 of FIG. 9. FIG. 36 shows the cross-section of the same position as FIG. 32, but corresponds to the same process stage as FIG. 35. FIG. 38 shows the cross-section of the same position as FIG. 32, but corresponds to the same process stage as FIG. 37.
  • First, in the steps S1 and S2, the wiring board 21 and the frame 31 are prepared. It does not matter if the wiring board 21 is prepared first, the frame 31 is prepared first or the wiring board 21 and the frame 31 are prepared at the same time.
  • Next, in the step S3, each heat sink 4 of the frame 31 is cut and separated from the frame portion 32 of the frame 31, and then, as shown in FIGS. 31 and 32, the heat sink 4 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in the step S5. In the manufacturing process described with reference to FIGS. 8 to 28, the heat sink 4 mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21, whereas the heat sink 4 not mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in FIGS. 31 and 32.
  • FIGS. 33 and 34 correspond to FIGS. 21 and 22, respectively, in which one semiconductor region 22 of the wiring board 21 is shown. In the step S5, as shown in FIG. 33, the heat sink 4 (heat sink 4 not mounted with the semiconductor chip 5) is inserted (plugged) into the through-hole 3 of wiring board 21 from the upper surface 21 a side of the wiring board 21 (side corresponding to the upper surface 2 a of the wiring board 2). More specifically, the heat sink 4 is inserted into the through-hole 3 of the wiring board 21 in the direction 35 shown by the arrow mark of FIG. 33 to achieve the state of FIG. 34.
  • Since the segmentation into the individual pieces of the heat sink 4 in the step S4 and the disposition of the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5 are performed similarly to the manufacturing process described with reference to FIGS. 8 to 28 except that the semiconductor chip 5 is not mounted on the heat sink 4, the detailed description thereof will be omitted here.
  • After the heat sink 4 is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 in the step S4, the semiconductor chip 5 is mounted and bonded on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 through the bonding agent 14 (step S3 a). The bonding process of the semiconductor chip 5 in the step S3 a can be performed as follows.
  • That is, as shown in FIGS. 35 and 36, a conductive paste material, preferably silver paste 14 b is coated on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21. Then, as shown in FIGS. 37 and 38, the semiconductor chip 5 is mounted on the upper surface 9 a of the heat sink 4 disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21 through the silver paste 14 b. Thereafter, heat treatment and the like are performed so as to harden the silver paste 14 b. By this means, the silver past 14 b in a paste state at the time of mounting the semiconductor chip 5 is hardened, and the semiconductor chip 5 is boded and fixed to the heat sink 4 by the hardened silver paste 14 b. This hardened silver paste 14 b serves as the bonding agent 14.
  • The subsequent process is the same as the manufacturing process described with reference to FIGS. 23 to 28. More specifically, the wire bonding process in the step S6 is performed as shown in FIGS. 23 and 24, the resin sealing process in the step S7 is performed as shown in FIG. 25 or FIG. 27, the connecting process of the solder balls 8 in the step S9 is performed as shown in FIG. 26 or 28, the marking process in the step S9 is performed as needed, and the cutting process in the step S10 is performed. In this manner, the semiconductor device 1 as shown in FIG. 1 or FIG. 29 is manufactured.
  • The wiring board 21 composed of a resin board is low in durability to high temperature heat treatment as compared with the frame 31 (heat sink 4) made of a metal material. In the manufacturing process described with reference to FIG. 8, the semiconductor chip 5 is bonded on the heat sink 4 in the step S3 before disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5, and therefore, the wiring board 21 is not heated at the time of heat treatment of the bonding process of the semiconductor chip 5 in the step S3. Hence, the high temperature heat treatment can be performed for the heat treatment of the bonding process of the semiconductor chip 5 in the step S3 without regard to the heat resistance of the wiring board 21. Therefore, in the case where the high temperature heat treatment is performed for the heat treatment of the bonding process of the semiconductor chip 5 in the step S3, for example, when the semiconductor chip 5 is bonded on the heat sink 4 by using the solder 14 a having a melting point higher than that of the solder (second solder) used for the external terminal (here, solder ball 8) formed on the land 18, it is preferable that the manufacturing process described with reference to FIG. 8 is applied because the wiring board 21 does not suffer from damages at the time of solder reflow in the bonding process of the semiconductor chip 5 in the step S3.
  • More specifically, the solder reflow temperature at the time of mounting the semiconductor device 1 when using the lead-free solder for the solder ball 8 (at the time of mounting the semiconductor to the wiring board 41 to be described later) is, for example, about 220° C., and the solder reflow temperature at the time of mounting the semiconductor device 1 when using the lead-containing solder for the solder ball 8 (at the time of mounting the semiconductor to the wiring board 41 to be described later) is, for example, about 180° C. On the other hand, the solder reflow temperature in the step S3 in which the high melting point solder is used for the solder 14 a is preferably 350 to 400° C., but there is the possibility that the wiring board 21 cannot endure such a high temperature. In the manufacturing process described with reference to FIG. 8, the semiconductor chip 5 is bonded on the heat sink 4 in the step S3 before disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5, and therefore, there arises no problem of the durability of the wiring board 21 at the time of solder reflow.
  • Further, if the solder is used as the bonding agent 14, the heat conductivity of the bonding agent 14 is increased as compared with a case of using the silver paste, and therefore, the heat conductivity to the heat sink 4 from the semiconductor chip 5 is more increased, so that the heat dissipation of the semiconductor device 1 can be more improved.
  • On the other hand, since the semiconductor chip 5 is bonded on the heat sink 4 in the step S3 a after disposing the heat sink 4 inside the through-hole 3 of the wiring board 21 in the step S5 in the manufacturing process described with reference to FIG. 30, the wiring board 21 is heated at the time of the heat treatment of the bonding process of the semiconductor chip 5 in the step S3 a. Hence, when the manufacturing process described with reference to FIG. 30 is performed, it is preferable that the heat treatment at a very high temperature is not performed for the heat treatment of the bonding process of the semiconductor chip 5 in the step S3 a, and the semiconductor chip 5 is preferably bonded on the heat sink 4 by using the silver paste 14 b as described above because the wiring board 21 does not suffer from damages at the time of the heat treatment for hardening the bonding agent (silver paste 14 b) in the bonding process of the semiconductor chip 5 in the step S3 a.
  • Also, the case where the wiring board 21 and the heat sink 4 (frame 31) are separately prepared, and then, the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 in the step S5 has been described, but as another embodiment, the step S5 is performed on a board manufacturer side to prepare the wiring board 21 in a state where the heat sink 4 is already disposed inside the through-hole 3, and the wiring board 21 in this state is received from the board manufacturer to perform the subsequent process on the semiconductor device manufacturer side.
  • For the improvement of the heat dissipation properties of the semiconductor device, the thickness of the heat sink 4 mounted with the semiconductor chip 5 is preferably increased. However, the weight of the heat sink 4 becomes heavy as the thickness of the heat sink 4 is increased. Meanwhile, in the structure of the present embodiment, as described above, the heat sink 4 is inserted into the through-hole 3 from the upper surface 21 a (upper surface 2 a of the wiring board 2) side of the wiring board 21, the protruded portion 11 is located on the upper surface 21 a of the wiring board 21, and the lower surface 12 of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21, so that the protruded portion 11 supports the weight of the heat sink 4. Therefore, even if the thickness of the heat sink 4 is increased and the heat sink 4 becomes heavy, the heat sink 4 is firmly supported by the protruded portion 11, so that the heat sink 4 can be prevented from falling off from the wiring board 21. Consequently, the thickness of the heat sink 4 (thickness t1) can be increased and preferably can be made larger than the thickness of the wiring board 21 (that is, thickness t2 of the wiring board 2), and it is thus possible to improve the heat dissipation properties of the semiconductor device. The same thing is true in the following second, fourth, and fifth embodiments, but those operating similarly to the protruded portion 11 of the present embodiment are the protruded portion 11 a in the following second embodiment and the joining portions 33 a in the following fourth and fifth embodiments.
  • Also, since the resin sealing process is performed in a state where the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 and the lower surface 12 of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21 for supporting the heat sink 4, this state (that is, a state where the protruded portion 11 is located on the upper surface 21 a of the wiring board 21 and the lower surface 12 of the protruded portion 11 contacts to the upper surface 21 a of the wiring board 21) is maintained even in the manufactured semiconductor device. The same thing is true in the following second, fourth, and fifth embodiments, but those operating similarly to the protruded portion 11 of the present embodiment are the protruded portion 11 a in the following second embodiment and the joining portions 33 a in the following fourth and fifth embodiments.
  • Since the weight of the heat sink 4 itself operates in the direction to fix the heat sink 4 to the wiring board 21, even if the fixing power of the heat sink 4 and the wiring board 21 by the tapered shape of the side surface 10 of the heat sink 4 is not so strong, the heat sink 4 can be fixed to the wiring board 21, and the process up to the resin sealing can be performed appropriately.
  • Also, since the heat sink 4 used in the present embodiment has a simple structure, the processing of the heat sink 4 (frame 31 connecting the heat sinks 4) is easy, and the manufacturing cost of the heat sink 4 (frame 31) can be reduced, so that the manufacturing cost of the semiconductor device can be reduced. Further, by inserting the heat sink 4 into the through-hole 3 from the upper surface 21 a side of the wiring board 21, the heat sink 4 can be fixed to the wiring board 21 by the tapered shape of the heat sink 4, and therefore, the heat sink 4 can be fixed to the wiring board 21 by a simple operation, and the manufacturing process of the semiconductor device is facilitated.
  • Next, the mounting of the semiconductor device 1 will be described.
  • FIG. 39 is a cross-sectional view (side cross-sectional view) showing a state in which the semiconductor device 1 of the present embodiment is mounted on a wiring board 41.
  • The wiring board (mounting board) 41 shown in FIG. 39 is a mounting board for mounting the semiconductor device 1, and an upper surface (front surface, main surface) 41 a which is a mounting surface for mounting the semiconductor device 1 is provided with a plurality of board side terminals (terminals, electrodes, pad electrodes, conductive lands) 42 for connecting the plurality of solder balls 8 of the semiconductor device 1, respectively. Although FIG. 39 shows a cross-sectional structure of the wiring board 41 in a simplified manner, the wiring board 41 is preferably a multilayer wiring board 41 (multilayer board), in which a plurality of insulating layers (dielectric layers, insulating base material layers) and a plurality of wiring layers (conductive layers, conductive pattern layers) are stacked and integrated. The board side terminal 42 is a terminal for connecting the solder ball 8 (bump electrode) which is the external terminal of the semiconductor device 1, and the board side terminal 42 is disposed at the position opposite to (planarly overlapped with) the solder ball 8 when the semiconductor device 1 is mounted on the upper surface 41 a of the wiring board 41.
  • For mounting the semiconductor device 1 on a wiring board 31, after the solder paste (this solder paste is integrated with the solder ball 8 by the solder reflow) is supplied to a plurality of board side terminals 42 of the wiring board 41 by a printing method or the like, the semiconductor device 1 is mounted (disposed) on the wiring board 41 so that the positions of the solder balls 8 of the semiconductor device 1 and the board side terminals 42 of the wiring board 41 are matched, and then, the solder reflow treatment is performed.
  • By this means, as shown in FIG. 39, the semiconductor device 1 is mounted (solder-mounted) on the wiring board 41 and the semiconductor device 1 is fixed to the wiring board 41, and at the same time, the plurality of solder balls 8 as the external terminals of the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41, respectively. Therefore, a plurality of electrodes 5 a of the semiconductor chip 5 in the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41 through the plurality of bonding wires 6, the plurality of connecting terminals 17 and wires of the wiring board 2, the conductors and the lands 18 inside the through-holes (not shown) of the wiring board 2, and the plurality of solder balls 8. Further, electronic parts and the like other than the semiconductor device 1 can be also mounted as needed on the region other than mounting region of the semiconductor device 1 on the upper surface 41 a of the wiring board 41. In the case of FIG. 39, the heat sink 4 of the semiconductor device 1 is not connected to the board side terminal of the wiring board 41.
  • When the heat sink 4 of the semiconductor device 1 is not connected to the board side terminal of the wiring board 41 as shown in FIG. 39, the heat generated in the semiconductor chip of the semiconductor device 1 is dissipated into the atmosphere through the heat sink 4.
  • As another mounting method of the semiconductor device 1, the heat sink 4 of the semiconductor device 1 can be connected to the board side terminal of the wiring board 41 at the time of mounting the semiconductor device 1 on the wiring board 41. FIG. 40 is a cross-sectional view (side cross-sectional view) of the case where the heat sink 4 of the semiconductor device 1 is connected to the board side terminal of the wiring board 41 at the time of mounting the semiconductor device 1 on the wiring board 41.
  • As compared with the case of FIG. 39, the wiring board 41 shown in FIG. 40 is further provided with a board side terminal (terminal, electrode) 42 a for connecting the heat sink 4 of the semiconductor device 1 on the upper surface 41 a. The board side terminal 42 a is a terminal for connecting the heat sink 4 of the semiconductor device 1, and the board side terminal 42 a is disposed at the position opposite to (planarly overlapped with) the heat sink 4 at the time of mounting the semiconductor device 1 on the upper surface 41 a of the wiring board 41. The planar dimension of the board side terminal 42 a for connecting the heat sink 4 is larger than the planar dimension of the board side terminal 42 for connecting the solder ball 8.
  • For mounting the semiconductor device 1 on the wiring board 41, after the solder paste is supplied on the plurality of board side terminals 42 and 42 a of the wiring board 41 by the printing method or the like, the semiconductor device 1 is mounted (disposed) on the wiring board 41 so that the positions of the solder balls 8 of the semiconductor device 1 and the board side terminals 42 of the wiring board 41 are matched, and then, the solder reflow treatment is performed. The solder paste supplied on the board side terminal 42 is integrated with the solder ball 8 by the solder reflow, and the solder paste supplied on the board side terminal 42 a is molten and solidified by the solder reflow to become solder 43.
  • By this means, as shown in FIG. 40, the semiconductor device 1 is mounted (solder-mounted) on the wiring board 41 and the semiconductor device 1 is fixed to the wiring board 41, and at the same time, the plurality of solder balls 8 as the external terminals of the semiconductor device 1 are electrically connected to the plurality of board side terminals 42 of the wiring board 41, respectively, and moreover, (lower surface 9 b of) the heat sink 4 of the semiconductor device 1 is bonded and electrically connected to the board side terminal 42 a of the wiring board 41 through the solder 43. The board side terminal 42 is preferably a ground terminal.
  • When the heat sink 4 of the semiconductor device 1 is connected to the board side terminal 42 a of the wiring board 41 by the solder 43 as shown in FIG. 40, the heat generated in the semiconductor chip 5 of the semiconductor device 1 is dissipated to the wiring board 41 through the heat sink 4 and the solder 43. By connecting the heat sink 4 to the board side terminal 42 a of the wiring board 41 by the solder 43, the heat dissipation properties of the semiconductor device 1 can be more improved.
  • FIG. 41 is another cross-sectional view (side cross-sectional view) showing a state in which the semiconductor device 1 is mounted on the wiring board 41. As shown in FIG. 41, the electrode 5 d (preferably, the electrode for ground potential) of the plurality of electrodes 5 a of the semiconductor chip 5 can be electrically connected to the heat sink 4 through the bonding wire 6 a (bonding wire 6 a of the bonding wires 6). In this case, by connecting the heat sink 4 of the semiconductor device 1 to the board side terminal 42 a of the wiring board 41 by solder 42 a at the time of mounting the semiconductor device 1 on the wiring board 41, the electrode 5 d of the semiconductor chip 5 can be electrically connected to the board side terminal 42 a of the wiring board 41 through the bonding wire 6 a, the heat sink 4 and the solder 43. If a ground terminal is used as the board side terminal 42 a of the wiring board 41, the ground potential can be supplied to the heat sink 4 and the electrode 5 d of the semiconductor chip 5 from the board side terminal 42 a of the wiring board 41 by mounting the semiconductor device 1 on the wiring board 41.
  • FIG. 42 is a cross-sectional view of another modified example of the semiconductor device 1 (semiconductor device of a modified example). In the semiconductor device 1 of FIGS. 1 to 3, the chip mounting surface (surface mounted with the semiconductor chip 5, upper surface 9 a) of the heat sink 4 is located almost on the same plane as the upper surface 2 a of the wiring board 2. In contrast to this, in the semiconductor device of FIG. 42 (modified example of the semiconductor device 1), the upper surface 9 a of the heat sink 4 is recessed and the semiconductor chip 5 is mounted on the recessed surface, and thus, the chip mounting surface of the heat sink 4 (surface mounted with the semiconductor chip 5) is lower than the upper surface 2 a of the wiring board 2. Therefore, as compared with the semiconductor device 1 of FIGS. 1 to 3, a height position of the upper surface of the semiconductor chip 5 is lowered and a height position of the top of the bonding wire 6 is lowered in the semiconductor device of FIG. 42 (modified example of the semiconductor device 1), so that the thickness of the sealing resin 7 can be reduced, and the semiconductor device can be made more thinner. This can be applied to the semiconductor devices of the following other modified examples and the semiconductor devices of the following second, fourth and fifth embodiments.
  • FIGS. 43 to 45 are a cross-sectional view (side cross-sectional view), a perspective plan view (upper surface view) and a lower surface view (bottom view, rear surface view, plan view) of still another modified example of the semiconductor device 1 (semiconductor device of modified example). FIG. 44 shows a perspective plan view when the sealing resin 7 is seen through, and the cross-section cut along the line A6-A6 of FIG. 44 almost corresponds to the cross-sectional view of FIG. 43. FIG. 45 is a lower surface view.
  • In the semiconductor device 1 of FIGS. 1 to 3, the semiconductor chip contained inside the semiconductor device 1 is only one, and the one semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2. In contrast to this, in the semiconductor device of FIGS. 43 to 45, a plurality of semiconductor chips (two chips in this case) are contained inside the semiconductor device, and one semiconductor chip 5 is mounted on the heat sink 4 disposed inside the through-hole 3 of the wiring board 2 and a semiconductor chip 5 e other than the semiconductor chip 5 is mounted and bonded on the upper surface 2 a of the wiring board 2 through a bonding agent 14 c instead of on the heat sink 4.
  • More specifically, in the semiconductor device of FIGS. 43 to 45, the semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2, and the electrodes on the upper surface of this semiconductor chip 5 e are electrically connected to the connecting terminals 17 on the upper surface 2 a of the wiring board 2 through the bonding wires 6, and the sealing resin 7 seals the semiconductor chips 5 and 5 e and the bonding wires 6 connected to the electrodes thereof.
  • FIG. 46 is a perspective plan view (upper surface view) of still another modified example of the semiconductor device 1 (semiconductor device of the modified example), and a perspective plan view when the sealing resin 7 is seen through is shown.
  • In the semiconductor device of FIGS. 43 to 45, one semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2. Meanwhile, in the semiconductor device of FIG. 46, still one more semiconductor chip 5 f is mounted and bonded through the bonding agent in addition to the semiconductor chip 5 e in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2. The electrodes on the upper surface of this semiconductor chip 5 f are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 6, and the sealing resin 7 seals the semiconductor chips 5, 5 e and 5 f and the bonding wires 6 connected to the electrodes thereof.
  • FIG. 47 is a cross-sectional view (side cross-sectional view) of still another modified example of the semiconductor device 1 (semiconductor device of the modified example). In the semiconductor device of FIG. 46, the semiconductor chip 5 e and the semiconductor chip 5 f are disposed in the different regions on the upper surface 2 a of the wiring board 2 so as not to be overlapped with each other, whereas the semiconductor chip 5 f is stacked on the semiconductor chip 5 e in the semiconductor device of FIG. 47. More specifically, in the semiconductor device of FIG. 47, the semiconductor chip 5 e is mounted and bonded through the bonding agent 14 c in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2, and the semiconductor chip 5 f is mounted and bonded through the bonding agent 14 d on the upper surface of this semiconductor chip 5 e. The electrodes of the upper surface of the semiconductor chip 5 e are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 6, and the electrodes of the upper surface of the semiconductor chip 5 f are electrically connected to the connecting terminals 17 of the upper surface 2 a of the wiring board 2 through the bonding wires 5, and the sealing resin 7 seals the semiconductor chips 5, 5 e and 5 f and the bonding wires 6 connected to the electrodes thereof.
  • Further, the number of semiconductor chips disposed in the region not having the through-hole 3 on the upper surface 2 a of the wiring board 2 may be three or more, and the number of stacked semiconductor chips may also be three or more.
  • As shown in the semiconductor device of FIGS. 43 to 45, the semiconductor device of FIG. 46 and the semiconductor device of FIG. 47, the number of semiconductor chips contained in the semiconductor device can be made plural. Since the heat generated in the semiconductor chip 5 mounted on the heat sink 4 can be dissipated by the heat sink 4, a large effect can be achieved if the semiconductor chip having a high calorific value is applied. Hence, when the number of the semiconductor chips contained in the semiconductor device is plural, the semiconductor chip having the highest calorific value of the chips (here, the semiconductor chip 5) is preferably mounted on the heat sink 4. Then, of the plurality of semiconductor chips contained in the semiconductor device, the semiconductor chips (here, the semiconductor chips 5 e and 5 f) having the calorific value lower than the semiconductor chip 5 mounted on the heat sink 4 (semiconductor chip having the highest calorific value) are disposed on the upper surface 2 a of the wiring board 2 (region not having the through-hole 3). By this means, while restraining the number of heat sinks 4 to the minimum, the heat generated in the semiconductor chip having a high calorific value can be dissipated to the outside of the semiconductor device 1 from the heat sink 4, thereby being able to achieve both the reduction in the manufacturing cost of the semiconductor device and the improvement of the heat dissipation properties of the semiconductor device. This can be applied also to the semiconductor devices of the following embodiments.
  • Further, in the semiconductor device of FIGS. 43 to 45, the semiconductor device of FIG. 46 and the semiconductor device of FIG. 47, the semiconductor chips 5 e and 5 f can be made to be a memory chip having a volatile memory (for example, DRAM) or a non-volatile memory (for example, a flash memory) formed therein, and the semiconductor chip 5 can be made to be a control chip (microcomputer) having a control circuit for controlling (the memories of) the semiconductor chips 5 e and 5 f formed therein. In this case, the semiconductor device of FIGS. 43 to 45, the semiconductor device of FIG. 46 and the semiconductor device of FIG. 47 can be taken as SIP (System in Package) semiconductor devices, in which one system is constituted by mounting a plurality of semiconductor chips 5 and 5 e or semiconductor chips 5, 5 e and 5 f provided with integrated circuits having different functions on the wiring board 2 including the heat sink 4, respectively. Since the control chip has a high calorific value as compared with the memory chip, the control chip liable to generate heat (here, the semiconductor chip 5) is mounted on the heat sink 4, thereby improving the heat dissipation properties, and the memory chips (here, the semiconductor chips 5 e and 5 f) are disposed on the upper surface 2 a of the wiring board 2 (region not having the through-hole 3), thereby restraining the number of heat sinks 4 to the minimum and reducing the manufacturing cost of the semiconductor device.
    • Second Embodiment
  • FIGS. 48 and 49 are cross-sectional views (side cross-sectional views) of a semiconductor device la of the second embodiment, FIG. 50 is a perspective plan view (upper surface view) of the semiconductor device la when the sealing resin 7 is seen through, and FIG. 51 is a lower surface view (bottom view, rear surface view, plan view) of the semiconductor device 1 a. A cross-section cut along the line A7-A7 of FIGS. 50 and 51 almost corresponds to FIG. 48, and the cross-section cut along the line A8-A8 of FIGS. 50 and 51 almost corresponds to FIG. 49. Also, FIGS. 52 and 53 are cross-sectional views (side cross-sectional views) of a heat sink 4 a used in the semiconductor device 1 a, FIG. 54 is an upper surface view (plan view) of the heat sink 4 a used in the semiconductor device 1 a, and FIG. 55 is a lower surface view (plan view) of the heat sink 4 a used in the semiconductor device 1 a. The cross-section cut along the line A9-A9 of FIGS. 54 and 55 corresponds to FIG. 52, and the cross-section cut along the line A10-A10 of FIGS. 54 and 55 corresponds to FIG. 53, but FIGS. 52 and 48 show the same cross-sectional positions and FIGS. 53 and 49 show the same cross-sectional positions. Further, FIG. 56 is a cross-sectional view (side cross-sectional view) of the wiring board 2 used for the semiconductor device 1 a, and FIG. 57 is an upper surface view (plan view) of the wiring board 2 used for the semiconductor device 1 a. The cross-section cut along the line A11-A11 of FIG. 57 corresponds to FIG. 56, but FIG. 56 and FIG. 48 show the same cross-sectional positions. Although FIG. 57 is a plan view, hatching is applied to the wiring board 2 and the connecting terminals 17 of its upper surface 2 a so as to make a position and a shape of the through-hole 3 in the wiring board 2 easily understood. In FIG. 50, the position of the through-hole 3 of the wiring board 2 which is invisible and concealed by the heat sink 4 a even when the sealing resin 7 is seen through is shown by a dotted line for easy understanding.
  • The semiconductor device 1 a of the present embodiment has almost the same structure as the semiconductor device 1 of the first embodiment except for the shape of the heat sink 4 a and the caulking method (fixing method) of the heat sink 4 a to the wiring board 2, and therefore, the description thereof will be omitted, and the points different from the semiconductor device 1 of the first embodiment will be mainly described.
  • Also in the semiconductor device 1 a of the present embodiment, the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 2 and the semiconductor chip 5 is mounted (bonded) on the upper surface 9 a of the heat sink 4 a through the bonding agent 14 like in the semiconductor device 1 of the first embodiment. The heat sink 4 a corresponds to the heat sink 4 of the first embodiment and is made of the same material as that of the heat sink 4. While the side surface 10 of the heat sink 4 is tapered, the side surface 10 of the heat sink 4 a (side surface 10 of the heat sink 4 a contacting to the inner wall of the through-hole 3) of the present embodiment is not tapered. In a state in which the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 2, the side surface 10 of the heat sink 4 a contacting to the inner wall of the through-hole 3 is almost vertical to the upper surface 2 a of the wiring board 2 (that is, α=0, L1=L2). Also, the inner wall of the through-hole 3 of the wiring board 2 before inserting the heat sink 4 a is vertical to the upper surface 2 a of the wiring board 2. Hence, when the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 2, the inner wall of the through-hole 3 of the wiring board 2 contacts to the side surface 10 of the heat sink 4 a, but the heat sink 4 a cannot be caulked to the wiring board 2 by utilizing the side wall 10 of the heat sink 4 a. Instead, in the present embodiment, in addition to the same protruded portion 11 as the first embodiment, the heat sink 4 a is further provided with a protruded portion 11 a and a pin portion (caulking portion, caulking pin portion, caulking pin, protruded portion, convex portion) 13 integrally connected to a lower surface 12 a of the protruded portion 11 a and disposed inside a hole portion 15 of the wiring board 2, and the heat sink 4 a is caulked (fixed) to the wiring board 2 by this pin portion 13. More specifically, the structure of the heat sink 4 a is the same as the heat sink 4 of the first embodiment except that the protruded portion 11 a and the pin portion 13 are provided and the taper (inclination) of the side surface 10 is eliminated. The protruded portions 11 and 11 a and the pin portion 13 are integrally formed with the heat sink 4 a and can be taken as a part of the heat sink 4 a.
  • In FIG. 52, a recess is formed on the upper surface of the protruded portion 11 a above the pin portion 13, but this recess is formed as a result of the formation of the pin portion 13, and the recess may not be formed on the upper surface of the protruded portion 11 a above the pin portion 13 depending on a forming method of the pin portion 13.
  • The wiring board 2 of the semiconductor device la of the present embodiment has the same structure as the wiring board 2 of the semiconductor device 1 of the first embodiment except that a hole portion 15 is provided in the vicinity of the through-hole 3. The hole portion 15 is a through-hole reaching a lower surface 2 b from the upper surface 2 a of the wiring board 2 and has sufficiently smaller planar dimensions as compared with the through-hole 3 for inserting a main portion of the heat sink 4 a (portion except for the protruded portions 11 and 11 a and the pin portion 13). The hole portion 15 is provided in the wiring board 2 in such a manner as to stay away from the connecting terminal 17 and the land 18. The pin portion 13 of the heat sink 4 a is fixed inside the hole portion 15 of the wiring board 2.
  • The heat sink 4 a has the protruded portion (projecting portion, overhang portion, hook portion) 11 a protruding to the outside (in the direction away from the center of the upper surface 9 a) from the side surface 10 of the heat sink 4 a (side surface 10 contacting to the inner wall of the through-hole 3 of the wiring board 2) in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a, and this protruded portion 11 a is located on the upper surface 2 a of the wiring board 2 outside the through-hole 3 and the lower surface of the protruded portion 11 a contacts to the upper surface 2 a of the wiring board 2. It is preferable to provide this protruded portion 11 a at the corner portions of the rectangular (rectangular planar shaped) upper surface 9 a of the heat sink 4 because the protruded portion 11 a does not interfere with the disposition of the connecting terminal 17, and it is more preferable to provide the protruded portion 11 a at the four corners of the rectangular upper surface 9 a of the heat sink 4 because the coupling (caulking) of the heat sink 4 and the wiring board 2 is well-balanced.
  • More specifically, the heat sink 4 a has the protruded portions 11 and 11 a protruding to the upper surface 2 a side of the wiring board 2 from above the through-hole 3 and extending on the upper surface 2 a of the wiring board 2 on a peripheral edge portion of the upper surface 9 a of the heat sink 4. The protruded portions 11 and 11 a overhang (project) on the upper surface 2 a of the wiring board 2 from above the through-hole 3, and the protruded portions 11 a of the four corners of the upper surface 9 a extend on the upper surface 2 a of the wiring board 2 up to the position away from the through-hole 3 as compared with the protruded portions 11 other than the four corners of the upper surface 9 a. In other words, in the heat sink 4 a, the protruded portions 11 a are provided at the four corners of the peripheral edge portion of the upper surface 9 a of the heat sink 4, and the protruded portions 11 are provided on the peripheral edge portion of the upper surface 9 a of the heat sink 4 other than the four corners thereof (except for the four corners having the protruded portions 11 a) in a flange shape or in an overhang shape, and the protruded portion 11 a extends on the upper surface 2 a of the wiring board 2 up to the position away from the through-hole 3 as compared with the protruded portion 11 in order to be able to connect the pin portion 13.
  • The protruded portions 11 and 11 a function as a stopper to prevent the heat sink 4 a from falling off from the through-hole 3 of the wiring board 2. Hence, the protruded portions 11 and 11 a are required to be provided at least on a part of the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a. Therefore, even if the protruded portions 11 and 11 a are not provided on the entire peripheral edge portion of the upper surface 9 a of the heat sink 4 a, it is possible to prevent the heat sink 4 a from falling off from the through-hole 3 of the wiring board 2 if the protruded portions 11 and 11 a are provided on at least a part of the peripheral edge portion of the upper surface 9 a of the heat sink 4 a.
  • Also in the heat sink 4 a of the present embodiment, the protruded portions 11 are provided (in a flange shape or in an overhang shape) on the entire peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 a like in the protruded portion 11 of the heat sink 4, and the heat sink 4 a can be stably disposed inside the through-hole 3 of the wiring board 2. However, even when the protruded portions 11 are not present, the heat sink 4 a can be prevented from falling off from the through-hole 3 of the wiring board 2 if the protruded portions 11 a are present. Hence, it is also possible to provide only the protruded portion 11 a by omitting the formation of the protruded portion 11 in the heat sink 4 a.
  • In the heat sink 4 a, the cross-sectional shapes of a portion located inside the through hole 3 and a portion protruding downward from the lower surface 2 b of the wiring board 2 (lower part of the heat sink 4 a) parallel to the upper surface 2 a of the wiring board 2 are almost the same as the planar shape of the through-hole 3 of the wiring board 2, and a side surface (side wall) 10 of the heat sink 4 a contacts to a side surface (side wall) of the through-hole 3 of the wiring board 2. Further, the lower surface 9 b of the heat sink 4 a also has almost the same planar shape as the planar shape of the through-hole 3 of the wiring board 2.
  • The protruded portions 11 and 11 a of the heat sink 4 a are projected (overhung) on the upper surface 2 a of the wiring board 2 from the through-hole 3, and the lower surface 12 of the protruded portion 11 and the lower surface 12 a of the protruded portion 11 a contact to the upper surface 2 a of the wiring board 2. Consequently, in the semiconductor device 1 a, when seen in a plane parallel to the upper surface 2 a of the wiring board 2, the portions other than the protruded portions 11 and 11 a and the pin portions 13 of the heat sink 4 are located at a planarly overlapped position with the through-hole 3, and the protruded portions 11 and 11 a and the pin portions 13 only are located outside the through-hole 3 (at the position not planarly overlapped with the through-hole 3, that is, at the position overlapped with the wiring board 2). For easy understanding, a planar position of the through-hole 3 when the heat sink 4 is disposed inside the through-hole 3 of the wiring board 2 is shown by a dotted line in FIG. 54.
  • Also in the present embodiment, the heat sink 4 a is inserted and fixed into the through-hole 3 from the upper surface 2 a (upper surface 21 a) side of the wiring board 2 (wiring board 21) before the sealing resin 7 is formed like in the first embodiment. Since the heat sink 4 a is provided with the protruded portion 11 a (protruded portions 11 a and 11 when the protruded portion 11 is provided), the protruded portion 11 a (protruded portions 11 a and 11 when the protruded portion 11 is provided) of the heat sink 4 a is caught on the upper surface 2 a of the wiring board 2 (upper surface 21 a of the wiring board 21) at the time of inserting the heat sink 4 a into the through-hole 3 from the upper surface 2 a side of the wiring board 2 (upper surface 21 a side of the wiring board 21), and therefore, it is possible to prevent the heat sink 4 a from falling off from the through-hole 3, and the heat sink 4 a can be retained inside the through-hole 3 of the wiring board 2 (wiring board 21).
  • FIG. 58 is a plan view (upper surface view) of a frame 31 used when the semiconductor device 1 a of the present embodiment is manufactured, and it corresponds to FIG. 11 of the first embodiment. Although FIG. 58 is a plan view, hatching is applied to the frame 31 so as to make a shape of the frame 31 easily understood.
  • In the frame 31 used for manufacturing the semiconductor device 1 a of the present embodiment, as shown in FIG. 58, a joining portion 33 for joining each heat sink 4 a and a frame portion 32 is provided between the frame portion 32 and the protruded portion 11 a of the heat sink 4 a so as to join the protruded portion 11 a of the heat sink 4 a with the frame portion 32. By cutting the joining portion 33 of the frame 31 so as to leave the protruded portion 11 a on the heat sink 4 a side in the step S4 described above, individual pieces of the heat sink 4 a having the protruded portion 11 a (and protruded portion 11 when the protruded portion 11 is present) can be obtained.
  • The manufacturing process of the semiconductor device la of the present embodiment is the same as the manufacturing process of the semiconductor device 1 of the first embodiment except that a caulking method (fixing method) of the heat sink 4 a to the wiring board 21 in the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S5 is different. Hence, the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S5 in the present embodiment will be described below.
  • FIGS. 59 and 60 are explanatory drawings (cross-sectional views) of the process of disposing the heat sink 4 a inside the through-hole 3 of the wiring board 21 in the step S5 in the manufacturing process of the semiconductor device 1 a of the present embodiment, and they correspond to FIGS. 33 and 34 of the first embodiment. Note that, although the case where the heat sink 4 a not mounted with the semiconductor chip 5 is disposed inside the through-hole 3 of the wiring board 21 like in the process described with reference to FIGS. 30 to 34 will be illustrated and described here, also in the present embodiment, the heat sink 4 a mounted with the semiconductor chip 5 can be disposed inside the through-hole 3 of the wiring board 21 after mounting (bonding) the semiconductor chip 5 on the heat sink 4 a like in the process described with reference to FIGS. 8 and 19 to 22.
  • As shown in FIG. 59, the wiring board 21 used for manufacturing the semiconductor device la of the present embodiment is provided with the hole portion 15 for inserting the pin portion 13 of the heat sink 4 a, and has almost the same structure as the wiring board 21 of the first embodiment other than that. However, FIGS. 59 and 60 correspond to the cross-section cut along the line A7-A7 of FIG. 50, and the connecting terminal 17 does not appear in the figure, and the illustration of the land 18 is omitted for the simplification of the drawing.
  • Also in the present embodiment, the heat sink 4 a is inserted (plugged) into the through-hole 3 of the wiring board 21 from the upper surface 21 a side (side corresponding to the upper surface 2 a of the wiring board 2) of the wiring board 21 in the process of disposing the heat sink 4 a into the through-hole 3 of the wiring board 21 in the step S5 as shown in FIG. 59 like in the first embodiment. More specifically, the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 in a direction 35 shown by an arrow mark of FIG. 59. At this time, the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21.
  • The through-hole 3 and the hole portion 15 of the wiring board 21 are disposed at the position so that the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 when the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21. Hence, in the step S5, the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21, and at the same time, the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a can be inserted into the hole portion 15 of the wiring board 21.
  • Since the heat sink 4 a is provided with the protruded portion 11 a (and protruded portion 11 when the protruded portion 11 is provided), when the heat sink 4 a is inserted into the through-hole 3 from the upper surface 21 a side of the wiring board 21 and the pin portion 13 is inserted into the hole portion 15 as shown in FIG. 59, the protruded portion 11 a (and protruded portion 11 when the protruded portion 11 is provided) of the heat sink 4 a is caught on the upper surface 21 a of the wiring board 21 as shown in FIG. 60. This protruded portion 11 a (and protruded portion 11 when the protruded portion 11 provided) functions as a stopper, so that the heat sink 4 a can be prevented from falling off downward, that is, in the direction 35 from the through-hole 3 of the wiring board 21. Consequently, the heat sink 4 a can be retained inside the through-hole 3 of the wiring board 21.
  • As described above, the heat sink 4 a has the protruded portion 11 a protruding to the outside (in the direction away from the center of the upper surface 9 a) from the side surface of the heat sink 4 a in the peripheral edge portion of the upper surface 9 a of the heat sink 4 a, and in the step S5, the main body portion and the pin portion 13 of the heat sink 4 a are disposed inside the through-hole 3 and the hole 15 of the wiring board 21 so that this protruded portion 11 a is located on the upper surface 21 a of the wiring board 21 outside the through-hole 3 and the lower surface 12 a of the protruded portion 11 a contacts to the upper surface 21 a of the wiring board 21.
  • In the first embodiment, the side surface 10 of the heat sink 4 is tapered, so that the portion of the heat sink 4 disposed inside the through-hole 3 is tightened up by the inner wall of the through-hole 3 of the wiring board 21, thereby caulking (fixing) the heat sink 4 to the wiring board 21. In contrast to this, in the present embodiment, the pin portion 13 provided on the lower surface 12 a of the protruded portion 11 a of the heat sink 4 a is used to caulk (fix) the heat sink 4 a to the wiring board 21. A technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a in the present embodiment will be described.
  • FIGS. 61 and 62 are explanatory drawings showing a first technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a. FIGS. 63 to 66 are the explanatory drawings showing a second technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a. FIGS. 67 to 70 are the explanatory drawings showing a third technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a. In each of FIGS. 61 to 70, A and B are cross-sectional views and plan views of the same stage, but the plan view of B corresponds to the plan view (lower surface view) of the region in the vicinity of the hole portion 15 when the wiring board 21 is seen from the lower surface 21 b side and the cross-section cut along the line A12-A12 of the plan view of B corresponds to the cross-sectional view of A. Although FIGS. 61B, 63B and 67B are plan views, hatching is applied to the wiring board 21 so as to make the figures easy to see. Also, although FIGS. 62B, 64B and 68B are plan views, hatching is applied to the wiring board 21 and the pin portions 13 of the heat sink 4 a so as to make the figures easy to see. Further, although FIG. 65B is a plan view, hatching is applied to a washer or ring-shaped member 25 so as to make the figure easy to see. Also, in the plan view of FIG. 66B, the position of the hole portion 15 concealed by the bottom 13 b of the crushed pin portion 13 is shown by a dotted line. Further, although FIG. 69B is a plan view, hatching is applied to the wiring board 21, the pin portion 13 of the heat sink 4 a and a sleeve 26 so as to make the figure easy to see. Also, in the plan view of FIG. 70B, the position of the hole portion 15 concealed by the bottom 13 b of the crushed pin portion 13 is shown by a dotted line.
  • In the present embodiment, the first technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a will be described with reference to FIGS. 61 and 62. FIG. 61 corresponds to a state of FIG. 59, and FIG. 62 corresponds to a state of FIG. 60.
  • The first technique is to form a side wall (side surface) 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape as shown in FIGS. 61 and 62. In other words, the cross-sectional shape of the pin portion 13 of the heat sink 4 a (shape of the cross-section vertical to the upper surface 21 a of the wiring board 21 when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21) has a tapered shape. Hence, the dimension of the pin portion 13 is larger on the upper side (side near the lower surface 12 a of the protruded portion 11 a) than on the lower side. More specifically, the dimension of the pin portion 13 becomes thinner (smaller) as approaching a top end portion 13 b and becomes thicker (larger) as approaching the protruded portion 11 a. In other words, the pin portion 13 is tapered. On the other hand, as shown in FIG. 61, the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted has no tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21. Then, the dimension of the hole portion 15 before the pin portion 13 is inserted is made the same as or slightly larger than the dimension of the top end portion 13 b (top end opposite to the side connected to the lower surface 12 a of the protruded portion 11 a) of the pin portion 13, and moreover, is made smaller than the dimension of the upper portion (portion close to the lower surface 12 a of the protruded portion 11 a) of the pin portion 13.
  • The planar shape (shape in a plane parallel to the upper surface 21 a of the wiring board 21) of the hole portion 15 of the wiring board 21 can be made, for example, circular, and the shape (cross-sectional shape) of the pin portion 13 in the cross-section parallel to the upper surface 21 a of the wiring board 21 when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 can be made the same shape as the through-hole 3, for example, the circular shape.
  • In the step S5, when the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 as shown in FIGS. 59 and 60, the pin portion 13 of the heat sink 4 a is inserted (plugged) into the hole portion 15 of the wiring board 21 as shown in FIGS. 61 and 62, and the pin portion 13 and the wiring board 21 can be caulked (fixed) by the tapered shape of the side wall 13 a of the pin portion 13. By this means, the heat sink 4 a can be fixed to the wiring board 21.
  • More specifically, when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 in the step S5, the side wall 13 a of the pin portion 13 contacts to the inner wall of the hole portion 15 of the wiring board 21, and the inner wall of the hole portion 15 of the wiring board 21 is expanded in a lateral direction by the tapered shape of the side wall 13 a of the pin portion 13, and the side wall 13 a of the pin portion 13 is tightened up by the inner wall of the hole portion 15 of the wiring board 21 by its reaction. By this means, the pin portion 13 can be caulked (fixed) to the wiring board 21, and the heat sink 4 a is fixed to the wiring board 21.
  • As shown in FIG. 62, in a state in which the pin portion 13 of the heat sink 4 a is disposed (inserted) inside the hole portion 15 of the wiring board 21 in the step S5, the side wall 13 a of the pin portion 13 contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21, and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21, and this state is maintained even in the manufactured semiconductor device 1 a.
  • By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the first technique described above, the heat sink 4 a can be fixed to the wiring board 21, and in addition to this, the following advantages can be further obtained. That is, by inserting the pin portion 13 of the heat sink 4 a into the hole portion 15 of the wiring board 21, the heat sink 4 a can be fixed to the wiring board 21, and therefore, the process of disposing and fixing the heat sink 4 a inside the through-hole 3 of the wiring board 21 can be easily performed in the step S5. Therefore, the manufacturing process of the semiconductor device can be simplified, and also, the manufacturing time of the semiconductor device can be reduced. The hole portion 15 into which the pin portion 13 of the heat sink 4 a is inserted can be made smaller than the through-hole 3 into which the main portion of the heat sink 4 a is inserted. When the hole of the wiring board 21 is expanded by the insertion of the tapered member into the hole of the wiring board 21, a stress is likely to occur in the wiring board 21, but in the present embodiment, the dimension of the hole portion 15 is made small (smaller than the through-hole 3), so that a place in which the stress occurs in the wiring board 21 can be restricted to the vicinity of the hole portion 15 and a load to the wiring board 21 can be reduced.
  • Next, in the present embodiment, a second technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a will be described with reference to FIGS. 63 to 66. FIG. 63 corresponds to a state of FIG. 59 and FIG. 64 corresponds to a state of FIG. 60. However, the operations (processes) of FIGS. 65 and 66 are sequentially performed after FIG. 64 in the second technique.
  • As shown in FIG. 63, different form the first technique, the second technique does not form the side wall 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape. Hence, the dimension of the pin portion 13 is the same on the upper surface side and on the lower side (side near the lower surface 12 a of the protruded portion 11 a). Also in the second technique, the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted has no tapered shape, and is kept almost vertical with respect to the upper surface 21 a of the wiring board 21 like in the first technique.
  • Further, the planar shape of the hole portion 15 of the wiring board 21 (shape in a plane parallel to the upper surface 21 a of the wiring board 21) can be made, for example, circular, and the pin portion 13 can be made, for example, columnar. In any case, the dimension of the hole portion 15 before the pin portion 13 is inserted is made the same as or slightly larger than the dimension of the pin portion 13.
  • When the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 in the step S5 as shown in FIGS. 59 and 60, the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 as shown in FIGS. 63 and 64. Since the side wall 13 a of the pin portion 13 has no tapered shape, the side wall 13 a of the pin portion 13 is not tightened up by the inner wall of the hole portion 15 of the wiring board 21 at this stage. Further, in the second technique, the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the thickness of the wiring board 21, so that the top end portion 13 b of the pin portion 13 protrudes from the lower surface 21 b of the wiring board 21 as shown in FIG. 64 at the stage when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21.
  • After the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21, a washer or ring-shaped member (washer, ring, buffer) 25 is fitted (installed) to the portion of the pin portion 13 protruding from the lower surface 21 b of the wiring board 21 as shown in FIG. 65. More specifically, the washer or ring-shaped member 25 is disposed on the lower surface 21 b of the wiring board 21 so that the top end portion 13 b of the pin portion 13 penetrates through it. By this means, the portion of the pin portion 13 protruding from the lower surface 21 b of the wiring board 21 is disposed inside the hole of the washer or ring-shaped member 25.
  • The washer or ring-shaped member 25 is preferably made of a metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the washer or ring-shaped member 25 from the same material as the heat sink 4 a because the heat expansion coefficient of the pin portion 13 and that of the washer or ring-shaped member 25 become the same.
  • Further, in the second technique, the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the total thickness of the wiring board 21 and the washer or ring-shaped member 25, so that the top end portion 13 b of the pin portion 13 protrudes from the washer or ring-shaped member 25 as shown in FIG. 65 at the stage where the washer or ring-shaped member 25 is fitted to the pin portion 13.
  • Then, as shown in FIG. 66, the portion of the pin portion 13 protruding from the lower surface 21 a of the wiring board 21, here, the portion of the pin portion 13 protruding from the washer or ring-shaped member 25 because the washer or ring-shaped member 25 is disposed is crushed by a tool (not shown) and the like. More specifically, the top end portion 13 b of the pin portion 13 is crushed by a tool (not shown) and the like. By this means, the pin portion 13 of the heat sink 4 a and the wiring board 21 can be caulked (fixed), and the heat sink 4 a can be fixed to the wiring board 21.
  • More specifically, since the top end portion 13 b of the pin portion 13 is pressed (crushed), the pin portion 13 is expanded in the lateral direction inside the hole portion 15 of the wiring board 21, and the side wall 13 a of the pin portion 13 contacts to (adheres to) the inner wall of the hole portion 15 of the wiring board 21. Then, by the reaction of the expansion of the inner wall of the hole portion 15 of the wiring board 21 in the lateral direction due to the expansion of the pin portion 13 in the lateral direction, the side wall 13 a of the pin portion 13 is tightened up by the inner wall of the hole portion 15 of the wiring board 21. By this means, the pin portion 13 of the heat sink 4 a can be caulked (fixed) to the wiring board 21, and the heat sink 4 a is fixed to the wiring board 21. In the second technique, the process up to here is performed by the step S5.
  • As described above, by the step S5, the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 21, and the pin portion 13 of the heat sink 4 a is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21. At this stage, the side wall 13 a of the pin portion 13 contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21, and this state is maintained also in the manufactured semiconductor device 1 a.
  • By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the second technique described above, the heat sink 4 a can be fixed to the wiring board 21, and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21, the pin portion 13 is crushed so as to be able to fix the heat sink 4 a to the wiring board 21, and therefore, the heat sink 4 a can be more firmly fixed to the wiring board 21. Hence, it is possible to prevent the heat sink 4 a from falling off from the through-hole 3 of the wiring board 21 more precisely in the manufacturing process of the semiconductor device (until the sealing resin 7 is formed). Further, the hole portion 15 into which the pin portion 13 of the heat sink 4 a is inserted can be made smaller than the through-hole 3 into which the main portion of the heat sink 4 a is inserted. Although there is the possibility that a stress causes in the wiring board 21 by crushing the pin portion 13 inserted into the hole portion 15 of the wiring board 21, a place in which the stress occurs in the wiring board 21 can be restricted to the vicinity of the hole portion by making the dimension of the hole portion 15 small, and a load to the wiring board 21 can be reduced. Further, when the top end portion 13 b of the pin portion 13 is crushed by a tool (not shown) and the like, the washer or ring-shaped member 25 functions as a buffer, and therefore, a load applied to the wiring board 21 (region in the vicinity of the hole portion 15 of the lower surface 21 b) can be reduced.
  • Next, in the present embodiment, a third technique for caulking (fixing) the heat sink 4 a to the wiring board 21 by using the pin portion 13 of the heat sink 4 a will be described with reference to FIGS. 67 to 70. FIG. 67 corresponds to a state of FIG. 59 and FIG. 68 corresponds to a state of FIG. 60. However, the operations (processes) of FIGS. 69 and 70 are sequentially performed after FIG. 68 in the third technique.
  • As shown in FIG. 67, the third technique does not form the side wall 13 a of the pin portion 13 of the heat sink 4 a into a tapered shape like in the second technique. Hence, the dimension of the pin portion 13 is the same on the lower side and on the upper side (side near the lower surface 12 a of the protruded portion 11 a). Further, also in the third technique, the inner wall of the hole portion 15 of the wiring board 21 before the pin portion 13 of the heat sink 4 a is inserted does not have the tapered shape, and is kept almost vertical with respect to the upper surface 21 a of the wiring board 21 like in the first and second techniques.
  • Also, the planar shape (shape in a plane parallel to the upper surface 21 a of the wiring board 21) of the hole portion 15 of the wiring board 21 can be made, for example, circular, and the pin portion 13 can be made, for example, columnar. However, the dimension of the hole portion 15 before the pin portion 13 is inserted is made larger than the dimension of the pin portion 13 so that the sleeve 26 to be described later can be inserted.
  • When the main body portion (portion except for the protruded portions 11 and 11 a and the pin portion 13) of the heat sink 4 a is inserted into the through-hole 3 of the wiring board 21 in the step S5 as shown in FIGS. 59 and 60, the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21 as shown in FIGS. 67 and 68. Since the side wall 13 a of the pin portion 13 has no tapered shape, the side wall 13 a of the pin portion 13 is not tightened up by the inner wall of the hole portion 15 of the wiring board 21 at this stage. Further, in the third technique, the length of the pin portion 13 before being inserted into the hole portion 15 is made larger than the thickness of the wiring board 21, so that the top end portion 13 b of the pin portion 13 protrudes from the lower surface 21 b of the wiring board 21 as shown in FIG. 68 at the stage when the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21.
  • After the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21, as shown in FIG. 69, the sleeve 26 is inserted from the lower surface 21 b side of the wiring board 21 into the hole portion 15 in which the pin portion 13 has been inserted. The sleeve 26 is a tube-shaped or a cylindrical member. More specifically, while disposing (inserting) the pin portion 13 into the hole of the sleeve 26, the sleeve 26 is disposed inside the hole portion 15 of the wiring board 21. Therefore, the sleeve 26 is interposed between the inner wall of the hole portion 15 of the wiring board 21 and the side wall 13 a of the pin portion 13. Hence, the external dimension of the sleeve 26 is made almost the same as or slightly smaller than the hole portion 15 of the wiring board 21, and the dimension of the hole of the sleeve 26 is made almost the same as or slightly larger than the pin portion 13.
  • The sleeve 26 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the sleeve 26 from the same material as the heat sink 4 a because the heat expansion coefficient of the pin portion 13 and that of the sleeve 26 become the same.
  • Then, as shown in FIG. 70, the portion of the pin portion 13 protruding from the lower surface 21 a of the wiring board 21, that is, the top end portion 13 b of the pin portion 13 is crushed by a tool (not shown) and the like. By this means, the pin portion 13 of the heat sink 4 a and the wiring board 21 can be caulked (fixed), and the heat sink 4 a can be fixed to the wiring board 21.
  • More specifically, since the top end portion 13 b of the pin portion 13 is crushed, the top end portion 13 b of the pin portion 13 is expanded in the lateral direction outside the hole portion 15 of the wiring board 21 and the sleeve 26, and the wiring board 21 and the sleeve 26 are sandwiched by the top end portion 13 b of the pin portion 13 expanded in the lateral direction and the protruded portion 11 a, so that the heat sink 4 a can be caulked (fixed) to the wiring board 21 and the heat sink 4 a is fixed to the wiring board 21. In the third technique, the process up to here is performed by the step S5. Further, even if the top end portion 13 b of the pin portion 13 is crushed, the sleeve 26 is interposed between the side wall of the pin portion 13 and the inner wall of the hole portion 15 inside the hole portion 15 of the wiring board 21, and the expansion of the pin portion 13 in the lateral direction is restricted by the sleeve 26, and since this sleeve 26 functions as a buffer, the application of a load to the inner wall of the hole portion 15 of the wiring board 21 can be prevented.
  • As described above, by the step S5, the heat sink 4 a is disposed inside the through-hole 3 of the wiring board 21, and the pin portion 13 of the heat sink 4 a is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21. At this stage, the sleeve 26 is interposed between the inner wall of the hole portion 15 and the side wall 13 a of the pin portion 13 inside the hole portion 15 of the wiring board 21, and this state is maintained even in the manufactured semiconductor device 1 a.
  • By caulking (fixing) the heat sink 4 a to the wiring board 21 by using the third technique described above, the heat sink 4 a can be fixed to the wiring board 21, and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 of the heat sink 4 a is inserted into the hole portion 15 of the wiring board 21, the pin portion 13 is crushed so as to be able to fix the heat sink 4 a to the wiring board 21, and therefore, the occurrence of the falling off of the heat sink 4 a from the through-hole 3 of the wiring board 21 can be reduced. Further, even if the top end portion 13 b of the pin portion 13 is crushed, the expansion of the pin portion 13 in the lateral direction is restricted by the sleeve 26 inside the hole portion 15 of the wiring board 21, and since this sleeve 26 functions as a buffer, the application of a load to the inner wall of the hole portion 15 of the wiring board 21 can be prevented. Therefore, it is possible to prevent the load from being applied to the wiring board 21.
  • Further, since the second and third techniques require the operations (processes) for crushing the top end portion 13 b of the pin portion 13 after the disposition inside the through-hole 3 of the wiring board 21, if the manufacturing process described with reference to FIGS. 30 to 38 is applied, the top end portion 13 b of the pin portion 13 can be crushed in a state in which the semiconductor chip 5 is not mounted on the heat sink 4 a, and therefore, the operation for crushing the pin portion 13 can be easily performed.
  • Further, also in this second embodiment, the side surface of the heat sink 4 a can be tapered like in the first embodiment. In this case, in addition to the fixing by the pin portion 13, the heat sink 4 a can be fixed to the wiring board 21 by the tapered shape of the side surface 10 of the heat sink 4 a, and therefore, a fixing power between the heat sink 4 a and the wiring board 21 can be further strengthened and the stability of the manufacturing process can be further increased.
  • FIG. 71 is an upper surface view (plan view) showing a modified example of the wiring board 2 used for the semiconductor device 1 a, and it corresponds to FIG. 57. In FIG. 71, no hatching is applied.
  • As shown in FIG. 71, in the wiring board 2 (that is, also in the wiring board 21), an angular portion of the through-hole 3 is eliminated so that the four corners can be made circular (to have a round shape). The same is true in the wiring board 2 of the semiconductor device 1 of the first embodiment. By this means, the load generated in the wiring board 21 (wiring board 2) by disposing (inserting) the heat sink 4 or 4 a inside the through-hole 3 of the wiring board 21 (wiring board 2) can be dispersed, and the reliability of the wiring board 2 in the semiconductor devices 1 and 1 a can be further improved.
    • Third Embodiment
  • FIG. 72 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 b of the third embodiment, and it corresponds to FIG. 1 of the first embodiment and FIG. 48 or FIG. 49 of the second embodiment.
  • As shown in FIG. 72, in the semiconductor device 1 b of the present embodiment, a heat sink 4 b is attached to a lower surface 2 b side of the wiring board 2, and the semiconductor chip 5 is mounted on an upper surface 9 c of the heat sink 4 b exposed at the bottom of the through-hole 3 of the wiring board 2. More specifically, the heat sink 4 b is not provided with a portion corresponding to the protruded portions 11 and 11 a, and has a flat plate shape (flat plate shape whose planar shape is rectangular) having the upper surface 9 c and the lower surface 9 d, and a pin portion (caulking portion, pin portion for caulking, caulking pin, protruded portion, convex portion) 13 c is integrally provided with the heat sink 4 b in the vicinity of the peripheral edge portion of the upper surface 9 c of the heat sink 4 b. Further, the heat sink 4 b is disposed on a lower surface 2 b of the wiring board 2 so as to planarly enclose the through-hole 3 of the wiring board 2 and the pin portion 13 c of the heat sink 4 b is disposed inside the hole portion 15 of the wiring board 2, and the heat sink 4 b is fixed to the wiring board 2 by this pin portion 13 c. The structure of the semiconductor device 1 b other than this is almost the same as the semiconductor devices 1 and 1 a of the first and second embodiments, and therefore, the description thereof will be omitted here. Also, the material of the heat sink 4 b is the same as those of the heat sinks 4 and 4 a of the first and second embodiments.
  • The manufacturing process of the semiconductor device 1 b of the present embodiment is the same as the manufacturing processes of the semiconductor devices 1 and 1 a of the first and second embodiments except that the step S5 is different. Hence, the process performed in place of the step S5 (process of disposing the heat sink 4 inside the through-hole 3 of the wiring board 21) in the present embodiment will be described below. For convenience, the process performed in place of the step S5 (process of disposing the heat sink 4 inside the through-hole 3 of the wiring board 21) in the present embodiment will be referred to as step S5 a or a process of fixing the heat sink 4 b to the wiring board 2.
  • FIGS. 73 and 74 are explanatory drawings (cross-sectional views) of the process of fixing the heat sink 4 b to the wiring board 21 in the step S5 in the manufacturing process of the semiconductor device 1 b of the present embedment, and they correspond to FIGS. 59 and 60 of the second embodiment. Here, the case of fixing the heat sink 4 b not mounted with the semiconductor chip 5 to the wiring board 21 like in the process described with reference to FIG. 30 to FIG. 34 will be described. However, also in the present embodiment, the heat sink 4 b mounted with the semiconductor chip 5 can be fixed to the wiring board 21 like in the process described with reference to FIG. 8 and FIGS. 19 to 22.
  • Different from the first and second embodiments, in the present embodiment, the heat sink 4 b is brought close to the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 b of the wiring board 2) of the wiring board 21 in the process of fixing the heat sink 4 b to the wiring board 21 in the step S5 a performed as the step S5 as shown in FIG. 73. Then, as shown in FIG. 74, the pin portion 13 c provided on the upper surface 9 c of the heat sink 4 b is inserted (plugged) into the hole portion 15 of the wiring board 21. More specifically, the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 in a direction 35 a shown by arrow marks of FIGS. 73 and 74. Then, by using a fourth technique shown in FIGS. 75 to 78 to be described later or a fifth technique shown in FIGS. 79 to 82 to be described later, the heat sink 4 b and the wiring board 21 are fixed. By this means, the heat sink 4 b is attached and fixed to the lower surface 2 b side of the wiring board 2, and the heat sink 4 b planarly encloses the through-hole 3 of the wiring board 21, and the through-hole 3 of the wiring board 21 is blocked by the heat sink 4 b on the lower surface 2 b side of the wiring board 2.
  • A technique for fixing the heat sink 4 b to the wiring board 21 (fourth and fifth techniques) by using the pin portion 13 c of the heat sink 4 b in the present embodiment will be described.
  • FIGS. 75 to 78 are explanatory drawings (cross-sectional views) showing the fourth technique for fixing (caulking) the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b. FIGS. 79 to 82 are explanatory drawings (cross-sectional view) showing the fifth technique for fixing (caulking) the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b. FIGS. 75 to 78 show the cross-section of the region in the vicinity of the hole portion 15 of the wiring board 21, and they correspond to FIGS. 63A, 64A, 65A and 66A of the second embodiment. FIGS. 79 to 82 show the cross-section of the region in the vicinity of the hole portion 15 of the wiring board 21, and they correspond to FIGS. 67A, 68A, 69A and 70A of the second embodiment.
  • In the present embodiment, the fourth technique for fixing the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b will be described with reference to FIGS. 75 to 78. This fourth technique is the same as the second technique (technique shown in FIGS. 63 to 66) described in the second embodiment except that the inserting direction of the pin portion 13 c into the hole portion 15 of the wiring board 21 is opposite.
  • The fourth technique used in the present embodiment is the same as the second technique (technique shown in FIGS. 63 to 66) of the second embodiment in the shapes and the dimensions of the pin portion 13 c and the hole portion 15, and therefore, the description thereof will be omitted here.
  • In the step S5 a, as shown in FIG. 75 corresponding to FIG. 73 and FIG. 76 corresponding to FIG. 74, respectively, the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 from the lower surface 21 b side of the wiring board 21, and the upper surface 9 c of the heat sink 4 b is made to contact to the lower surface 21 b (lower surface 21 b in the peripheral region of the through-hole 3) of the wiring board 21. At this stage, as shown in FIG. 76, the top end portion 13 d of the pin portion 13 c protrudes from the upper surface 21 a of the wiring board 21.
  • After the pin portion 13 c is inserted into the hole portion 15 of the wiring board 21, a washer or ring-shaped member 25 similar to the second embodiment is fitted (installed) to the portion of the pin portion 13 c protruding from the upper surface 21 a of the wiring board 21 as shown in FIG. 77. More specifically, the portion of the pin portion 13 c protruding from the upper surface 21 a of the wiring board 21 is disposed inside the hole of the washer or ring-shaped member 25. Further, in the fourth technique, a length of the pin portion 13 c before being inserted into the hole portion 15 is made larger than the total thickness of the wiring board 21 and the washer or ring-shaped member 25. By this means, as shown in FIG. 77, at the stage in which the washer or ring-shaped member 25 is fitted into the pin portion 13 c, the top end portion 13 d of the pin portion 13 c protrudes from the washer or ring-shaped member 25.
  • The washer or ring-shaped member 25 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is preferable to form the washer or ring-shaped member 25 from the same material as the heat sink 4 b because the heat expansion coefficient of the pin portion 13 c and that of the washer or ring-shaped member 25 become the same.
  • Then, as shown in FIG. 78, the top end portion 13 d of the pin portion 13 c is crushed by a tool (not shown) and the like. By this means, the pin portion 13 c of the heat sink 4 b and the wiring board 21 can be caulked (fixed), and the heat sink 4 b can be fixed to the wiring board 21.
  • More specifically, since the top end portion 13 d of the pin portion 13 c is pressed (crushed), the pin portion 13 c is expanded in the lateral direction inside the hole portion 15 of the wiring board 21, and the side wall of the pin portion 13 c contacts to (adhered to) the inner wall of the hole portion 15 of the wiring board 21. Then, by the reaction of the expansion of the inner wall of the hole portion 15 of the wiring board 21 in the lateral direction due to the expansion of the pin portion 13 c in the lateral direction, the side wall of the pin portion 13 c is tightened up by the inner wall of the hole portion 15 of the wiring board 21. By this means, the pin portion 13 c of the heat sink 4 b can be caulked (fixed) to the wiring board 21, and the heat sink 4 b is fixed to the wiring board 21. In the fourth technique, the process up to here is performed by the step S5 a corresponding to the step S5.
  • As described above, by the step S5 a, the pin portion 13 c of the heat sink 4 b is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21. At this stage, the side wall of the pin portion 13 c contacts and adheres to the inner wall of the hole portion 15 of the wiring board 21, and this state is maintained even in the manufactured semiconductor device 1 b.
  • By caulking (fixing) the heat sink 4 b to the wiring board 21 by using the fourth technique described above, the heat sink 4 b can be fixed to the wiring board 21, and in addition to this, the following advantages can be further obtained. That is, after the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21, the pin portion 13 c is crushed so as to be able to fix the heat sink 4 b to the wiring board 21, and therefore, the heat sink 4 b can be firmly fixed to the wiring board 21. Further, when the top end portion 13 d of the pin portion 13 c is crushed by a tool (not shown) and the like, since the washer or ring-shaped member 25 functions as a buffer, a load applied to the wiring board 21 (region in the vicinity of the hole portion 15 of the lower surface 21 b) can be reduced.
  • Next, in the present embodiment, the fifth technique for fixing the heat sink 4 b to the wiring board 21 by using the pin portion 13 c of the heat sink 4 b will be described with reference to FIGS. 79 to 82. This fifth technique is the same as the third technique (technique shown in FIGS. 67 to 70) described in the second embodiment except that the inserting direction of the pin portion 13 c to the hole portion 15 of the wiring board 21 is opposite.
  • The fifth technique used in the present embodiment is the same as the third technique (technique shown in FIGS. 67 to 70) of the second embodiment in the shapes and the dimensions of the pin portion 13 c and the hole portion 15, and therefore, the description thereof will be omitted here.
  • In the step S5 a, as shown in FIG. 79 corresponding to FIG. 73 and FIG. 80 corresponding to FIG. 74, the pin portion 13 c of the heat sink 4 b is inserted into the hole portion 15 of the wiring board 21 from the lower surface 21 b side of the wiring board 21, and the lower surface 21 b (lower surface 21 b in the peripheral region of the through-hole 3) of the wiring board 21 is made to contact to the upper surface 9 c of the heat sink 4 b. At this stage, as shown in FIG. 80, the top end portion 13 d of the pin portion 13 c protrudes from the upper surface 21 a of the wiring board 21.
  • After the pin portion 13 c is inserted into the hole portion 15 of the wiring board 21, as shown in FIG. 81, the sleeve 26 similar to the second embodiment is inserted from the upper surface 21 a side of the wiring board 21 into the hole portion 15 in which the pin portion 13 c has been inserted. More specifically, while disposing (inserting) the pin portion 13 c into the hole of the sleeve 26, the sleeve 26 is disposed inside the hole portion 15 of the wiring board 21. Therefore, the sleeve 26 is interposed between the inner wall of the hole portion 15 of the wiring board 21 and the side wall 13 a of the pin portion 13 c.
  • The sleeve 26 is preferably made of the metal material in view of necessity of the strength and the processing easiness. Further, it is more preferable to form the sleeve 26 from the same material as the heat sink 4 b because the heat expansion coefficient of the pin portion 13 c and that of the sleeve 26 become the same.
  • Then, as shown in FIG. 82, the top end portion 13 d of the pin portion 13 c is crushed by a tool (not shown) and the like. By this means, the pin portion 13 c of the heat sink 4 b and the wiring board 21 can be caulked (fixed), and the heat sink 4 b can be fixed to the wiring board 21.
  • More specifically, since the top end portion 13 d of the pin portion 13 c is crushed, the top end portion 13 d of the pin portion 13 c is expanded in the lateral direction outside the hole portion 15 of the wiring board 21 and the sleeve 26, and the wiring board 21 and the sleeve 26 are sandwiched by the top end portion 13 d of the pin portion 13 c expanded in the lateral direction and (the upper surface 9 c of) the heat sink 4 b, so that the heat sink 4 b can be caulked (fixed) to the wiring board 21, and the heat sink 4 b is fixed to the wiring board 21. In the fifth technique, the process up to here is performed by the step S5 a.
  • As described above, by the step S5 a, the pin portion 13 c of the heat sink 4 b is disposed (inserted) and caulked inside the hole portion 15 of the wiring board 21. At this stage, the sleeve 26 is interposed between the inner wall of the hole portion 15 and the side wall of the pin portion 13 c inside the hole portion 15 of the wiring board 21, and this state is maintained even in the manufactured semiconductor device 1 b.
  • By caulking (fixing) the heat sink 4 b to the wiring board 21 by using the fifth technique described above, the heat sink 4 b can be fixed to the wiring board 21, and in addition to this, the following advantages can be further obtained. That is, even if the top end portion 13 d of the pin portion 13 c is crushed, the expansion of the pin portion 13 c in the lateral direction is restricted by the sleeve 26 inside the hole portion 15 of the wiring board 21, and since this sleeve 26 functions as a buffer, the application of a load to the inner wall of the hole portion 15 of the wiring board 21 can be prevented. Hence, the application of a load to the wiring board 21 can be prevented.
  • FIG. 83 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 b 1 of an modified example of the third embodiment and FIGS. 84 and 85 are explanatory drawings (cross-sectional views) of the process of fixing a heat sink 4 b 1 to the wiring board 21 in the step S5 a in the manufacturing process of the semiconductor device of FIG. 83, and they correspond to FIGS. 72 to 74, respectively. Also in the case of FIGS. 83 to 85, the heat sink 4 b 1 is fixed to the wiring board 21 from the lower surface 21 b side of the wiring board 21 like in the case of FIGS. 72 to 82. However, in the case of FIGS. 72 to 82, a fixing technique uses the pin portion 13 c of the heat sink 4 b, whereas in the case of FIGS. 83 to 85, the fixing technique uses the tapered shape of the side surface 10 of the heat sink 4 b 1. Note that, although the case where the heat sink 4 b 1 mounted with the semiconductor chip 5 is fixed to the wiring board 21 in the step S5 a will be illustrated and described in FIGS. 84 and 85, the heat sink 4 b 1 not mounted with the semiconductor chip 5 can also be fixed to the wiring board 21 in the step S5 a as shown in FIGS. 73 and 74.
  • For the manufacture of the semiconductor device 1 b 1 shown in FIG. 83, the process of fixing the heat sink 4 b 1 to the wiring board 21 in the step S5 a is performed as shown in FIGS. 84 and 85. More specifically, as shown in FIG. 84, the heat sink 4 b 1 mounted with the semiconductor chip 5 is brought close to the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 b of the wiring board 2) of the wiring board 21. Then, as shown in FIG. 85, the heat sink 4 b 1 mounted with the semiconductor chip 5 is inserted (plugged) into the through-hole 3 of the wiring board 21 from the lower surface 21 b side (side corresponding to the lower surface 2 a of the wiring board 2) of the wiring board 21. That is, the heat sink 4 b 1 mounted with the semiconductor chip 5 is inserted into the through-hole 3 of the wiring board 21 in a direction 35 a shown by the arrow marks of FIGS. 84 and 85.
  • Since the heat sink 4 b 1 does not have a protruded portion like the protruded portions 11 and 11 a in the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1, the heat sink 4 b 1 can be inserted into the through-hole 3 of the wiring board 21 from the lower surface 21 b side of the wiring board 21. Further, the heat sink 4 b 1 is integrally provided with a protruded portion (projecting portion, overhang portion, hook portion) 11 b protruding to the outside further than the side surface 10 of the heat sink 4 b 1 in the peripheral edge portion of the lower surface 9 b of the heat sink 4 b 1, and this protruded portion 11 b functions as a stopper when the heat sink 4 b 1 is inserted into the through-hole 3 of the wiring board 21 from the lower surface 21 b side of the wiring board 21.
  • Further, the side surface 10 of the heat sink 4 b 1 has a tapered shape. However, the tapered shape of the side surface 10 of the heat sink 4 b 1 is reversed in direction with respect to the tapered shape of the side surface 10 of the heat sink 4 of the first embodiment, and the dimension of the heat sink 4 b 1 (dimension of the cross-section parallel to the upper surface 2 a of the wiring board 2) is made slightly smaller on the upper side than on the lower side. On the other hand, the inner wall of the through-hole 3 of the wiring board 21 before the heat sink 4 b 1 is inserted does not have the tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21.
  • Hence, by inserting the heat sink 4 b 1 into the through-hole 3 from the lower surface 21 b side of the wiring board 21 as shown in FIGS. 84 and 85, the heat sink 4 b 1 and the wiring board 21 can be caulked by the tapered shape of the side surface 10 of the heat sink 4 b 1, and the heat sink 4 b 1 can be fixed to the wiring board 21. More specifically, when the heat sink 4 b 1 is inserted into the through-hole 3 from the lower surface 21 b side of the wiring board 21 in the step S5 a, the side surface 10 of the heat sink 4 b 1 contacts to the inner wall of the through-hole 3 of the wiring board 21, and the inner wall of the through-hole 3 of the wiring board 21 is expanded in the lateral direction by the tapered shape of the side surface 10 of the heat sink 4 b 1, so that the side surface 10 of the heat sink 4 b 1 is tightened up by the inner wall of the through-hole 3 of the wiring board 21 by its reaction, and the heat sink 4 b 1 is fixed to the wiring board 21. Since the protruded portion like the above-described protruded portion 11 is not present in the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1, a stopper effect to the lower side (in the direction 35) of the protruded portion 11 is eliminated as compared with the first embodiment and an effect of preventing the heat sink from falling off is reduced, but the heat sink 4 b 1 can be retained to the wiring board 21 by the tightening up by the tapered shape of the side surface 10 of the heat sink 4 b 1.
  • Hence, as shown in FIG. 85, in a state in which the heat sink 4 b 1 is disposed (inserted) inside the through-hole 3 of the wiring board 21 in the step S5 a, the side surface 10 of the heat sink 4 b 1 contacts and adheres to the inner wall of the through-hole 3 of the wiring board 21 and is inclined with respect to the direction vertical to the upper surface 21 a of the wiring board 21, and this state is maintained even in the manufactured semiconductor device 1 b 1 as shown in FIG. 83.
  • Since the manufacturing process of the semiconductor device 1 b 1 of FIG. 83 is almost the same as the manufacturing process of the semiconductor device 1 of the first embodiment except that the step S5 a as shown in FIGS. 84 and 85 is performed in place of the step S5 of the first embodiment, the description thereof will be omitted here. Since the heat sink 4 b 1 and the wiring board 21 are caulked and fixed by the tapered shape of the side surface 10 of the heat sink 4 b 1, the heat sink 4 b 1 can be retained (fixed) to the wiring board 21 until the resin sealing is performed in the step S7 after the step S5 a.
  • In the manufactured semiconductor device 1 b 1 of FIG. 83, the heat sink 4 b 1 is disposed inside the through-hole 3 of the wiring board 2. However, since the portions equivalent to the protruded portions 11 and 11 a are not present on the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1, the heat sink 4 b 1 does not extend on the upper surface 2 a of the wiring board 2. Also, although the protruded portion 11 b is provided on the peripheral edge portion of the lower surface 9 b of the heat sink 4 b 1, this protruded portion 11 b is located on the lower surface 2 b of the wiring board 2 outside the through-hole 3, and the upper surface of the protruded portion 11 b contacts to the lower surface 2 b of the wiring board 2. Hence, in the semiconductor device 1 b 1, when seen on the plane parallel to the upper surface 2 a of the wiring board 2, the portion other than the protruded portion 11 b of the heat sink 4 b 1 is located at the position planarly overlapped with the through-hole 3, and only the protruded portion 11 b is located outside the through-hole 3 (position not planarly overlapped with the through-hole 3, that is, the position overlapped with the wiring board 2). Since the structure of the semiconductor device 1 b 1 other than this is almost the same as the semiconductor device 1 of the first embodiment, the description thereof will be omitted here. Also, the material of the heat sink 4 b 1 is the same as that of the heat sink 4 of the first embodiment.
  • In the semiconductor device 1 b 1 of FIG. 83, the connecting terminal 17 can be disposed close to the through-hole 3 (that is, the semiconductor chip 5 on the heat sink 4 b 1 disposed inside the through-hole 3) in the wiring board 21 (wiring board 2) because the portions corresponding to the protruded portions 11 and 11 a are not present on the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1. Hence, this is advantageous for the miniaturization (reduction in area) of the semiconductor device. Further, since the portions corresponding to the protruded portions 11 and 11 a are not present on the peripheral edge portion of the upper surface 9 a of the heat sink 4 b 1, the bonding wire 6 is less likely to contact to the heat sink 4 b 1.
  • FIGS. 72 to 82 of the third embodiment are similar to the second and third techniques described in the second embodiment in that the washer or ring-shaped member 25 or the sleeve 26 is used, and FIGS. 83 to 85 of the third embodiment are similar to the first embodiment in that the tapered shape of the side surface of the heat sink is used. However, as compared with the third embodiment, the first and second embodiments and the following fourth and fifth embodiments have still other advantages as follows.
  • That is, since the first and second embodiments and the following fourth and fifth embodiments have a structure provided with the heat sinks 4, 4 a and 4 c inside the through-hole 3 of the wiring board 21, the thickness of the heat sinks 4, 4 a and 4 c can be made large, and the heat dissipation properties of the semiconductor device can be more improved.
  • Further, when the heat sink 4 b and 4 b 1 are fixed to the wiring board 21 from the lower surface 21 b side of the wiring board 21 like in the third embodiment, the weight of the heat sink 4 b and 4 b 1 (gravity working on the heat sink 4 b and 4 b 1) operates so that the heat sink 4 b and 4 b 1 fall off from the wiring board 21. Therefore, if a force to fix the heat sink 4 b and the wiring board 21 by the pin portion 13 c and a force to fix the heat sink 4 b 1 and the wiring board 21 by the tapered shape of the side surface 10 of the heat sink 4 b 1 are weak, the heat sinks 4 b and 4 b 1 are likely to fall off (peel off) from the wiring board 21 in the manufacturing process of the semiconductor device, and this will lower the manufacturing yield of the semiconductor device.
  • In contrast to this, in the first and second embodiments and the following fourth and fifth embodiments, the heat sinks 4, 4 a and 4 c are disposed inside the through-hole 3 of the wiring board 21 from the upper surface 21 a side of the wiring board 21, and the weight of the heat sinks 4, 4 a and 4 c h (gravity working on the heat sinks 4, 4 a and 4 c) can be received by the protruded portions 11 and 11 a of the heat sinks 4 and 4 a or a joining portion 33 a to be described later. More specifically, since the protruded portions 11 and 11 a or the joining portion 33 a to be described later are located on the upper surface 21 a of the wiring board 21 so that the lower surfaces of the protruded portions 11 and 11 a or the joining portion 33 a to be described later contact to the upper surface 21 a of the wiring board 21 in the first and second embodiments and the following fourth and fifth embodiments, the protruded portions 11 and 11 a or the joining portion 33 a to be described later support the weight of the heat sinks 4, 4 a and 4 c. Hence, in the first and second embodiments and the following fourth and fifth embodiments, even if the force for fixing the heat sinks 4, 4 a and 4 c to the wiring board 21 is not so much strong, it is possible to prevent the heat sinks 4, 4 a and 4 c from falling off from the wiring board 21 in the manufacturing process of the semiconductor device. Also, since the gravity working on the heat sinks 4, 4 a and 4 c rather operates so as to make the heat sinks 4, 4 a and 4 c less likely to fall off from the wiring board 21 in the first and second embodiments and the following fourth and fifth embodiments, it is not necessary to make the force for fixing the heat sinks 4, 4 a and 4 c to the wiring board 21 so large, and a load operating on the wiring board 21 by this fixing force can be reduced. In the following fourth and fifth embodiments, those corresponding to the wiring board 21 are wiring boards 21 c, 21 d and 2 f.
  • Further, since the completed semiconductor device is mounted while directing the lower surface 2 b of the wiring board 2 toward the mounting board (corresponding to the wiring board 41) side, the heat sinks 4, 4 a, 4 b, 4 b 1 and 4 c are required to be surely fixed inside the through-hole 3 of the wiring board 2. Hence, if the reliability of the semiconductor device is taken into consideration, it is more preferable to insert the heat sinks 4, 4 a and 4 c into the through-hole 3 from the upper surface 21 a side of the wiring board 21 like in the first and second embodiments and the fourth and fifth embodiments to be described later rather than fixing the heat sinks 4 b and 4 b 1 to the wiring board 21 from the lower surface 21 b side of the wiring board 21 like in the third embodiment. In the following fifth embodiment, that corresponding to the wiring board 2 is a wiring board 2 f.
    • Fourth Embodiment
  • In the first and second embodiments, the individually segmented heat sinks 4 and 4 a are disposed inside the through-hole 3 of the wiring board 21 to manufacture the semiconductor devices 1 and 1 a. In the present embodiment, however, a resin sealing process is performed in a state in which a plurality of heat sinks 4 c are joined, and then, the sealing body is individually segmented, thereby manufacturing the semiconductor device 1 c.
  • FIG. 86 is a process flowchart showing the manufacturing process of a semiconductor device of the present embodiment. FIG. 87 is an upper surface view (plan view) of a frame 31 a used for the manufacture of the semiconductor device of the present embodiment, FIG. 88 is a lower surface view (plan view) of the frame 31 a, and FIGS. 89 and 90 are cross-sectional views of the frame 31 a. The cross-section cut along the line A13-A13 of FIGS. 87 and 88 corresponds to FIG. 89, and the cross-section cut along the line A14-A14 of FIGS. 87 and 88 corresponds to FIG. 90. Although FIG. 87 is a plan view, hatching is applied to the frame 31 a so that the shape of the frame 31 a is easily understood. Further, FIGS. 91 and 92 are a plan view (upper surface view) and a cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 91 shows a planar region corresponding to FIG. 87 and FIG. 92 shows the cross-section corresponding to FIG. 89. FIG. 93 is an upper surface view (plan view) of the wiring board 21 c used for the manufacturing process of the semiconductor device of the present embodiment, and FIGS. 94 and 95 are cross-sectional views of the wiring board 21 c. The cross-section cut along the line A15-A15 of FIG. 93 corresponds to FIG. 94, and the cross-section cut along the line A16-A16 of FIG. 93 corresponds to FIG. 95. Further, FIGS. 96 to 98 are a plan view (upper surface view) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 96 shows a planar region corresponding to FIGS. 87 and 93, FIG. 97 shows the cross-section corresponding to FIGS. 89 and 94, and FIG. 98 shows the cross-section corresponding to FIGS. 90 and 95. FIGS. 99 and 100 are explanatory drawings (cross-sectional views) showing a technique of fixing the frame 31 a to the wiring board 21 c by using a pin portion 13 e of the frame 31 a. Further, FIGS. 101 to 105 are plan views (upper surface views) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment. FIGS. 101 and 102 show the same process stage, and FIG. 101 shows the planar region corresponding to FIG. 96 and FIG. 102 shows the cross-section corresponding to FIG. 97. FIGS. 103 and 104 show the same process stage, and FIG. 103 shows the planar region corresponding to FIG. 101 and FIG. 104 shows the cross-section corresponding to FIG. 102. FIG. 105 is a process stage subsequent to FIG. 104, and shows the cross-section corresponding to FIG. 104.
  • Further, FIGS. 106 and 107 are cross-sectional views (side cross-sectional views) of the semiconductor device 1 c of the present embodiment, and FIG. 108 is a perspective plan view (upper surface view) of the semiconductor device 1 c when the sealing resin 7 is seen through. The cross-section cut along the line A17-A17 of FIG. 108 almost corresponds to FIG. 106, and the cross-section cut along the line A18-A18 of FIG. 108 almost corresponds to FIG. 107. Further, FIG. 109 is a lower surface view of the wiring board 2 in the semiconductor conductor device 1 c. Although FIG. 109 is a plan view, hatching is applied to a solder resist layer 19 so that the planar shape (pattern) of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 is easily understood. Further, though FIG. 103 is a plan view, hatching is applied to the sealing resin 7 a and the outer shape of the frame 31 a located below the sealing resin 7 a is shown by a dotted line for easy understanding. FIG. 103 shows a cutting position (cutting line, dicing line) DL of the cutting process in the step S10 b by a two-dot chain line.
  • For the manufacture of the semiconductor device, the frame 31 a in which a plurality of heat sinks 4 c are joined as shown in FIGS. 87 to 90 is prepared (step S2 b). The frame 31 a has a structure in which a plurality of heat sinks 4 c are integrally joined with the frame portion 32. More specifically, a plurality of heat sink 4 c are disposed in a row at the predetermined intervals (preferably equal intervals) between the two frame portions 32 extending in parallel in the same direction at the predetermined interval, and each heat sink 4 c is joined with the frame portion 32 through a joining portion (suspension lead) 33 a. The joining portion 33 a can be taken also as a suspension lead for suspending (retaining) the heat sink 4 c for mounting the semiconductor chip 5 later on the frame portion 32.
  • The heat sink 4 c corresponds to the heat sinks 4 and 4 a of the first and second embodiments and is made of the same material as the heat sinks 4 and 4 a. The heat sink 4 c has the same structure as the heat sinks 4 and 4 a of the first and second embodiments except that the protruded portions 11 and 11 a and the pin portion 13 are not formed, the taper (inclination) of the side surface 10 of the heat sink 4 c is eliminated, and the dimension of the heat sink 4 c is made slightly smaller than the dimension of the through-hole 3 of the wiring board 21.
  • In the frame 31 a, one end portion of each joining portion 33 a is connected to the heat sink 4 c, and the other end portion is connected to the frame portion 32. The joining portion 33 a is connected to the upper portion of the heat sink 4 c, and the joining portion 33 a and the heat sink 4 c are integrally formed, and therefore, the joining portion 33 a extends until reaching the frame portion 32 in the peripheral edge portion of the upper surface 9 a of the heat sink 4 c so as to protrude outside from the side surface of the heat sink 4 c. Therefore, the one obtained by adding the protruded portion 11 a from which the pin portion 13 c is omitted and the joining portion 33 integrally connected to the protruded portion 11 a in the frame 31 of the second embodiment corresponds to the joining portion 33 a in the frame 31 a of the present embodiment. Further, it can be said that the one in which the protruded portion 11 a provided with no pin portion 13 c is extended until reaching the frame portion 32 in the second embodiment corresponds to the joining portion 33 a in the frame 31 a of the present embodiment.
  • Further, it is more preferable that the joining portion 33 a is connected to each of the four corners of the upper surface 9 a of the heat sink 4 c as shown in FIGS. 87 and 88, and by this means, the heat sink 4 c can be stably joined (retained) to the frame portion 32, and at the same time, when the frame 31 a is fixed to the wiring board 21 c later, the joining portion 33 a and the connecting terminal 17 b are less likely to overlap with each other. For the same reason, the extending direction of the joining portion 33 a is preferably the diagonal direction of the upper surface 9 a of the heat sink 4 c.
  • As shown in FIGS. 88 and 90, the lower surface 32 a of the frame portion 32 has pin portions (caulking portions, pin portions for caulking, caulking pins, protruded portions, convex portions) 13 e integrally formed with the frame portion 32. As described later, the pin portion 13 e is used for fixing the frame portion 32 and the wiring board 21. In the frame 31 a, the heat sink 4 c, the frame portion 32, the joining portion 33 a, and the pin portion 13 e are integrally formed of the same material. The frame 31 a can be formed by, for example, processing a copper plate and the like by a metal mold. Although the heat sinks 4 c appear to be separated from each other in the cross-sectional view of FIG. 89, as evident from FIGS. 87 and 88, the heat sinks 4 c are mutually joined in reality through the joining portion 33 a and the frame portion 32.
  • After the frame 31 a is prepared, as shown in FIGS. 91 and 92, the semiconductor chip 5 is bonded on the upper surface 9 a of each heat sink 4 c of the frame 31 a through the bonding agent 14 (step S3 b). The bonding process of the semiconductor chip 5 in the step S3 b can be performed in the same manner as the bonding process of the semiconductor chip 5 in the step S3 of the first embodiment, and therefore, the detailed description thereof will be omitted here.
  • Further, as shown in FIGS. 93 to 95, the wiring board 21 c for the semiconductor device manufacture is prepared (step S1 b). Although this wiring board 21 c corresponds to the wiring boards of the first and second embodiments, in the present embodiment, the wiring board 21 c has a structure in which a plurality of semiconductor device regions 22 from each of which one semiconductor device 1 is formed are disposed (joined) in a row. The wiring board 21 c is cut by a cutting process to be described later, and the one separated into each semiconductor device region (board region, unit board region) 22 corresponds to the wiring board 2 of the semiconductor device 1 c to be described later. The structure of each semiconductor device region 22 in the wiring board 21 c is almost the same as the structure of each semiconductor device region 22 of the wiring board 21 in the first embodiment, and the through-hole 3 is formed in each semiconductor device region 22 of the wiring board 21 c, a plurality of connecting terminals 17 and the wirings connected thereto are formed in each of the semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c, and a plurality of lands 18 are formed in each of the semiconductor device regions 22 of the lower surface 21 b of the wiring board 21.
  • Further, a plurality of hole portions 15 a similar to the hole portion 15 of the second embodiment are formed in the wiring board 21 c of the present embodiment, but the forming position of the hole portion 15 a is different from that of the hole portion 15 of the second embodiment. More specifically, in the wiring board 21 c of the present embodiment, the hole portion 15 a is formed at the position planarly overlapped with the pin portion 13 e provided on the lower surface 32 a of the frame portion 32 when the frame 31 a is fixed to the wiring board 21 c in the step S5 b to be described later. Consequently, the hole portion 15 a is formed in the vicinity of the side end portion of the wiring board 21 c. The hole portion 15 a is a through-hole reaching the lower surface 21 b from the upper surface 21 a of the wiring board 21 c, but the planar dimension of the hole portion 15 a is sufficiently smaller as compared with the through-hole 3 for inserting the heat sink 4 c.
  • Next, as shown in FIGS. 96 to 98, the frame 31 a is fixed to the wiring board 21 c (step S5 b). It is necessary to prepare the wiring board 21 c in the step S1 b before performing this step S5 b. Hence, the preparation of the wiring board 21 c in the step S1 b can be performed also before the step S2 b, simultaneously with the step S2 b, before the step S3 b and after the step S2 b, simultaneously with the step S3 b or before the step S5 b and after the step S3 b.
  • In the first and second embodiments, each of the heat sinks 4 and 4 a is separated from the frame 31 into individual pieces, and then, the heat sinks 4 and 4 a are disposed inside each of the through-holes 3 of the wiring board 21. However, in the present embodiment, in the step S5 b, the frame 31 a in a state in which a plurality of heat sinks 4 c are joined is fixed to the wiring board 21 c.
  • More specifically, in the step S5 b, the frame 31 a is positioned and disposed on the upper surface 21 a of the wiring board 21 c and each heat sink 4 c of the frame 31 a is inserted (plugged) into each through-hole 3 of the wiring board 21 c from the upper surface 21 a side of the wiring board 21 c, and at the same time, each pin portion 13 e of the frame 31 a is inserted (plugged) into each hole portion 15 a of the wiring board 21 c. The through-hole 3 and the hole portion 15 a of the wiring board 21 c are disposed at the position in which each pin portion 13 e of the frame 31 a is inserted into each hole portion 15 a of the wiring board 21 c when each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c.
  • In the frame 31 a, each heat sink 4 c is connected to the frame portion 32 through the joining portion 33 a. Hence, when each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 and each pin portion 13 e of the frame 31 a is inserted into each hole portion 15 a from the upper surface 21 a side of the wiring board 21 c in the step S5 b, the frame portion 32 and the joining portion 33 a are overlapped with the upper surface 21 a of the wiring board 21 c as shown in FIGS. 96 to 98, and therefore, the heat sink 4 c does not fall off downward from the through-hole 3 of the wiring board 21 c. Consequently, the heat sink 4 c can be retained inside the through-hole 3 of the wiring board 21 c, each heat sink 4 c of the frame 31 a is disposed inside each through-hole 3 of the wiring board 21 c, and the frame 31 a is fixed to the wiring board 21 c by the pin portion 13 e of the frame 31 a.
  • More specifically, each heat sink 4 c in the frame 31 a has the joining portion 33 a which protrudes to the outside (in the direction away from the center of the upper surface 9 a) from the side surface of each heat sink 4 c on the peripheral edge portion of the upper surface 9 a of each heat sink 4 c, and in the step S5 b, each heat sink 4 c is disposed inside the through-hole 3 of the wiring board 21 c so that this joining portion 33 a is located on the upper surface 21 a of the wiring board 21 c outside the through-hole 3 and the lower surface of the joining portion 33 a contacts to the upper surface 21 a of the wiring board 21 c.
  • Here, the frame 31 a and the wiring board 21 c are fixed by the same technique as the first technique of the second embodiment. More specifically, for fixing the frame 31 a to the wiring board 21 c, the pin portion 13 e provided on the frame 31 a is used.
  • FIGS. 99 and 100 are explanatory drawings (cross-sectional views) showing a technique for fixing (caulking) the frame 31 a to the wiring board 21 c by using the pin portion 13 e of the frame 31 a, and they correspond to FIGS. 61 and 62A of the second embodiment. FIGS. 99 and 100 show the cross-sectional views of the region in the vicinity of the hole portion 15 a of the wiring board 21 c.
  • The shape of the pin portion 13 e of the frame 31 a is the same as the shape of the pin portion 13 in the first technique of the second embodiment. More specifically, as shown in FIG. 99, the side wall (side surface) 13 f of the pin portion 13 e of the frame 31 a is tapered. In other words, the cross-sectional shape (shape of the cross-section vertical to the lower surface 32 a of the frame portion 32) of the pin portion 13 e of the frame 31 a has a tapered shape. Hence, the dimension of the pin portion 13 e becomes thinner (smaller) as approaching a top end portion 13 g and becomes thicker (larger) as approaching the frame portion 32. In other words, the pin portion 13 e is tapered. On the other hand, as shown in FIG. 99, the inner wall of the hole portion 15 a of the wiring board 21 c before the pin portion 13 e of the frame 31 a is inserted has no tapered shape, and is kept almost vertical to the upper surface 21 a of the wiring board 21 c. Then, the dimension of the hole portion 15 a before the pin portion 13 e is inserted is made the same as or slightly larger than the dimension of the top end portion 13 g of the pin portion 13 e, and moreover, is made smaller than the dimension of a root portion (portion close to the frame 32) of the pin portion 13 e.
  • In the step S5 b, as shown in FIGS. 99 to 100, the pin portion 13 e of the frame 31 a is inserted (plugged) into the hole portion 15 a of the wiring board 21 c, and the pin portion 13 e of the frame 31 a and the wiring board 21 c can be caulked (fixed) by the tapered shape of the pin portion 13 e. By this means, the frame 31 a can be fixed to the wiring board 21 c.
  • More specifically, when the pin portion 13 e of the frame 31 a is inserted into the hole portion 15 a of the wiring board 21 c in the step S5 b, the side wall 13 f of the pin portion 13 e contacts and adheres to the inner wall of the hole portion 15 a of the wiring board 21 c, and the inner wall of the hole portion 15 a of the wiring board 21 c is expanded in the lateral direction by the tapered shape of the side wall 13 f of the pin portion 13 e, and the side wall 13 f of the pin portion 13 e is tightened up by the inner wall of the hole portion 15 a of the wiring board 21 c by its reaction. By this means, the pin portion 13 e of the frame 31 a can be caulked (fixed) to the wiring board 21 c, and the frame 31 a can be fixed to the wiring board 21 c.
  • Further, the step S3 b (bonding process of the semiconductor chip 5) can be performed before the step S6 b to be described later (wire bonding process) and after the step S5 b (process of fixing the frame 31 a to the wiring board 21 c).
  • After the frame 31 a is fixed to the wiring board 21 c in the step S5 b, as shown in FIGS. 101 and 102, the wire bonding process is performed, and each electrode 5 d of the semiconductor chip 5 and the connecting terminal 17 formed in the wiring board 21 c corresponding thereto are electrically connected through the bonding wire 6 (step S6 b). More specifically, a plurality of connecting terminals 17 of each semiconductor device region 22 of the upper surface 21 a of the wiring board 21 c and a plurality of electrodes 5 a of the semiconductor chip 5 bonded (mounted) on the heat sink 4 c disposed inside the through-hole 3 of the semiconductor device region 22 are electrically connected through a plurality of bonding wires 6, respectively.
  • After the wire bonding process, as shown in FIGS. 103 and 104, the resin sealing by a molding process (for example, transfer molding process) is performed so as to form a sealing resin 7 a (sealing portion), thereby sealing (resin-sealing) the semiconductor chip 5 and the bonding wire 6 by the sealing resin 7 a (step S7 b).
  • In the present embodiment, as shown in FIGS. 103 and 104, the collective sealing for collectively sealing the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c by the sealing resin 7 a is performed in the molding process in the step S7 b. More specifically, the sealing resin 7 a is formed so as to cover the semiconductor chip 5 and the bonding wire 6 on the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c. In this case, the sealing resin 7 a is formed to cover the plurality of semiconductor device regions 22 of the upper surface 21 a of the wiring board 21 c, and the frame 31 a disposed on the upper surface 21 a of the wiring board 21 c is also covered (sealed) with the sealing resin 7 a except for a part of the frame portion 32.
  • After the frame 31 a is fixed to the wiring board 21 c in the step S5 b, a state in which the upper surface 21 a of the wiring board 21 c is directed upward without turning the wiring board 21 c upside down is preferably maintained until the molding process in the step S7 b is performed. More specifically, after fixing the frame 31 a to the wiring board 21 c in the step S5 b, the wiring board 21 c has the upper surface 21 a directed upward so that the lower surface 21 b thereof is not directed upward until the molding process in the step S7 b is performed. As a result, the falling off of the frame 31 a from the wiring board 21 c before the sealing resin 7 a is formed can be prevented more precisely. By forming the sealing resin 7 a, the frame 31 a and the wiring board 21 c are solidly bonded by the sealing resin 7 a, and therefore, after forming the sealing resin 7 a, the wiring board 21 c may be directed to any direction (lower surface 21 b of the wiring board 21 c may be directed upward).
  • Next, as shown in FIG. 105, the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 21 b of the wiring board 21 c (step S8 b). Then, marking is performed as needed and a mark such as a product number and the like is applied on the surface of the sealing resin 7 a (step S9 b). Since the connecting process of the solder balls 8 in the step S8 b and the marking process in the step S9 b can be performed in the same manner as the connecting process of the solder balls 8 in the step S8 and the marking process in the step S9 of the first embodiment, the detailed description thereof will be omitted here. The marking process in the step S9 b may be performed after the connecting process of the solder balls 8 in the step S8 b is performed, the connecting process of the solder balls 8 in the step S8 b may be performed after the marking process in the step S9 b is performed, or the marking process in the step S9 b may be omitted if not required.
  • Next, the wiring board 21 c and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22 (step S10 b). In the step S10 b, the wiring board 21 c, the frame 31 a and the sealing resin 7 a are cut along a cutting position (cutting line, dicing line) DL shown by the two-dot chain line in FIG. 103. In the present embodiment, the cutting process in the step S10 b is performed by dicing.
  • By the cutting/segmentation into individual pieces performed in this manner, the semiconductor device 1 c as shown in FIGS. 106 to 109 is manufactured. The wiring board 21 c cut and separated (divided) into each semiconductor device region corresponds to the wiring board 2 of the semiconductor device 1 c, and the sealing resin 7 a cut and separated (divided) into each semiconductor device region 22 corresponds to the sealing resin 7 of the semiconductor device 1 c.
  • In the present embodiment, since the sealing resin 7 a is formed in a state in which the frame 31 a is disposed (fixed) on the upper surface 21 a of the wiring board 21 c, when the wiring board 21 c and the sealing resin 7 a formed thereon are cut in the step S10 b, the frame 31 a is also cut. In this step S10 b, as shown in FIG. 103, the wiring board 21 c, the frame 31 a and the sealing resin 7 a thereon are cut so that the frame portion 32 is not contained in the semiconductor device 1 c. More specifically, an excess region not contained in the semiconductor device region 22 is provided in advance at a side end portion of the wiring board 21 c, so that the frame portion 32 is positioned on this excess region when the frame 31 a is fixed to the wiring board 21 c in the step S5 b. Then, in the step S10 b, the excess region of the wiring board 21 c is cut and removed together with the frame portion 32 and the sealing resin 7 a thereon. In this manner, the frame portion 32 is not contained in the semiconductor device 1 c. Since the pin portion 13 e of the frame 31 a is provided in the frame portion 32 and the hole portion 15 a of the wiring board 21 c is provided in the excess region, the pin portion 13 e and the hole portion 15 a are not contained in the manufactured semiconductor device 1 c.
  • The structure of the manufactured semiconductor device 1 c will be described in relation to the difference from the semiconductor device 1 a of the second embodiment.
  • The heat sink 4 c has almost the same structure as the heat sinks 4 and 4 a of the first and second embodiments except that the protruded portions 11 and 11 a and the pin portion 13 are not formed, the taper (inclination) of the side surface 10 of the heat sink 4 c is eliminated, and the dimension of the heat sink 4 c is made slightly smaller than the dimension of the through-hole 3 of the wiring board 21 (wiring board 2). In the semiconductor device 1 c of the present embodiment, the side surface (side wall) 10 a of the heat sink 4 c disposed inside the through-hole 3 of the wiring board 2 and the inner wall of the through-hole 3 of the wiring board 2 are slightly spaced apart, and a resin material constituting the sealing resin 7 is interposed (for example, with the thickness of about 50 to 100 μm) between the inner wall of the through-hole 3 of the wiring board 2 and the side surface (side wall) 10 a of the heat sink 4 c. The reason therefor is as follows.
  • In the first and second embodiments, after the heat sinks 4 and 4 a are segmented into individual pieces, the individually segmented heat sinks 4 and 4 a are inserted into each of the plurality of through-holes 3 of the wiring board 21 in the step S5. Hence, even if the dimension of these heat sinks 4 and 4 a and the dimension of the through-hole 3 are matched, it is easy to dispose the heat sinks 4 and 4 a inside each through-hole 3 of the wiring board 21. Hence, the side surfaces 10 of the heat sinks 4 and 4 a contact to the inner wall of the through-hole 3, and it is possible to prevent the resin material from flowing between the side surfaces 10 of the heat sinks 4 and 4 a and the inner wall of the through-hole 3 in the resin sealing process.
  • In contrast to this, in the present embodiment, the heat sink 4 c is not segmented into individual pieces, and the heat sink 4 c is inserted into each of the plurality of through-holes 3 of the wiring board 21 c in a state in which the plurality of heat sinks 4 c are joined by the joining portion 33 a and the frame portion 32 in the step S5 b. Hence, if the dimension of the heat sink 4 c and the dimension of the through-hole 3 are matched, it is difficult to insert each of the plurality of heat sinks 4 c joined to each other into the through-hole 3 of the wiring board 21 c. Therefore, in the present embodiment, the dimension (planar dimension of the portion inserted into the through-hole 3) of the heat sink 4 c is made slightly smaller than the dimension (planar dimension) of the through-hole 3. By this means, even when the heat sink 4 c is inserted into each of the plurality of through-holes 3 of the wiring board 21 c in a state in which the plurality of heat sinks 4 c are mutually joined, the heat sink 4 c can be easily and precisely disposed (inserted) inside each through-hole 3 of the wiring board 21 c.
  • Since the dimension of the heat sink 4 c is slightly smaller than the dimension of the through-hole 3 in the present embodiment, the resin material constituting the sealing resin 7 a flows between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c in the molding process in the step S7 b. As a result, the resin material constituting the sealing resin 7 is interposed between the inner wall of the through-hole 3 of the wiring board 21 c (wiring board 2) and the side surface (side wall) 10 a of the heat sink 4 c, and therefore, the heat sink 4 c is further firmly fixed. More specifically, in the molding process in the step S7 b, a part of the sealing resin 7 a is formed between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c.
  • Further, in the molding process in the step S7 b, a gap between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c into which the resin material flows is a gap at most equivalent to an air vent of a resin sealing metal mold and is about 50 to 100 μm, and therefore, the filler of the resin material constituting the sealing resin 7 a does not flow in this gap, but the liquid resin flows therein. Hence, in the semiconductor device 1 c, the portion of the sealing resin 7 interposed between the inner wall of the though-hole 3 of the wiring board 2 and the side surface (side wall) 10 a of the heat sink 4 c does not contain the filler, but the other portion of the sealing resin 7 (portion on the upper surface 2 a of the wiring board 2, on the upper surface of the heat sink 4 c and on the semiconductor chip 5) contains the filler.
  • Further, in the present embodiment, in the molding process in the step S7 b, in order to prevent the resin material, which flows between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c, from overflowing to the lower surface 21 a side of the wiring board 21 c and adhering to the land 18, a shape of the solder resist layer 19 formed on the lower surface 21 b (that is, the lower surface 2 b of the wiring board 2) of the wiring board 21 c is devised as follows.
  • On the upper surface 2 a and the lower surface 2 b of the wiring board 2, the solder resist layer to expose the connecting terminal 17 and the land 18 is formed. In FIGS. 106, 107 and 109, the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 is illustrated. Note that, although the solder resist layer is formed also on the upper surface 2 a of the wiring board 2, the illustration thereof is omitted. Further, in the first and second embodiments, the illustrations of both of the solder resist layer formed on the upper surface 2 a of the wiring board 2 and the solder resist layer formed on the lower surface 2 b are omitted.
  • On the lower surface 2 b of the wiring board 2, the solder resist layer 19 is formed in the hatched region in FIG. 109. A region 20 is a region in which the solder resist layer 19 is not formed on the lower surface 2 b of the wiring board 2 and is a region in which the lower surface of the base material layer (base material layer 16) of the wiring board 2 is exposed.
  • As evident also from FIG. 109, though the solder resist layer 19 is formed on the lower surface 2 b of the wiring board 2 in the present embodiment, the solder resist layer 19 of the lower surface 2 b of the wiring board 2 includes a first solder resist portion 19 a provided to surround the periphery of the through-hole 3 in the vicinity of the through-hole 3 and a second solder resist portion 19 b located on the periphery (outer periphery) of the first solder resist portion 19 a. Between the first solder resist portion 19 a and the second solder resist portion 19 b, a region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16) of the wiring board 2 is exposed is present. Consequently, the first solder resist portion 19 a and the second solder resist portion 19 b are isolated with interposing the region 20 therebetween. The plurality of lands 18 provided on the lower surface 2 b of the wiring board 2 are exposed from an opening formed in the second solder resist portion 19 b. The second solder resist portion 19 b has an opening for exposing the land 18, and a conductive pattern for the land 18 is exposed from this opening. The opening of the solder resistor layer 19 for exposing the land 18 is formed in the second solder resist portion 19 b and is not formed in the first solder resist portion 19 a.
  • The pattern shape of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 has been illustrated and described, but since the wiring board 21 c cut in the step S10 b becomes the wiring board 2, the pattern shape of the solder resist layer on the lower surface 21 b of the wiring board 21 c is also the same as the pattern shape of the solder resist layer 19 on the lower surface 2 b of the wiring board 2.
  • In the molding process in the step S7 b, the resin material (mold resin) which flows between the inner wall of the through-hole 3 of the wiring board 21 c and the side surface (side wall) 10 a of the heat sink 4 c is likely to overflow to the lower surface 21 b side of the wiring board 21 c. For its prevention, in the present embodiment, since the region (dam region) 20 in which the solder resist layer 19 is not present and the base material layer (base material layer 16) of the wiring board 21 is exposed is provided between the first solder resist portion 19 a and the second solder resist portion 19 b, the resin material (mold resin) overflowed to the lower surface 21 b side of the wiring board 21 c from the gap between the through-hole 3 and the heat sink 4 c can be prevented from spreading on the second solder resist portion 19 b over the region 20. Hence, it is possible to prevent the resist material from adhering to the land 18 of the lower surface 21 b of the wiring board 21 c in the molding process in the step S7 b, and the reliability of the connection between the land 18 and the solder ball 8 can be improved.
  • Further, in the present embodiment, a plurality of heat sinks 4 c are joined by the joining portion 33 a and the frame portion 32 until the cutting process in the step S10 b is performed, and these heat sinks 4 c are segmented into individual pieces in the step S10 b. Therefore, in the semiconductor device 1 c, the joining portion 33 a of the frame 31 a is left on the upper surface 2 a of the wiring board 2 and sealed by the sealing resin 7 while being connected to the heat sink 4 c, and a cut surface (end portion) of the joining portion 33 a is exposed on the cut surface (that is, the side surface of the semiconductor device 1 c) in the step S10 b. In the first and second embodiments, the protruded portions 11 and 11 a of the heat sinks 4 and 4 a prevent the heat sinks 4 and 4 a from falling off from the through-hole 3 of the wiring board 21, whereas the joining portion 33 a has this function in the present embodiment. Consequently, in the semiconductor device 1 c, the joining portion 33 a integrally connected to the heat sink 4 c has the same structure as the protruded portion 11 a of the second embodiment except that the pin portion 13 is not formed and the joining portion 33 a extends on the upper surface 2 a of the wiring board 2 until reaching the side surface of the semiconductor device 1 c. Therefore, in the semiconductor device 1 c, the heat sink 4 c is integrally provided with the joining portion 33 a which is a protruded portion protruding to the outside (in the direction away from the center of the upper surface 9 a) of the side surface 10 of the heat sink 4 c in the peripheral edge portion (peripheral portion) of the upper surface 9 a of the heat sink 4 c, and this joining portion 33 a is positioned (extended) on the upper surface 2 a of the wiring board 2 outside the through-hole 3. More specifically, in the semiconductor device 1 c, the heat sink 4 c is integrally provided with the joining portion 33 a, which protrudes to the upper surface 2 a side of the wiring board 2 from the through-hole 3 and extends on the upper surface 2 a of the wiring board 2 (extends until reaching the side surface of the wiring board 2), on the peripheral edge portion of the upper surface 9 a of the heat sink 4 c, and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2.
  • Since other structure of the semiconductor device 1 c is almost the same as the semiconductor device 1 of the first embodiment, the description thereof will be omitted here.
  • In the manufacturing process described with reference to FIGS. 86 to 105, a technique for inserting the pin portion 13 e provided in the frame 31 a into the hole portion 15 a provided in the wiring board 21 c is used for fixing the frame 31 a to the wiring board 21 c in the step S5 b. However, as another embodiment, the frame 31 a can be fixed to the wiring board 21 c by using the bonding agent in the step S5 b. FIGS. 110 and 111 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 a to the wiring board 21 c by using the bonding agent, and they correspond to FIGS. 99 and 100, respectively.
  • When the frame 31 a is fixed to the wiring board 21 c by using the bonding agent, the pin portion 13 e is not provided in the frame 31 a, and the hole portion 15 a is not provided in the wiring board 21 c. Instead, in the step S5 b, as shown in FIG. 110, a bonding agent 51 is coated (disposed) in advance on the upper surface 21 a of the wiring board 21 c, and then, the frame 31 a is disposed on the upper surface 21 a of the wiring board 21 c so that the frame portion 32 of the frame 31 a is positioned on the bonding agent. At this time, each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c from the upper surface 21 a side of the wiring board 21 c. More specifically, the bonding agent 51 is coated at the position on the upper surface 21 a of the wiring board 21 c on which the frame portion 32 overlaps when each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 of the wiring board 21 c. By this means, each heat sink 4 c of the frame 31 a is inserted into each through-hole 3 from the upper surface 21 a side of the wiring board 21 c, and at the same time, as shown in FIG. 111, the lower surface 32 a of the frame portion 32 of the frame 31 a is bonded to the upper surface 21 a of the wiring board 21 c through the bonding agent 51, so that the frame 31 a is fixed to the wiring board 21 c. As the bonding agent 51, a film type bonding agent such as a DAF (die attach film) can be also used.
  • In the manufacturing process described with reference to FIGS. 86 to 105, the pin portion 13 e and the hole portion 15 a are provided in the region not contained later in the semiconductor device 1 c. However, as another embodiment, the pin portion 13 e and the hole portion 15 a can be provided in the region contained later inside the semiconductor device 1 c, and the manufacturing process in this case will be described with reference to FIGS. 112 to 124.
  • FIG. 112 is an upper surface view (plan view) of the frame 31 b used in another manufacturing process of the present embodiment, FIG. 113 is a lower surface view (plan view) of the frame 31 b of FIG. 112, and FIGS. 114 and 115 are cross-sectional views of the frame 31 b of FIG. 112. The cross-section cut along the line A19-A19 of FIG. 112 corresponds to FIG. 114, and the cross-section cut along the line A20-A20 of FIG. 112 corresponds to FIG. 115. Also, FIG. 116 is an upper surface view (plan view) of the wiring board 21 d used in another manufacturing process of the present embodiment, and it corresponds to FIG. 93. FIGS. 117 to 119 are a plan view (upper surface view) and cross-sectional view in another manufacturing process of the present embodiment, and FIG. 117 shows a planar region corresponding to FIGS. 112 and 116, and FIG. 118 shows the cross-section corresponding to FIG. 114, and FIG. 119 shows the cross-section corresponding to FIG. 115. FIGS. 120 and 121 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the pin portion 13 e of the frame 31 b, and FIGS. 122 and 123 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the bonding agent 51. FIG. 124 is a plan view (upper surface view) showing a state in which the sealing resin 7 a is formed in another manufacturing process of the present embodiment, and it shows a planar region corresponding to FIG. 117. Also, although FIG. 124 is a plan view, hatching is applied to the sealing resin 7 a for easy understanding, and an outer shape of the frame 31 b located below the sealing resin 7 a is shown by a dotted line. Further, a cutting position (cutting line, dicing line) DL of the cutting process in the step S10 b is shown by the two-dot chain line in FIG. 124.
  • For the manufacture of the semiconductor device, the frame 31 b in which a plurality of heat sinks 4 c are joined as shown in FIGS. 112 to 115 is prepared in the step S2 b. The frame 31 b has the same structure as the frame 31 a used in the manufacturing process described with reference to FIGS. 86 to 105 except that a wide portion (island portion) 33 b is provided in the joining portion 33 a and the pin portion 13 e is provided on the lower surface of the wide portion 33 b instead of the lower surface of the frame portion 32. The material of the frame 31 b is the same as those of the frames 31 and 31 a.
  • The wide portion 33 b is provided in the midst of the joining portion 33 a and is a portion in which the width of the joining portion 33 a is locally widened. Consequently, the wide portion 33 b can be also taken as a part of the joining portion 33 a, and in the joining portion 33 a, the width of the wide portion 33 b is larger than the width of the region other than the wide portion 33 b, and the pin portion 13 e is integrally formed on the lower surface of this wide portion 33 b. Also, it is not always necessary to provide the wide portion 33 b and the pin portion 13 e for all of the joining portions 33 a, and the wide portion 33 b and the pin portion 13 e may be provided for at least one of the plurality (four in this case) of the joining portions 33 a joined to each heat sink 4 c. However, it is more preferable to provide the wide portion 33 b and the pin portion 13 e for two joining portions located in the diagonal direction with interposing the heat sink 4 c therebetween of the four joining portions 33 a joined to each heat sink 4 c as shown in FIG. 112 because both the easiness of fixing of the frame 31 b to the wiring board 21 d and the strengthening of the fixing force can be satisfied. Although the frame 31 a and the frame 31 b are different in the position of the pin portion 13 e, since the shape of the pin portion 13 e is the same, the description thereof will be omitted here.
  • Further, in the step S1 b, as shown in FIG. 116, the wiring board 21 d for the manufacture of the semiconductor device is prepared. However, the wiring board 21 d has the same structure as the wiring board 21 c used in the manufacturing process described with reference to FIGS. 86 to 105 except that the position of the hole portion 15 a is different. More specifically, as a result of the change of the position of the pin portion 13 e between the frame 31 a and the frame portion 31 b, the position of the hole portion 15 a is also changed between the wiring board 21 c and the wiring board 21 d. While the hole portion 15 a is formed in an excess region outside the semiconductor device region 22 (region not contained in the semiconductor device 1 c in the cutting process in the step S10 b) in the wiring board 21 c, the hole portion 15 a is formed inside each semiconductor device region 22 in the wiring board 21 d. The wiring board 21 c and the wiring board 21 d are different in the position of the hole portion 15 a. However, since the shape of the hole portion 15 a is the same, the description thereof will be omitted here.
  • After the frame 31 b is prepared, the semiconductor chip 5 is bonded on the upper surface 9 a of each heat sink 4 c of the frame 31 b through the bonding agent 14 in the step S3 b. This process is the same as the manufacturing process described with reference to FIGS. 86 to 105.
  • Next, in the step S5 b, the frame 31 b is fixed to the wiring board 21 d. FIGS. 117 to 119 show a state in which the frame 31 b is fixed to the wiring board 21 d.
  • The frame 31 b is fixed to the wiring board 21 d in the step S5 b, but this process is the same as the manufacturing process described with reference to FIGS. 86 to 105 except for the positions of the pin portion 13 e and the hole portion 15 a for fixing the frame 31 b and the wiring board 21 d.
  • More specifically, in the step S5 b, the frame 31 b is positioned and disposed on the upper surface 21 a of the wiring board 21 d and each heat sink 4 c of the frame 31 b is inserted (plugged) into each through-hole 3 of the wiring board 21 d from the upper surface 21 a side of the wiring board 21 d, and at the same time, each pin portion 13 e of the frame 31 b is inserted (plugged) into each hole portion 15 a of the wiring board 21 d. Since the frame portion 32 and the joining portion 33 a are overlapped with the upper surface 21 a of the wiring board 21 d, the heat sink 4 c does not fall off downward from the through-hole 3 of the wiring board 21 d. The through-hole 3 and the hole portion 15 a of the wiring board 21 d are located at the position at which each pin portion 13 e of the frame 31 b is inserted into each hole portion 15 a of the wiring board 21 d when each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d.
  • A principle of fixing the frame 31 b to the wiring board 21 d is the same as the case where the frame 31 a is fixed to the wiring board 21 c. More specifically, as shown in FIG. 120, the pin portion 13 e provided on the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 b is also tapered, and in the step S5 b, as shown in FIGS. 120 and 121, the pin portion 13 e of the frame 31 b is inserted (pushed) into the hole portion 15 a of the wiring board 21 d, and the pin portion 13 e of the frame 31 b and the wiring board 21 d can be caulked (fixed) by the tapered shape of the pin portion 13 e. By this means, the frame 31 b is fixed to the wiring board 21 d.
  • While the case where a technique for inserting the pin portion 13 e provided in the frame 31 b into the hole portion 15 a provided in the wiring board 21 d is used for fixing the frame 31 b to the wiring board 21 d has been described, as another embodiment, the frame 31 b can be fixed to the wiring board 21 d by using the bonding agent in the step S5 b. FIGS. 122 and 123 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 b to the wiring board 21 d by using the bonding agent.
  • When the frame 31 b is fixed to the wiring board 21 d by using the bonding agent, the pin portion 13 e is not provided in the frame 31 b, and the hole portion 15 a is not provided in the wiring board 21 d. Instead, in the step S5 b, as shown in FIG. 122, the bonding agent 51 is coated (disposed) in advance on the upper surface 21 a of the wiring board 21 d, and then, the frame 31 b is disposed on the upper surface 21 a of the wiring board 21 d so that the wide portion 33 b of the joining portion 33 a of the frame 31 b is positioned on the bonding agent 51. At this time, each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d from the upper surface 21 a side of the wiring board 21 d. More specifically, the bonding agent 51 is coated at the position on the upper surface 21 a of the wiring board 21 d on which the wide portion 33 b of the joining portion 33 a of the frame 31 b overlaps when each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 of the wiring board 21 d. By this means, each heat sink 4 c of the frame 31 b is inserted into each through-hole 3 from the upper surface 21 a side of the wiring board 21 d, and at the same time, as shown in FIG. 123, the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 b is bonded to the upper surface 21 a of the wiring board 21 d through the bonding agent 51, so that the frame 31 b is fixed to the wiring board 21 d.
  • The subsequent process is the same as the manufacturing process described with reference to FIGS. 86 to 105. More specifically, the wire bonding process in the step S6 b, the molding process in the step S7 b, the solder ball 8 connecting process in the step S8 b, the marking process in the step S9 b, and the cutting process in the step S10 b are performed.
  • In this step S10 b, the wiring board 21 d, the frame 31 b and the sealing resin 7 a are cut along the cutting position (cutting line, dicing line) DL shown by the two-dot chain line in FIG. 124. However, in the manufacturing process described with reference to FIGS. 86 to 105, the pin portion 13 e and the hole portion 15 a are provided in the region (excess region) not contained later inside the semiconductor device 1 c in the frame 31 a and the wiring board 21 c, but in this case, the pin portion 13 e and the hole portion 15 a are provided in the region (semiconductor device region 22) contained later inside the semiconductor device 1 c in the frame 31 b and the wiring board 21 d. Therefore, as evident from FIG. 124 and FIGS. 125 and 126 to be described later, the wide portion 33 b, the pin portion 13 e and the hole portion 15 a are contained in the manufactured semiconductor device 1 c.
  • FIGS. 125 and 126 are a cross-sectional view and an upper surface perspective view (seen through the sealing resin 7) of the semiconductor device 1 c manufactured by the manufacturing process described with reference to FIGS. 112 to 124, and they almost correspond to FIGS. 107 and 108, respectively. The semiconductor device 1 c of FIGS. 125 and 126 manufactured by the manufacturing process described with reference to FIGS. 112 to 124 is different from the semiconductor device 1 c of FIGS. 106 to 108 manufactured by the manufacturing process described with reference to FIGS. 86 to 105 in the following points. That is, in the semiconductor device of FIGS. 125 and 126, the hole portion 15 a is present in the wiring board 2, the wide portion 33 b is present in the joining portion 33 a, and the pin portion 13 e integrally formed on the lower surface of the wide portion 33 b is inserted (disposed) inside the hole portion 15 a of the wiring board 2. Further, when the frame 31 b is fixed to the wiring board 21 d through the bonding agent 51 as shown in FIGS. 122 and 123 without providing the pin portion 13 e in the frame 31 b, the wide portion 33 b is present in the joining portion 33 a in the semiconductor device of FIGS. 125 and 126, but the hole portion 15 a is not present in the wiring board 2, and the wide portion 33 b and the upper surface 2 a of the wiring board 2 are bonded through the bonding agent 51. Further, in the wiring board 2 (that is, the wiring board 21 d) of the semiconductor device of FIGS. 125 and 126, the hole portion 15 a is disposed in such a manner to stay away from the connecting terminal 17 and the land 18.
  • For the improvement of the heat dissipation properties of the semiconductor device, it is preferable to increase the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted, but the weight of the heat sink 4 c increases as the thickness increases. Meanwhile, in the structure of the present embodiment, as described above, the plurality of heat sinks 4 c mutually joined are inserted into the through-holes 3 from the upper surface 21 a side of the wiring boards 21 c and 21 d, respectively, and the joining portion 33 a is located on the upper surface 21 a of the wiring boards 21 c and 21 d and the lower surface of the joining portion 33 a contacts to the upper surface 21 a of the wiring boards 21 c and 21 d, so that the joining portion 33 a supports the weight of the heat sink 4 c. Hence, even if the thickness of the heat sink 4 c is increased and the heat sink 4 c becomes heavy, the heat sink 4 c is firmly supported by the joining portion 33 a, and the heat sink 4 c can be prevented from falling off from the wiring boards 21 c and 21 d. Consequently, the thickness of the heat sink 4 c (thickness t1) can be increased and preferably made larger than the thickness of the wiring boards 21 c and 21 d (that is, the thickness t2 of the wiring board 2), so that the heat dissipation properties of the semiconductor device can be improved. Further, since the resin sealing process is performed in a state in which the joining portion 33 a supporting the heat sink 4 c is located on the upper surface 21 a of the wiring boards 21 c and 21 d and the lower surface of the joining portion 33 a contacts to the upper surface 21 a of the wiring boards 21 c and 21 d, this state is maintained even in the manufactured semiconductor device 1 c.
  • Further, in the fourth embodiment, the heat sink 4 c is not segmented into individual pieces, and the frames 31 a and 31 b and the wiring boards 21 c and 21 d are integrally resin-sealed in the step S7 b, and then, the sealing body is segmented into individual pieces by the cutting process in the step S10 b. Therefore, as compared with the first and second embodiments, the cutting process (process corresponding to step S4) for the segmentation into individual pieces of the heat sink 4 c can be omitted, and the manufacturing process can be simplified.
  • Further, in the fourth embodiment, by integrating the frame 31 a and the wiring board 21 c (or the frame 31 b and the wiring board 21 d), a process conveyance form can be made into a frame 31 a (or frame 31 b) support type. Therefore, regardless of the thickness of the wiring board 21 c (or the wiring board 21 d), it can be adapted to the case where the groove of a process conveyance system is constant. Further, the frame 31 a (or frame 31 b) retaining the heavy heat sink 4 c is made as a conveyance system support, thereby preventing the falling off of the heat sink 4 c more surely.
  • Further, in the manufacturing process and the structure shown in FIGS. 112 to 126, the bonding portion (bonding portion through the pin portion 13 e or the bonding agent 51) between the joining portion 33 a and the wiring board 21 d remains inside the manufactured semiconductor device 1 c, and therefore, also in the manufactured semiconductor device 1 c, the supporting (retaining, fixing) of the heavy heat sink 4 c can be strengthened without committing the bonding and supporting of the heat sink 4 c and the wiring board 2 to only the curing fixation of the sealing resin 7.
    • Fifth Embodiment
  • In the fourth embodiment above, the frame 31 b in which a plurality of heat sinks 4 c are joined and the multiply-connected wiring board are fixed to manufacture the semiconductor devices. However, in the present embodiment, individually segmented wiring boards 2 f are fixed to a frame 31 c in which a plurality of heat sinks 4 c are joined, thereby manufacturing the semiconductor devices.
  • FIG. 127 is a process flowchart showing a manufacturing process of the semiconductor device of the present embodiment. FIG. 128 is an upper surface view (plan view) of the frame 31 c used for the manufacture of the semiconductor device of the present embodiment, FIG. 129 is an lower surface view (plan view) of the frame 31 c, and FIG. 130 is a cross-sectional view of the frame 31 c. The cross-section cut along the line A21-A21 of FIGS. 128 and 129 corresponds to FIG. 130. Although FIG. 128 is a plan view, hatching is applied to the frame 31 c so as to make a shape of the frame 31 c easily understood. Further, FIGS. 131 and 132 are a plan view (upper surface view) and a cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 131 shows a planar region corresponding to FIG. 128 and FIG. 132 shows the cross-section corresponding to FIG. 130. FIG. 133 is an upper surface view (plan view) of the wiring board 2 f used for the manufacture of the semiconductor device of the present embodiment. FIGS. 134 to 136 are plan views (upper surface view and lower surface view) and a cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment, and FIG. 134 which is the upper surface view shows the planar region corresponding to FIGS. 128 and 131, FIG. 135 which is the lower surface view shows the planar region corresponding to FIG. 129, and FIG. 136 which is the cross-sectional view shows the cross-section corresponding to FIG. 132. FIGS. 137 to 140 are explanatory drawings (cross-sectional views) for explaining a technique for fixing the wiring board 2 f to the frame 31 c. Also, FIGS. 141 to 145 are plan views (upper surface view and lower surface view) and cross-sectional views in the manufacturing process of the semiconductor device of the present embodiment. FIG. 141 is a cross-sectional view and shows the cross-section corresponding to FIG. 136. FIG. 142 which is the upper surface view, FIG. 143 which is the lower surface view, and FIG. 144 which is the cross-sectional view show the same process stage (process stage after FIG. 141), and FIG. 142 shows the same planar region as FIG. 134, FIG. 143 shows the same planar region as FIG. 135, and FIG. 144 shows the cross-section corresponding to FIGS. 136 and 141. Note that, in FIG. 142, an outer shape of the frame 31 c located below the sealing resin 7 is shown by a dotted line for easy understanding. Also, FIG. 145 is a cross-sectional view of the process stage after FIG. 144 and shows the cross-section corresponding to FIG. 144.
  • For the manufacture of the semiconductor device, as shown in FIGS. 128 to 130, the frame 31 c in which a plurality of heat sinks 4 c are joined is prepared (step S2 c).
  • The structure of the frame 31 c is almost the same as the frame 31 b of the fourth embodiment expect the following points. That is, in the frame 31 c, a joining portion 34 for mutually joining the frame portions 32 is provided to reinforce the frame 31 c. Further, in the frame 31 c, the wide portion (island portion) 33 b similar to that of the frame 31 b is provided for each joining portion 33 a for joining the heat sink 4 c and the frame portion 32. Further, in the frame 31 c, the pin portion 13 e is not provided on the lower surface of the wide portion 33 b. Except for these, the frame 31 c has the same structure as the frame 31 b of the fourth embodiment, and the material of the frame 31 c is also the same as the frames 31, 31 a and 31 b.
  • Similar to the frames 31 a and 31 b of the fourth embodiment, the frame 31 c has a structure in which a plurality of unit regions (unit frame region, semiconductor region) 23 are disposed (joined) in a row. This unit region 23 is a region used for manufacturing one semiconductor device (semiconductor device 1 e to be described later) and has one heat sink 4 c and four joining portions 33 a joined to the heat sink 4 c.
  • Further, it is not always necessary to provide the wide portion 33 b for all of the joining portions 33 a in the frame 31 c, and the wide portion 33 b may be provided for at least one of the plurality (four in this case) of the joining portions 33 a joined to each heat sink 4 c. For example, like in the frame 31 b of the fourth embodiment, the wide portion 33 b may be provided for two joining portions located in a diagonal direction with interposing the heat sink 4 c therebetween of the four joining portions 33 a connected to each heat sink 4 c. However, in the present embodiment, as described later, it is necessary to fix one individually segmented wiring board 2 f to each unit region (one heat sink 4 c and four joining portions 33 a joined thereto) of the frame 31 c. Therefore, it is more preferable that the wide portion 33 b is provided for all the four joining portions 33 a connected to each heat sink 4 c as shown in FIGS. 128 and 129 because the wiring board 2 f can be precisely and stably fixed to each unit region of the frame 31 c.
  • After the frame 31 c is prepared, as shown in FIGS. 131 and 132, the semiconductor chip 5 is bonded on the upper surface 9 a of each heat sink 4 c of the frame 31 c through the bonding agent 14 (step S3 c). Since the bonding process of the semiconductor chip 5 in the step S3 c can be performed in the same manner as the bonding process of the semiconductor chip 5 in the step S3, the detailed description thereof will be omitted here.
  • Further, as shown in FIG. 133, the wiring board 2 f is prepared (step S1 c). Although this wiring board 2 f almost corresponds to the one obtained by separating the wiring board 21 d used in the fourth embodiment into the semiconductor device region 22, the hole portion 15 a is not formed in the wiring board 2 f. More specifically, this wiring board 2 f is not the multiply-connected wiring board, and one semiconductor device is manufactured from one wiring board 2 f. The wiring board 2 f has the same structure as the wiring board 2 in the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment except for the shape of the solder resist layer 19 to be described later. Consequently, the through-hole 3 is formed in the wiring board 2 f, a plurality of connecting terminals 17 and the wirings connected thereto are formed on the upper surface 2 a of the wiring board 2 f, and a plurality of lands 18 are formed on the lower surface 2 b of the wiring board 2 f.
  • Next, as shown in FIGS. 134 to 136, the wiring board 2 f is fixed to the frame 31 c (step S5 c). Before performing this step S5 c, it is necessary to prepare the wiring board 2 f in the step S1 c. Therefore, the preparation of the wiring board 2 f in the step S1 c can be performed before the step S2 c, simultaneously with the step S2 c, before the step S3 c and after the step S2 c, simultaneously with the step S3 c or before the step S5 c and after the step S3 c.
  • The multiply-connected wiring boards 21 c and 21 d are fixed to the multiply-connected frames 31 a and 31 b in the fourth embodiment, but in the present embodiment, a plurality of wiring boards 2 f are fixed to the frame 31 c in which a plurality of heat sinks 4 c are joined in the step S5 c. The wiring board 2 f is fixed to each of the plurality of unit regions 23 of the frame 31 c.
  • More specifically, in the step S5 c, the plurality of wiring boards 2 f are disposed side by side and the frame 31 c is positioned and disposed thereon, so that each heat sink 4 c of the frame 31 c is inserted (plugged) into each through-hole 3 of the wiring board 2 f from the upper surface 2 a side of the wiring board 2 f, and at the same time, the wiring board 2 f is fixed to the frame 31 c.
  • Here, the frame 31 c and the wiring board 2 f are fixed by the bonding agent. FIGS. 137 and 138 are explanatory drawings (cross-sectional views) showing a technique for fixing the frame 31 c to the wiring board 2 f by using the bonding agent.
  • In the step S5 c, before the heat sink 4 c of the frame 31 c is interested into the through-hole 3 of the wiring board 2 f, as shown in FIG. 137, the bonding agent 51 is coated (disposed) in advance on the upper surface 2 a of the wiring board 2 f, and then, the frame 31 c is disposed on the upper surface 2 a of the wiring board 2 f so that the wide portion 33 b of the joining portion 33 a of the frame 31 c is positioned on the bonding agent 51. At this time, each heat sink 4 c of the frame 31 c is inserted into each through-hole 3 of the plurality of wiring boards 2 f from the upper surface 2 a side of the wiring board 2 f. More specifically, the bonding agent 51 is coated at the position on the upper surface 2 a of each wiring board 21 f on which the wide portion 33 b of the joining portion 33 a of the frame 31 c overlaps when each heat sink 4 c of the frame 31 c is inserted into the through-hole 3 of each wiring board 21 f. By this means, each heat sink 4 c of the frame 31 c is inserted into the through-hole 3 of each wiring board 2 f from the upper surface 2 a side of the wiring board 2 f, and at the same time, as shown in FIG. 138, the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 is bonded to the upper surface 2 a of the wiring board 2 f through the bonding agent 51, so that the wiring board 2 f is fixed to the frame 31 c. More specifically, in each unit region 23 of the frame 31 c, the lower surface of the wide portion 33 b of the joining portion 33 a is bonded and fixed to the upper surface 2 a of the wiring board 2 f through the bonding agent 51. As the bonding agent 51, a film type bonding agent such as a DAF (die attach film) can be also used.
  • As described above, each heat sink 4 c in the frame 31 c has the joining portion 33 a protruding to the outside (in the direction away from the center of the upper surface 9 a) from the side surface of each heat sink 4 c in the peripheral edge portion of the upper surface 9 a of each heat sink 4 c, and in the step S5 c, each heat sink 4 c is disposed inside the through-hole 3 of the wiring board 2 f so that this joining portion 33 a is located on the upper surface 2 a of the wiring board 2 f outside the through-hole 3 and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 f.
  • The case where the bonding agent 51 is used to fix the frame 31 c and the wiring board 2 f in the step S5 c has been described, but as another embodiment, in the step S5 c, a technique for inserting the pin portion 13 e provided in the frame 31 c into the hole portion 15 a provided in the wiring board 2 f can be also used, and FIGS. 139 and 140 are the explanatory drawings thereof (cross-sectional views). This principle is the same as the technique described with reference to FIGS. 120 and 121 in the fourth embodiment. More specifically, like in the frame 31 b and the wiring board 21 d of the fourth embodiment, the pin portion 13 e is formed in advance on the lower surface of the wide portion 33 b also in the frame 31 c, and the hole portion 15 a is formed in advance in the wiring board 2 f. Then, in the step S5 c, the pin portion 13 e (pin portion 13 e having a tapered shape) provided on the lower surface of the wide portion 33 b of the joining portion 33 a of the frame 31 c as shown in FIG. 139 is inserted (pushed) into the hole portion 15 a of the wiring board 2 f as shown in FIG. 140, and the pin portion 13 e of the frame 31 c and the wiring board 2 f can be caulked (fixed) by the tapered shape of the pin portion 13 e. By this means, the frame 31 c and the wiring board 2 f are fixed.
  • Further, the step S3 c (bonding process of the semiconductor chip 5) can also be performed after the step S5 c (process of fixing the frame 31 c and the wiring board 2 f) and before the step S6 c (wire bonding process) to be described later.
  • After the plurality of wiring boards 2 f are fixed to the frame 31 c in the step S5 c, as shown in FIG. 141, a wire bonding process is performed, so that each electrode 5 a of the semiconductor chip 5 and the connecting terminal 17 formed on the wiring board 2 f corresponding to the electrode 5 a are electrically connected through the bonding wire 6 (step S6 c). More specifically, the plurality of connecting terminals 17 on the upper surface 21 a of each wiring board 2 f and the plurality of electrodes 5 a of the semiconductor chip 5 bonded (mounted) on the heat sink 4 c disposed inside the through-hole 3 of the wiring board 2 f are electrically connected through the plurality of bonding wires 6, respectively.
  • After the wire bonding process, as shown in FIGS. 142 to 144, the resin sealing by the molding process (for example, the transfer-molding process) is performed to form the sealing resin 7 (sealing portion), and the semiconductor chip 5 and the bonding wire 6 are sealed (resin-sealed) by the sealing resin 7 (step S7 c).
  • In the present embodiment, as shown in FIGS. 142 to 144, in the molding process in the step S7 c, the individual sealing for individually sealing each unit region 23 of the frame 31 c by the sealing resin 7 is performed. More specifically, in each unit region 23 of the frame 31 c, the sealing resin 7 is formed on the upper surface 2 a of the wiring board 2 f so as to cover the semiconductor chip 5 and the bonding wire 6. In this case, the sealing resin 7 is formed for each unit region 23 of the frame 31 c, and is not integrally formed for the adjacent unit regions 23. The sealing resin 7 is made of, for example, a resin material such as a thermosetting resin material and can contain the filler and the like. For example, the sealing resin 7 can be formed by using the epoxy resin and the like containing the filler. For example, the sealing resin material is injected into a cavity of the metal mold in which the frame 31 c to which the wiring board 2 f is fixed is disposed, and this sealing resin material is hardened by heating, so that the sealing resin 7 can be formed.
  • In the present embodiment, as described later, the sealing resin 7 is formed so as to cover not only the upper surface 2 a of the wiring board 2 f but also the side surface of the wiring board 2 f. Further, the sealing resin 7 is formed so that the frame portion 32 of the frame 31 is located outside the sealing resin 7.
  • After the frame 31 c and the plurality of wiring boards 2 f are fixed in the step S5 c, a state in which the upper surface 2 a of the wiring board 2 f is directed upward without turning the frame 31 c upside down is preferably maintained until the molding process in the step S7 c is performed. More specifically, after fixing the frame 31 c to the plurality of wiring boards 2 f in the step S5 c, the wiring board 2 f has the upper surface 2 a directed upward (that is, the upper surface of the frame 31 c is also directed upward) so that the lower surface 2 b thereof is not directed upward until the molding process in the step S7 c is performed. As a result, the falling off of the frame 31 c from the wiring board 2 f before the sealing resin 7 is formed can be prevented more precisely. By forming the sealing resin 7, the frame 31 c and the wiring board 2 f are solidly bonded by the sealing resin 7, and therefore, after forming the sealing resin 7, the wiring board 2 f may be directed to any direction (lower surface 2 b of the wiring board 2 f may be directed upward).
  • Next, as shown in FIG. 145, the solder balls 8 are connected (bonded) to the lands 18 of the lower surface 2 b of each wiring board 2 f (step S8 c). Then, marking is performed as needed, and a mark such as a product number and the like is applied onto the front surface of the sealing resin 7 (step S9 c). Since the connecting process of the solder ball 8 in the step S8 c and the marking process in the step S9 c can be performed in the same manner as the connecting process of the solder ball 8 in the step S8 and the marking process in the step S9 of the first embodiment, the detailed description thereof will be omitted here. The marking process in the step S9 c may be performed after the connecting process of the solder ball 8 in the step S8 c is performed, or the connecting process of the solder ball 8 in the step S8 c may be performed after the marking process in the step S9 c is performed. Alternatively, if not needed, the marking process in the step S9 c may be omitted.
  • Next, the frame 31 c is cut (step S10 c). More specifically, the portion protruding from the side surface of the sealing resin 7 of the frame 31 c is cut and removed.
  • FIGS. 146 and 147 are explanatory drawings (cross-sectional views) of the cutting process of the frame 31 c, and FIG. 146 is a cross-sectional view showing the state before the cutting process in the step S10 c and FIG. 147 is a cross-sectional view showing the state after the cutting process in the step S10 c, in which the cross-sections along the joining portion 33 a of the frame 31 c are illustrated.
  • Before the cutting process in the step S10 c, as shown in FIG. 146, the sealing bodies 24 (structure sealing the wiring board 5, the heat sink 4 and the semiconductor chip 5 by the sealing resin 7) of the adjacent unit regions 23 are joined by a part of the frame 31 c (joining portion 33 a and frame portion 32). In the cutting process in the step S10 c, the frame 31 c outside the sealing body 24 (portion of the joining portion 33 a not sealed by the sealing resin 7, the frame portion 32 and the jointing portion 34) is cut and removed. By this means, the individually segmented sealing body 24 as shown in FIG. 147, that is, the semiconductor device 1 e is obtained (manufactured).
  • By performing the cutting and the individual segmentation in this manner, the semiconductor device 1 e of the present embodiment is manufactured.
  • FIGS. 148 and 149 are cross-sectional views (side cross-sectional views) of the semiconductor device 1 e of the present embodiment, and FIG. 150 is a perspective plan view (upper surface view) of the semiconductor device 1 e when the sealing resin 7 is seen through. FIG. 151 is a lower surface view of the wiring board 2 f used in the semiconductor device 1 e of the present embodiment. FIGS. 148 to 150 correspond to FIGS. 106 to 109 of the fourth embodiment, respectively. The cross-section cut along the line A22-A22 of FIG. 150 almost corresponds to FIG. 148, and the cross-section cut along the line A23-A23 of FIG. 150 almost corresponds to FIG. 149. Further, though FIG. 151 is plan view, hatching is applied to the solder resist layer 19 so that the planar shape (pattern) of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 f is easily understood.
  • A structure of the semiconductor device 1 e will be described in relation to the difference from the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment.
  • In the semiconductor device 1 e shown in FIGS. 148 to 150, the wide portion 33 is present in the joining portion 33 a, and the lower surface of the wide portion 33 b is bonded to the upper surface 2 a of the wiring board 2 f through the bonding agent 51 (illustration thereof is omitted in FIG. 149). Further, the sealing resin 7 is formed so as to cover not only the upper surface 2 a of the wiring board 2 f but also a side surface 55 of the wiring board 2 f. In the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment, the side surface of the wiring board 2 and the side surface of the sealing resin 7 are flush with each other, and the joining portion 33 a connected to the heat sink 4 c extends on the upper surface 2 a of the wiring board 2 until reaching the side surface of the sealing resin 7. In contrast to this, in the semiconductor device 1 e of the present embodiment, since not only the upper surface 2 a of the wiring board 2 f but also the side surface 55 thereof is covered by the sealing resin 7 (that is, not exposed), the joining portion 33 a connected to the heat sink 4 c extends on the upper surface 2 a of the wiring board 2 f, and further extends in the sealing resin 7 over an end portion of the upper surface 2 a of the wiring board 2 f until reaching the side surface of the sealing resin 7. Further, when the frame 31 c and the wiring board 2 f are fixed by a technique described with reference to FIGS. 139 and 140, the hole portion 15 a is formed in the wiring board 2 f like in FIG. 125, and the pin portion 13 e integrally provided on the lower surface of the wide portion 33 b is inserted (disposed) into the hole portion 15 a. Further, a shape of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f is devised as follows. Except for this, the structure of the semiconductor device 1 e of the present embodiment is the same as the semiconductor device 1 c of FIGS. 106 to 108 of the fourth embodiment, and therefore, the description thereof will be omitted here.
  • Next, the shape of the solder resist layer 19 on the lower surface 2 b of the wiring board 2 f will be described with reference to FIG. 151. Although the solder resist layer exposing the connecting terminal 17 and the land 18 is formed on the upper surface 2 a and the lower surface 2 b of the wiring board 2 f, hereinafter, an illustration and a description of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f will be made, whereas an illustration and a description of the solder resist layer formed on the upper surface 2 a of the wiring board 2 f will be omitted.
  • In the structure of the present embodiment, not only the upper surface 2 a of the wiring board 2 f but also the side surface 55 of the wiring board 2 f is covered by the sealing resin 7, and therefore, a gap is present between the side surface 55 of the wiring board 2 f and a metal mold in the molding process in the step S7 c. Hence, the resin material invades between the metal mold and the lower surface 2 b of the wiring board 2 f, and a resin burr is formed on the lower surface 2 b of the wiring board 2 f, so that the resin is easily adhered to the land 18. Therefore, the shape of the solder resist layer 19 formed on the lower surface 2 b of the wiring board 2 f is made as shown in FIG. 151.
  • On the lower surface 2 b of the wiring board 2 f, the solder resist layer 19 is formed in the hatched region in FIG. 151. The region 20 is a region in which the solder resist layer 19 is not formed on the lower surface 2 b of the wiring board 2 f, and is a region in which the lower surface of the base material layer (base material layer 16) of the wiring board 2 f is exposed.
  • Also in the present embodiment, the solder resist layer 19 is formed on the lower surface 2 b of the wiring board 2 f. In the present embodiment, as shown in FIG. 151, the solder resist layer 19 of the lower surface 2 b of the wiring board 2 f includes a first solder resist portion 19 a provided in the vicinity of the through-hole 3 so as to surround the periphery of the through-hole 3, a second solder resist portion 19 b located in the periphery (outer periphery) of the first solder resist portion 19 a, and a third solder resist portion 19 c located further in the periphery (outer periphery) of the second solder resist portion 19 b. More specifically, the first solder resist portion 19 a is formed in the periphery of the through-hole 3, the third solder resist portion 19 c is formed in the peripheral edge portion of the lower surface 2 b of the wiring board 2 f, and the second solder resist portion 19 b is formed between the first solder resist portion 19 a and the third solder resist portion 19 c.
  • Between the first solder resist portion 19 a and the second solder resist portion 19 b, there is the region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16) of the wiring board 2 f is exposed. Consequently, the first solder resist portion 19 a and the second solder resist portion 19 b are isolated with interposing the region 20 therebetween. Further, between the second solder resist portion 19 b and the third solder resist portion 19 c, there is the region (dam region) 20 in which the solder resist layer 19 is not formed and the base material layer (base material layer 16) of the wiring board 2 f is exposed. Consequently, the second solder resist portion 19 b and the third solder resist portion 19 c are isolated with interposing the region 20 therebetween.
  • The plurality of lands 18 provided on the lower surface 2 b of the wiring board 2 f are exposed from the openings formed in the second solder resist portion 19 b. The second solder resist portion 19 b has the openings for exposing the lands 18, and a conductive pattern for the land 18 is exposed from the opening. The opening of the solder resist layer 19 for exposing the land 18 is formed in the second solder resist portion 19 b, and is not formed in the first solder resist portion 19 a and the third solder resist portion 19 c.
  • In the molding process in the step S7 c, as described in the fourth embodiment, the resin material (mold resin) flowing between the inner wall of the through-hole 3 of the wiring board 2 f and the side surface (side wall) 10 a of the heat sink 4 c is likely to overflow to the lower surface 2 b side of the wiring board 2 f. For its prevention, in the present embodiment, the region (dam region) 20 in which no solder resist layer 19 is present and the base material layer (base material layer 16) of the wiring board 2 f is exposed is provided between the first solder resist portion 19 a and the second solder resist portion 19 b, so that the resin material (mold resin) overflowing to the lower surface 2 b side of the wiring board 2 f from the gap between the through-hole 3 and the heat sink 4 c can be prevented from spreading up to the second solder resist portion 19 b over the region 20.
  • Further, in the structure of the present embodiment, since the side surface 55 of the wiring board 2 f is also covered by the sealing resin 7, the resin material is likely to invade between the metal mold and the lower surface 2 b of the wiring 2 f in the molding process in the step S7 c.
  • For its prevention, in the present embodiment, the region (dam region) 20 in which no solder resist layer 19 is present and the base material layer (base material layer 16) of the wiring board 2 f is exposed is provided between the third solder resist portion 19 c and the second solder resist portion 19 b. By this means, the resin material (mold resin) intending to invade between the metal mold and the lower surface 2 b of the wiring board 2 f from an external end portion (lower end of the side surface 55) of the lower surface 2 b of the wiring board 2 f can be prevented from spreading up to the second solder resist portion 19 b over the region 20 between the third solder resist portion 19 c and the second solder resist portion 19 b.
  • Therefore, it is possible to prevent the resin material from adhering to the land 18 of the lower surface 2 b of the wiring board 2 f in the molding process in the step S7 c, and the reliability of the connection between the land 18 and the solder ball 8 can be improved.
  • For the improvement of the heat dissipation properties of the semiconductor device, it is preferable to increase the thickness of the heat sink 4 c on which the semiconductor chip 5 is mounted, but the weight of the heat sink 4 c increases as the thickness increases. Meanwhile, in the structure of the present embodiment, as described above, the plurality of heat sinks 4 c mutually joined are inserted into the through-holes 3 of the wiring boards 2 f from the upper surface 2 a side of the wiring board 2 f, respectively, and the joining portion 33 a is located on the upper surface 2 a of each wiring board 2 f and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 f, so that the joining portion 33 a supports the weight of the heat sink 4 c. Hence, even if the thickness of the heat sink 4 c is increased and the heat sink 4 c becomes heavy, the heat sink 4 c is firmly supported by the joining portion 33 a, and the heat sink 4 c can be prevented from falling off from the wiring board 2 f. Consequently, the thickness of the heat sink 4 c (thickness t1) can be increased and preferably made larger than the thickness of the wiring board 2 f (that is, the thickness t2 of the wiring board 2), so that the heat dissipation properties of the semiconductor device can be improved. Further, since the resin sealing process is performed in a state in which the joining portion 33 a supporting the heat sink 4 c is located on the upper surface 2 a of the wiring board 2 f and the lower surface of the joining portion 33 a contacts to the upper surface 2 a of the wiring board 2 f, this state is maintained even in the manufactured semiconductor device 1 e.
  • Further, since the individually segmented (individualized) wiring board 2 f is used in the fifth embodiment, it is possible to use only the non-defective wiring board 2 f. Ordinarily, according to the nature of the processing of the wiring board, in the multiply-connected wiring board in which a plurality of unit board regions (equivalent to the semiconductor device regions 22) are disposed (connected) in a row or plural rows, the plurality of unit board regions constituting the multiply-connected wiring board are not always constituted of only the non-defective products, and the case where the unit board region having a defect is present in the plurality of unit board regions constituting the multiply-connected wiring board occurs frequently. In such a case, when the semiconductor device is manufactured by using the multiply-connected wiring board, a series of processing must be performed for the plurality of unit board regions including the unit board region having a defect, and the semiconductor device manufactured from the unit board region having a defect has to be eliminated after the manufacture of the semiconductor devices, so that the processing materials are wasted. However, in the present embodiment, since the individually segmented (individualized) wiring boards 2 f are used, the wiring board having a defect is removed in advance and only the wiring board 2 f having no defect can be attached to the frame 31 c in which the plurality of heat sinks 4 c are joined, so that the processing material can be efficiently used.
  • Further, also in the present embodiment, the bonding portion (bonding portion through the pin portion 13 e or the bonding agent 51) between the joining portion 33 a and the wiring board 2 f remains inside the manufactured semiconductor device 1 e like in the manufacturing process and the structure shown in FIGS. 112 to 126 of the fourth embodiment. Hence, also in the manufactured semiconductor device 1 e, the support (retaining, fixing) of the heavy heat sink 4 c can be strengthened without committing the bonding and supporting of the heat sink 4 c and the wiring board 2 f to only the curing fixation of the sealing resin 7.
    • Sixth Embodiment
  • FIG. 152 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 f of the sixth embodiment, and it corresponds to FIG. 1 of the first embodiment.
  • The semiconductor device 1 f of the present embodiment has almost the same structure as the semiconductor device 1 of the first embodiment except that a heat sink (Heat Spreader) 61 is mounted on a front surface 5 b of the semiconductor chip 5 through a bonding agent 62 and an upper surface 61 a of the heat sink 61 is exposed from an upper surface 7 b of the sealing resin 7, and therefore, the description thereof will be omitted and the difference from the semiconductor device 1 of the first embodiment will be mainly described.
  • In the semiconductor device 1 f of the present embodiment, the heat sink 61 is mounted (disposed, bonded) on the front surface 5 b of the semiconductor chip 5 mounted (disposed) on the heat sink 4 through the bonding agent (adhering material) 62. Hence, the semiconductor chip 5 is vertically sandwiched between the heat sink 61 and the heat sink 4. The heat sink 61 is disposed on an inner region with respect to the electrode 5 a on the front surface 5 b of the semiconductor chip 5 so that the heat sink 61 does not contact to the electrode 5 a of the semiconductor chip 5 and the bonding wire 6. For example, if a planar shape of the semiconductor chip 5 is a rectangular shape, the planar shape of the heat sink 61 can be made into a rectangular shape smaller than the semiconductor chip 5. As the bonding agent 62, a bonding agent having high heat conductivity is preferably used, and for example, solder and a conductive paste material (the paste material preferable as a conductive paste material is silver paste) and the like can be used.
  • The upper surface 61 a of the heat sink 61 is exposed from the upper surface 7 b of the sealing resin 7, and this upper surface 61 a is a surface (main surface) opposite to the side opposing to the front surface 5 b of the semiconductor chip 5.
  • The heat sink 61 is a member for dissipating the heat generated in the semiconductor chip 5 and preferably has high heat conductivity, and it is necessary that the heat conductivity (heat conductivity coefficient) of the heat sink is higher than at least the heat conductivity (heat conductivity coefficient) of the sealing resin 7. Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat sink 61 is preferably made of a conductive material and is more preferably formed of a metal material. It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 61 because high heat conductivity of the heat sink 61 can be obtained and the processing thereof (formation of the heat sink 61) is easy. Further, it is more preferable that the heat sink 61 is made of the same material as the heat sink 4, and by this means, the heat sink 61 and the heat sink 4 sandwiching the semiconductor chip 5 come to have the same heat expansion coefficient. Thus, the heat stress acting on the semiconductor chip 5 can be reduced, so that the reliability of the semiconductor device can be more improved. Therefore, it is most preferable that both the heat sink 61 and the heat sink 4 are formed of copper (Cu) or copper (Cu) alloy.
  • In the semiconductor device 1 f of the present embodiment, the heat generated in the semiconductor chip 5 is transmitted to the heat sink 4 through the bonding agent 14 and dissipated to the outside of the semiconductor device 1 from the portion of the heat sink 4 (lower portion of the heat sink 4) exposed on the lower surface (lower surface 2 a of the wiring board 2) side of the semiconductor device 1 like in the semiconductor device 1 of the first embodiment. Further, in the semiconductor device 1 f of the present embodiment, the heat generated in the semiconductor chip 5 is transmitted also to the heat sink 61 through the bonding agent 62, and the heat is dissipated to the outside of the semiconductor device 1 f from the portion of the heat sink 61 (upper surface 61 a of the heat sink 61) exposed from the upper surface 7 b of the sealing resin 7. As described above, the semiconductor device 1 f of the present embodiment can dissipate the heat from both below and above, and therefore, the heat dissipation properties can be further improved.
  • Next, the manufacturing method of the semiconductor device 1 f of the present embodiment will be described with reference to the drawings. FIGS. 153 to 158 are cross-sectional views in the manufacturing process of the semiconductor device 1 f of the present embodiment.
  • The structure of FIG. 153 similar to that of FIG. 16 is obtained in the same manner as the first embodiment. Since the process up to this stage (up to the step S3) is the same as the first embodiment, the description thereof will be omitted. Since FIG. 153 is a cross-sectional view of the same region as FIG. 16, each of the heat sinks 4 is not segmented, but is integrated as the frame 31 at the stage of FIG. 153.
  • After the structure of FIG. 153 is obtained, solder (solder paste) 62 a is coated on the front surface 5 b of each semiconductor chip 5 mounted on each heat sink 4 of the frame 31 through a nozzle (not shown), and then, as shown in FIG. 154, the heat sink 61 is mounted on the front surface 5 b of each semiconductor chip 5 through the solder 62 a. In place of the paste-like solder 62 a, a sheet-like solder may be supplied on the front surface 5 b of the semiconductor chip 5 by using the printing method and the transfer method. Then, by performing a solder reflow process (heat treatment), the heat sink 61 can be bonded and fixed on the front surface 5 b of each semiconductor chip 5 through the solder 62 a (bonding agent 62). The molten and solidified solder 62 a by this solder reflow becomes the bonding agent 62. Further, at the time of the solder reflow, not only the solder 62 a but also the solder 14 a can be melted and re-solidified.
  • High melting point solder similar to the solder 14 a is preferably used for the solder 62 a, and the solder having a melting point at least higher than the melting point of the solder used for an external terminal (in this case, solder ball 8) formed on the land 18 later is preferably used as the solder 62 a. By this means, even when the solder ball 8 is melt in the connecting process of the solder ball 8 in the step S8 and the mounting process of the completed semiconductor device if (process of mounting the semiconductor device if on the wiring board 41), the solder 62 a (that is, the bonding agent 62 made of the solder 62 a) for bonding the semiconductor chip 5 and the heat sink 61 can be prevented from melting. Accordingly, the bonding reliability of the semiconductor chip 5 and the heat sink 62 can be improved, and the heat conductivity from the semiconductor chip 5 to the heat sink 62 is improved, so that the heat dissipation properties of the semiconductor device if can be improved.
  • The subsequent process is almost the same as the first embodiment (steps S4 to S10).
  • More specifically, after the individual segmentation of the heat sink 4 in the step S4 is performed in the same manner as the first embodiment, the step S5 is performed in the same manner as the first embodiment, and as shown in FIG. 155, the heat sink 4 mounted with the semiconductor chip 5 having the heat sink 61 mounted thereon is disposed inside the through-hole 3 of each semiconductor device region 22 of the wiring board 21. Since step S5 has been described in detail in the first embodiment, the description thereof will be omitted here.
  • Next, the wire bonding process in the step S6 is performed in the same manner as the first embodiment, and as shown in FIG. 156, each electrode 5 a of the semiconductor chip 5 and the corresponding connecting terminal 17 formed on the wiring board 21 are electrically connected through the bonding wire 6.
  • Next, the molding process in the step S7 is performed in the same manner as the first embodiment, and as shown in FIG. 157, the sealing resin 7 a is formed and the semiconductor chip 5, the bonding wire 6 and the heat sink 61 are sealed (resin-sealed) by the sealing resin 7 a. At this time, the sealing resin 7 a is formed so that the upper surface 61 a of the heat sink 61 is exposed from the upper surface of the sealing resin 7 a, and this is the difference between the present embodiment and the first embodiment.
  • Next, the connecting process of the solder ball in the step S8 is performed in the same manner as the first embodiment, and as shown in FIG. 158, the solder ball 8 is connected (bonded) to the land 18 of the lower surface 21 b of the wiring board 21.
  • Thereafter, the marking process in the step S9 and the cutting process in the step S10 are performed in the same manner as the first embodiment, and the wiring board 21 and the sealing resin 7 a formed thereon are cut (diced) and separated (divided) into each semiconductor device region 22. By this means, the semiconductor device if as shown in FIG. 152 can be manufactured.
  • In the manufacturing process of FIGS. 153 to 158, before the heat sink 4 is disposed inside the through-hole 3 of the wiring board 21 in the process of FIG. 155 (corresponding to step S5), the semiconductor chip 5 is bonded on the heat sink 4 and the heat sink 61 is bonded on the semiconductor chip 5 in the process of FIG. 153 (corresponding to step S3) and the process of FIG. 154. Hence, there is an advantage that a high temperature heat treatment can be performed as the heat treatment for bonding the heat sink 4 and the semiconductor chip 5 and for bonding the semiconductor chip 5 and the heat sink 61 without regard to the heat resistance of the wiring board 21. When the high temperature heat treatment is performed as the heat treatment for bonding the semiconductor chip 5 to the heat sink 4 and for bonding the heat sink 61 to the semiconductor chip 5, for example, when the solders 14 a and 62 a having a melting point higher than that of the solder used for the external terminal (in this case, solder ball 8) formed on the land 18 are used, it is preferable to apply the manufacturing process described with reference to FIGS. 153 to 158 because the wiring board 21 is not damaged at the time of high temperature heat treatment (solder reflow). Further, if the solder is used as the bonding agent 62, the heat conductivity of the bonding agent 62 becomes high as compared with the case of using the silver paste, and therefore, the heat transmission from the semiconductor chip 5 to the heat sink 61 is more increased, so that the heat dissipation properties of the semiconductor device 1 f can be more improved.
  • As another embodiment of the manufacturing process of the semiconductor device 1 f, the heat sink 61 can be bonded on the front surface 5 b of the semiconductor chip 5 after the process up to the wire bonding process in the step S6 is performed in the same manner as the first embodiment. Then, after the molding process and the connecting process of the solder ball are performed in the same manner as the process of FIG. 157 and the process of FIG. 158, the marking process in the step S9 and the cutting process in the step S10 may be performed.
  • When the process of bonding the heat sink 61 on the front surface 5 b of the semiconductor chip 5 is performed after the wire bonding process in the step S6, since the wire bonding is performed in a state in which the heat sink 61 is not provided, the heat sink 61 does not hinder a capillary motion of the wire bonding apparatus even if the planar shape of the heat sink 61 is made larger. Hence, there is an advantage that the dimension (planar shape) of the heat sink 61 can be made large. Further, when the process of bonding the heat sink 61 on the front surface 5 b of the semiconductor chip 5 is performed after the wire bonding process in the step S6, it is preferable that the heat sink 61 is bonded to the semiconductor chip 5 by using a conductive paste type bonding agent such as the silver paste because the temperature of thermosetting heat treatment of this conductive paste type bonding agent is not so high as the temperature by which the wiring board 21 is damaged.
  • Further, also in the present embodiment, an individual sealing (divided sealing) as shown in FIG. 27 can also be performed in the molding process of FIG. 157. FIG. 159 is a cross-sectional view (side cross-sectional view) of the semiconductor device if in the case when the individual sealing is performed. The semiconductor device if of FIG. 159 has almost the same structure as the semiconductor device if of FIG. 152 except that the sealing resin 7 is not formed on the peripheral edge portion of the upper surface 2 a of the wiring board 2 and the sealing resin 7 is formed on the region other than the peripheral edge portion of the upper surface 2 a of the wiring board 2, and therefore, the description thereof will be omitted.
  • FIG. 160 is a cross-sectional view (side cross-sectional view) showing a state in which a heat dissipation fin 63 is mounted further on the upper surface of the semiconductor device if of FIG. 152, and FIG. 161 is a cross-sectional view (side cross-sectional view) showing a state in which the heat dissipation fin 63 is mounted further on the upper surface of the semiconductor device if of FIG. 159.
  • As shown in FIGS. 160 and 161, the heat dissipation fin (heat sink) 63 is mounted (disposed) on the upper surface of the semiconductor device 1 f. The upper surface of the semiconductor device 1 f is formed of the upper surface 7 b of the sealing resin 7 and the upper surface 61 a of the heat sink 61. The heat dissipation fin 63 is required to be overlapped at least with a part of the upper surface 61 a of the heat sink 61 when seen planarly, and it is more preferable if the heat dissipation fin 63 encloses the upper surface 61 a of the heat sink 61 when seen planarly.
  • The heat dissipation fin 63 is attached to the upper surface 61 a of the heat sink 61 exposed from the upper surface 7 b of the sealing resin 7. Specifically, (the lower surface of) the heat dissipation fin 63 is bonded and fixed to the upper surface 61 a of the heat sink 61 through the bonding agent 64 made of, for example, solder. For dissipating the heat generated in the semiconductor chip 5 from the heat dissipation fin 63 through the heat sink 61, it is not necessary to bond the upper surface 7 b of the sealing resin 7 to the heat dissipation fin 63, but the upper surface 61 a of the heat sink 61 is required to be bonded to the heat dissipation fin 63. As the bonding agent 64 for bonding the heat dissipation fin 63 and the heat sink 61, the bonding agent having high conductivity (conductive bonding agent) is preferably used, and the solder is preferable. As another embodiment, the heat dissipation fin 63 can be also bonded and fixed to the upper surface 61 a of the heat sink 61 through a heat conductive bonding sheet (not shown) and the like having high heat conductivity. In this case, the heat dissipation fin 63 can be bonded and fixed to both of the upper surface 61 a of the heat sink 61 and the upper surface 7 b of the sealing resin 7 through the heat conductive bonding sheet.
  • The heat dissipation fin 63 is a member for dissipating the heat of the semiconductor device 1 f (heat generated in the semiconductor chip 5) and preferably has high heat conductivity, and the heat conductivity (heat conductivity coefficient) of the heat dissipation fin 63 is required to be at least higher than the heat conductivity (heat conductivity coefficient) of the sealing resin 7. Since conductive materials (particularly metal materials) are also high in heat conductivity, the heat dissipation fin 63 is preferably made of a conductive material and is more preferably formed of a metal material. It is more preferable that a metal material such as copper (Cu) or copper (Cu) alloy whose main component is copper (Cu) is used for the heat sink 61 because high heat conductivity of the heat dissipation fin 63 can be obtained and the processing thereof is easy. Further, it is more preferable that the heat dissipation fin 63 is made of the same material as the heat sink 61, and by this means, the heat dissipation fin 63 and the heat sink 61 come to have the same heat expansion coefficient, and thus, a heat stress can be reduced. Therefore, it is most preferable that the heat dissipation fin 63, the heat sink 61 and the heat sink 4 are formed of copper (Cu) or copper (Cu) alloy.
  • When the heat dissipation fin 63 is further attached to the upper surface of the semiconductor device 1 f as shown in FIG. 160 or FIG. 161, the heat transmitted also to the heat sink 61 from the semiconductor chip 5 through the bonding agent 62 can be dissipated from the heat dissipation fin 63, and therefore, the heat dissipation properties can be further improved.
  • The present embodiment can be applied to any one of the first to fifth embodiments. More specifically, in any of the semiconductor devices ( semiconductor devices 1, 1 a, 1 b, 1 b 1, 1 c and 1 e) shown in the first to fifth embodiments, the heat sink 61 can be mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the upper surface 61 a of the heat sink 61 can be exposed from the upper surface 7 b of the sealing resin 7 by applying the present embodiment. Further, the heat dissipation fin 63 can be further attached to the upper surface of the semiconductor device. Also, in any of the manufacturing processes of the semiconductor device shown in the first to fifth embodiments, the heat sink 61 can be mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the sealing resins 7 and 7 a can be formed so that the upper surface 61 a of the heat sink 61 is exposed by applying the present embodiment. By doing so, a heat dissipation path can be secured not only to the lower side but also to the upper side of the semiconductor chip 5, and therefore, the heat dissipation properties of the semiconductor device can be further improved.
  • As an example, the case where the present embodiment is applied to the semiconductor device 1 b of the third embodiment is shown in FIG. 162. The semiconductor device shown in FIG. 162 has almost the same structure as the semiconductor device 1 b of FIG. 72 of the third embodiment except that the heat sink 61 is mounted on the front surface 5 b of the semiconductor chip 5 through the bonding agent 62 and the upper surface 61 a of the heat sink 61 is exposed from the upper surface 7 b of the sealing resin 7. The semiconductor device of FIG. 162 can secure the heat dissipation path not only to the lower side but also to the upper side of the semiconductor chip 5 by providing the heat sink 61, and therefore, the heat dissipation properties can be further improved as compared with the semiconductor device 1 b of FIG. 72 of the third embodiment.
    • Seventh Embodiment
  • FIG. 163 is a cross-sectional view (side cross-sectional view) of a semiconductor device 1 g of the seventh embodiment.
  • The semiconductor device 1 g of the present embodiment is the same as the first embodiment in that a heat sink 4 d (corresponding to the heat sink 4) is caulked inside the through-hole 3 of the wiring board 2 and fixed to the wiring board 2. However, unlike the first embodiment, the side surface (surface between the upper surface 9 a and the lower surface 9 b) 10 of the heat sink 4 d is not inclined and is a surface almost vertical to the upper surface 9 a (or the lower surface 9 b). Further, in the semiconductor device 1 g, a groove 71 is formed in a part (upper surface 9 a in the present embodiment) of the heat sink 4 d along each side of the heat sink 4 d whose planar shape is rectangular (square in the present embodiment). This groove 71 is used in the following manner. That is, when the semiconductor device 1 g is manufactured, this groove 71 is hit (pressed, crushed) by a jig (jig 73 to be described later) so that a part of the heat sink 4 d is expanded in a horizontal direction inside the through-hole 3 of the wiring board 2 and the heat sink 4 d is fixed to the wiring board 2. Since the adhesion of the side surface 10 of the heat sink 4 d and the inner wall surface of the through-hole 3 of the wiring board 2 is improved as described above, the heat sink 4 d can be fixed to the wiring board 2.
  • For the further improvement of the adhesion, also in the present embodiment, if the protruded portion 11 is formed in the peripheral edge portion of the upper surface 9 a of the heat sink 4 d like in the first embodiment, a trouble of the heat sink 4 d falling off from the wiring board 2 can be prevented even when the thickness of the heat sink 4 d is increased so as to improve the heat dissipation properties and the weight of the heat sink 4 d is increased.
  • Next, a caulking method (fixing method) of the heat sink 4 d of the present embodiment will be described with reference to the drawings. FIGS. 164 and 165 are cross-sectional views (explanatory drawings) showing a technique of caulking (fixing) the heat sink 4 d in the present embodiment to the wiring board 2.
  • First, as shown in FIG. 164, the heat sink 4 d is disposed inside the through-hole 3 of the wiring board 2. At this time, since the protruded portion 11 is not formed in the peripheral edge portion of the upper surface 9 a of the heat sink 4 d as shown in FIG. 164, the wiring board 2 is disposed on a stage 72, and then, the heat sink 4 d individually segmented and obtained in advance is disposed inside the through-hole 3 of the wiring board 2 as shown in FIG. 164 in the same manner as the above-described embodiments.
  • Here, as described above, the heat sink 4 d is made thicker than the wiring board 2 so that the heat sink 4 d can also be electrically connected to a mother board (specifically, the board side terminal 42 a of the wiring board 41) when the completed semiconductor device 1 g is mounted on the mother board (corresponding to the wiring board 41). Therefore, it is preferable to form a groove (recess) 72 a at a position corresponding to the heat sink 4 d in the stage 72.
  • Further, the external dimension of the heat sink 4 d is preferably smaller than a size of the internal dimension of the through-hole 3 of the wiring board 2. This is for the purpose of suppressing the trouble that a part of the heat sink 4 d contacts to the wiring board 2 and a crack is formed in the wiring board 2 at the time of inserting the heat sink 4 d into the through-hole 3. However, if the heat sink 4 d can be inserted into the through-hole 3 so that the heat sink 4 d does not contact to the wiring board 2, the heat sink 4 d having the same size as the inner dimension of the through-hole 3 may be used.
  • Next, as shown in FIG. 165, the jig 73 having a top end portion larger than a width (opening area on the upper surface 9 a side of the heat sink 4 d) W1 of the groove 71 is caused to descend toward the groove 71 in the direction (that is, the direction toward the lower surface 9 b of the heat sink 4 d from the upper surface 9 a of the heat sink 4 d) shown by an arrow mark 74 of FIG. 165, thereby hitting this groove 71. By this means, a part of the heat sink 4 d is expanded in the horizontal direction by a cubic volume by which the groove 71 is crushed (pushed and expanded) by the jig 73, and the side surface 10 of the heat sink 4 d can be adhered to the inner wall surface of the through-hole 3 of the wiring board 2. Therefore, the heat sink 4 d and the wiring board 2 can be caulked, and the heat sink 4 d can be fixed to the wiring board 2.
  • In the foregoing, the invention made by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention.
  • For example, the cases where the lower portion of each of the heat sinks 4, 4 a, 4 b, 4 c and 4 d (including the lower surface 9 b) protrudes from the lower surface 2 b of the wiring board 2 have been described in the first to seventh embodiments, but this is not restrictive, and the structure in which the lower portion does not protrude from the lower surface 2 b of the wiring board 2 and is flush with this lower surface 2 b is also possible. However, when the heat sinks 4, 4 a, 4 b, 4 c and 4 d do not protrude from the lower surface 2 b of the wiring board 2, the thicknesses of the heat sinks 4, 4 a, 4 b, 4 c and 4 d become smaller as compared with the first to seventh embodiments, and moreover, since the electrical connection between the entire surface of the heat sinks 4, 4 a, 4 b, 4 c and 4 d exposed from the lower surface 2 b of the wiring board 2 and the mounting board (equivalent to the wiring board 41) becomes difficult, the heat dissipation effect is decreased as compared with the cases shown in the first to seventh embodiments.
  • Further, for example, the structure in which the heat sink 4 (or the heat sink 4 a or 4 b) obtained by performing individual segmentation is disposed inside the through-hole 3 of the wiring board 21 has been described in the first to third embodiments, but a plurality of heat sinks 4 (or a plurality of heat sinks 4 a or 4 b) in a state of being fixed to the lead frame may be disposed and fixed inside the plurality of through-holes 3 of the wiring board 21, respectively, and then, the separation of the wiring board 21 and the lead frame may be performed at the same time.
  • Further, for example, the structure in which the groove 71 is formed on the upper surface 9 a of the heat sink 4 d and the inside of this groove 71 is hit by the jig has been described in the seventh embodiment, but the heat sink 4 d may be expanded in the horizontal direction by directly hitting the upper surface 9 a of the heat sink 4 d by the jig without forming the groove 71.
  • The present invention is suitably applied to the semiconductor device of a semiconductor package configuration and the manufacturing method thereof.

Claims (3)

1. A semiconductor device, comprising:
a board having a first surface, a second surface opposite to the first surface, a through-hole reaching one of the first and second surfaces from the other, and a plurality of electrodes formed on the first surface, and arranged next to the through-hole;
a heat-sink having a third surface, a protruding portion protruded from the third surface in a vertical direction, and a fourth surface opposite to the third surface, and arranged at the second surface side of the board such that the protruding portion of the heat-sink is arranged inside of the through-hole of the board, and such that the third surface of the heat-sink faces the second surface of the board;
a semiconductor chip having a front surface, a plurality of pads formed on the front surface, and a rear surface opposite to the front surface, and mounted on a protruding surface of the protruding portion of the heat-sink such that the rear surface of the semiconductor chip faces the protruding surface of the protruding portion of the heat-sink;
a plurality of wires electrically connected the pads with the electrodes, respectively; and
a sealing body sealing the first surface of the board, the semiconductor chip, and the wires.
2. The semiconductor device according to claim 1, wherein the protruding portion of the heat-sink has a side surface located between the protruding surface and the third surface in a cross-section view; and
wherein the side surface of the heat-sink is contacted with an inner surface of the through-hole.
3. The semiconductor device according to claim 1, wherein the board has wiring layers, and insulating layers; and
wherein the heat-sink is formed of a metal material.
US13/049,109 2008-06-12 2011-03-16 Semiconductor device and manufacturing method of the same Abandoned US20110163438A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/049,109 US20110163438A1 (en) 2008-06-12 2011-03-16 Semiconductor device and manufacturing method of the same
US13/299,666 US8232634B2 (en) 2008-06-12 2011-11-18 Semiconductor device having a pin mounted heat sink

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2008-154497 2008-06-12
JP2008154497 2008-06-12
JP2009-6240 2009-01-15
JP2009006240A JP5155890B2 (en) 2008-06-12 2009-01-15 Semiconductor device and manufacturing method thereof
US12/481,078 US7923826B2 (en) 2008-06-12 2009-06-09 Semiconductor device mounted on heat sink having protruded periphery
US13/049,109 US20110163438A1 (en) 2008-06-12 2011-03-16 Semiconductor device and manufacturing method of the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/481,078 Continuation US7923826B2 (en) 2008-06-12 2009-06-09 Semiconductor device mounted on heat sink having protruded periphery

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/299,666 Continuation US8232634B2 (en) 2008-06-12 2011-11-18 Semiconductor device having a pin mounted heat sink

Publications (1)

Publication Number Publication Date
US20110163438A1 true US20110163438A1 (en) 2011-07-07

Family

ID=41413978

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/481,078 Active US7923826B2 (en) 2008-06-12 2009-06-09 Semiconductor device mounted on heat sink having protruded periphery
US13/049,109 Abandoned US20110163438A1 (en) 2008-06-12 2011-03-16 Semiconductor device and manufacturing method of the same
US13/299,666 Expired - Fee Related US8232634B2 (en) 2008-06-12 2011-11-18 Semiconductor device having a pin mounted heat sink

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/481,078 Active US7923826B2 (en) 2008-06-12 2009-06-09 Semiconductor device mounted on heat sink having protruded periphery

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/299,666 Expired - Fee Related US8232634B2 (en) 2008-06-12 2011-11-18 Semiconductor device having a pin mounted heat sink

Country Status (2)

Country Link
US (3) US7923826B2 (en)
JP (1) JP5155890B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150348864A1 (en) * 2014-05-29 2015-12-03 Infineon Technologies Ag Connectable Package Extender for Semiconductor Device Package
US10692794B2 (en) * 2016-01-14 2020-06-23 Mitsubishi Electric Corporation Radiation plate structure, semiconductor device, and method for manufacturing radiation plate structure

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8415703B2 (en) * 2008-03-25 2013-04-09 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange
US8310043B2 (en) * 2008-03-25 2012-11-13 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with ESD protection layer
US20100181594A1 (en) * 2008-03-25 2010-07-22 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and cavity over post
US20100072511A1 (en) * 2008-03-25 2010-03-25 Lin Charles W C Semiconductor chip assembly with copper/aluminum post/base heat spreader
US8212279B2 (en) * 2008-03-25 2012-07-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader, signal post and cavity
US8329510B2 (en) * 2008-03-25 2012-12-11 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a post/base heat spreader with an ESD protection layer
US8232576B1 (en) 2008-03-25 2012-07-31 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and ceramic block in post
US8207553B2 (en) * 2008-03-25 2012-06-26 Bridge Semiconductor Corporation Semiconductor chip assembly with base heat spreader and cavity in base
US20110163348A1 (en) * 2008-03-25 2011-07-07 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump
US20110156090A1 (en) * 2008-03-25 2011-06-30 Lin Charles W C Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts
US8193556B2 (en) 2008-03-25 2012-06-05 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and cavity in post
US8531024B2 (en) * 2008-03-25 2013-09-10 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and multilevel conductive trace
US8354688B2 (en) 2008-03-25 2013-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump
US8314438B2 (en) * 2008-03-25 2012-11-20 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and cavity in bump
US20090284932A1 (en) * 2008-03-25 2009-11-19 Bridge Semiconductor Corporation Thermally Enhanced Package with Embedded Metal Slug and Patterned Circuitry
US8269336B2 (en) * 2008-03-25 2012-09-18 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and signal post
US8129742B2 (en) * 2008-03-25 2012-03-06 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and plated through-hole
US8378372B2 (en) * 2008-03-25 2013-02-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and horizontal signal routing
US20100052005A1 (en) * 2008-03-25 2010-03-04 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and conductive trace
US8067784B2 (en) * 2008-03-25 2011-11-29 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and substrate
US8288792B2 (en) 2008-03-25 2012-10-16 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/post heat spreader
US8324723B2 (en) * 2008-03-25 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and dual-angle cavity in bump
US8203167B2 (en) * 2008-03-25 2012-06-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and adhesive between base and terminal
US8525214B2 (en) * 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
JP5550225B2 (en) * 2008-09-29 2014-07-16 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Circuit equipment
US8324653B1 (en) 2009-08-06 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with ceramic/metal substrate
JP5581029B2 (en) * 2009-09-18 2014-08-27 パナソニック株式会社 Lighting module
TWI405307B (en) * 2009-09-18 2013-08-11 Novatek Microelectronics Corp Chip package and process thereof
US8405203B2 (en) * 2010-09-10 2013-03-26 Cisco Technology, Inc. Semiconductor package with integrated substrate thermal slug
US20120314419A1 (en) * 2011-06-08 2012-12-13 Wen-Kung Sung Heat dissipation structure of light-emitting diode
CN103688598B (en) * 2011-07-22 2017-06-09 京瓷株式会社 Circuit board and electronic installation
US8614502B2 (en) * 2011-08-03 2013-12-24 Bridge Semiconductor Corporation Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device
JP5873108B2 (en) * 2011-12-22 2016-03-01 京セラ株式会社 Wiring board and electronic device
WO2013150772A1 (en) * 2012-04-02 2013-10-10 富士電機株式会社 Power converter
US9093420B2 (en) 2012-04-18 2015-07-28 Rf Micro Devices, Inc. Methods for fabricating high voltage field effect transistor finger terminations
WO2013172420A1 (en) * 2012-05-18 2013-11-21 京セラ株式会社 Semiconductor-element-accommodating package, semiconductor device and mounting structure
US9917080B2 (en) 2012-08-24 2018-03-13 Qorvo US. Inc. Semiconductor device with electrical overstress (EOS) protection
US9147632B2 (en) 2012-08-24 2015-09-29 Rf Micro Devices, Inc. Semiconductor device having improved heat dissipation
US9673162B2 (en) * 2012-09-13 2017-06-06 Nxp Usa, Inc. High power semiconductor package subsystems
US9852961B2 (en) * 2013-08-28 2017-12-26 Infineon Technologies Ag Packaged semiconductor device having an encapsulated semiconductor chip
CN103715163B (en) * 2013-12-31 2017-01-04 日月光封装测试(上海)有限公司 Lead frame and semiconductor packages
US9536803B2 (en) * 2014-09-05 2017-01-03 Qorvo Us, Inc. Integrated power module with improved isolation and thermal conductivity
JP6357415B2 (en) * 2014-12-26 2018-07-11 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US10615158B2 (en) 2015-02-04 2020-04-07 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US10062684B2 (en) 2015-02-04 2018-08-28 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US9953903B2 (en) * 2015-07-22 2018-04-24 Nxp B.V. Heatsink very-thin quad flat no-leads (HVQFN) package
WO2017145331A1 (en) * 2016-02-25 2017-08-31 三菱電機株式会社 Semiconductor package and module
US10068866B2 (en) * 2016-09-29 2018-09-04 Intel Corporation Integrated circuit package having rectangular aspect ratio
EP3340293A1 (en) * 2016-12-20 2018-06-27 Siemens Aktiengesellschaft Semiconductor module with support structure on the bottom
WO2018135650A1 (en) * 2017-01-19 2018-07-26 株式会社村田製作所 Electronic component and method for producing electronic component
JP6789886B2 (en) * 2017-06-09 2020-11-25 株式会社東芝 Electronic device
JP7135382B2 (en) * 2018-03-30 2022-09-13 住友大阪セメント株式会社 Optical modulator and optical transmitter
CN110798961B (en) * 2018-08-01 2022-10-21 苏州旭创科技有限公司 Circuit board and optical module with same
CN208847999U (en) * 2018-09-03 2019-05-10 重庆惠科金渝光电科技有限公司 Display module assembly and display device
DE102018218175A1 (en) * 2018-10-24 2020-04-30 Osram Gmbh LIGHT AND HEADLIGHT
JP7215206B2 (en) * 2019-02-19 2023-01-31 富士電機株式会社 Semiconductor device manufacturing method
CN112216658A (en) * 2019-07-10 2021-01-12 恩智浦美国有限公司 Semiconductor device having lead frame adaptable to various die sizes
CN110690122B (en) * 2019-10-12 2021-01-29 合肥圣达电子科技实业有限公司 Processing method of metal shell for packaging electronic component
US20210335689A1 (en) * 2020-04-24 2021-10-28 Vitesco Technologies USA, LLC Semiconductor power device with press-fit mounting
US11729915B1 (en) * 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
US5172301A (en) * 1991-10-08 1992-12-15 Lsi Logic Corporation Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same
US5570272A (en) * 1993-08-18 1996-10-29 Lsi Logic Corporation Apparatus for encapsulating an integrated circuit package
US5583377A (en) * 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US5793613A (en) * 1995-12-29 1998-08-11 Sgs-Thomson Microelectronics S.R.1. Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic device
US6156980A (en) * 1998-06-04 2000-12-05 Delco Electronics Corp. Flip chip on circuit board with enhanced heat dissipation and method therefor
US6268239B1 (en) * 1999-04-20 2001-07-31 Nec Corporation Semiconductor chip cooling structure and manufacturing method thereof
US6271581B2 (en) * 1999-11-08 2001-08-07 Siliconware Precision Industries Co., Ltd. Semiconductor package structure having universal lead frame and heat sink
US20020066954A1 (en) * 2000-12-01 2002-06-06 Chien-Ping Huang Super low profile package with high efficiency of heat dissipation
US6462413B1 (en) * 1999-07-22 2002-10-08 Polese Company, Inc. LDMOS transistor heatsink package assembly and manufacturing method
US6538303B1 (en) * 1999-06-02 2003-03-25 Sharp Kabushiki Kaisha Lead frame and semiconductor device using the same
US6755229B2 (en) * 2001-07-27 2004-06-29 Samsung Electro-Mechanics Co., Ltd. Method for preparing high performance ball grid array board and jig applicable to said method
US6861474B2 (en) * 2001-12-28 2005-03-01 Taylor Made Golf Company, Inc. Golf ball layers and method of manufacture
US20060038282A1 (en) * 2004-08-23 2006-02-23 Texas Instruments Incorporated Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages
US7119422B2 (en) * 2004-11-15 2006-10-10 Unity Opto Technology Co., Ltd. Solid-state semiconductor light emitting device
US7138667B2 (en) * 2003-04-11 2006-11-21 Weldon Technologies, Inc. High power light emitting diode
US7192163B2 (en) * 2004-12-27 2007-03-20 Lg.Philips Lcd Co. Ltd. Light-emitting unit with enhanced thermal dissipation and method for fabricating the same
US7268429B2 (en) * 2005-06-27 2007-09-11 Delphi Technologies, Inc. Technique for manufacturing an overmolded electronic assembly
US7446408B2 (en) * 2001-09-24 2008-11-04 St Assembly Test Services Pte Ltd Semiconductor package with heat sink
US7456499B2 (en) * 2004-06-04 2008-11-25 Cree, Inc. Power light emitting die package with reflecting lens and the method of making the same
US7521863B2 (en) * 2006-01-13 2009-04-21 Nichia Corporation Light emitting device and method for producing the same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56955B2 (en) * 1972-12-12 1981-01-10
US5144412A (en) * 1987-02-19 1992-09-01 Olin Corporation Process for manufacturing plastic pin grid arrays and the product produced thereby
JPH01261848A (en) * 1988-04-13 1989-10-18 Toshiba Corp Semiconductor device
JP3137977B2 (en) * 1990-09-19 2001-02-26 富士通株式会社 Semiconductor device having many lead bins
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
JPH07221218A (en) * 1994-02-03 1995-08-18 Toshiba Corp Semiconductor device
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
KR100214552B1 (en) * 1997-01-25 1999-08-02 구본준 Carrier frame and substrate and method for manufacture ball grid array and the use
US6472252B2 (en) * 1997-07-23 2002-10-29 Micron Technology, Inc. Methods for ball grid array (BGA) encapsulation mold
JP2001035975A (en) * 1999-07-22 2001-02-09 Nec Corp Bga-type semiconductor device package
JP3414388B2 (en) * 2000-06-12 2003-06-09 株式会社日立製作所 Electronics
JP4608763B2 (en) * 2000-11-09 2011-01-12 日本電気株式会社 Semiconductor device
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
CN1460293A (en) * 2001-04-09 2003-12-03 株式会社住友金属电设备 Radiation type BGA package and production method therefor
JP2003046027A (en) 2001-07-27 2003-02-14 Sumitomo Metal Electronics Devices Inc Heat-radiating type bga package and manufacturing method therefor
JP2003197835A (en) * 2001-12-26 2003-07-11 Tdk Corp Power amplification module and element aggregate therefor
JP3904934B2 (en) * 2002-01-29 2007-04-11 京セラ株式会社 Semiconductor device
JP3908113B2 (en) 2002-07-30 2007-04-25 株式会社住友金属エレクトロデバイス Heat dissipation type BGA package and manufacturing method thereof
JP4131935B2 (en) * 2003-02-18 2008-08-13 株式会社東芝 Interface module, LSI package with interface module, and mounting method thereof
JP2004296565A (en) 2003-03-26 2004-10-21 Sumitomo Metal Electronics Devices Inc Method for manufacturing package for housing semiconductor element
US20040264195A1 (en) * 2003-06-25 2004-12-30 Chia-Fu Chang Led light source having a heat sink
US6953891B2 (en) * 2003-09-16 2005-10-11 Micron Technology, Inc. Moisture-resistant electronic device package and methods of assembly
CN101036238B (en) * 2004-10-04 2014-01-08 株式会社东芝 Light emitting device, lighting equipment or liquid crystal display device using such light emitting device
KR100646093B1 (en) * 2004-12-17 2006-11-15 엘지이노텍 주식회사 Light emitting device package
US7741158B2 (en) * 2006-06-08 2010-06-22 Unisem (Mauritius) Holdings Limited Method of making thermally enhanced substrate-base package
US7592693B2 (en) * 2007-09-06 2009-09-22 Advanced Interconnections Corporation Interconnecting electrical devices

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
US5172301A (en) * 1991-10-08 1992-12-15 Lsi Logic Corporation Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same
US5583377A (en) * 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5570272A (en) * 1993-08-18 1996-10-29 Lsi Logic Corporation Apparatus for encapsulating an integrated circuit package
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US5793613A (en) * 1995-12-29 1998-08-11 Sgs-Thomson Microelectronics S.R.1. Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic device
US6156980A (en) * 1998-06-04 2000-12-05 Delco Electronics Corp. Flip chip on circuit board with enhanced heat dissipation and method therefor
US6268239B1 (en) * 1999-04-20 2001-07-31 Nec Corporation Semiconductor chip cooling structure and manufacturing method thereof
US6538303B1 (en) * 1999-06-02 2003-03-25 Sharp Kabushiki Kaisha Lead frame and semiconductor device using the same
US6462413B1 (en) * 1999-07-22 2002-10-08 Polese Company, Inc. LDMOS transistor heatsink package assembly and manufacturing method
US6271581B2 (en) * 1999-11-08 2001-08-07 Siliconware Precision Industries Co., Ltd. Semiconductor package structure having universal lead frame and heat sink
US20020066954A1 (en) * 2000-12-01 2002-06-06 Chien-Ping Huang Super low profile package with high efficiency of heat dissipation
US6755229B2 (en) * 2001-07-27 2004-06-29 Samsung Electro-Mechanics Co., Ltd. Method for preparing high performance ball grid array board and jig applicable to said method
US7446408B2 (en) * 2001-09-24 2008-11-04 St Assembly Test Services Pte Ltd Semiconductor package with heat sink
US6861474B2 (en) * 2001-12-28 2005-03-01 Taylor Made Golf Company, Inc. Golf ball layers and method of manufacture
US7138667B2 (en) * 2003-04-11 2006-11-21 Weldon Technologies, Inc. High power light emitting diode
US7456499B2 (en) * 2004-06-04 2008-11-25 Cree, Inc. Power light emitting die package with reflecting lens and the method of making the same
US20060038282A1 (en) * 2004-08-23 2006-02-23 Texas Instruments Incorporated Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages
US7119422B2 (en) * 2004-11-15 2006-10-10 Unity Opto Technology Co., Ltd. Solid-state semiconductor light emitting device
US7192163B2 (en) * 2004-12-27 2007-03-20 Lg.Philips Lcd Co. Ltd. Light-emitting unit with enhanced thermal dissipation and method for fabricating the same
US7268429B2 (en) * 2005-06-27 2007-09-11 Delphi Technologies, Inc. Technique for manufacturing an overmolded electronic assembly
US7521863B2 (en) * 2006-01-13 2009-04-21 Nichia Corporation Light emitting device and method for producing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150348864A1 (en) * 2014-05-29 2015-12-03 Infineon Technologies Ag Connectable Package Extender for Semiconductor Device Package
US9892991B2 (en) * 2014-05-29 2018-02-13 Infineon Technologies Ag Connectable package extender for semiconductor device package
US10692794B2 (en) * 2016-01-14 2020-06-23 Mitsubishi Electric Corporation Radiation plate structure, semiconductor device, and method for manufacturing radiation plate structure

Also Published As

Publication number Publication date
US20090309213A1 (en) 2009-12-17
JP5155890B2 (en) 2013-03-06
JP2010021515A (en) 2010-01-28
US20120061817A1 (en) 2012-03-15
US8232634B2 (en) 2012-07-31
US7923826B2 (en) 2011-04-12

Similar Documents

Publication Publication Date Title
US8232634B2 (en) Semiconductor device having a pin mounted heat sink
JP5271886B2 (en) Semiconductor device and manufacturing method thereof
US6790710B2 (en) Method of manufacturing an integrated circuit package
US5843808A (en) Structure and method for automated assembly of a tab grid array package
KR100384260B1 (en) Semiconductor device and manufacturing method of the same
TWI441299B (en) Pre-molded clip structure
JP3170182B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
TWI450373B (en) Dual side cooling integrated power device package and module and methods of manufacture
US20030178719A1 (en) Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US8426983B2 (en) Semiconductor device
US9520374B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
US20060223237A1 (en) Method of manufacturing enhanced thermal dissipation integrated circuit package
US20130009300A1 (en) Semiconductor device and method for manufacturing same
JP2010062365A (en) Semiconductor device and method of manufacturing the same
JP2012084840A (en) Semiconductor device and manufacturing method thereof
JPH09237807A (en) Manufacture of heat radiating resin sealed semiconductor device
JP2010050262A (en) Semiconductor device and manufacturing method thereof
JP2010010269A (en) Semiconductor device, intermediate for manufacturing semiconductor device, and method of manufacturing them
US8722465B1 (en) Method of assembling semiconductor device including insulating substrate and heat sink
KR100487135B1 (en) Ball Grid Array Package
JP2011165793A (en) Semiconductor device and method of manufacturing the same, and electronic device
US20070273010A1 (en) Design and Method for Attaching a Die to a Leadframe in a Semiconductor Device
JP4840305B2 (en) Manufacturing method of semiconductor device
JPH02181956A (en) Semiconductor device
JP2008071847A (en) Manufacturing method for semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION