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US20110079580A1 - Lower chamber heaters for improved etch processes - Google Patents

Lower chamber heaters for improved etch processes Download PDF

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Publication number
US20110079580A1
US20110079580A1 US12/900,355 US90035510A US2011079580A1 US 20110079580 A1 US20110079580 A1 US 20110079580A1 US 90035510 A US90035510 A US 90035510A US 2011079580 A1 US2011079580 A1 US 2011079580A1
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Prior art keywords
etch
etching chamber
chamber
heaters
outside surface
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Abandoned
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US12/900,355
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John Christopher Shriner
Kyran Morris
Esequiel Torres
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Texas Instruments Inc
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Texas Instruments Inc
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Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US12/900,355 priority Critical patent/US20110079580A1/en
Publication of US20110079580A1 publication Critical patent/US20110079580A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
    • H01J2237/2001—Maintaining constant desired temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Definitions

  • This invention relates generally to an etching process chamber and more particularly to a temperature control assembly for use in etching processes.
  • Plasma etching of semiconductor materials is typically performed in a plasma etching chamber that has gas inlet ports, gas exhaust ports, a mechanism for transporting wafers into and out of the etching chamber, and a pedestal on which the wafer rests while being etched.
  • a plasma etching chamber typically has gas inlet ports, gas exhaust ports, a mechanism for transporting wafers into and out of the etching chamber, and a pedestal on which the wafer rests while being etched.
  • portions of the etching chamber may be heated.
  • Gaseous reactants typically contain carbon. Products of the etching reaction that are in the plasma may further react to form a polymeric material that may deposit on the sidewalls of the semiconductor geometries being etched and may also deposit on interior surfaces of the etching chamber. This polymeric deposition maybe used to control the sidewall profile geometries being etched.
  • Etch product deposition on the walls of the chamber may build up and start delaminating causing particulates. These particulates may deposit on the wafer during etch causing blocked etch defects and may deposit on the wafer post etch causing defects that later result in circuit failure during electrical test.
  • Running additional chamber cleaning cycles and opening the chamber to perform preventative maintenance (PM) to remove the deposition reduces machine availability and increases manufacturing cost. Particle defects reduce yield also increasing manufacturing cost.
  • PM preventative maintenance
  • build up of deposition within the etch chamber may change the performance of the etching as more wafers are etched resulting in more variability in the critical dimension, CD, or sidewall profile of the geometry being formed.
  • Heating devices are added to the cooler portions of a Hitachi plasma etching chamber, to the gate valve, and to the wafer transport tunnel.
  • FIG. 1 is a cross-section of an example etch chamber
  • FIG. 2 is a cross-section of an example etch chamber according to an embodiment.
  • FIG. 3 is a plot of linewidth comparing the variation in a line formed with and without an embodiment.
  • FIG. 4 is a plot of particles formed during etching before and after implementation of an embodiment.
  • Polymer or process deposition occurs in a number of plasma etches performed in Hitachi etchers such as the shallow trench isolation (STI) etch and aluminum metal etch.
  • This deposition may occur on the inside walls of the etch chamber, especially in the cooler regions.
  • This deposition may build up and delaminate depositing particulates onto the wafer during or post etch which result in defects that may limit yield.
  • build up of the deposition on the inside walls of the chamber may change the etch performance resulting in increased variability in the critical dimension, CD, of the geometry being formed.
  • STI etch in a Hitachi M-712 is used as an embodiment to illustrate the instant invention, any etch process that deposits polymer or process films on the inner walls of a Hitachi etch chamber may also be used.
  • FIG. 1 A cross sectional diagram of a Hitachi M-712 STI etch chamber is shown in FIG. 1 .
  • the wafer being etched, 1006 sets atop the wafer pedestal, 1002 . Wafers are brought into and out of the chamber through wafer transport tunnel, 1008 , and isolation valve, 1014 .
  • Isolation valve, 1010 may be open while the wafer is being loaded and unloaded from the chamber and may be closed during etch processing.
  • Vacuum valve, 1010 may be open during normal processing and closed when the chamber is opened for cleaning or maintenance.
  • films formed from etching products in the plasma may deposit on the inner walls, 1012 , and on valve surfaces, 1014 . These deposits may cause the process performance to change as the deposition gets thicker and may also delaminate depositing particles on the wafer resulting in defects which may reduce yield.
  • heaters have been added to the lower portion of the chamber, 2002 and 2006 , and the wafer transport tunnel 2002 . These heaters, warm the outer surface of these areas to about 35 C or more. The preferred temperature of the outside surfaces is about 65 C.
  • the heaters are heater blankets that are custom made by TGM, Inc., of Richardson, TX, to custom fit the lower chamber surfaces, 2002 and 2006 , and the wafer transport tunnel, 2002 of the Hitachi M-712 etching chamber.
  • FIG. 3 is a plot of a critical dimension, CD, line width vs time for two time periods, 3002 and 3004 , prior to the heater installation and for two time periods, 3006 and 3008 , after the heater installation.
  • the CD Prior to heater installation, the CD ranged from the lower specification limit, 3018 , to the upper specification limit, 3024 .
  • this change of CD in the first interval, 3002 between chamber wet cleans, 3010 and 3012 , is 3 weeks.
  • the second interval, 3004 between chamber wet cleans, 3012 and 3014 , the CD change occurred in just 2.5 weeks.
  • the CD during time periods, 3006 and 3008 remained for the most part between the lower control limit, 3020 , and the upper control limit, 3022 .
  • the interval between wet cleans, 3014 and 3016 , during the first time period with the heaters installed is 4.5 weeks and the interval after wet clean 3016 during the second time period with the heaters installed is more than 5 weeks.
  • process performance is improved and the time between chamber wet cleans in significantly improved.
  • the improved CD control improves yield by reducing STI voids and extends time between wet cleans improving equipment uptime thus reducing manufacturing cost.
  • Particles per wafer vs time between wet cleans is shown in FIG. 4 .
  • Heaters were not installed on the Hitachi M-712 STI etch chamber during the first interval, 3002 , between wet cleans at 0 weeks and at 4 weeks and also during the second interval, 3004 , between wet cleans at 4 weeks and at 7 weeks. Particles exceeded the upper control limit, 3010 , and upper specification limit, 3012 , many time during these two intervals. Heaters were installed during interval, 3006 , after the wet clean at week 7 and also during interval, 3008 , after wet clean at week 11.
  • Particles with the heater installed are much reduced exceeding the upper control limit only a few times and exceeding the upper specification limit only one time during these two intervals, 3006 and 3008 .
  • the reduced particle count is evidence of reduced deposition within the chamber. Yield is improved by reducing particle related defects such as blocked etch and embedded particles and machine uptime is also improved.
  • the STI etch may consist of a series of etching steps to etch through a bottom antireflective coating (BARC), 5008 , a silicon nitride layer, 5008 , a pad oxide layer, 5004 , and silicon substrate, 5002 .
  • BARC bottom antireflective coating
  • STI resist pattern, 5010 is formed on silicon substrate, 5002 , and the STI etch is performed to etch STI trenches, 5012 .
  • heaters were installed on Hitachi M-712 etch chamber and the BARC etch endpoint time range was reduced from 2.1 to 1.1 seconds, the nitride etch endpoint time was reduced from 1.8 to 1.0 seconds, the average particle defectivity per wafer was reduced from 35 to 10 particles per wafer, the blocked etch defects were reduced from 5.7 to 0.6 per wafer, wafers scrapped due to blocked etch defects was reduced from 5 to 1 wafer per month, the margin for STI voids was improved by 10 times, and the number of wet cleans was reduced from 42 to 28 per year. Manufacturing cost was significantly reduced with improved yield and with improved machine uptime. In this embodiment the performance of the etching equipment and the STI etch is improved with no changes to the etch recipe. This also saved manufacturing cost by avoiding expensive process and product requalification.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of improving a plasma etch chamber by installing heaters on outer surfaces. A method of improving STI etch. A method of improving STI etch in a Hitachi M700 series etcher.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of priority under U.S.C. §119(e) of U.S. Provisional Application 61/249,387 (Texas Instruments docket number TI-68259, filed Oct. 7, 2009.
    • FIELD OF THE INVENTION
  • This invention relates generally to an etching process chamber and more particularly to a temperature control assembly for use in etching processes.
    • BACKGROUND OF THE INVENTION
  • Plasma etching of semiconductor materials is typically performed in a plasma etching chamber that has gas inlet ports, gas exhaust ports, a mechanism for transporting wafers into and out of the etching chamber, and a pedestal on which the wafer rests while being etched. Typically to accelerate the etching rate, portions of the etching chamber may be heated. Gaseous reactants typically contain carbon. Products of the etching reaction that are in the plasma may further react to form a polymeric material that may deposit on the sidewalls of the semiconductor geometries being etched and may also deposit on interior surfaces of the etching chamber. This polymeric deposition maybe used to control the sidewall profile geometries being etched. Etch product deposition on the walls of the chamber may build up and start delaminating causing particulates. These particulates may deposit on the wafer during etch causing blocked etch defects and may deposit on the wafer post etch causing defects that later result in circuit failure during electrical test. Running additional chamber cleaning cycles and opening the chamber to perform preventative maintenance (PM) to remove the deposition reduces machine availability and increases manufacturing cost. Particle defects reduce yield also increasing manufacturing cost.
  • Additionally, build up of deposition within the etch chamber may change the performance of the etching as more wafers are etched resulting in more variability in the critical dimension, CD, or sidewall profile of the geometry being formed.
    • SUMMARY OF THE INVENTION
  • The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
  • Heating devices are added to the cooler portions of a Hitachi plasma etching chamber, to the gate valve, and to the wafer transport tunnel.
    • DESCRIPTION OF THE VIEWS OF THE DRAWING
  • FIG. 1 (Prior art) is a cross-section of an example etch chamber
  • FIG. 2 is a cross-section of an example etch chamber according to an embodiment.
  • FIG. 3 is a plot of linewidth comparing the variation in a line formed with and without an embodiment.
  • FIG. 4 is a plot of particles formed during etching before and after implementation of an embodiment.
  • FIG. 5 (Prior art) is a crossection of a semiconductor device illustrating an STI structure.
    •  DETAILED DESCRIPTION
  • The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • Polymer or process deposition occurs in a number of plasma etches performed in Hitachi etchers such as the shallow trench isolation (STI) etch and aluminum metal etch. This deposition may occur on the inside walls of the etch chamber, especially in the cooler regions. This deposition may build up and delaminate depositing particulates onto the wafer during or post etch which result in defects that may limit yield. In addition, build up of the deposition on the inside walls of the chamber may change the etch performance resulting in increased variability in the critical dimension, CD, of the geometry being formed.
  • Although STI etch in a Hitachi M-712 is used as an embodiment to illustrate the instant invention, any etch process that deposits polymer or process films on the inner walls of a Hitachi etch chamber may also be used.
  • A cross sectional diagram of a Hitachi M-712 STI etch chamber is shown in FIG. 1. The wafer being etched, 1006, sets atop the wafer pedestal, 1002. Wafers are brought into and out of the chamber through wafer transport tunnel, 1008, and isolation valve, 1014. Isolation valve, 1010, may be open while the wafer is being loaded and unloaded from the chamber and may be closed during etch processing. Vacuum valve, 1010, may be open during normal processing and closed when the chamber is opened for cleaning or maintenance.
  • As shown in FIG. 1, because the lower portion of the STI etch chamber, is cooler than the upper portion, films formed from etching products in the plasma may deposit on the inner walls, 1012, and on valve surfaces, 1014. These deposits may cause the process performance to change as the deposition gets thicker and may also delaminate depositing particles on the wafer resulting in defects which may reduce yield.
  • In FIG. 2, heaters have been added to the lower portion of the chamber, 2002 and 2006, and the wafer transport tunnel 2002. These heaters, warm the outer surface of these areas to about 35 C or more. The preferred temperature of the outside surfaces is about 65 C. In a preferred embodiment, the heaters are heater blankets that are custom made by TGM, Inc., of Richardson, TX, to custom fit the lower chamber surfaces, 2002 and 2006, and the wafer transport tunnel, 2002 of the Hitachi M-712 etching chamber.
  • As mention before, the deposition buildup in the chamber may change the performance of the etch over time as more and more wafers are processed. FIG. 3 is a plot of a critical dimension, CD, line width vs time for two time periods, 3002 and 3004, prior to the heater installation and for two time periods, 3006 and 3008, after the heater installation. Prior to heater installation, the CD ranged from the lower specification limit, 3018, to the upper specification limit, 3024. In addition, this change of CD in the first interval, 3002, between chamber wet cleans, 3010 and 3012, is 3 weeks. In the second interval, 3004, between chamber wet cleans, 3012 and 3014, the CD change occurred in just 2.5 weeks. With the heaters turned on, the CD during time periods, 3006 and 3008 remained for the most part between the lower control limit, 3020, and the upper control limit, 3022. The interval between wet cleans, 3014 and 3016, during the first time period with the heaters installed is 4.5 weeks and the interval after wet clean 3016 during the second time period with the heaters installed is more than 5 weeks. With the heaters installed, process performance is improved and the time between chamber wet cleans in significantly improved. The improved CD control improves yield by reducing STI voids and extends time between wet cleans improving equipment uptime thus reducing manufacturing cost.
  • Particles per wafer vs time between wet cleans is shown in FIG. 4. Heaters were not installed on the Hitachi M-712 STI etch chamber during the first interval, 3002, between wet cleans at 0 weeks and at 4 weeks and also during the second interval, 3004, between wet cleans at 4 weeks and at 7 weeks. Particles exceeded the upper control limit, 3010, and upper specification limit, 3012, many time during these two intervals. Heaters were installed during interval, 3006, after the wet clean at week 7 and also during interval, 3008, after wet clean at week 11. Particles with the heater installed are much reduced exceeding the upper control limit only a few times and exceeding the upper specification limit only one time during these two intervals, 3006 and 3008. The reduced particle count is evidence of reduced deposition within the chamber. Yield is improved by reducing particle related defects such as blocked etch and embedded particles and machine uptime is also improved.
  • The STI etch may consist of a series of etching steps to etch through a bottom antireflective coating (BARC), 5008, a silicon nitride layer, 5008, a pad oxide layer, 5004, and silicon substrate, 5002. As shown in FIG. 5, STI resist pattern, 5010, is formed on silicon substrate, 5002, and the STI etch is performed to etch STI trenches, 5012. In a preferred embodiment, heaters were installed on Hitachi M-712 etch chamber and the BARC etch endpoint time range was reduced from 2.1 to 1.1 seconds, the nitride etch endpoint time was reduced from 1.8 to 1.0 seconds, the average particle defectivity per wafer was reduced from 35 to 10 particles per wafer, the blocked etch defects were reduced from 5.7 to 0.6 per wafer, wafers scrapped due to blocked etch defects was reduced from 5 to 1 wafer per month, the margin for STI voids was improved by 10 times, and the number of wet cleans was reduced from 42 to 28 per year. Manufacturing cost was significantly reduced with improved yield and with improved machine uptime. In this embodiment the performance of the etching equipment and the STI etch is improved with no changes to the etch recipe. This also saved manufacturing cost by avoiding expensive process and product requalification.
  • While the STI etch in a Hitachi M-712 is used to illustrate an embodiment of the instant invention, other etching chambers that experience deposition on chamber inside walls during etch such as aluminum metal etch may also benefit.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (19)

1. A plasma etching chamber, comprising:
heaters coupled to a lower portion of said plasma etching chamber; and
heaters coupled to a wafer tunnel of said plasma etching chamber.
2. The plasma etching chamber of claim 1 where said heaters are blanket resistance heaters.
3. The plasma etching chamber of claim 2 where said blanket resistance heaters are manufactured by TGM company.
4. The plasma etching chamber of claim 1 where said plasma etching chamber is a Hitachi M700 series etch chamber.
5. The plasma etching chamber of claim 1 where said plasma etching chamber is a Hitachi aluminum metal etching chamber.
6. A method for improving the performance of a plasma etch, comprising:
installing heaters on a lower outside surface of a plasma etching chamber; and
heating said lower outside surface of said plasma etching chamber to a temperature of at least 35 C.
7. The method of claim 6 where said plasma etch is an STI etch and where said plasma etching chamber is a Hitachi M700 series etch chamber.
8. The method of claim 6 where said heaters are blanket resistance heaters.
9. The method of claim 8 where said blanket resistance heaters are manufactured by TGM company.
10. The method of claim 6 where said temperature is about 65 C.
11. The method of claim 7 where said lower outside surface includes a lower outside surface of said etching chamber and an outside surface of a wafer tunnel.
12. The method of claim 6 where said plasma etch is an aluminum etch in a Hitachi etching chamber.
13. A method for improving an STI etch, comprising:
installing heaters on an outside surface of an STI etching chamber; and
heating said outside surface of said STI etching chamber to a temperature of at least 35 C.
14. The method of claim 13 where said STI etching chamber is a Hitachi M700 series etch chamber.
15. The method of claim 13 where said heaters are blanket resistance heaters.
16. The method of claim 15 where said blanket resistance heaters are manufactured by TGM company.
17. The method of claim 13 where said temperature is about 65 C.
18. The method of claim 13 where said outside surface includes an outside surface of said etching chamber and an outside surface of a wafer tunnel.
19. The method of claim 14 where said outside surface includes a lower outside surface of said etching chamber and an outside surface of a wafer tunnel.
US12/900,355 2009-10-07 2010-10-07 Lower chamber heaters for improved etch processes Abandoned US20110079580A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998300A (en) * 1992-10-23 1999-12-07 Yamaha Corporation Method of manufacturing a semiconductor device using antireflection coating
US6564811B2 (en) * 2001-03-26 2003-05-20 Intel Corporation Method of reducing residue deposition onto ash chamber base surfaces
US20050268848A1 (en) * 2004-04-28 2005-12-08 Nanodynamics, Inc Atomic layer deposition apparatus and process
US20080078744A1 (en) * 2006-09-28 2008-04-03 Lam Research Corporation High chamber temperature process and chamber design for photo-resist stripping and post-metal etch passivation
US20080190893A1 (en) * 2007-02-13 2008-08-14 Hitachi High-Technologies Corporation Plasma processing method and plasma processing apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998300A (en) * 1992-10-23 1999-12-07 Yamaha Corporation Method of manufacturing a semiconductor device using antireflection coating
US6564811B2 (en) * 2001-03-26 2003-05-20 Intel Corporation Method of reducing residue deposition onto ash chamber base surfaces
US20050268848A1 (en) * 2004-04-28 2005-12-08 Nanodynamics, Inc Atomic layer deposition apparatus and process
US20080078744A1 (en) * 2006-09-28 2008-04-03 Lam Research Corporation High chamber temperature process and chamber design for photo-resist stripping and post-metal etch passivation
US20080190893A1 (en) * 2007-02-13 2008-08-14 Hitachi High-Technologies Corporation Plasma processing method and plasma processing apparatus

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