Nothing Special   »   [go: up one dir, main page]

US20020046874A1 - Thin film metal barrier for electrical interconnections - Google Patents

Thin film metal barrier for electrical interconnections Download PDF

Info

Publication number
US20020046874A1
US20020046874A1 US09/759,258 US75925801A US2002046874A1 US 20020046874 A1 US20020046874 A1 US 20020046874A1 US 75925801 A US75925801 A US 75925801A US 2002046874 A1 US2002046874 A1 US 2002046874A1
Authority
US
United States
Prior art keywords
layer
tan
interconnect structure
metal
hexagonal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/759,258
Other versions
US6437440B1 (en
Inventor
Cyril Cabral
Patrick Dehaven
Daniel Edelstein
David Klaus
James Pollard
Carol Stanis
Cyprian Uzoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US09/759,258 priority Critical patent/US6437440B1/en
Publication of US20020046874A1 publication Critical patent/US20020046874A1/en
Application granted granted Critical
Publication of US6437440B1 publication Critical patent/US6437440B1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Adjusted expiration legal-status Critical
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to metal interconnects and more particularly to a metal diffusion barrier and liner for VLSI and ULSI metal interconnects, studs, for CMOS gate stacks on semiconductor chips, and for electrical interconnections in packaging and display devices.
  • Al and alloys of Al are used for conventional chip wiring material.
  • the incorporation of Cu and alloys of Cu as a chip wiring material results in improved chip performance and superior reliability when compared to Al and alloys of Al.
  • Cu must be successfully isolated from the devices formed in the silicon substrate below and from the surrounding back end of the line (BEOL) insulators.
  • BEOL back end of the line
  • a thin liner material is deposited on the patterned BEOL insulator e.g. trenches formed in the Damascene process or unpatterned insulator e.g. Cu reactive ion etching (RIE) or through mask Cu deposition process before the Cu is deposited.
  • the thin film liner must also serve as an adhesion layer to adhere the copper to the surrounding dielectric. Adhesion of copper directly to most insulators is generally poor.
  • TiN has been evaluated as a Cu Barrier and has been reported in the literature as a barrier for Cu interconnects in SiO 2 .
  • various barrier systems including TiN are shown for placement between Si/SiO 2 and Cu.
  • TiN has good adhesion to SiO 2 .
  • Cu adheres poorly to TiN.
  • a very thin glue or adhesion layer of Ti may be used to enhance the adhesion of Cu to TiN; however, this Ti layer drastically degrades the conductivity of the copper film during subsequent thermal processing.
  • TiN has been known to form corrosion couple with copper in certain copper polishing slurry used in chemical mechanical polishing (CMP).
  • Ta 2 N has been proposed as a good copper diffusion barrier, but its adhesion to BEOL insulators and copper is relatively poor. In contrast, the adhesion of TaN (N ⁇ 50%) is adequate, while the adhesion of Cu to TaN is poor.
  • a thin Ta layer can be used to enhance the adhesion of Cu to TaN, without the Ta degrading the performance of Cu BEOL.
  • Such a dual-component liner has been previously disclosed in U.S. Pat. No. 5,281,485 Jan. 25, 1994 to E. G. Colgan and P. M. Fryer. However, the resistivity of this TaN is at least 1200 Micro Ohm-cm, which leads to larger vias or stud resistances, and the inability of the metal liner to act as a redundant current strap or path.
  • the series resistance of the above Ta-based liners is in the range from 1 to 5 Ohms.
  • the copper stud resistance would be less than 10% of the Ta based liner.
  • a barrier layer comprising a layer of TaN in the hexagonal phase positioned between a first material to be confined and a second material whereby the second material is isolated from said first material.
  • the first material may be one or a combination of Cu, Al, W and PbSn.
  • the invention further provides a layer of TaN in the hexagonal phase may be positioned between the gas WF6 and a second material to be isolated from the first material.
  • the invention further provides an interconnect structure comprising a first insulation layer having an upper and lower surface and having a plurality of grooves formed in the upper surface, some of the grooves having regions extending to the lower surface to expose respective conducting surfaces in a second interconnect structure below the first insulation layer, a liner including a layer of TaN in the hexagonal phase formed on the sidewalls and bottom of the plurality of grooves and on the exposed respective conducting surfaces, and a metal formed in the plurality of grooves to substantially fill the plurality of grooves.
  • the invention further provides a liner or barrier layer for VLSI/ULSI interconnects and C 4 solder bumps made mostly of Pb-Sn which simultaneously achieves good diffusion barrier performance, good adhesion to BEOL insulators, good adhesion of interconnect metal to this liner, low resistivity, and good conformality in trenches and vias.
  • the interconnects and studs may comprise aluminum, copper,tungsten, or C 4 solder balls made of lead-tin alloy.
  • the invention provides a liner composed of predominately highly oriented and non-highly oriented (random) hexagonal phase TaN (30-60% nitrogen) (which may contain up to 50% cubic phase TaN) deposited alone or as a thin film laminate in combination with other suitable metal films such as Ta.
  • the TaN is 100% hexagonal phase.
  • the liner material described above provides a high integrity barrier, low stress, low resistivity and excellent adhesion to both metal and various dielectrics, such as polymers, silicon dioxide, BPSG, and diamond-like carbon and isolates lead-tin solder metallurgy from Cu and Al interconnects.
  • the invention further provides a thin film material for isolating Al wiring levels from an immediate Cu interconnection level above or below.
  • the invention further provides a liner which isolates a metal layer of W, Cu, alloys of Cu, Al and alloys of Al from the contact silicide (WSi 2 , COSi 2 , TiSi 2 , TaSi 2 and PtSi) and polycrystalline silicon in a MOSFET (metal oxide semiconductor field effect transistor) gate stack.
  • a liner which isolates a metal layer of W, Cu, alloys of Cu, Al and alloys of Al from the contact silicide (WSi 2 , COSi 2 , TiSi 2 , TaSi 2 and PtSi) and polycrystalline silicon in a MOSFET (metal oxide semiconductor field effect transistor) gate stack.
  • MOSFET metal oxide semiconductor field effect transistor
  • the invention further provides a liner to shield existing metal from certain gases such as WF6 which is corrosive used as a precursor gas for the deposition of W.
  • the invention further provides a liner which provides good contact resistance to preceding levels of metal, such as aluminum in BEOL wiring.
  • the invention further provides a liner which provides markedly better conformality than Ti-based compounds even without collimation sputtering or chemical vapor deposition (CVD).
  • the invention further provides a thin film to isolate BEOL interconnect metals from alloying or mixing with the lead-tin in for example, C 4 solder balls.
  • the invention further provides a liner material exhibiting good conformality when deposited in trenches and vias BEOL structures.
  • the invention further provides a liner material which will not form a corrosion couple with Cu, Al, or W during or after chemical mechanical polishing of the liner material.
  • FIG. 1 is a cross section view of one embodiment of the invention.
  • FIG. 2 is a cross section view of a second embodiment of the invention.
  • FIG. 3 is a cross section view of a third embodiment of the invention.
  • FIG. 4 is a cross section view of a fourth embodiment of the invention.
  • FIG. 5 is a graph of an X-ray diffraction pattern for a TaN (hexagonal) film.
  • FIG. 6 is a Transmission Electron Microscope (TEM) micrograph of a diffraction pattern from TaN (hexagonal) film.
  • TEM Transmission Electron Microscope
  • FIG. 7A is a Transmission Electron Microscope (TEM) micrograph of the same highly oriented TaN (hexagonal) film used to provide the X-ray diffraction pattern of FIG. 5.
  • TEM Transmission Electron Microscope
  • FIG. 7B is a Transmission Electron Microscope (TEM) micrograph of non-highly oriented (random) TaN (hexagonal) film.
  • FIG. 8 is a graph of the resistance versus temperature profile of a SiO 2 /Cu/TaN (hexagonal)/Al layered structure.
  • FIG. 9 is a cross-section view of a liner of TaN (hexagonal) for isolating Cu from Al.
  • FIG. 10 is a cross section view of a fifth embodiment of the invention.
  • Interconnect structure 10 includes a layer of insulation 12 having an lower surface 13 and an upper surface 14 .
  • a plurality of grooves or trenches 15 are formed in upper surface 14 of insulation layer 12 .
  • the plurality of grooves 15 may correspond to a wiring layer of a semiconductor chip 16 .
  • Additional interconnect structures may be provided to complete the interconnections for a semiconductor chip 16 .
  • Vias or stud openings 11 are formed at the bottom 17 of grooves 15 in selected regions to make contact to conducting surfaces in a second interconnect structure 18 below the insulation layer 12 .
  • Interconnect structure 18 has a conductor 19 in a groove 20 in insulation layer 21 .
  • a liner 22 is shown between conductor 19 and the bottom and sidewalls of groove 20 .
  • a liner 23 of TaN is formed in grooves 15 on the sidewalls 27 and bottom 17 followed by formation of metal 24 in grooves 15 to substantially fill grooves 15 .
  • Metal 24 may be Cu, Al, W and alloys thereof.
  • Metal 24 may be formed by sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating.
  • Liner 23 may be formed by sputtering in an atmosphere of nitrogen.
  • Liner 23 may include a second layer of Ta (alpha phase) formed adjacent to such as over TaN (hexagonal).
  • Insulation layer 12 as well as insulation layer 21 may be for example SiO 2 , Si 3 N 4 , polymer such as polyamide, diamond-like carbon (DLC) and Fluorinated diamond-like carbon (F-DLC).
  • liner 23 is a highly oriented layer of TaN in the hexagonal phase, the resistivity will be in the range from 150 to 300 micro ohm-cm. Where liner 23 is a non-highly oriented layer of TaN in the hexagonal phase, the resistivity will be greater than 300 micro ohm-cm. Where a layer of Ta in the alpha phase is formed adjacent the TaN (hexagonal), the resistivity of the Ta (alpha phase) will be in the range from 15 to 60 micro ohm-cm.
  • FIG. 2 is a cross section view of interconnect structure 34 .
  • FIG. 2 shows a semiconductor substrate 16 which may be for example Si, SiGe, Ge, or GaAs. Above substrate 16 may be a layer of insulation 35 which may be for example silicon dioxide.
  • a layer of insulation 36 may be formed over layer of insulation 35 having a groove or trench 38 formed therein filled with metal 24 .
  • Layer of insulation 36 and metal 24 may be a coplanar upper surface 39 formed by chemical-mechanical polishing (CMP).
  • CMP chemical-mechanical polishing
  • Layer of insulation 40 is formed on upper surface 39 .
  • a groove or trench 42 is formed in layer of insulation 40 down to metal 24 .
  • a liner 23 is formed on the sidewalls and bottom of groove 42 and on the upper surface 43 of layer of insulation 40 (not shown).
  • Groove or trench 42 is filled with metal 46 over liner 23 and on the liner on upper surface 43 (not shown).
  • the excess metal 46 and liner 23 are removed by CMP to provide a planarized upper surface 43 as shown in FIG. 2.
  • metal 24 may be for example Al and metal 46 may be tungsten.
  • FIG. 3 is a cross section view of interconnect structure 50 .
  • semiconductor substrate 16 has an insulation layer 52 thereover which may be formed by thermal oxidation.
  • a layer 54 of insulation is formed on upper surface 53 on insulation layer 52 .
  • a groove or trench 56 is formed in insulation layer 54 and filled with metal 24 and may be for example Al.
  • Insulation layer 54 and metal 24 may have a coplanar upper surface 58 formed by CMP.
  • a layer 12 of insulation is formed on upper surface 58 .
  • Layer 12 has an upper surface 14 .
  • a groove 15 and via 11 is formed in upper surface 14 .
  • a liner 23 is formed on sidewalls 27 and bottom 17 of groove 15 and via or stud 11 .
  • Metal 24 is formed over liner 23 in groove 15 and via or stud 11 .
  • Upper surface 14 is planar which may be formed by CMP.
  • a layer of insulation 62 is formed on upper surface 14 .
  • An opening 64 is formed in layer 62 to expose metal 24 ′.
  • Liner 23 ′ is formed on the sidewalls 65 of opening 64 and on exposed metal 24 .
  • a blanket metal layer 66 is formed on upper surface 67 on insulation layer 62 and metal 24 ′. Blanket metal layer 66 is etched through a mask not shown to form a metal pattern for wiring or interconnects.
  • metal layer 66 may be for example Al.
  • Metal 24 ′ may be for example Cu and metal 24 may be for example Al.
  • liner 23 separates metal 24 and 24 ′ and liner 23 ′ separates metal 24 ′ and metal 66 .
  • FIG. 4 is a cross section view of interconnect structure 70 .
  • substrate 16 has a layer of insulation 72 thereover which may be for example silicon dioxide.
  • Interconnect structure 12 is formed over layer of insulation 72 .
  • Insulation layer 62 is formed on upper surface 14 .
  • An opening 64 is formed in layer 62 to expose metal 24 ′.
  • Liner 23 ′ is formed on the sidewalls 65 of opening 64 and on exposed metal 24 .
  • a C 4 contact bump 74 of mostly Pb-Sn is formed on liner 23 ′ in opening 64 .
  • the C 4 bump is manufactured by the IBM Corp on integrated circuit chips for making interconnections.
  • the C 4 bump extends above the integrated circuit chip by about 0.125 millimeters and is round or circular in cross-section parallel to the plane of the upper surface of the integrated circuit chip and is curved from its sides to the top surface of the bump where an interconnection is made to another electrode supported by a substrate.
  • FIGS. 2 - 4 like references are used for functions corresponding to the apparatus of FIG. 1 or of an earlier FIG. than the FIG. being described.
  • FIG. 5 is a graph of an X-ray diffraction pattern for a TaN (hexagonal phase) film formed by physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • the following PVD arrangement was used to provide highly-oriented and non-oriented TaN (hexagonal) films.
  • the TaN (hexagonal) films were reactively sputter deposited using a magnetron system in either the direct current or radio frequency mode i.e. dc or rf mode.
  • the highly oriented and non-oriented TaN (hexagonal) films made under the above conditions had resistivities in the range from 150 to 800 micro ohm-cm.
  • the ordinate represents intensity and the abscissa represents two theta.
  • Curve 76 shows the X-ray diffraction pattern for two films; the first film has a high degree of preferred orientation and the second film is a non-oriented film.
  • Curve portion 78 shows a
  • FIG. 6 is a Transmission Electron Microscope (TEM) diffraction pattern of a TaN (hexagonal phase) highly oriented film previously measured with X-rays in FIG. 5.
  • the micrograph confirms the hexagonal structure of the TaN barrier showing rings indexed to the hexagonal phase.
  • FIG. 7A is a Transmission Electron Microscope (TEM) micrograph of a TaN (hexagonal phase) film previously measured with X-rays in FIG. 5.
  • the micrograph shows hexagonal TaN grains which are highly oriented and approximately 20-30 nm in size.
  • FIG. 7B is a Transmission Electron Microscope (TEM) micrograph of a TaN (hexagonal phase). The micrograph show hexagonal TaN grains which are randomly oriented and also approximately 20-30 nm in size.
  • TEM Transmission Electron Microscope
  • FIG. 8 is a graph of the resistance versus temperature provided of a SiO 2 /Cu/TaN (hexagonal)/Al multilayer structure.
  • the ordinate represents resistance in ohms/square and the abscissa represents Temperature in degrees Centigrade.
  • Curve 80 shows the resistance with increasing temperature and curve 82 shows the resistance with decreasing temperature.
  • Curves 80 and 82 provide evidence of the effectiveness of TaN (hexagonal) in isolating Cu from Al up to temperatures greater than 500 degrees Centigrade.
  • FIG. 9 is a cross-section view of a liner of TaN (hexagonal) to isolate Cu from Al.
  • an interconnect structure is shown with a layer of Al(Cu) 84 , insulation layer 85 of SiO 2 , and opening or via 86 with a liner 87 on the bottom and sidewalls. Opening 86 is filled with Cu 88 inside liner 87 . The excess liner 87 and Cu 88 is removed to form upper surface 89 on insulation layer 85 and upper surface 90 of Cu 88 by CMP. After a temperature anneal at 500 degrees Centigrade for 6 hours, the integrity and the definition of liner 87 remains showing no penetration of Cu through liner 87 to the Al(Cu) layer.
  • FIG. 10 is a cross-section view which depicts the disclosed TaN(hexagonal) barrier used between the silicide gate contact and the W stud in a P-MOSFET (P-type metal oxide semiconductor field effect transistor).
  • P-MOSFET P-type metal oxide semiconductor field effect transistor
  • TaN hexagonal
  • the resulting via resistances for deep-submicron copper vias with a composite TaN (hexagonal)/alpha phase Ta liner would be in the resistivity range from 0.25 to 1 Ohms.
  • This resistivity is a substantial improvement, about 5 times better, over the previous copper via systems using Ta alone or another material.
  • the resistivity is probably an order of magnitude better than the Al(Cu)/W via system presently used by some major semiconductor manufacturers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)

Abstract

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Description

    FIELD OF THE INVENTION
  • This invention relates to metal interconnects and more particularly to a metal diffusion barrier and liner for VLSI and ULSI metal interconnects, studs, for CMOS gate stacks on semiconductor chips, and for electrical interconnections in packaging and display devices. [0001]
    • BACKGROUND OF THE INVENTION
  • On VLSI and ULSI semiconductor chips, Al and alloys of Al are used for conventional chip wiring material. The incorporation of Cu and alloys of Cu as a chip wiring material results in improved chip performance and superior reliability when compared to Al and alloys of Al. However, Cu must be successfully isolated from the devices formed in the silicon substrate below and from the surrounding back end of the line (BEOL) insulators. To accomplish this isolation i.e. to prevent diffusion of Cu, a thin liner material is deposited on the patterned BEOL insulator e.g. trenches formed in the Damascene process or unpatterned insulator e.g. Cu reactive ion etching (RIE) or through mask Cu deposition process before the Cu is deposited. The thin film liner must also serve as an adhesion layer to adhere the copper to the surrounding dielectric. Adhesion of copper directly to most insulators is generally poor. [0002]
  • TiN has been evaluated as a Cu Barrier and has been reported in the literature as a barrier for Cu interconnects in SiO[0003] 2. In a publication by S-Q Wang MRS Bulletin 19, 30, (1994) entitled “Barriers against copper diffusion into silicon and drift through silicon dioxide”, various barrier systems including TiN are shown for placement between Si/SiO2 and Cu. TiN has good adhesion to SiO2. However, Cu adheres poorly to TiN. A very thin glue or adhesion layer of Ti may be used to enhance the adhesion of Cu to TiN; however, this Ti layer drastically degrades the conductivity of the copper film during subsequent thermal processing. In addition, TiN has been known to form corrosion couple with copper in certain copper polishing slurry used in chemical mechanical polishing (CMP).
  • Unlike TiN, pure or oxygen-doped Ta adheres poorly to some insulators such as SiO[0004] 2. It also forms the high-resistivity beta-phase Ta when deposited directly on the insulator. Furthermore, the Cu barrier properties of Ta fail when it is in contact with Al at moderate temperatures. See for example, the publication by C.-K Hu et al., Proc. VLSI Multilevel Interconn. Conf. 181, (1986) which described an investigation of diffusion barriers to Cu wherein Tantalum, silicon nitride and titanium nitride were found to be the good diffusion barriers to Cu. It is reported that oxygen in the Ta films may have inhibited Cu diffusion.
  • In a publication by L. A. Clevenger et al., J. Appl. Phys. 73, 300 (1993), the effects of deposition pressure, in situ oxygen dosing at the Cu/Ta interface, hydrogen and oxygen contamination and microstructure on diffusion barrier failure temperatures for HV and UHV electron-beam deposited Ta thin films penetrated by Cu were investigated. [0005]
  • Ta[0006] 2N has been proposed as a good copper diffusion barrier, but its adhesion to BEOL insulators and copper is relatively poor. In contrast, the adhesion of TaN (N ˜50%) is adequate, while the adhesion of Cu to TaN is poor. A thin Ta layer can be used to enhance the adhesion of Cu to TaN, without the Ta degrading the performance of Cu BEOL. Such a dual-component liner has been previously disclosed in U.S. Pat. No. 5,281,485 Jan. 25, 1994 to E. G. Colgan and P. M. Fryer. However, the resistivity of this TaN is at least 1200 Micro Ohm-cm, which leads to larger vias or stud resistances, and the inability of the metal liner to act as a redundant current strap or path.
  • For deep-submicron vias (e.g. less than 0.5 um wide) with [0007] ˜250 A liner at the bottom, the series resistance of the above Ta-based liners is in the range from 1 to 5 Ohms. By contrast, the copper stud resistance would be less than 10% of the Ta based liner. Although these via resistances compare very favorably with those of Al(Cu)/W-stud values, it is desirable to reduce them below the 1 Ohm range.
    • SUMMARY OF THE INVENTION
  • In accordance with the present invention, a barrier layer is provided comprising a layer of TaN in the hexagonal phase positioned between a first material to be confined and a second material whereby the second material is isolated from said first material. The first material may be one or a combination of Cu, Al, W and PbSn. [0008]
  • The invention further provides a layer of TaN in the hexagonal phase may be positioned between the gas WF6 and a second material to be isolated from the first material. [0009]
  • The invention further provides an interconnect structure comprising a first insulation layer having an upper and lower surface and having a plurality of grooves formed in the upper surface, some of the grooves having regions extending to the lower surface to expose respective conducting surfaces in a second interconnect structure below the first insulation layer, a liner including a layer of TaN in the hexagonal phase formed on the sidewalls and bottom of the plurality of grooves and on the exposed respective conducting surfaces, and a metal formed in the plurality of grooves to substantially fill the plurality of grooves. [0010]
  • The invention further provides a liner or barrier layer for VLSI/ULSI interconnects and C[0011] 4 solder bumps made mostly of Pb-Sn which simultaneously achieves good diffusion barrier performance, good adhesion to BEOL insulators, good adhesion of interconnect metal to this liner, low resistivity, and good conformality in trenches and vias. The interconnects and studs may comprise aluminum, copper,tungsten, or C4 solder balls made of lead-tin alloy.
  • The invention provides a liner composed of predominately highly oriented and non-highly oriented (random) hexagonal phase TaN (30-60% nitrogen) (which may contain up to 50% cubic phase TaN) deposited alone or as a thin film laminate in combination with other suitable metal films such as Ta. Preferably, the TaN is 100% hexagonal phase. [0012]
  • The liner material described above provides a high integrity barrier, low stress, low resistivity and excellent adhesion to both metal and various dielectrics, such as polymers, silicon dioxide, BPSG, and diamond-like carbon and isolates lead-tin solder metallurgy from Cu and Al interconnects. [0013]
  • The invention further provides a thin film material for isolating Al wiring levels from an immediate Cu interconnection level above or below. [0014]
  • The invention further provides a liner which isolates a metal layer of W, Cu, alloys of Cu, Al and alloys of Al from the contact silicide (WSi[0015] 2, COSi2, TiSi2, TaSi2 and PtSi) and polycrystalline silicon in a MOSFET (metal oxide semiconductor field effect transistor) gate stack.
  • The invention further provides a liner to shield existing metal from certain gases such as WF6 which is corrosive used as a precursor gas for the deposition of W. [0016]
  • The invention further provides a liner which provides good contact resistance to preceding levels of metal, such as aluminum in BEOL wiring. [0017]
  • The invention further provides a liner which provides markedly better conformality than Ti-based compounds even without collimation sputtering or chemical vapor deposition (CVD). [0018]
  • The invention further provides a thin film to isolate BEOL interconnect metals from alloying or mixing with the lead-tin in for example, C[0019] 4 solder balls.
  • The invention further provides a liner material exhibiting good conformality when deposited in trenches and vias BEOL structures. [0020]
  • The invention further provides a liner material which will not form a corrosion couple with Cu, Al, or W during or after chemical mechanical polishing of the liner material.[0021]
    • BRIEF DESCRIPTION OF THE DRAWING
  • These and other features, objects, and advantages of the present invention will become apparent upon consideration of the following detailed description of the invention when read in conjunction with the drawing in which: [0022]
  • FIG. 1 is a cross section view of one embodiment of the invention. [0023]
  • FIG. 2 is a cross section view of a second embodiment of the invention. [0024]
  • FIG. 3 is a cross section view of a third embodiment of the invention. [0025]
  • FIG. 4 is a cross section view of a fourth embodiment of the invention. [0026]
  • FIG. 5 is a graph of an X-ray diffraction pattern for a TaN (hexagonal) film. [0027]
  • FIG. 6 is a Transmission Electron Microscope (TEM) micrograph of a diffraction pattern from TaN (hexagonal) film. [0028]
  • FIG. 7A is a Transmission Electron Microscope (TEM) micrograph of the same highly oriented TaN (hexagonal) film used to provide the X-ray diffraction pattern of FIG. 5. [0029]
  • FIG. 7B is a Transmission Electron Microscope (TEM) micrograph of non-highly oriented (random) TaN (hexagonal) film. [0030]
  • FIG. 8 is a graph of the resistance versus temperature profile of a SiO[0031] 2/Cu/TaN (hexagonal)/Al layered structure.
  • FIG. 9 is a cross-section view of a liner of TaN (hexagonal) for isolating Cu from Al. [0032]
  • FIG. 10 is a cross section view of a fifth embodiment of the invention.[0033]
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to the drawing and more particularly to FIG. 1, a cross section view of [0034] interconnect structures 10 and 18. Interconnect structure 10 includes a layer of insulation 12 having an lower surface 13 and an upper surface 14. A plurality of grooves or trenches 15 are formed in upper surface 14 of insulation layer 12. The plurality of grooves 15 may correspond to a wiring layer of a semiconductor chip 16. Additional interconnect structures may be provided to complete the interconnections for a semiconductor chip 16. Vias or stud openings 11 are formed at the bottom 17 of grooves 15 in selected regions to make contact to conducting surfaces in a second interconnect structure 18 below the insulation layer 12.
  • Interconnect structure [0035] 18 has a conductor 19 in a groove 20 in insulation layer 21. A liner 22 is shown between conductor 19 and the bottom and sidewalls of groove 20.
  • A [0036] liner 23 of TaN (hexagonal) is formed in grooves 15 on the sidewalls 27 and bottom 17 followed by formation of metal 24 in grooves 15 to substantially fill grooves 15. Metal 24 may be Cu, Al, W and alloys thereof. Metal 24 may be formed by sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating. Liner 23 may be formed by sputtering in an atmosphere of nitrogen. Liner 23 may include a second layer of Ta (alpha phase) formed adjacent to such as over TaN (hexagonal). Insulation layer 12 as well as insulation layer 21 may be for example SiO2, Si3N4, polymer such as polyamide, diamond-like carbon (DLC) and Fluorinated diamond-like carbon (F-DLC).
  • Where [0037] liner 23 is a highly oriented layer of TaN in the hexagonal phase, the resistivity will be in the range from 150 to 300 micro ohm-cm. Where liner 23 is a non-highly oriented layer of TaN in the hexagonal phase, the resistivity will be greater than 300 micro ohm-cm. Where a layer of Ta in the alpha phase is formed adjacent the TaN (hexagonal), the resistivity of the Ta (alpha phase) will be in the range from 15 to 60 micro ohm-cm.
  • FIG. 2 is a cross section view of [0038] interconnect structure 34. FIG. 2 shows a semiconductor substrate 16 which may be for example Si, SiGe, Ge, or GaAs. Above substrate 16 may be a layer of insulation 35 which may be for example silicon dioxide. A layer of insulation 36 may be formed over layer of insulation 35 having a groove or trench 38 formed therein filled with metal 24. Layer of insulation 36 and metal 24 may be a coplanar upper surface 39 formed by chemical-mechanical polishing (CMP). Layer of insulation 40 is formed on upper surface 39. A groove or trench 42 is formed in layer of insulation 40 down to metal 24. A liner 23 is formed on the sidewalls and bottom of groove 42 and on the upper surface 43 of layer of insulation 40 (not shown). Groove or trench 42 is filled with metal 46 over liner 23 and on the liner on upper surface 43 (not shown). The excess metal 46 and liner 23 are removed by CMP to provide a planarized upper surface 43 as shown in FIG. 2. In FIG. 2, metal 24 may be for example Al and metal 46 may be tungsten.
  • FIG. 3 is a cross section view of [0039] interconnect structure 50. In FIG. 3, semiconductor substrate 16 has an insulation layer 52 thereover which may be formed by thermal oxidation. A layer 54 of insulation is formed on upper surface 53 on insulation layer 52. A groove or trench 56 is formed in insulation layer 54 and filled with metal 24 and may be for example Al. Insulation layer 54 and metal 24 may have a coplanar upper surface 58 formed by CMP. A layer 12 of insulation is formed on upper surface 58. Layer 12 has an upper surface 14. A groove 15 and via 11 is formed in upper surface 14. A liner 23 is formed on sidewalls 27 and bottom 17 of groove 15 and via or stud 11. Metal 24 is formed over liner 23 in groove 15 and via or stud 11. Upper surface 14 is planar which may be formed by CMP. A layer of insulation 62 is formed on upper surface 14. An opening 64 is formed in layer 62 to expose metal 24′. Liner 23′ is formed on the sidewalls 65 of opening 64 and on exposed metal 24. A blanket metal layer 66 is formed on upper surface 67 on insulation layer 62 and metal 24′. Blanket metal layer 66 is etched through a mask not shown to form a metal pattern for wiring or interconnects. In FIG. 3, metal layer 66 may be for example Al. Metal 24′, may be for example Cu and metal 24 may be for example Al.
  • Thus as shown in FIG. 3, [0040] liner 23 separates metal 24 and 24′ and liner 23′ separates metal 24′ and metal 66.
  • FIG. 4 is a cross section view of [0041] interconnect structure 70. In FIG. 4, substrate 16 has a layer of insulation 72 thereover which may be for example silicon dioxide. Interconnect structure 12 is formed over layer of insulation 72. Insulation layer 62 is formed on upper surface 14. An opening 64 is formed in layer 62 to expose metal 24′. Liner 23′ is formed on the sidewalls 65 of opening 64 and on exposed metal 24. A C4 contact bump 74 of mostly Pb-Sn is formed on liner 23′ in opening 64. The C4 bump is manufactured by the IBM Corp on integrated circuit chips for making interconnections. The C4 bump extends above the integrated circuit chip by about 0.125 millimeters and is round or circular in cross-section parallel to the plane of the upper surface of the integrated circuit chip and is curved from its sides to the top surface of the bump where an interconnection is made to another electrode supported by a substrate.
  • In FIGS. [0042] 2-4, like references are used for functions corresponding to the apparatus of FIG. 1 or of an earlier FIG. than the FIG. being described.
  • FIG. 5 is a graph of an X-ray diffraction pattern for a TaN (hexagonal phase) film formed by physical vapor deposition (PVD). The following PVD arrangement was used to provide highly-oriented and non-oriented TaN (hexagonal) films. The TaN (hexagonal) films were reactively sputter deposited using a magnetron system in either the direct current or radio frequency mode i.e. dc or rf mode. The highly oriented and non-oriented TaN (hexagonal) films made under the above conditions had resistivities in the range from 150 to 800 micro ohm-cm. In FIG. 5, the ordinate represents intensity and the abscissa represents two theta. [0043] Curve 76 shows the X-ray diffraction pattern for two films; the first film has a high degree of preferred orientation and the second film is a non-oriented film. Curve portion 78 shows a single peak at about 37 degrees.
  • FIG. 6 is a Transmission Electron Microscope (TEM) diffraction pattern of a TaN (hexagonal phase) highly oriented film previously measured with X-rays in FIG. 5. The micrograph confirms the hexagonal structure of the TaN barrier showing rings indexed to the hexagonal phase. [0044]
  • FIG. 7A is a Transmission Electron Microscope (TEM) micrograph of a TaN (hexagonal phase) film previously measured with X-rays in FIG. 5. The micrograph shows hexagonal TaN grains which are highly oriented and approximately 20-30 nm in size. [0045]
  • FIG. 7B is a Transmission Electron Microscope (TEM) micrograph of a TaN (hexagonal phase). The micrograph show hexagonal TaN grains which are randomly oriented and also approximately 20-30 nm in size. [0046]
  • FIG. 8 is a graph of the resistance versus temperature provided of a SiO[0047] 2/Cu/TaN (hexagonal)/Al multilayer structure. In FIG. 8, the ordinate represents resistance in ohms/square and the abscissa represents Temperature in degrees Centigrade. Curve 80 shows the resistance with increasing temperature and curve 82 shows the resistance with decreasing temperature. Curves 80 and 82 provide evidence of the effectiveness of TaN (hexagonal) in isolating Cu from Al up to temperatures greater than 500 degrees Centigrade.
  • FIG. 9 is a cross-section view of a liner of TaN (hexagonal) to isolate Cu from Al. In FIG. 9, an interconnect structure is shown with a layer of Al(Cu) [0048] 84, insulation layer 85 of SiO2, and opening or via 86 with a liner 87 on the bottom and sidewalls. Opening 86 is filled with Cu 88 inside liner 87. The excess liner 87 and Cu 88 is removed to form upper surface 89 on insulation layer 85 and upper surface 90 of Cu 88 by CMP. After a temperature anneal at 500 degrees Centigrade for 6 hours, the integrity and the definition of liner 87 remains showing no penetration of Cu through liner 87 to the Al(Cu) layer.
  • FIG. 10 is a cross-section view which depicts the disclosed TaN(hexagonal) barrier used between the silicide gate contact and the W stud in a P-MOSFET (P-type metal oxide semiconductor field effect transistor). [0049]
  • TaN has the advantage as published that it acts to seed only the low-resistivity alpha phase Ta (rho=15 to 60 micro ohm-cm), in contrast to the higher-resistivity beta phase Ta. By using TaN (hexagonal), the resulting via resistances for deep-submicron copper vias with a composite TaN (hexagonal)/alpha phase Ta liner would be in the resistivity range from 0.25 to 1 Ohms. This resistivity is a substantial improvement, about 5 times better, over the previous copper via systems using Ta alone or another material. The resistivity is probably an order of magnitude better than the Al(Cu)/W via system presently used by some major semiconductor manufacturers. [0050]
  • While there has been described and illustrated a barrier layer and an interconnect structure containing a layer of TaN (hexagonal phase) alone or with a second layer of Ta (alpha phase), it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto. [0051]

Claims (24)

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is:
1. A barrier layer comprising:
a layer of TaN in the hexagonal phase positioned between a first material to be confined and a second material whereby said second material is isolated from said first material.
2. The barrier layer of claim 1 wherein said first material is selected from the group consisting of Cu, alloys of Cu, Al, alloys of Al, W, and PbSn.
3. The barrier layer of claim 1 wherein said second material is selected from the group consisting of SiO2, spin-on-glass, Si3N4, polyamide, diamond-like carbon (DLC), and fluorinated diamond-like carbon (F-DLC), WSi2, CoSi2, TiSi2, PtSi.
4. The barrier of claim 1 wherein said layer of TaN in the hexagonal phase is highly oriented having a resistivity in the range from 150 to 300 micro ohm-cm.
5. The barrier of claim 1 wherein said layer of TaN in the hexagonal phase is non-highly oriented having a resistivity greater than 300 micro ohm-cm.
6. The barrier layer of claim 1 further including a Ta layer formed adjacent to said layer of TaN.
7. The barrier layer of claim 6 wherein said Ta layer is in the alpha phase.
8. The barrier layer of claim 7 wherein said Ta layer is formed on said layer of TaN.
9. The barrier layer of claim 8 wherein said Ta layer has a resistivity in the range from 15 to 60 micro ohm-cm.
10. An interconnect structure comprising:
a first insulation layer having an upper and lower surface and having a plurality of grooves formed in said upper surface, some of said grooves having regions extending to said lower surface to expose respective conducting surfaces in a second interconnect structure below said first insulation layer,
a liner including a layer of TaN hexagonal phase formed on the sidewalls and bottom of said plurality of grooves and on said exposed respective conducting surfaces; and a metal formed in said plurality of grooves to substantially fill said plurality of grooves.
11. The interconnect structure of claim 10 wherein said metal is selected from the group consisting of Cu, Al, and W and alloys thereof.
12. The interconnect structure of claim 10 wherein said first insulation layer includes a material selected from the group consisting of SiO2, spin-on-glass, Si3N4, polyamide, diamond-like carbon (DLC) and fluorinated diamond-like carbon (F-DLC).
13. The interconnect structure of claim 10 wherein said layer of TaN in the hexagonal phase is highly oriented having a resistivity in the range from 150 to 300 micro ohm-cm.
14. The interconnect structure of claim 10 wherein said layer of TaN in the hexagonal phase is non-highly oriented having a resistivity greater than 300 micro ohm-cm.
15. The interconnect structure of claim 10 wherein said liner further includes a layer of Ta adjacent said TaN in the hexagonal phase.
16. The interconnect structure of claim 12 wherein said Ta layer is in the alpha phase.
17. The interconnect structure of claim 14 wherein said Ta layer has a resistivity in the range from 15 to 60 micro ohm-cm.
18. The interconnect structure of claim 10 wherein said interconnect structure is formed on a semiconductor chip.
19. The interconnect structure of claim 10 wherein said interconnect structure is formed on a display device.
20. A gate stack over a channel of a MOS transistor comprising:
a layer SiO2,
a layer of poly crystalline silicon,
a layer of TaN (hexagonal); and
a metal layer whereby atoms of said metal layer are isolated from said polycristalline silicon layer.
21. The gate stack of claim 20 wherein said metal is selected from the group consisting of W, Cu, alloys of Cu, Al, and alloys of al.
22. The gate stack over a channel of a MOS transistor comprising:
a layer of SiO2,
a layer of poly crystalline silicon,
a layer of silicide,
a layer of TaN (hexagonal); and
a metal layer whereby atoms of said metal layer are isolated from said silicide layer.
23. The gate stack of claim 21 wherein said layer of a silicide is a silicide selected from the group consisting of WSi2, CoSi2, TiSi2, TaSi2 and PtSi.
24. The gate stack of claim 22 wherein said metal is selected from the group consisting of W, Cu, alloys of Cu, Al, and alloys of Cu.
US09/759,258 1995-06-30 2001-01-16 Thin film metal barrier for electrical interconnections Expired - Lifetime US6437440B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/759,258 US6437440B1 (en) 1995-06-30 2001-01-16 Thin film metal barrier for electrical interconnections

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US49706595A 1995-06-30 1995-06-30
US08/896,925 US6291885B1 (en) 1995-06-30 1997-07-18 Thin metal barrier for electrical interconnections
US37000399A 1999-08-06 1999-08-06
US09/759,258 US6437440B1 (en) 1995-06-30 2001-01-16 Thin film metal barrier for electrical interconnections

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US37000399A Continuation 1995-06-30 1999-08-06

Publications (2)

Publication Number Publication Date
US20020046874A1 true US20020046874A1 (en) 2002-04-25
US6437440B1 US6437440B1 (en) 2002-08-20

Family

ID=23975322

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/896,925 Expired - Lifetime US6291885B1 (en) 1995-06-30 1997-07-18 Thin metal barrier for electrical interconnections
US09/759,258 Expired - Lifetime US6437440B1 (en) 1995-06-30 2001-01-16 Thin film metal barrier for electrical interconnections

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/896,925 Expired - Lifetime US6291885B1 (en) 1995-06-30 1997-07-18 Thin metal barrier for electrical interconnections

Country Status (3)

Country Link
US (2) US6291885B1 (en)
EP (1) EP0751566A3 (en)
JP (2) JP3330495B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010023988A1 (en) * 2000-03-27 2001-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US20050048775A1 (en) * 2001-07-19 2005-03-03 Hilke Donohue Depositing a tantalum film
US20050221612A1 (en) * 2004-04-05 2005-10-06 International Business Machines Corporation A low thermal budget (mol) liner, a semiconductor device comprising said liner and method of forming said semiconductor device
US20050275103A1 (en) * 2002-09-05 2005-12-15 Armin Fischer Integrated circuit comprising intermediate materials and corresponding components
US20100219486A1 (en) * 2005-03-08 2010-09-02 Spansion Llc Method for containing a silicided gate within a sidewall spacer in integrated circuit technology
US20120217591A1 (en) * 2011-02-25 2012-08-30 Fujitsu Limited Semiconductor device and method of manufacturing the same, and power supply apparatus
CN103871977A (en) * 2012-12-14 2014-06-18 英飞凌科技股份有限公司 SEMICONDUCTOR DEVICE and production method thereof
US9698305B2 (en) * 2015-06-12 2017-07-04 Enraytek Optoelectronics Co., Ltd. High voltage LED flip chip

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057237A (en) * 1997-04-29 2000-05-02 Applied Materials, Inc. Tantalum-containing barrier layers for copper
US6437441B1 (en) 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
JPH11135506A (en) * 1997-10-31 1999-05-21 Nec Corp Manufacture of semiconductor device
US6887353B1 (en) * 1997-12-19 2005-05-03 Applied Materials, Inc. Tailored barrier layer which provides improved copper interconnect electromigration resistance
US7253109B2 (en) 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
JP2001511318A (en) * 1997-12-10 2001-08-07 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Semiconductor device and manufacturing method thereof
KR100417725B1 (en) 1997-12-16 2004-02-11 인피니언 테크놀로지스 아게 Intergrated electrical circuit and method for fabricating it
US6251528B1 (en) * 1998-01-09 2001-06-26 International Business Machines Corporation Method to plate C4 to copper stud
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal
CN1222641C (en) * 1998-02-12 2005-10-12 Acm研究公司 Plating apparatus and method
EP0949672A3 (en) * 1998-04-08 2002-09-11 Texas Instruments Incorporated PO Flow for copper metallization
JP3149846B2 (en) * 1998-04-17 2001-03-26 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6287977B1 (en) * 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6221757B1 (en) * 1999-01-20 2001-04-24 Infineon Technologies Ag Method of making a microelectronic structure
US6303500B1 (en) * 1999-02-24 2001-10-16 Micron Technology, Inc. Method and apparatus for electroless plating a contact pad
JP3266195B2 (en) 1999-03-23 2002-03-18 日本電気株式会社 Method for manufacturing semiconductor device
US6251775B1 (en) 1999-04-23 2001-06-26 International Business Machines Corporation Self-aligned copper silicide formation for improved adhesion/electromigration
US6375693B1 (en) 1999-05-07 2002-04-23 International Business Machines Corporation Chemical-mechanical planarization of barriers or liners for copper metallurgy
JP5053471B2 (en) * 1999-05-11 2012-10-17 株式会社東芝 Wiring film manufacturing method and electronic component manufacturing method
DE19922557B4 (en) 1999-05-17 2004-11-04 Infineon Technologies Ag Process for depositing a TaN / Ta two-layer diffusion barrier
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6339258B1 (en) * 1999-07-02 2002-01-15 International Business Machines Corporation Low resistivity tantalum
US6498385B1 (en) 1999-09-01 2002-12-24 International Business Machines Corporation Post-fuse blow corrosion prevention structure for copper fuses
US6426557B1 (en) * 2000-02-25 2002-07-30 International Business Machines Corporation Self-aligned last-metal C4 interconnection layer for Cu technologies
DE10014917B4 (en) 2000-03-17 2004-12-02 Infineon Technologies Ag Method of making a contact layer
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
JP2002064190A (en) * 2000-08-18 2002-02-28 Mitsubishi Electric Corp Semiconductor device
US20020142589A1 (en) * 2001-01-31 2002-10-03 Applied Materials, Inc. Method of obtaining low temperature alpha-ta thin films using wafer bias
US6566242B1 (en) 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6429524B1 (en) 2001-05-11 2002-08-06 International Business Machines Corporation Ultra-thin tantalum nitride copper interconnect barrier
JP2002343859A (en) 2001-05-15 2002-11-29 Mitsubishi Electric Corp Connection structure between wires and its manufacturing method
TW518680B (en) * 2001-06-13 2003-01-21 Matsushita Electric Ind Co Ltd Semiconductor device and method for fabricating the same
JP3442065B2 (en) * 2001-06-13 2003-09-02 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
WO2003009372A2 (en) * 2001-07-20 2003-01-30 Applied Materials, Inc. Low resistivity tantalum nitride/tantalum bilayer stack
JP2003133312A (en) * 2001-10-25 2003-05-09 Hitachi Ltd Semiconductor device and manufacturing method therefor
US6873027B2 (en) 2001-10-26 2005-03-29 International Business Machines Corporation Encapsulated energy-dissipative fuse for integrated circuits and method of making the same
US6727176B2 (en) * 2001-11-08 2004-04-27 Advanced Micro Devices, Inc. Method of forming reliable Cu interconnects
US6727592B1 (en) * 2002-02-22 2004-04-27 Advanced Micro Devices, Inc. Copper interconnect with improved barrier layer
US6794753B2 (en) * 2002-12-27 2004-09-21 Lexmark International, Inc. Diffusion barrier and method therefor
US7294241B2 (en) * 2003-01-03 2007-11-13 Chartered Semiconductor Manufacturing Ltd. Method to form alpha phase Ta and its application to IC manufacturing
JP2004253781A (en) * 2003-01-31 2004-09-09 Nec Electronics Corp Semiconductor device and its manufacturing method
CN1317745C (en) * 2003-06-13 2007-05-23 联华电子股份有限公司 Method and structure for forming barrier layer
JP2005019493A (en) * 2003-06-24 2005-01-20 Renesas Technology Corp Semiconductor device
US20050037613A1 (en) * 2003-08-14 2005-02-17 Stephan Grunow Diffusion barrier for copper lines in integrated circuits
US6992390B2 (en) * 2003-11-07 2006-01-31 International Business Machines Corp. Liner with improved electromigration redundancy for damascene interconnects
US20050118796A1 (en) * 2003-11-28 2005-06-02 Chiras Stefanie R. Process for forming an electrically conductive interconnect
MXPA06010834A (en) * 2004-03-24 2007-03-23 Starck H C Inc Methods of forming alpha and beta tantalum films with controlled and new microstructures.
US7071097B2 (en) * 2004-07-09 2006-07-04 International Business Machines Corporation Method for improved process latitude by elongated via integration
JP4455214B2 (en) * 2004-08-05 2010-04-21 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7157795B1 (en) * 2004-09-07 2007-01-02 Advanced Micro Devices, Inc. Composite tantalum nitride/tantalum copper capping layer
US7196014B2 (en) * 2004-11-08 2007-03-27 International Business Machines Corporation System and method for plasma induced modification and improvement of critical dimension uniformity
US7078810B2 (en) * 2004-12-01 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication method thereof
US7449409B2 (en) * 2005-03-14 2008-11-11 Infineon Technologies Ag Barrier layer for conductive features
US7323780B2 (en) * 2005-11-10 2008-01-29 International Business Machines Corporation Electrical interconnection structure formation
US7517736B2 (en) * 2006-02-15 2009-04-14 International Business Machines Corporation Structure and method of chemically formed anchored metallic vias
US7435674B2 (en) * 2006-03-27 2008-10-14 International Business Machines Corporation Dielectric interconnect structures and methods for forming the same
US7446058B2 (en) * 2006-05-25 2008-11-04 International Business Machines Corporation Adhesion enhancement for metal/dielectric interface
US7713866B2 (en) 2006-11-21 2010-05-11 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
JP2008281196A (en) * 2007-04-11 2008-11-20 Ntn Corp Bearing for two-wheeled vehicle reduction gear
US7977798B2 (en) * 2007-07-26 2011-07-12 Infineon Technologies Ag Integrated circuit having a semiconductor substrate with a barrier layer
US20090194846A1 (en) * 2008-02-02 2009-08-06 Edward Yi Chang Fully Cu-metallized III-V group compound semiconductor device with palladium/germanium/copper ohmic contact system
US7928569B2 (en) * 2008-08-14 2011-04-19 International Business Machines Corporation Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture
US7863106B2 (en) 2008-12-24 2011-01-04 International Business Machines Corporation Silicon interposer testing for three dimensional chip stack
US8242600B2 (en) * 2009-05-19 2012-08-14 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
US8336204B2 (en) * 2009-07-27 2012-12-25 International Business Machines Corporation Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application
US8420531B2 (en) 2011-06-21 2013-04-16 International Business Machines Corporation Enhanced diffusion barrier for interconnect structures
US9831122B2 (en) 2012-05-29 2017-11-28 Globalfoundries Inc. Integrated circuit including wire structure, related method and design structure
CN103280447B (en) * 2013-04-25 2015-12-09 京东方科技集团股份有限公司 Circuit board, its manufacture method and display unit
CN104576513B (en) * 2013-10-29 2017-08-08 中芯国际集成电路制造(上海)有限公司 Prevent barrier bi-layer and corresponding manufacture method that copper spreads
US9583417B2 (en) 2014-03-12 2017-02-28 Invensas Corporation Via structure for signal equalization
US9991330B1 (en) 2017-01-11 2018-06-05 International Business Machines Corporation Resistors with controlled resistivity
US10283583B2 (en) 2017-01-11 2019-05-07 International Business Machines Corporation 3D resistor structure with controlled resistivity
US9972672B1 (en) 2017-01-11 2018-05-15 International Business Machines Corporation Tunable resistor with curved resistor elements
US10916503B2 (en) 2018-09-11 2021-02-09 International Business Machines Corporation Back end of line metallization structure
JP6640391B2 (en) * 2019-01-22 2020-02-05 ルネサスエレクトロニクス株式会社 Semiconductor device
US20210143061A1 (en) * 2019-11-07 2021-05-13 International Business Machines Corporation Hybrid metallization and dielectric interconnects in top via configuration
FR3108205A1 (en) * 2020-03-12 2021-09-17 Stmicroelectronics (Grenoble 2) Sas Integrated circuit comprising an interconnection part comprising a protruding solder element and corresponding manufacturing method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3063506D1 (en) * 1979-08-31 1983-07-07 Fujitsu Ltd A tantalum thin film capacitor and process for producing the same
US4385116A (en) 1980-07-15 1983-05-24 Eli Lilly And Company Demethylmacrocin and process for its production
US4386116A (en) 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
US4640004A (en) * 1984-04-13 1987-02-03 Fairchild Camera & Instrument Corp. Method and structure for inhibiting dopant out-diffusion
US4789648A (en) 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4944836A (en) 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
JPH0819516B2 (en) * 1990-10-26 1996-02-28 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Method and structure for forming thin film alpha Ta
US5221449A (en) 1990-10-26 1993-06-22 International Business Machines Corporation Method of making Alpha-Ta thin films
US6475903B1 (en) 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
US5744376A (en) 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909191B2 (en) * 2000-03-27 2005-06-21 Kabushiki Kaisha Toshiba Semiconductor device
US20010023988A1 (en) * 2000-03-27 2001-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US20050048775A1 (en) * 2001-07-19 2005-03-03 Hilke Donohue Depositing a tantalum film
US7129161B2 (en) * 2001-07-19 2006-10-31 Trikon Holdings Limited Depositing a tantalum film
US7315998B2 (en) * 2002-09-05 2008-01-01 Infineon Technologies Ag Integrated circuit arrangement with intermediate materials and associated components
US20050275103A1 (en) * 2002-09-05 2005-12-15 Armin Fischer Integrated circuit comprising intermediate materials and corresponding components
US20050221612A1 (en) * 2004-04-05 2005-10-06 International Business Machines Corporation A low thermal budget (mol) liner, a semiconductor device comprising said liner and method of forming said semiconductor device
US20100219486A1 (en) * 2005-03-08 2010-09-02 Spansion Llc Method for containing a silicided gate within a sidewall spacer in integrated circuit technology
US8252676B2 (en) * 2005-03-08 2012-08-28 Spansion Llc Method for containing a silicided gate within a sidewall spacer in integrated circuit technology
US20120217591A1 (en) * 2011-02-25 2012-08-30 Fujitsu Limited Semiconductor device and method of manufacturing the same, and power supply apparatus
US9741662B2 (en) 2011-02-25 2017-08-22 Fujitsu Limited Semiconductor device and method of manufacturing the same, and power supply apparatus
CN103871977A (en) * 2012-12-14 2014-06-18 英飞凌科技股份有限公司 SEMICONDUCTOR DEVICE and production method thereof
US9698305B2 (en) * 2015-06-12 2017-07-04 Enraytek Optoelectronics Co., Ltd. High voltage LED flip chip

Also Published As

Publication number Publication date
JPH0917790A (en) 1997-01-17
JP2003007707A (en) 2003-01-10
EP0751566A3 (en) 1997-02-26
US6437440B1 (en) 2002-08-20
US6291885B1 (en) 2001-09-18
JP4346866B2 (en) 2009-10-21
EP0751566A2 (en) 1997-01-02
JP3330495B2 (en) 2002-09-30

Similar Documents

Publication Publication Date Title
US6437440B1 (en) Thin film metal barrier for electrical interconnections
US7679193B2 (en) Use of AIN as cooper passivation layer and thermal conductor
US6218302B1 (en) Method for forming a semiconductor device
US5892282A (en) Barrier-less plug structure
US6181012B1 (en) Copper interconnection structure incorporating a metal seed layer
US5084412A (en) Method of manufacturing a semiconductor device with a copper wiring layer
US7247946B2 (en) On-chip Cu interconnection using 1 to 5 nm thick metal cap
US6740985B1 (en) Structure for bonding pad and method for its fabrication
US6720261B1 (en) Method and system for eliminating extrusions in semiconductor vias
US4910580A (en) Method for manufacturing a low-impedance, planar metallization composed of aluminum or of an aluminum alloy
US6174799B1 (en) Graded compound seed layers for semiconductors
US6506668B1 (en) Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US20030045093A1 (en) Method for metal fill by treatment of mobility layers
US5798301A (en) Method of manufacturing metal interconnect structure for an integrated circuit with improved electromigration reliability
US6624516B2 (en) Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer
US20060216925A1 (en) Semiconductor integrated circuit device and a method of manufacturing the same
US6229213B1 (en) Germanium alloy electrical interconnect structure
US20030085470A1 (en) Semiconductor device and method of manufacturing the same
US6724087B1 (en) Laminated conductive lines and methods of forming the same
US6110829A (en) Ultra-low temperature Al fill for sub-0.25 μm generation of ICs using an Al-Ge-Cu alloy
US7067917B2 (en) Gradient barrier layer for copper back-end-of-line technology
EP0987752A2 (en) Improved-reliability damascene interconnects and process of manufacture
US6979642B1 (en) Method of self-annealing conductive lines that separates grain size effects from alloy mobility
JP2795277B2 (en) Semiconductor device

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

AS Assignment

Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001

Effective date: 20181127

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001

Effective date: 20201117