TWI737967B - Chip carrier - Google Patents

Abstract

A chip carrier is provided, and includes a bearing surface, a plurality of grooves, a plurality of vacuum suction holes, and a plurality of blocks. The grooves are recessed on the bearing surface and disposed along a lateral direction and a longitudinal direction respectively, so that the bearing surface defines a plurality of chip placement areas. The vacuum suction holes are disposed on the bearing surface, and located in each of the chip placement areas. The blocks are disposed in the grooves respectively corresponding to the chip placement areas, and protrude from the bearing surface. Therefore, the chip carrier can carry a plurality of chips to be tested, thereby improving the testing efficiency.

Description

Wafer carrier

The present invention relates to a bearing seat, in particular to a wafer bearing seat.

The wafer carrier is generally loaded in a wafer testing device, and a wafer to be tested is placed on it, and then the probe of the wafer testing device contacts the contact of the wafer to test the electrical characteristics of the wafer.

The current industry practice is that a wafer testing device has a wafer carrier, which can only carry and test one wafer; when a wafer is tested, the wafer is removed from the wafer carrier, and then the next wafer to be tested Place it on the wafer carrier. Therefore, if there are multiple wafers to be tested at the same time, a plurality of wafer testing devices need to be prepared for each of them. However, because multiple wafer test devices are required, the test cost will increase, and more space is needed to swing the wafer test devices; in addition, the maintenance and repair time and cost of these wafer test devices will also increase.

Therefore, in the technical field of wafer testing, there are still several problems to be improved.

One objective of the present invention is to provide a wafer carrier that can simultaneously carry a plurality of wafers for the wafer testing device to test the wafers at the same time, so as to save testing time, cost, and the like.

In order to achieve the above objective, the chip carrier disclosed in the present invention includes: a carrier surface; a plurality of grooves are recessed on the carrier surface, and are arranged horizontally and longitudinally, so that the carrier surface defines a plurality of grooves. A wafer placement area and a plurality of vacuum suction holes are arranged on the carrying surface and located in each of the wafer placement areas; and, a plurality of stoppers are respectively provided in the wafer placement areas corresponding to the wafer placement areas In the grooves and protruding from the bearing surface.

Preferably, the wafer placement areas are two wafer placement areas, and one of the grooves is located between the two wafer placement areas.

Preferably, the wafer placement areas are two wafer placement areas, and the two wafer placement areas are located between two of the trenches.

Preferably, the wafer placement areas are four wafer placement areas, and one of the grooves is located between two of the four wafer placement areas.

Preferably, the wafer placement areas are four wafer placement areas, and the four wafer placement areas are surrounded by the grooves.

Preferably, the number of the stoppers is equal to or greater than the number of the chip placement areas.

Another object of the present invention is to provide a wafer testing device, which can test a plurality of wafers at the same time, so as to save testing time, cost and the like.

In order to achieve the above objective, a wafer testing device disclosed in the present invention includes the above-mentioned wafer carrier and a test head, and the test head is vertically movably arranged above the carrier surface of the wafer carrier.

Preferably, the wafer testing device further includes a position adjuster, and the wafer carrier is disposed on the position adjuster.

Preferably, the wafer testing device further includes a wafer pusher, and the wafer pusher is horizontally movably arranged above the carrying surface.

Preferably, the test head includes a plurality of probes, and the probes are horizontal or vertical.

In order to make the above objectives, technical features, and advantages more obvious and understandable, a detailed description will be given below with a preferred embodiment in conjunction with the accompanying drawings.

In order to make the above objectives, technical features, and advantages more obvious and understandable, a detailed description will be given below with a preferred embodiment in conjunction with the accompanying drawings.

10A‧‧‧Chip Carrier

100‧‧‧Loading surface

101‧‧‧Groove

102‧‧‧Vacuum suction hole

103‧‧‧Block

104‧‧‧Chip placement area

105‧‧‧chip

20A‧‧‧Chip Tester

201‧‧‧Test head

201A‧‧‧Probe

202‧‧‧Position adjuster

203‧‧‧Lifting device

204‧‧‧Chip Pusher

Fig. 1A is a perspective exploded view of the chip carrier according to the first preferred embodiment of the present invention; Fig. 1B is a three-dimensional assembly view of the chip carrier shown in Fig. 1A; Fig. 2A is the one shown in Fig. 1A A top view of a chip carrier; Fig. 2B is a top view of a chip carrier according to the second preferred embodiment of the present invention; Fig. 2C and Fig. 2D are of a chip carrier according to the third preferred embodiment of the present invention Top view; FIG. 3A is a top view of a chip carrier according to the fourth preferred embodiment of the present invention; FIG. 3B is a top view of a chip carrier according to the fifth preferred embodiment of the present invention; FIGS. 4A and 4B Figures are a side view of a wafer testing device according to a sixth embodiment of the present invention; and Figures 5A and 5B are schematic diagrams of a wafer stepper and a wafer in the wafer testing device shown in Figure 4A.

The following will specifically describe some specific embodiments according to the present invention; however, without departing from the spirit of the present invention, the present invention can still be practiced in many different forms of embodiments, and the protection scope of the present invention should not be construed as being limited to that described in the specification. Presenter. In addition, each technical content in the foregoing invention content can also be used as the technical content of the embodiment, or as a possible variation of the embodiment. In addition, the following orientations (such as front, back, top, bottom, sides, etc.) are relative orientations, which can be defined according to the usage state of the chip test stand (for example, horizontal placement). The so-called chip may include unpackaged die or packaged die.

Please refer to FIG. 1A, FIG. 1B and FIG. 2A, which are the three-dimensional exploded view, assembly view and top view of the chip carrier 10A according to the first preferred embodiment of the present invention. The wafer carrier 10A (hereinafter referred to as the carrier 10A) is made of an insulating material and is as large as a block or plate, and can be installed in a wafer testing device 20A described later (as shown in FIG. 5A). Structurally, the supporting base 10A may include a supporting surface 100, a plurality of grooves 101, a plurality of vacuum suction holes 102, and a plurality of stoppers 103. These structural features are further described in sequence below.

The bearing surface 100 may be the upper surface of the bearing seat 10A, and may be a flat surface. The grooves 101 are recessed on the carrying surface 100. In other words, the grooves 101 are open on the carrying surface 100; the grooves 101 are also arranged in the horizontal and vertical directions, one of which is arranged in the horizontal direction, and The other is vertical configuration, not all horizontal and vertical configurations. The horizontal or vertical direction is staggered with the normal direction of the bearing surface 100. In this embodiment, the trenches 101 can be connected to form a T-shaped trench as a whole, but the trenches 101 can also be separated (not shown).

The grooves 101 are used to define a plurality of chip placement areas on the bearing surface 100 104. The boundary of the wafer placement areas 104 is one of the trenches 101; in this embodiment, the carrying surface 100 is divided into two wafer placement areas 104, and one of the trenches 101 is located on the two wafers Between the placement areas 104, another trench 101 is located on the same side of the two wafer placement areas 104, so that the two wafer placement areas 104 are completely separated by the trenches 101.

The plurality of vacuum suction holes 102 are also provided on the carrying surface 100, and can penetrate to the other surface (the lower surface or side) of the carrier 10A; in addition, each wafer placement area 104 has one or more vacuum suction holes.孔102. The vacuum suction holes 102 can be connected to a vacuum pump (not shown) to provide suction on the carrying surface 100 to suck the wafer 105 (shown in Figure 2A) placed on the carrying surface 100 to prevent the wafer 105 from moving. Measurement error, or probe damage, etc.

The stoppers 103 are respectively disposed in the grooves 101 corresponding to the wafer placement regions 104 and protrude from the carrying surface 100. Specifically, the stoppers 103 are placed at a specific position in the trench 101 as a part of the boundary of the wafer placement area 104. Because it protrudes from the carrying surface 100, the stopper 103 can be pressed against the wafer 105 on the carrying surface 100, thereby positioning the wafer 105 on the carrying surface 100; therefore, if the size of the wafer 105 is large, the position of the stopper 103 Or the length can be adjusted accordingly, so that the wafer 105 can be firmly abutted. In addition, the stopper 103 can be made of various materials such as metal, rubber, plastic, etc., and the stopper 103 can be locked in the groove 101 by bolts, or fixed in other appropriate ways.

In this embodiment, there are three stoppers 103, which are respectively arranged in the middle of the three grooves 101 and are separated from each other (the number of stoppers 103 is equal to the number of grooves 101); in other embodiments, the The stoppers 103 can be integrally connected to form a T-shaped structure (not shown in the figure). Or, two of the stoppers 103 are integrally connected to form a long stopper, and the other stopper 103 is relatively short, And it is separated from the long block (not shown in the figure). Through the design of the above-mentioned long block or T-shaped block, the adjustment time for the size of the chip 105 when the block 103 is installed can be reduced.

The above-mentioned groove 101 configuration and the corresponding stop configuration can have other implementations, which will be described in the following second embodiment to fifth embodiment in sequence.

Please refer to FIG. 2B. In the second embodiment, there are also two wafer placement areas 104 for two wafers 105 to be placed, and the two wafer placement areas 104 are located in two of the trenches 101 Between. More specifically, the grooves 101 extend from the same side of the two wafer placement areas 104 to the left and right sides of the two wafer placement areas 104, forming a U-shaped groove as a whole, surrounding the two wafer placement areas 104 Among them; the two wafer placement areas 104 are not completely separated by the trench 101. As for the stoppers 103, four stoppers 103 can be arranged in the three grooves 101 (the number of stoppers 103 is greater than the number of grooves 101 by the same amount), and the two stoppers 103 correspond to one wafer placement area 104.

In other implementations (not shown in the figure), the two stoppers 103 can also be integrally formed to form an L-shaped stopper and abut the two sides of the wafer 105 at the same time; or the four stoppers 103 can be integrally formed to form a U Or, the grooves 101 on the left and right sides each place a stop 103, and the groove 101 on the front side places a longer stop 103, and simultaneously abuts the front side of the two wafers 105.

Please refer to FIG. 2C and FIG. 2D. In the third embodiment, there are two wafer placement areas 104, and one of the wafer placement areas 104 is located between the two longitudinally arranged trenches 101, and the other A wafer placement area 104 is located on one side of a trench 101 arranged in a longitudinal direction. In other words, one of the longitudinally arranged trenches 101 is located between the two wafer placement areas 104.

Please refer to FIG. 3A. In the fourth embodiment, the wafer placement areas There are four more 104, which can be used for placing four wafers 105 therein; one of the grooves 101 is located between two of the four wafer placing regions 104. More specifically, the cross-shaped grooves formed by the staggered grooves 101 divide the carrying surface 100 into four separate wafer placement areas 104, and the four wafers 105 are respectively disposed in the wafer placement areas 104 . Then, the four stoppers 103 are respectively corresponding to the chip 105 and arranged in the groove 101; in addition, the stoppers 103 can also be connected as described above to form an elongated stopper or a cross-shaped stopper (not shown in the figure).式) etc.

Please refer to FIG. 3B. In the fifth embodiment, the number of wafer placement areas 104 is also four, but the four wafer placement areas 104 are surrounded by the trenches 101 without being separated. Therefore, when the four wafers 105 are placed in the four wafer placement areas 104, they will be surrounded by the grooves 101. The stoppers 103 are arranged in the grooves 101 corresponding to the four chip placement areas 104, and as described above, they can be integrally connected to form a long stopper, an L-shaped stopper, or a square-shaped stopper (Figure Unstyled).

It is also noted that in the fourth or fifth embodiment, only two or three wafers 105 may be placed in the wafer placement areas 104.

Thereby, the bearing surface 100 of each bearing seat 10A has a plurality of chip placement areas 104 for placement of a plurality of chips 105 (instead of a single chip), and each chip 105 can abut at least two stoppers 103. Positioning, and then fixed by the suction force of the vacuum suction hole 102. Each carrier 10A described above includes two or four chip placement areas 104 as an example. By increasing the number of grooves 101 and/or adjusting the arrangement of the grooves 101, the carrier 10A can include more chip placement areas 104 ( Such as six, eight, twelve, sixteen, thirty-two, etc.) to carry more chips 105 for one-time testing.

Each of the above-mentioned carriers 10A can be applied to, for example, the wafer test device 20A (hereinafter referred to as the test device 20A) described below, so that the test device 20A can test a plurality of devices at the same time. Wafer 105.

Please refer to FIGS. 4A and 4B, which are schematic diagrams of a testing device 20A according to a sixth preferred embodiment of the present invention. The testing device 20A may include the carrier 10A of the above-mentioned embodiment and a testing head 201, The test head 201 is vertically movably arranged above the bearing surface 100 of the bearing base 10A. Specifically, the testing device 20A may include a lifting device 203, which is arranged beside the bearing base 10A, and the lifting device 203 is equipped with the test head 201 so that the test head 201 can move vertically relative to the bearing base 10A.

In addition, the test head 201 includes a plurality of probes 201A. The probes 201A can be horizontal (as shown in Figure 4A) or vertical (as shown in Figure 4B), and the number and position of the probes can be adapted to the test. The contact of the chip 105. When the test head 201 is lowered, its probe 201A can contact the contact of the wafer 105 and give proper pressure to the contact to start the wafer test operation.

In addition, the testing device 20A may further include a position adjuster 202, and the carrier 10A is disposed on the position adjuster 202. In other words, under the carrier 10A is provided with a position adjuster 202 that can adjust the XYZ three-axis or angle, and the carrier 10A can adjust the position or angle of the XYZ three-axis so that the chip 105 on it can be connected. The point can accurately correspond to the probe 201A of the test head 201.

Next, referring to FIGS. 5A and 5B, the testing device 20A may further include a wafer pusher 204 (hereinafter referred to as the pusher 204). The pusher 204 is horizontally movably disposed above the carrying surface 100 of the carrying base 10A. The wafer 105 on the supporting surface 100 is pushed to the stopper 103. Specifically, the number of pushers 204 can correspond to the number of wafer carrying areas 104 (wafers 105); taking two wafer placement areas 104 as an example, four pushers 240 can be provided, with two as a group corresponding to one Wafer placement area 104. After the chip 105 is placed on the carrying surface 100, the The pushers 204 horizontally move to the side of the wafer 105 individually, and then push the wafer 105 to abut the stopper 103. Since one wafer 105 is provided with two pushers 204 corresponding to each other, the wafer 105 can be pushed horizontally and vertically at the same time. After pushing, the vacuum pump can be activated to make the vacuum suction hole 102 adsorb the wafer 105, and the pusher 204 is moved back to the initial position.

In addition, there may be only one pusher 204, which pushes the wafer 105 to the stopper 103 in sequence. In addition, as shown in Figure 5B, the pusher 204 including the push rod or the needle can be inclined with respect to the wafer 105, and the end of the push rod or needle touches one side of the wafer 105 to push the wafer 105; the push rod or needle can also be The wafer 105 is pushed against the wafer 105 to be horizontal.

In summary, the chip carrier proposed by the present invention can carry multiple chips instead of a single chip to be tested. Therefore, one chip testing device can test multiple chips, thereby reducing the time and cost of chip testing, and can Reduce the number of wafer test devices and the space occupied.

The above-mentioned embodiments are only used to illustrate the implementation of the present invention and explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equivalence arrangements that can be easily completed by those familiar with this technology belong to the scope of the present invention, and the scope of protection of the rights of the present invention shall be subject to the scope of the patent application.

10A‧‧‧Chip Carrier

100‧‧‧Loading surface

101‧‧‧Groove

102‧‧‧Vacuum suction hole

103‧‧‧Block

104‧‧‧Chip placement area

Claims (10)

A wafer bearing seat, comprising: a bearing surface; a plurality of grooves, recessed on the bearing surface, and arranged horizontally and longitudinally, respectively, so that the bearing surface defines a plurality of wafer placement areas; and a plurality of vacuums Suction holes are provided on the carrying surface and located in each of the wafer placement areas, and a plurality of stoppers are respectively provided in the grooves corresponding to the wafer placement areas and protrude from the On the carrying surface, the stoppers can be used to abut the chips on the carrying surface, so that the chips are positioned on the carrying surface. The wafer carrier according to claim 1, wherein the wafer placement areas are two wafer placement areas, and one of the grooves is located between the two wafer placement areas. The wafer carrier according to claim 1, wherein the wafer placement areas are two wafer placement areas, and the two wafer placement areas are located between two of the grooves. The chip carrier according to claim 1, wherein the chip placement areas are four chip placement areas, and one of the grooves is located between two of the four chip placement areas. The wafer carrier according to claim 1, wherein the wafer placement areas are four wafer placement areas, and the four wafer placement areas are surrounded by the grooves. The chip carrier according to any one of claims 1 to 5, wherein the number of the stoppers is equal to or greater than the number of the chip placement areas. A wafer testing device, comprising: a wafer carrier according to any one of claims 1 to 5; and a test head, which is vertically movably arranged above the carrier surface of the wafer carrier. The wafer testing device according to claim 7 further includes a position adjuster, and the wafer carrier is disposed on the position adjuster. The wafer testing device according to claim 7, further comprising a wafer pusher, and the wafer pusher is horizontally movably arranged above the carrying surface. The wafer testing device according to claim 7, wherein the test head includes a plurality of probes, and the probes are of a horizontal type or a vertical type.

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