TWI715095B - Methods and memory systems of parity training for a dram - Google Patents

Abstract

A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.

Description

DRAM parity check training method and memory system

Cross-reference: This application claims priority for the U.S. Provisional Application 62/693,495 filed on July 3, 2018 with the title of "ECC Parity Training Method" and the U.S. Application 16/459,621 filed on July 2, 2019 . The entire content of the aforementioned application is incorporated into the present invention.

The present invention relates to memory, especially a parity check training method for DRAM that supports link error checking and correction functions.

Dynamic Random Access Memory (DRAM) supports link error checking and correction (Error Checking And Correcting, ECC) functions for read and write operations to recover (recover) Data, even when errors are introduced due to transmission or storage (charge loss) of data. When the link ECC function is enabled, the Data Mask Inversion (DMI) pin is used to read parity from DRAM, and Read Data Strobe , RDQS) pin is used to write parity check into DRAM. In short, when the Write Link ECC (Write Link ECC) is enabled, the RDQS pin is used for parity checking.

In order to reach the RDQS lead aligned with the data (DQ) of the data (DQ) pin For the RDQS of the latch to enable the DRAM controller to read/write to the DRAM, the RDQS needs to be trained to make it phase alignment with the DQ. In traditional parity training (parity training), read and write First Input First Output (First Input First Output, FIFO) commands can be used to read data from/to DRAM through the RDQS pin from DRAM's FIFO file (file) Write data to the FIFO file. Specifically, the DRAM controller uses the Write FIFO (Write FIFO) command to write data to the FIFO file of the DRAM via the RDQS pin, and then uses the Read FIFO (Read FIFO) command to read back via the DMI pin. In this way, the DRAM controller repeats writing and reading by adjusting the RDQS time until the data transferred to the DRAM via the RDQS pin is correct, thereby completing the parity check training.

It can be seen that the traditional parity check training method requires additional FIFO files in the DRAM, and the read and write FIFOs are limited in length, so the training mode cannot be complex enough to allow the DRAM controller to optimize write/read The latch point of the parity check bit.

In order to solve the above-mentioned problems, an object of the present invention is to provide a parity check training method for dynamic random access memory that supports the link ECC function.

The present invention discloses a parity check training method for dynamic random access memory. The method includes enabling link error checking and correction functions in the write operation of the dynamic random access memory; and writing The parity check function of the parity check pin is remapped to a data inversion function, a data replacement function, or a logic function, wherein the data transmitted to the dynamic random access memory through the write parity check pin is used to indicate data The pin data is reversed, logically operated or replaced.

The present invention also discloses a memory system. The memory system includes a dynamic random access memory; and a memory controller for writing in the dynamic random access memory Enable the link error check and correction function, and remap the parity check function written to the parity check pin to a data inversion function, a data replacement function, or a logic function, wherein the write parity check pin is transmitted to the The data of the dynamic random access memory is used to instruct the data pin data inversion operation, logic operation or replacement operation.

After reading the implementation of the following preferred embodiments, the above-mentioned objects and other objects of the present invention will become apparent to those having ordinary knowledge in the art, and the preferred embodiments can be illustrated in the respective drawings.

10: Memory system

110: Memory Controller

120: DRAM

Figure 1 is a schematic diagram of a memory system according to an embodiment of the invention.

Figure 2 is a schematic diagram of a DRAM according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a DRAM write/read operation according to an embodiment of the present invention.

Please refer to FIG. 1, which illustrates a schematic diagram of a memory system 10 according to an embodiment of the present invention. The memory system 10 may include a memory controller 110 and a DRAM 120. The memory controller 110 and the DRAM 120 can be connected via a data bus to send/receive command (Command, CMD) signals, different clock (Clock, CLK) signals, and data bus inversion (Data Bus Inversion). , DBI) signal, data DQ[7:0], DMI signal and RDQS signal. The memory controller 110 can perform write/read operations with the DRAM 120 via corresponding pins (such as DQ pins, DMI pins, and RDQS pins) to write/read data bits to/from the DRAM 120 DQ0-DQ7, DMI and RDQS. The DRAM 120 can support the link ECC function, and when the link ECC function is enabled in a write operation, it can be written to a parity pin (write parity pin) (such as RDQS pin) to perform write parity check pin training operation.

When the link ECC function is enabled in the write operation, the RDQS pin can be used to 120 write parity check bit. However, the data (parity check bit) transferred from the memory controller 110 to the DRAM 120 through the RDQS pin is not written into the DRAM 120, so that the memory controller 110 cannot receive data from the DRAM 120 through the DMI pin during a read operation. Read back. Therefore, the memory controller 110 cannot train the write parity check pin (such as the RDQS pin), which may affect the write/read operation.

The present invention aims to provide a parity check training method when the RDQS pin is used for writing parity check operations. Specifically, in the write parity check pin training operation, the RDQS pin is not used for the write parity check operation, but is used for the data inversion function, data replacing function or logic function. (logical function).

In summary, the write parity check pin training operation can be performed by remapping the parity check function of the RDQS pin into the following functions: data bit DQ[7:0] inversion operation (ie DMI/DBI); Replace one of the data bits DQ[7:0]; other logical operations on part or all of the data bits DQ[7:0].

More specifically, the data (called parity check bit) transmitted to the DRAM 120 through the RDQS pin can be used to indicate whether to invert the data of the DQ pin, and to indicate whether to perform a predetermined logical operation on the data of the DQ pin ( For example, and (AND), or (OR), not (NOT), NAND, NOR, XOR or XNOR operations), or used to indicate whether to use RDQS The data transferred from the pin to the DRAM 120 replaces the data of the DQ pin.

With reference to Figure 2, Figure 2 describes the operation of the DRAM according to the embodiment of the present invention.

In the RDQS pin training, the data transmitted to the DRAM through the RDQS pin is not regarded as an ECC parity check, but is remapped as a DMI operation on the data bit DQ[7:0]. As shown in Figure 2, the data bits DQ[7:0], RDQS and DMI can be sent to the "de-serialize" of DRAM Module. Please note that the data transmitted to the "deserialization" module via the RDQS pin can replace the data on the DMI pin. Therefore, the data bits DQ[7:0] and DMI can be sent to the "DBI Decoding" module to write the inverted data bits DQ[7:0] to the DRAM. Please note that in other embodiments, as long as the data (parity check bit) transferred to the DRAM through the RDQS pin can be observed (observe) by reading back the data bit DQ[7:0] from the DRAM, then pass The data transferred from the RDQS pin to the DRAM can be remapped as a replacement operation for the data bit DQ[7:0] or any logical operation.

In one embodiment, during RDQS training, the RDQS pin can be used for DMI operations on data bits DQ[7:0]. Refer to Figure 3. As shown in FIG. 3, the memory controller 110 can use the DQ pins DQ0-DQ7 to write data bits to the DRAM 120 (hereinafter referred to as the WRITE pattern). At the same time, the memory controller 110 can use the RDQS pin to write parity check bits to the DRAM 120. Because the parity check bit can be regarded as a DMI operation on the written data of the DQ pins DQ0-DQ7, the write mode of the DQ pins DQ0-DQ7 in the first data beat (data beat) "0" is "0". "", "0", "0", "0", "0", "0", "0", "0" together with the parity check bit "1" of the RDQS pin in the first data beat "0" Write DRAM with "1", "1", "1", "1", "1", "1", "1", and "1". As shown in Figure 3, when the memory controller 110 reads back the written data from the DRAM 120, since the written data and the read data are reversed, the memory controller 110 knows the transmission The parity check bit to the DRAM 120 is "1". In addition, the write modes of DQ pins DQ0-DQ7 in the second data beat "1" are "1", "0", "0", "0", "0", "0", "0", " 0" together with the parity check bit "0" of the RDQS pin in the second data beat "1" with "1", "0", "0", "0", "0", "0", "0" "" and "0" are written into DRAM 120. Therefore, when the memory controller 110 reads back data from the DRAM 120, since the written data and the read data are the same, the memory controller 110 knows that the parity check bit transmitted to the DRAM 120 is " 0". It can be seen that the RDQS pin can be remapped to the DQ bus inversion function, so the write mode of the RDQS pin can be compared with the data bits that have been written Yuan DQ[7:0] and the read data bits DQ[7:0] are read back to realize RDQS pin training. In this embodiment, the write mode of the RDQS pin can be read back via the DQ pin or the DMI pin. It can also be said that the data transferred to the DRAM by writing the parity check pin can be read back through the data pin or the DMI pin. Please note that regardless of whether the RDQS pin is remapped to another function/operation, the DQ pin or the DMI pin can maintain the same function during the read operation.

In other embodiments, during the RDQS training process, the RDQS pin can be used for data replacement operations or logic operations of data bits DQ[7:0]. For example, the write mode "1010101011010101" of the RDQS pin in the data beat "0-15" can be used to replace the write mode "0111111110000000" of the DQ pin DQ0 in the data beat "0-15". Or, the write mode "1010101011010101" of the RDQS pin in the data beat "0-15" can be expressed as the predetermined logic operation (such as AND , OR, NOT, NAND, NOR, XOR or XNOR operation).

In this way, the memory controller 110 can write/read the parity check bit of the RDQS pin to/from the DRAM 120 to train the RDQS pin. In addition, the write mode of the RDQS pin can be complicated according to system requirements, and is not limited by the size of the FIFO file. In addition, the DRAM controller 110 can use the same training idea (ie, function/operation remapping) for the DQ/DMI pins.

The above processing steps (including the recommended steps) can be implemented by hardware and firmware. The firmware can be referred to as a combination of hardware devices and computer instructions and data. Computer instructions and data can be used as The read-only software resides on the hardware device or electronic system. Exemplary hardware may include analog, digital, and hybrid circuits called microcircuits, microchips, or silicon chips. Exemplary electronic systems may include System On Chip (SOC), System in Package (SiP), and Computer On Module (COM).

In a word, the present invention discloses a method of re-setting the ECC parity check function of the RDQS pin It is a method of performing parity check training by mapping data inversion function, logic operation function or data replacement function. Therefore, the data carried on the RDQS pin can be written into the DRAM along with the data bits DQ[7:0] so that the DRAM controller can read back the parity check bits from the DRAM to train the RDQS pin.

Those with ordinary knowledge in the field can easily see that while maintaining the teachings of the present invention, various modifications and changes can be made to the above-mentioned equipment and methods. Accordingly, the content disclosed above should be construed as being limited by the limits of the scope of the appended application. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (10)

A parity check training method for dynamic random access memory, the method comprising: enabling a link error checking and correction function in a write operation of the dynamic random access memory; and writing a The parity check function of the parity check pin is remapped to a data inversion function, a data replacement function, or a logic function, wherein the data transmitted to the dynamic random access memory through the write parity check pin is used To indicate a reverse operation, a logic operation or a replacement operation on the data of a data pin. The parity check training method for dynamic random access memory described in the first item of the scope of patent application, wherein the write parity check pin is a read data strobe pin. The parity check training method for dynamic random access memory as described in the scope of patent application 1, wherein the data transmitted to the dynamic random access memory through the write parity check pin is used The data indicating whether to invert the data pin is used to indicate whether to perform a predetermined logical operation on the data of the data pin, or to indicate whether to use the write parity check guide The data transmitted by the pin to the dynamic random access memory replaces the data of the data pin. The parity check training method for dynamic random access memory as described in item 1 of the scope of patent application, which further includes: using the data pin or a data mask reversal pin to verify the write The data transferred from the parity check pin to the dynamic random access memory is read back. The parity check training method for dynamic random access memory as described in item 3 of the scope of patent application, wherein the predetermined logical operation includes AND, OR, NOT, NAND, NOR, XOR, or Same Or operation. A memory system for parity check training of dynamic random access memory, comprising: the dynamic random access memory; and a memory controller for writing to the dynamic random access memory In the input operation, a link error checking and correction function is enabled, and a parity check function written to a parity check pin is remapped to a data inversion function, a data replacement function, or a logic function. The data transferred from the parity check pin to the dynamic random access memory is used to instruct to perform an inversion operation, a logic operation or a replacement operation on the data of a data pin. As described in item 6 of the scope of patent application, the memory system for parity check training of dynamic random access memory, wherein the write parity check pin is a read data strobe pin. The memory system for parity check training of dynamic random access memory as described in item 6 of the scope of patent application, wherein the write parity check pin is transmitted to all the dynamic random access memory The data is used to indicate whether to invert the data of the data pin, to indicate whether to perform a predetermined logical operation on the data of the data pin, or to indicate whether to use The data transferred from the parity check pin to the dynamic random access memory replaces the data of the data pin. Parity check for dynamic random access memory as described in item 6 of the scope of patent application The trained memory system, wherein the memory controller is also used to transmit data to the dynamic random memory through the write parity check pin through the data pin or a data mask inversion pin. Take the data in the memory and read it back. The memory system for parity check training of dynamic random access memory as described in item 8 of the scope of patent application, wherein the predetermined logical operation includes AND, OR, NOT, NAND, NOR, XOR , Or the same or operation.

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