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TWI774221B - 發光裝置及其製造方法 - Google Patents

發光裝置及其製造方法 Download PDF

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Publication number
TWI774221B
TWI774221B TW110103577A TW110103577A TWI774221B TW I774221 B TWI774221 B TW I774221B TW 110103577 A TW110103577 A TW 110103577A TW 110103577 A TW110103577 A TW 110103577A TW I774221 B TWI774221 B TW I774221B
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Taiwan
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conductive
layer
light
reflective layer
emitting device
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TW110103577A
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English (en)
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TW202231157A (zh
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賴隆寬
梁建欽
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隆達電子股份有限公司
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Priority to TW110103577A priority Critical patent/TWI774221B/zh
Priority to CN202110608573.2A priority patent/CN114824048A/zh
Priority to US17/572,649 priority patent/US20220246813A1/en
Publication of TW202231157A publication Critical patent/TW202231157A/zh
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Publication of TWI774221B publication Critical patent/TWI774221B/zh

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    • HELECTRICITY
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    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract

一種發光裝置包括基板、導電線路層、複數導電連接部及複數半導體發光源。導電線路層位於基板上。導電線路層包括複數導電結構,其中每一導電結構具有至少一焊墊,且兩相鄰的導電結構之間具有間隔。每一導電連接部設置於對應的每一焊墊上。每一半導體發光源對應每一間隔以跨設於兩相鄰的導電連接部上,進而電性連接至複數導電結構中兩相鄰者的焊墊。

Description

發光裝置及其製造方法
本發明涉及一種發光裝置及其製造方法,特別涉及一種半導體發光裝置及其製造方法。
發光二極體裝置已廣泛應用於多種產品上,且為配合許多產品皆以輕、薄、小為其發展趨勢,用於承載及導通發光二極體的印製線路板也需隨之更加薄型化。
傳統印製線路板在許多情況下,已不能滿足越來越尖端、苛刻的工藝及技術條件要求,且發光二極體焊接在印製線路板上,有時會發生脫落的風險。因此,需要對發光裝置的印製線路板進行改良。
有鑑於此,本發明之一目的在於提出一種可解決上述問題的發光裝置。發光裝置包括基板、導電線路層、複數導電連接部及複數半導體發光源。導電線路層位於基板上。導電線路層包括複數導電結構,其中每一導電結構具有至少一焊墊,且兩相鄰的導電結構之間具有間隔。每一導電連接部設置於對應的每一焊墊上。每一半導體發光源對應每一間隔以跨設於兩相鄰的導電連接部上,進而電性連接至導電結構中兩相鄰者的焊墊。
在本發明的一個或多個實施方式中,發光裝置更包括一反射層,反射層設置於導電線路層上並覆蓋導電結構,其中反射層包括複數開口分別對應間隔,導電結構中兩相鄰者的焊墊位於開口的一者中。
在本發明的一個或多個實施方式中,導電連接部接觸反射層的側面。
在本發明的一個或多個實施方式中,導電連接部與反射層的側面間隔分離。
在本發明的一個或多個實施方式中,導電連接部的材料包括銅、鎳、釟、銀、金、錫或其合金。
在本發明的一個或多個實施方式中,導電連接部是由銅漿料、銀漿料、金錫漿料或錫膏所製成。
在本發明的一個或多個實施方式中,半導體發光源為發光二極體晶片,其包括二電極分別位於兩相鄰的導電連接部上。
在本發明的一個或多個實施方式中,電極的水平位置不超過反射層的水平位置。
在本發明的一個或多個實施方式中,反射層為白色反射層或金屬反射層。
本發明的另一目的在於提供一種發光裝置的製造方法,包括以下步驟:提供一基板;形成一導電線路層於基板上,導電線路層包括複數導電結構,其中每一導電結構具有至少一焊墊,且兩相鄰的導電結構之間具有一間隔;形成複數導電連接部,其中每一導電連接部位於每一焊墊上;以及提供複數半導體發光源,每一半導體發光源對應每一間隔以跨設於兩相鄰的導電連接部,進而電性連接至導電結構中兩相鄰者的焊墊。
在本發明的一個或多個實施方式中,形成導電連接部包括以下步驟:提供反射層覆蓋導電結構,其中反射層包括複數開口分別對應間隔,每一開口用以曝露導電結構中兩相鄰者的焊墊;形成一晶種層,用以覆蓋反射層的頂面且沿著該些開口的側壁覆蓋所曝露的焊墊表面;於晶種層表面上形成光阻層,其中光阻層暴露焊墊上方的部分晶種層;以及經由晶種層形成導電連接部。
在本發明的一個或多個實施方式中,光阻層覆蓋位於反射層頂面上的晶種層之一部分。
在本發明的一個或多個實施方式中,其中光阻層覆蓋從反射層頂面延伸至開口的側壁上的晶種層之一部分。
在本發明的一個或多個實施方式中,形成該些導電連接部包括以下步驟:在晶種層上形成複數個增厚部;以及移除光阻層並部分移除晶種層,進而形成導電連接部。
在本發明的一個或多個實施方式中,形成該些導電連接部包括以下步驟:在晶種層上形成複數個增厚部;以及移除光阻層並至少移除反射層頂面上的晶種層之一部分,進而得到導電連接部。
在本發明的一個或多個實施方式中,晶種層的材料包括銅、鎳、釟、銀、金、錫或其合金。
在本發明的一個或多個實施方式中,形成導電連接部包括以下步驟:利用印刷製程或噴塗製程將導電漿料形成於每一焊墊上,以形成導電連接部。
在本發明的一個或多個實施方式中,形成該至少二導電連接部包括:提供反射層覆蓋導電結構,其中反射層包括複數開口分別對應間隔,每一開口用以曝露導電結構中兩相鄰者的焊墊;以及在每一開口中,利用印刷製程或噴塗製程將導電漿料形成於每一焊墊上,以形成導電連接部,其中導電連接部接觸反射層的側面。
在本發明的一個或多個實施方式中,印刷製程為鋼板印刷製程。
在本發明的一個或多個實施方式中,半導體發光源為發光二極體晶片,其包括二電極以覆晶方式電性連接兩相鄰的導電連接部上。
綜上所述,本發明提供一種具有特殊導電連接部的發光裝置及其製造方法,導電連接部可以使發光裝置的半導體發光源與焊墊之間的接合更穩固,進而改善發光裝置的導電特性及機械特性。
以上所述僅係用以闡述本發明所欲解決的問題、解決問題的技術手段、及其產生的功效等等,本發明之具體細節將在下文的實施方式及相關圖式中詳細介紹。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。除此之外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
請參考第1A圖,第1A圖繪示為本發明一個或多個實施方式中發光裝置100的立體示意圖,其中發光裝置100包括基板110、導電線路層120及多個半導體發光源170,其中導電線路層120位於基板110上,而半導體發光源170位於導電線路層120上。半導體發光源170電性連接於導電線路層120的電路結構,且半導體發光源170可例如為發光二極體光源,例如發光二極體晶片、甚至是尺寸更小的次毫米發光二極體晶片或微發光二極體晶片,但本發明並不以此為限。此外,如第1B圖所示,發光裝置100更可以包括透明封裝層T,透明封裝層T用於覆蓋導電線路層120及半導體發光源170,且透明封裝層T的折射率可例如介於1.49至1.6,其材料包括矽氧樹脂、環氧樹脂或壓克力,但本發明並不以此為限。以下將進一步詳細敘述本發明中關於發光裝置100的製造方法及其他結構上的細節。
請參考第2A圖,第2A圖繪示為第1圖中發光裝置100的製造方法流程圖。在本發明的一些實施方式中,第3A圖至第3H圖為根據第2A圖的製造方法200,於各個不同階段的截面圖,第3H圖可以表示為第1A圖中發光裝置100經A-A截面線繪製的截面圖。在本發明的一些實施方式中,發光裝置100的製造方法200始於步驟210,步驟210為提供基板。接著,進行步驟230,形成導電線路層於基板上,導電線路層包括複數導電結構,其中每一導電結構具有至少一焊墊,且兩相鄰的導電結構之間具有一間隔。接著,進行步驟250,形成複數導電連接部,其中每一導電連接部位於每一焊墊上。接著進行步驟270,提供複數半導體發光源,每一半導體發光源對應每一間隔以跨設於兩相鄰的導電連接部上,進而電性連接至導電結構中兩相鄰者的焊墊。
請參考第2A圖及第3A圖,第3A圖為根據步驟210之提供基板110。基板110可以是透光基板或不透光基板,基板110例如為剛性基板、可撓性基板、玻璃基板、藍寶石基板、矽基板、印刷電路板、金屬基板、陶瓷基板,但不限於此。此外,基板110的厚度例如介於0.1 mm至0.6 mm之間,但本發明並不以此為限。
請參考第2A圖及第3B圖,第3B圖為根據步驟230,形成導電線路層120於基板110上,導電線路層120包括複數導電結構121,其中每一導電結構121具有至少一焊墊123。具體而言,複數導電結構121至少在一方向上規則性地連續間隔排列,兩相鄰的導電結構121之間具有一間隔D(例如是兩相緊鄰的導電結構121之間具有一間隔D),且每一導電結構121具有設置於相反兩側的第一焊墊123a及第二焊墊123b。焊墊123具有小於或等於1.5μm的厚度。例如,焊墊123的厚度小於或等於1.4 μm。在本發明的一些實施方式中,導電線路層120的材料包括鈦銅合金、鉬銅合金或白金,可以利用濺鍍(sputtering)製程或蒸鍍(vapor deposition)製程在基板110上形成導電層,接著對導電層塗佈光阻和實施微影蝕刻製程,進而得到圖形化的導電線路層120及導電結構121。在本發明的另外一些實施方式中,可以重複執行形成導電層、光阻塗佈和蝕刻製程的步驟,進而得到多層的圖形化導電線路層120及導電結構121。此外,可以在多層的導電線路層120內形成絕緣薄膜,以便於進一步定義導電線路層120的電路結構,絕緣薄膜的材料包括二氧化矽(silicon dioxide)或氮化鋁(aluminium nitride),但本發明並不以此為限。
請參考第2A圖、第2B圖及第3C圖至第3G圖。第2B圖進一步揭露第2A圖中關於步驟250的詳細步驟251至步驟257。第3C圖至第3G圖為根據第2B圖的步驟251至步驟257,於各個不同階段的截面圖。在本發明的一個或多個實施方式中,如第3C圖所示,根據步驟251提供反射層130覆蓋導電結構121,其中反射層130包括複數開口131,其中這些開口131分別對應每一間隔D並位於間隔D上方,每一開口131暴露複數導電結構121中兩相鄰者 (例如是複數導電結構121中兩相緊鄰者)的焊墊123,亦即開口131暴露一導電結構121的第一焊墊123a及暴露與其相鄰的另一導電結構121的第二焊墊123b。
除此之外,反射層130的反射率高於85%。在一實施例中,反射層的厚度例如為介於20 μm至30 μm之間的厚度,例如反射層130的厚度為25 μm。在一實施例中,反射層130的材料包括金屬,例如可為銀(silver)、鋁(aluminium)、鉻(chromium)或其合金,或是金屬鏡面(例如銀鏡面、鋁鏡面、鉻鏡面等),但本發明並不以此為限。在一實施例中,反射層130為反射率高的白色材料,例如是由二氧化鈦(titanium dioxide)與矽膠(silicone) 所製成的白色反射層或是由二氧化鈦與環氧樹脂(epoxy)所製成的白色反射層,但本發明並不以此為限。在步驟251中,反射層130係形成於導電線路層120之上,可以利用非等向性蝕刻製程在反射層130中形成複數開口131,進而暴露出導電結構121上的焊墊123,但本發明並不以此為限。
在本發明的一個或多個實施方式中,如第3D圖所示,根據步驟253形成晶種層140a,晶種層140a覆蓋反射層130的頂面並沿著開口131的側壁131a覆蓋至所曝露的焊墊123表面,亦即晶種層140a會覆蓋在反射層130的頂面及側面上,且晶種層140a更覆蓋在焊墊123的表面之上,但本發明並不以此為限。晶種層140a的材料包括銅、鎳、釟、銀、金、錫或其合金,且晶種層140a可以是由化學氣相沉積法(chemical vapor deposition)所形成,例如是原子層沈積法(atomic layer deposition),但本發明並不以此為限。
在本發明的一個或多個實施方式中,如第3E圖所示,根據步驟255,於晶種層140a表面上形成光阻層150a,其中光阻層150a暴露位於焊墊123上方的部分晶種層140a,即光阻層150a至少在垂直方向上不會遮蔽焊墊123也不會在垂直方向上與焊墊123重疊。此外,光阻層150a覆蓋位於反射層130頂面之上的晶種層140a之一部分,其中光阻層150a是完全位於反射層130的頂面之上,但本發明並不以此為限。
在本發明的一個或多個實施方式中,如第3F圖及第3G圖所示,根據步驟257,經由晶種層140a形成複數個導電連接部160a,其中每一導電連接部160a位於導電結構121的每一個焊墊123之上。在第3F圖中,對晶種層140a實施濺鍍製程、電鍍(electroplating)製程或化學鍍(chemical plating)製程,其中晶種層140a沒有被光阻層150a覆蓋到的部分會增厚,進而形成具有複數個增厚部141a的晶種層140a,其中增厚部141a是一體成形於晶種層140a。接著,在第3G圖中,光阻層150a被合適的溶劑所移除,晶種層140a則被部分移除以形成導電連接部160a,例如是移除反射層130頂面上和側面上的晶種層140a之一部分,例如可以利用等向性蝕刻製程搭配適合的蝕刻液體以部分地移除具有複數個增厚部141a的晶種層140a,進而得到導電連接部160a,但本發明並不以此為限。在另外一些實施方式中,可以利用非等向性蝕刻製程部分地移除晶種層140a,進而形成導電連接部160a。由於導電連接部160a是對應於晶種層140a所產生,因此導電連接部160a的材料可以包括銅、鎳、釟、銀、金、錫或其合金(例如為錫合金、銀合金或銅合金),本發明並不以此為限。此外,導電連接部160a的厚度介於8 μm至15 μm之間,導電連接部160a會接觸反射層130的側面,且導電連接部160a位於開口131之中並與開口131的側壁131a接觸。
請參考第3H圖,其根據第2A圖中方法200的步驟270,提供複數半導體發光源170,每一半導體發光源170對應每一間隔D跨設於兩相鄰的導電連接部160a上,每一個半導體發光源170位於每一個間隔D的上方,使得每一半導體發光源170電性連接至複數個導電結構121中兩相鄰者的焊墊123,藉此完成發光裝置100a。
此外,半導體發光源170可例如為發光二極體光源,例如發光二極體晶片。發光二極體晶片包含氮化物半導體疊層與二電極171。氮化物半導體疊層可包含n型半導體層、活化層、p型半導體層,其中半導體層可例如由III-V族化合物半導體、II-VI族化合物半導體等半導體材料形成,例如GaN 、InGaN 、AlN 、InN、AlGaN、InGaAlN等氮化物系半導體材料。二電極171(正、負電極)位於氮化物半導體疊層同一側上,n電極位於n型半導體層上,而p電極位於p型半導體層上。如第3H圖所示,發光二極體晶片170的二電極171以覆晶方式連接於兩導電連接部160a上。具體而言,每一個發光二極體晶片170的二電極171是跨設在一導電結構121的第一焊墊123a上的導電連接部160a及與其相鄰的另一導電結構121的第二焊墊123b上的導電連接部160a。電極171的材質可例如為金屬材質,如金、銀、錫等。電極171固定於導電連接部160a的方式可採用如焊接或共晶製程,以穩固地將半導體發光源170固定在導電連接部160a上。由於導電連接部160a可以穩固地接合在半導體發光源170與焊墊123之間,因此導電連接部160a可以改善導電線路層120與半導體發光源170之間的導電特性及機械特性。
在本發明的一些實施方式中,第4A圖至第4H圖為根據第2A圖的製造方法200,於各個不同階段的截面圖,其中第4H圖為第1A圖中發光裝置100經A-A截面線繪製的截面圖。第4A圖至第4D圖與第3A圖至第3D圖大致相同,其根據的步驟相同,故在此不再重複贅述。請參考第4E圖,根據第2B圖中的步驟255,在晶種層140b表面上形成光阻層150b,其中光阻層150b暴露位於焊墊123上方的部分晶種層140b,亦即光阻層150b至少在垂直方向上不會遮蔽焊墊123和焊墊123上方的部分晶種層140b。此外,光阻層150b覆蓋位於反射層130上的晶種層140b之一部分,光阻層150b從反射層130的頂面延伸至反射層130的側面上。換句話說,光阻層150b從反射層130的頂面延伸至開口131的側壁131a上,且光阻層150b的一部份平行於開口131的側壁131a,光阻層150b覆蓋從反射層130的頂面延伸至開口131的側壁131a上的晶種層140b之一部分,但本發明並不以此為限。具體而言,晶種層140b的材料包括銅、鎳、釟、銀、金、錫或其合金,且晶種層140b是由化學氣相沉積法所製成,例如晶種層140b是由原子層沈積法製成,但本發明並不以此為限。
在本發明的一個或多個實施方式中,如第4F圖及第4G圖所示,根據步驟257,經由晶種層140b形成複數個導電連接部160b,其中每一導電連接部160b位於每一個導電結構121的焊墊123之上。在第4F圖中,對晶種層140b實施濺鍍製程、電鍍製程或化學鍍製程,晶種層140b沒有被光阻層150a覆蓋到的部分會增厚,進而形成具有複數個增厚部141b的晶種層140b,其中增厚部141b是一體成形於晶種層140b。由於光阻層150b覆蓋從反射層130頂面至開口131的側壁131a上的晶種層140b之一部分,因此晶種層140b的增厚部141b與反射層130之間會形成凹入部143b,但本發明並不以此為限。
在第4G圖中,光阻層150b被合適的溶劑所移除,晶種層140b則被部分移除以形成導電連接部160b,例如是移除在反射層130的頂面上和側面上的晶種層140b之一部分。在本發明的一些實施方式中,可以利用等向性蝕刻製程搭配適合的蝕刻液體以部分地移除晶種層140b,進而得到導電連接部160b,但本發明並不以此為限。在本發明的另一些實施方式中,利用非等向性蝕刻製程部分地移除晶種層140b,進而形成導電連接部160b。由第4G圖中可知,導電連接部160b會與反射層130間隔分離,其中導電連接部160b位於開口131之中並與開口131的側壁131a分離。由於導電連接部160b是經由晶種層140b所產生,因此導電連接部160b的材料可以包括銅、鎳、釟、銀、金、錫或其合金(例如為錫合金、銀合金或銅合金),但本發明並不以此為限。
請參考第4H圖,其根據第2A圖中方法200的步驟270,提供複數半導體發光源170,每一半導體發光源170對應每一間隔D跨設於兩相鄰的導電連接部160b上,使得每一半導體發光源170電性連接至複數個導電結構121中兩相鄰者的焊墊123,藉此完成發光裝置100b。具體而言,每一個半導體發光源170是跨設於一導電結構121的第一焊墊123a上的導電連接部160b及與其相鄰的另一導電結構121的第二焊墊123b上的導電連接部160b。此外,半導體發光源170包括二電極171以覆晶方式連接於兩導電連接部160b,可以對焊墊123、導電連接部160b及半導體發光源170執行焊接製程,以穩固地將半導體發光源170固定在導電連接部160b上。由於導電連接部160b可以穩固地接合於半導體發光源170與焊墊123之間,因此導電連接部160b可以改善導電線路層120與半導體發光源170之間的導電特性及機械特性。具體而言,導電連接部160b的寬度與電極171的寬度大致相同,因此使用焊爐焊接導電連接部160b及電極171時,半導體發光源170能精確地被對準在導電線路層120上的特定位置,縱然半導體發光源170的尺寸非常微小也可以被正確地排列在導電線路層120之上。
在本發明的一些實施方式中,第5A圖至第5E圖為根據第2A圖的製造方法200,於各個不同階段的截面圖,第5E圖為第1A圖中發光裝置100經A-A截面線繪製的截面圖。第5A圖至第5B圖與第3A圖至第3B圖大致相同,其根據的步驟也相同,故在此不再重複贅述。請參考第5C圖至5D圖,第5C圖至第5D圖根據製造方法200的步驟250,形成複數導電連接部160c,其中每一導電連接部160c位於每一焊墊123上。在第5C圖中,反射層130覆蓋導電結構121,其中反射層130包括複數開口131分別對應間隔D,每一開口131用以曝露導電結構121中兩相鄰者的焊墊123。請參考第5D圖,在每一開口131中,利用印刷製程或噴塗製程將導電漿料形成於每一焊墊123上,導電漿料例如是銅漿料、銀漿料、金錫漿料或錫膏。接著,對導電漿料執行熱烘乾製程,進而形成導電連接部160c。導電連接部160c接觸反射層130的側面,因此導電連接部160c接觸於開口131的側壁131a。在本發明的一些實施方式中,用於印刷導電漿料的製程為鋼板印刷製程,鋼板印刷製程可以十分精準地控制導電連接部160c的尺寸及形狀,以便於有效地接合焊墊123及電極171。
請參考第5E圖,其根據第2A圖的步驟270,提供複數半導體發光源170,每一半導體發光源170對應每一間隔D跨設於兩相鄰的導電連接部160c,使得每一半導體發光源170電性連接至複數個導電結構121中兩相鄰者的焊墊123,藉此得到發光裝置100c。具體而言,每一個半導體發光源170是跨設於一導電結構121的第一焊墊123a上的導電連接部160c及與其相鄰的另一導電結構121的第二焊墊123b上的導電連接部160c。此外,半導體發光源170的二電極171以覆晶方式連接於兩導電連接部160c上,可以對焊墊123、導電連接部160c及半導體發光源170執行焊接製程,以穩固地將半導體發光源170固定在導電連接部160c上。由於導電連接部160c可以穩固地接合在半導體發光源170與焊墊123之間,因此導電連接部160c可以改善導電線路層120與半導體發光源170之間的導電特性及機械特性。
以下段落分別介紹第1圖中發光裝置100的不同實施方式,某些細節由於已經被詳細地介紹在前面的段落,因此不再重複贅述。請參考第3H圖,發光裝置100a包括基板110、導電線路層120、複數導電連接部160a及複數半導體發光源170。導電線路層120位於基板110上,導電線路層120包括複數導電結構121,其中每一導電結構121具有至少一焊墊123,兩相鄰的導電結構121之間具有間隔D。此外,每一導電連接部160a設置於對應的每一焊墊123上,每一半導體發光源170對應每一間隔D以跨設於兩相鄰的導電連接部160a上,進而電性連接至複數個導電結構121中兩相鄰者的焊墊123。複數導電結構121至少在一方向上規則性地連續間隔排列,相鄰的導電結構121之間具有一間隔D,且每一導電結構121具有設置於相反兩側的第一焊墊123a及第二焊墊123b。
在本發明的一些實施方式中,發光裝置100a更包括反射層130,反射層130設置於導電線路層120上並覆蓋導電結構121,其中反射層130包括複數開口131,這些開口131分別對應並連通於每一間隔D上方,每一開口131暴露複數導電結構中兩相鄰者的焊墊,亦即開口131暴露一導電結構121的第一焊墊123a及暴露與其相鄰的另一導電結構121的第二焊墊123b。具體而言,每一個半導體發光源170是跨設於一導電結構121的第一焊墊123a上的導電連接部160a及與其相鄰的另一導電結構121的第二焊墊123b上的導電連接部160a。除此之外,導電連接部160a接觸反射層130的側面,因此導電連接部160a會接觸開口131的側壁131a,以便於固定半導體發光源170。反射層130可以為金屬反射層(涵蓋金屬鏡面反射層)或白色反射層,反射層130的製造方法及其他細節已詳細介紹在前面的段落中,在此不再重複贅述。
在本發明的一個或多個實施方式中,半導體發光源170的二電極171分別位於兩相鄰的導電連接部160a上,二電極171以覆晶方式電性連接兩相鄰的導電連接部160a,進而電性連接複數個導電結構121中兩相鄰者的焊墊123。除此之外,電極171的水平位置不超過反射層130的水平位置,電極171與導電連接部160a之間的接觸面低於反射層130的頂面,因此反射層130可以有效地調整半導體發光源170所發出的光線,但本發明並不以此為限。
請參考第4H圖,發光裝置100b包括基板110、導電線路層120、複數導電連接部160b及複數半導體發光源170。發光裝置100b大致上與發光裝置100a相同,其主要差異在於導電連接部160b與反射層130的側面間隔分離,亦即導電連接部160b會與開口131的側壁131a間隔分離。導電連接部160b的寬度與電極171的寬度大致相同,因此在利用焊爐焊接導電連接部160b及電極171時,半導體發光源170能被精確地對準在導電線路層120上的特定位置,縱然半導體發光源170的尺寸非常微小也可以被精確地排列在導電線路層120之上。導電連接部160b的製造方法及其他細節已經介紹在前面的段落,因此不再重複贅述。
請參考第5E圖,發光裝置100c包括基板110、導電線路層120、複數導電連接部160c及複數半導體發光源170。發光裝置100b大致上與發光裝置100c相同,其主要差異在於導電連接部160c。導電連接部160c是由導電漿料所製成,導電漿料可以是銅漿料、銀漿料、金錫漿料或錫膏,可以利用印刷或噴塗將導電漿料形成在焊墊123上,並對導電漿料執行熱烘乾製程以形成導電連接部160c。在本發明的一些實施方式中,用於印刷導電漿料的製程為鋼板印刷製程,鋼板印刷製程可以十分精準地控制導電連接部160c的尺寸及形狀,以便於有效地接合焊墊123及電極171。除此之外,導電連接部160c接觸反射層130的側面,導電連接部160c接觸開口131的側壁131a,但本發明並不以此為限。在一實施例中,導電連接部160c與反射層130間隔分離,亦即導電連接部160c與開口131的側壁131a間隔分離,以便於固定半導體發光源170。
綜上所述,本發明提供一種具有特殊導電連接部的發光裝置及其製造方法,導電連接部可以使發光裝置的半導體發光源與焊墊之間的接合更穩固,進而改善發光裝置的導電特性及機械特性。此外,本發明之發光裝置可應用在多種的發光裝置、多種顯示器或液晶顯示器的背光模組上。
以上所述僅係用以闡述本發明所欲解決的問題、解決問題的技術手段、及其產生的功效等等,本發明之具體細節將在下文的實施方式及相關圖式中詳細介紹。
100:發光裝置 110:基板 120:導電線路層 121:導電結構 123:焊墊 123a:第一焊墊 123b:第二焊墊 130:反射層 131:開口 131a:側壁 140a, 140b:晶種層 141a, 141b:增厚部 150a, 150b:光阻層 160a, 160b, 160c:導電連接部 170:半導體發光源 200:方法 210, 230, 250, 270:步驟 251, 253, 255, 257:步驟 T:透明封裝層 D:間隔
為達成上述的優點和特徵,將參考實施方式對上述簡要描述的原理進行更具體的闡釋,而具體實施方式被展現在附圖中。這些附圖僅例示性地描述本發明,因此不限制發明的範圍。通過附圖,將清楚解釋本發明的原理,且附加的特徵和細節將被完整描述,其中: 第1A圖根據本發明一個或多個實施方式繪示為本發明發光裝置的立體示意圖; 第1B圖根據本發明一個或多個實施方式繪示為本發明發光裝置的立體示意圖; 第2A圖及第2B圖繪示為第1A圖中發光裝置的製造方法流程圖; 第3A圖至第3H圖為根據第2A圖與第2B圖中的製造方法,於各個不同階段的截面圖,其中第3H圖為第1A圖中發光裝置經由A-A截面線所繪示之截面圖; 第4A圖至第4H圖為根據第2A圖與第2B圖中的製造方法,於各個不同階段的截面圖,其中第4H圖為第1A圖中發光裝置經由A-A截面線所繪示之截面圖;以及 第5A圖至第5E圖為根據第2A圖中的製造方法,於各個不同階段的截面圖,其中第5E圖為第1A圖中的發光裝置經由A-A截面線所繪示之截面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
200:方法 210, 230, 250, 270:步驟

Claims (20)

  1. 一種發光裝置,包括: 一基板; 一導電線路層,位於該基板上,該導電線路層包括複數導電結構,其中每一該導電結構具有至少一焊墊,且兩相鄰的該些導電結構之間具有一間隔; 複數導電連接部,每一該導電連接部設置於對應的每一該焊墊上;以及 複數半導體發光源,每一該半導體發光源對應每一該間隔以跨設於兩相鄰的該些導電連接部上,進而電性連接至該些導電結構中兩相鄰者的該焊墊。
  2. 如請求項1所述之發光裝置,更包括一反射層,設置於該導電線路層上並覆蓋該些導電結構,其中該反射層包括複數開口分別對應該些間隔,該兩相鄰者的該焊墊位於該些開口的一者中。
  3. 如請求項2所述之發光裝置,其中該些導電連接部接觸該反射層的側面。
  4. 如請求項2所述之發光裝置,其中該些導電連接部與該反射層的側面間隔分離。
  5. 如請求項1所述之發光裝置,其中該些導電連接部的材料包括銅、鎳、釟、銀、金、錫或其合金。
  6. 如請求項1所述之發光裝置,其中該些導電連接部是由銅漿料、銀漿料、金錫漿料或錫膏所製成。
  7. 如請求項2所述之發光裝置,其中每一該半導體發光源為發光二極體晶片,其包括二電極分別位於兩相鄰的該些導電連接部上。
  8. 如請求項7所述之發光裝置,其中該些電極的水平位置不超過該反射層的水平位置。
  9. 如請求項2所述之發光裝置,其中該反射層為白色反射層或金屬反射層。
  10. 一種發光裝置的製造方法,包括以下步驟: 提供一基板; 形成一導電線路層於該基板上,該導電線路層包括複數導電結構,其中每一該導電結構具有至少一焊墊,且兩相鄰的該些導電結構之間具有一間隔; 形成複數導電連接部,其中每一該導電連接部位於每一該焊墊上;以及 提供複數半導體發光源,每一該半導體發光源對應每一該間隔以跨設於兩相鄰的該些導電連接部,進而電性連接至該些導電結構中兩相鄰者的該焊墊。
  11. 如請求項10所述之製造方法,其中形成該些導電連接部包括以下步驟: 提供一反射層覆蓋該些導電結構,其中該反射層包括複數開口分別對應該些間隔,每一該開口用以曝露該兩相鄰者的該焊墊; 形成一晶種層,該晶種層覆蓋該反射層的頂面且沿著該些開口的側壁覆蓋所曝露的該焊墊表面; 於該晶種層表面上形成光阻層,其中該光阻層暴露該些焊墊上方的部分該晶種層上;以及 經由該晶種層形成該些導電連接部。
  12. 如請求項11所述之製造方法,其中該光阻層覆蓋位於該反射層頂面上的該晶種層之一部分。
  13. 如請求項11所述之製造方法,其中該光阻層覆蓋從該反射層頂面延伸至該些開口的側壁上的該晶種層之一部分。
  14. 如請求項11所述之製造方法,其中形成該些導電連接部包括以下步驟: 在該晶種層上形成複數個增厚部;以及 移除該光阻層並部分移除該晶種層,進而得到該些導電連接部。
  15. 如請求項11所述之製造方法,其中形成該些導電連接部包括以下步驟: 在該晶種層上形成複數個增厚部;以及 移除該光阻層並至少移除該反射層頂面上該晶種層之一部分,進而得到該些導電連接部。
  16. 如請求項11所述之製造方法,其中該晶種層的材料包括銅、鎳、釟、銀、金、錫或其合金。
  17. 如請求項10所述之製造方法,其中形成該些導電連接部包括以下步驟: 利用印刷製程或噴塗製程將導電漿料形成於每一該焊墊上,以形成該些導電連接部。
  18. 如請求項10所述之製造方法,其中形成該至少二導電連接部包括: 提供一反射層覆蓋該些導電結構,其中該反射層包括複數開口分別對應該些間隔,每一該開口用以曝露該些導電結構中兩相鄰者的該焊墊;以及 在每一該開口中,利用印刷製程或噴塗製程將導電漿料形成於每一該焊墊上,以形成該些導電連接部,其中該些導電連接部接觸該反射層的側面。
  19. 如請求項17或18所述之製造方法,其中該印刷製程為鋼板印刷製程。
  20. 如請求項10所述之製造方法,其中每一該半導體發光源為發光二極體晶片,其包括二電極以覆晶方式電性連接兩相鄰的該些導電連接部上。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201234682A (en) * 2010-12-22 2012-08-16 Microconnections Sas Circuit for a light emitting component and method of manufacturing the same
TW201517218A (zh) * 2013-10-29 2015-05-01 Stats Chippac Ltd 具有仿真銅圖案的嵌入式印刷電路板單元之均衡表面的半導體裝置和方法
TW201947728A (zh) * 2018-05-14 2019-12-16 聯發科技股份有限公司 半導體封裝結構
CN212113750U (zh) * 2020-04-22 2020-12-08 深圳大道半导体有限公司 半导体发光器件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101763972B1 (ko) * 2010-02-09 2017-08-01 니치아 카가쿠 고교 가부시키가이샤 발광 장치
JP2011253925A (ja) * 2010-06-02 2011-12-15 Toshiba Corp 発光装置の製造方法
US9159892B2 (en) * 2010-07-01 2015-10-13 Citizen Holdings Co., Ltd. LED light source device and manufacturing method for the same
US20240038819A1 (en) * 2020-10-23 2024-02-01 Toray Industries, Inc. Display device and method for manufacturing display device
KR20220085184A (ko) * 2020-12-15 2022-06-22 엘지디스플레이 주식회사 광원유닛 및 이를 포함하는 표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201234682A (en) * 2010-12-22 2012-08-16 Microconnections Sas Circuit for a light emitting component and method of manufacturing the same
TW201517218A (zh) * 2013-10-29 2015-05-01 Stats Chippac Ltd 具有仿真銅圖案的嵌入式印刷電路板單元之均衡表面的半導體裝置和方法
TW201947728A (zh) * 2018-05-14 2019-12-16 聯發科技股份有限公司 半導體封裝結構
CN212113750U (zh) * 2020-04-22 2020-12-08 深圳大道半导体有限公司 半导体发光器件

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