TWI600097B - Manufacturing method of package substrate for mounting semiconductor device, package substrate for mounting semiconductor device, and semiconductor package - Google Patents

Description

Method for manufacturing a semiconductor device mounting package substrate, package substrate for semiconductor device mounting, and semiconductor package

The present invention relates to a method of manufacturing a semiconductor device mounting package substrate, a semiconductor device mounting package substrate, and a semiconductor package, and more particularly to a semiconductor device mounting package including a flip chip connection terminal. A method of manufacturing a substrate, a package substrate for mounting a semiconductor element, and a semiconductor package, wherein the flip chip connection terminal is connected to a semiconductor element having bumps.

A flip-chip is used as a method of electrically connecting a connection terminal between a semiconductor element and a package substrate for mounting a semiconductor element (hereinafter, a case where the "semiconductor element mounting package substrate" is referred to as a "package substrate"). Flip chip connection. In this flip chip connection, since a good solder fillet is formed with the bump of the semiconductor element, most of the following methods are used: a pre-solder is formed on the flip-chip connection terminal of the package substrate, The amount of solder is ensured by both the pre-solder and the solder formed at the bump of the semiconductor element to be connected to the bump provided on the semiconductor element. On the other hand, with the miniaturization and high density of electronic components, it is necessary to arrange the connection terminals connected to the semiconductor elements with high density, and the miniaturization of the flip chip connection terminals is required.

If the flip chip connection terminal is made fine, the area of the connection terminal where the pre-solder is formed is reduced, so that it is formed on the flip chip connection end. The amount of pre-solder on the sub-solder is also reduced, and as a result, the solder fillet formed by the bumps of the semiconductor element is insufficiently formed, and the connection reliability is lowered. Further, if it is desired to form a pre-solder on the fine flip chip connection terminal and to make the pre-solder a sufficient amount for connection with the semiconductor element, as shown in FIG. 1, since the flip chip is used in a general method. The connection terminal 26 is formed in a convex shape with respect to the surface of the package substrate, so that the pre-solder 19 will flow to the side of the flip-chip connection terminal 26, and the pre-solder 19 will be generated between the adjacent flip-chip connection terminals 26. The problem of bridging. That is, even if solder is supplied to form the pre-solder 19 on the flip-chip connecting terminal 26, a considerable proportion of solder is consumed to cover the side of the flip-chip connecting terminal 26, which is required for forming a connection. The proportion of the pre-solder 19 of the solder fillet is reduced, and not only the adjacent flip chip connection terminals 26 but also bridging.

As a method for improving such a problem, a method of forming a wiring pattern in a region of a package substrate as a flip chip connection terminal to be relatively long to increase the amount of solder in this region is disclosed (Patent Document 1), or A method of partially widening the width of the wiring pattern in the region to be the flip-chip connecting terminal to increase the amount of pre-solder on the flip-chip connecting terminal (Patent Document 2).

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2002-329744

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2005-101137

According to the methods of Patent Documents 1 and 2 described above, the amount of pre-solder on the flip chip connection terminal to be connected to the semiconductor element can be secured to some extent. However, as shown in FIG. 1, the circuit pattern of the flip-chip connecting terminal 26 is formed as a circuit pattern which is formed in a convex shape from the surface of the package substrate 1 (hereinafter, also referred to as a "convex circuit"). The surface of the insulating layer 3 of the package substrate 1 is only the bottom surface of the convex circuit 32. Further, since the convex circuit 32 is generally formed by a method such as a semi-additive method accompanied by etching, a so-called undercut phenomenon occurs, and as a result, the width of the circuit pattern is The middle portion and the bottom portion (bottom side) in the thickness direction become narrower than at the top (surface side). Therefore, if the flip chip connection terminal 26 is made fine, the adhesion area between the flip chip connection terminal 26 and the insulating layer 3 under it and the width of the circuit pattern are reduced, and the adhesion is lowered, and the flip chip is flipped. Only a small amount of external force needs to be applied during the connection, and the flip chip connection terminal 26 may have a possibility of peeling.

The present invention has been made in view of the above problems, and an object of the invention is to provide a method for manufacturing a package substrate for mounting a semiconductor element, a package substrate for mounting a semiconductor element, and a semiconductor package, which can form a close contact force even if it is fine. Flip-chip connection terminals, and by providing flip-chip connection terminals, which ensure the amount of pre-solder necessary for flip-chip connection with bumps of semiconductor elements, and can correspond to high density And reliability is also excellent.

The present invention relates to the following invention.

1. A method of producing a package substrate for mounting a semiconductor element, comprising: preparing a plurality of metal foils in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order, and the multilayer metal foil a process of forming a core substrate by laminating a base metal foil side and a base material; and a method of rationally stripping the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil; a process of applying a first pattern plating film on the second carrier metal foil of the core substrate, and a process of forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating film. a process in which the laminate and the second carrier metal foil are separated from the core substrate by rational separation between the second carrier metal foil and the base metal foil of the multilayered metal foil; and by being stripped in the foregoing An etching resist is formed on the second carrier metal foil of the laminate, and etching is performed to expose the first pattern plating film from the insulating layer on the surface of the laminate to form a buried circuit, or Forming a three-dimensional circuit on the first pattern plating film on the surface of the laminated body, or forming a three-dimensional circuit on the insulating layer on the surface of the laminated body, or forming a concave shape on the first pattern plating film on the surface of the laminated body Process.

2. A method of producing a package substrate for mounting a semiconductor element, comprising: preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order, and the multilayer metal foil base a process of forming a core substrate by laminating a bottom metal foil side and a base material; and a method of rationally stripping the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil; a process of applying a first pattern plating film on the second carrier metal foil of the core substrate, and a process of forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating film. a process of separating the laminate between the second carrier metal foil of the multilayer metal foil and the base metal foil, and separating the laminate from the second carrier metal foil from the core substrate; and separating the laminate On the second carrier metal foil, a process of applying the second pattern plating film is performed; and an etching resist is formed on the portion of the second carrier metal foil other than the portion where the second pattern plating portion has been formed, and etching is performed by etching. The second carrier metal foil other than the portion where the second pattern plating has been performed and the portion where the etching resist has been formed are removed, and the first pattern plating film is exposed from the insulating layer on the surface of the laminate. a process of forming a buried circuit, or a process of forming a three-dimensional circuit on the first pattern plating film on the surface of the laminate, or a process of forming a three-dimensional circuit on the insulating layer on the surface of the laminate, or in the laminate A process of forming a recessed shape on the first pattern plating film on the surface.

3. The method of manufacturing a package substrate for mounting a semiconductor device according to the first aspect, wherein the second carrier metal foil including the first pattern plating film is formed by forming an insulator, a conductor circuit, and an interlayer connection. a process for laminating a process, and separating the laminate from the second carrier metal foil and the base metal foil of the multilayer metal foil, and separating the laminate from the second carrier metal foil from the core substrate Between processes There are: a process for forming an insulating layer and a conductor circuit of a desired number of layers.

(4) The method for producing a package substrate for mounting a semiconductor device according to any one of the first aspect, wherein the first pattern plating film is exposed from the insulating layer on the surface of the laminate to form a buried circuit. In the process of forming a flip-chip connection terminal on the first pattern plating film on the surface of the laminate, a pillar is formed or a portion of the long-side direction of the flip-chip connecting terminal is formed to be convex. The shape is a dummy terminal formed in a process of forming a three-dimensional circuit on the insulating layer on the surface of the laminate.

The packaged substrate for semiconductor element mounting, which is a package substrate for mounting a semiconductor element, which is manufactured by the method for manufacturing a package substrate for mounting a semiconductor element according to any one of the first to fourth aspects, Providing an insulating layer; a buried circuit is disposed such that a top surface thereof is exposed on a surface of the insulating layer; and a solder resist is disposed on the insulating layer and the buried circuit; wherein the buried The circuit is disposed in the opening of the solder resist and forms a flip chip connection terminal, and the flip chip connection terminal is covered with a pre-solder having a thickness of 3 μm or more.

6. The package substrate for mounting a semiconductor element according to the item 5, wherein a through hole is connected to a bottom surface of the buried circuit in which the flip chip connection terminal is formed.

7. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a convex shape.

The package substrate for mounting a semiconductor element according to any one of the items 5 to 7, wherein the flip chip connection terminal has a longitudinal direction The portion is formed with a concave shape.

The package substrate for mounting a semiconductor element according to any one of the items 5 to 8, wherein the tip end of the flip chip connection terminal is disposed in the opening of the solder resist.

The package substrate for mounting a semiconductor element according to any one of the items 5 to 9, wherein the embedded circuit is provided on both sides or one side in the longitudinal direction of the flip chip connection terminal. With an extension.

The package substrate for mounting a semiconductor element according to any one of the items 5 to 10, wherein a part of the flip chip connection terminal is expanded in a short side direction.

A semiconductor package in which a bump of a semiconductor element is mounted by flip chip bonding on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to any one of items 5 to 11.

According to the present invention, it is possible to provide a method of manufacturing a package substrate for mounting a semiconductor element, a package substrate for mounting a semiconductor element, and a semiconductor package, which are capable of forming a flip chip connection terminal which secures adhesion even when fine, and The flip-chip connection terminal is provided, which ensures the amount of pre-solder necessary for the flip-chip connection to the bump of the semiconductor element, and can be made higher in density and reliability.

Hereinafter, with reference to FIGS. 2 to 9, the semiconductor component of the present invention is used. An example of carrying a package substrate will be described.

A first example of the package substrate for mounting a semiconductor device of the present invention (hereinafter referred to as a "package substrate") is a package substrate 1 for mounting a semiconductor element as shown in FIG. 2, which is provided with an insulating layer. 3; the buried circuit 2 is disposed such that its top surface is exposed on the surface of the insulating layer 3; and the solder resist 4 is disposed on the insulating layer 3 and the buried circuit 2; wherein, the inner The buried circuit is disposed in the opening 31 of the solder resist 4 and forms a flip chip connection terminal 26 which is covered with a pre-solder 19 having a thickness of 3 μm or more. According to this configuration, the flip chip connection terminal 26 is formed by the buried circuit 2 whose top surface is exposed on the surface of the insulating layer 3. Therefore, since the side surface and the bottom surface of the flip chip connection terminal 26 are buried in the insulating layer 3, even if the buried circuit 2 forming the flip chip connection terminal 26 is line/space (line/space) The fine circuit pattern of the order of 20 μm/20 μm or less is also capable of forming a flip chip connection terminal 26 which ensures adhesion to the insulating layer 3. Since the embedded circuit 2 having the both sides in the longitudinal direction of the flip chip connection terminal 26 is provided, the buried circuit 2 is also fixed to the flip chip connection terminal 26 from both sides, so that the viewpoint of ensuring the adhesion is obtained. In view of the above, the present invention can be formed as a flip-chip connecting terminal 26 capable of securing a close contact with the insulating layer 3 even if it is finer than the convex-shaped circuit 32 shown in FIG. Therefore, as shown in FIG. 3, it is also possible to provide the buried circuit 2 which is extended only on one side in the longitudinal direction of the flip-chip connecting terminal 26, in which case the size of the flip-chip connecting terminal 26 can be changed. Since it is reduced, it is desirable to achieve higher density. also Further, as shown in FIG. 4, both of the one side in the longitudinal direction of the flip chip connection terminal 26 and the buried circuit 2 which are extended on both sides can be provided. In this way, the buried circuit 2 that is extended in the longitudinal direction of the flip-chip connecting terminal 26 can be provided on both sides in the longitudinal direction of the flip-chip connecting terminal 26 or on only one side. Increase the freedom of design. Further, since the flip chip connection terminal 26 is covered with the pre-solder 19 having a thickness of 3 μm or more, the amount of solder necessary for ensuring connection to the flip chip of the bump 25 of the semiconductor element 15 is obtained. Therefore, it is possible to provide a package substrate 1 for mounting a semiconductor element, which is excellent in density and reliability.

The insulating layer of the present invention refers to an insulating substrate, a core substrate, a thin film, an interlayer insulating layer, a build-up layer, or the like formed using an organic insulating material. As such an insulating layer, those generally used for packaging substrates can be used, and a prepreg in which an epoxy resin or a polyimide resin is impregnated into a glass cloth, an epoxy-based adhesive sheet or a polymer can be used. It is formed by heat and pressure of a bismuth imide-based adhesive sheet.

The buried circuit of the present invention refers to a circuit provided such that at least a portion of the bottom surface and a side surface thereof are buried in the insulating layer and at least the top surface thereof is exposed on the surface of the insulating layer. Such a buried circuit can be formed, for example, by a so-called transfer method or the like: that is, a metal foil is used as a power supply layer, and pattern plating is used thereon to form a specific circuit pattern, and then formed on the circuit pattern. After the insulating layer is buried in the insulating layer, the metal foil as the power supply layer is removed by etching or the like, and the surface of the circuit pattern buried in the pattern insulating layer is exposed from the insulating layer.

The solder resist of the present invention protects the surface of the package substrate such that the pre-solder does not adhere to a portion other than the buried circuit of the flip chip connection terminal. Further, by inserting an opening provided in the solder resist to define a portion of the buried circuit to be a flip chip connection terminal, the buried circuit in the opening forms a flip chip connection terminal. As the solder resist, a photosensitive solder resist is preferable from the viewpoint of accurately forming a minute opening having a length of 100 μm × a width of 100 μm or less for forming a flip chip connection terminal.

The flip chip connection terminal of the present invention is a connection terminal for mounting a semiconductor element on a package substrate by flip chip bonding. Moreover, the flip chip connection refers to a method of connecting the active device surface of the semiconductor element toward the package substrate, which is a mounting position on the package substrate after the semiconductor element is formed as a bump on the semiconductor element and then turned over on the package substrate. A method of connecting a bump of a semiconductor element to a flip chip connection terminal formed on a package substrate. The flip chip connection terminal of the present invention not only refers to a connection portion that actually abuts the bump of the semiconductor element, but also refers to a buried circuit and a bump of the semiconductor element and is exposed in the insulating layer in the opening of the solder resist. Part of the surface. On the surface of the flip-chip connection terminal, in order to prevent surface oxidation and ensure the wettability of the pre-solder, a nickel/gold plating film (formed with a nickel plating film and a gold plating film thereon), a nickel/palladium/gold plating film may be provided. A protective plating film (such as a nickel plating film, a palladium plating film on a nickel plating film, or a gold plating film on a palladium plating film).

The pre-solder of the present invention refers to a solder provided on a flip chip connection terminal for connection to a flip chip of a semiconductor element. Pre-solder can be used It is formed by a method of printing and reflowing a solder paste, and other known methods. As an example of the solder paste, solder particles such as Sn (tin)-Pb (lead), Sn (tin)-Ag (silver)-Cu (copper), and rosin and organic are used for electronic component mounting. Solvent mixer, etc. In the printing of the solder paste, a metal mask or a silk screen or the like can be used. The reflow can be performed using infrared reflow, hot air reflow, VPS (vapor phase soldering) reflow, which is generally used for electronic component mounting. The reflow conditions vary depending on the solder paste, but the following conditions can be given: for example, in the case of Sn-Pb (tin-lead), the peak temperature is about 240 ° C, and if it is Sn (tin) - Ag (silver) - For the Cu (copper) system, the peak temperature is about 260 °C.

The flip chip connection terminal of the package substrate of the present invention is covered with a pre-solder having a thickness of 3 μm or more. When the thickness of the pre-solder is less than 3 μm, the solder fillet may not be sufficiently formed between the flip chip connection terminal and the bump of the semiconductor element, and it is difficult to ensure connection reliability. On the other hand, if the thickness of the pre-solder exceeds 20 μm, there is a possibility that solder bridging occurs with the pre-solder on the adjacent flip chip connection terminals. Therefore, the thickness of the pre-solder is preferably 3 μm or more and 20 μm or less. Further, since the top surface of the flip chip connection terminal is generally elongated in plan view, the pre-solder formed by reflowing the solder paste or the like is formed into a slightly semi-cylindrical shape (fish plate shape) due to the surface tension of the solder. . Therefore, the thickness of the pre-solder is formed to be the thickest at the center in the longitudinal direction (longitudinal direction) and the short-side direction (width direction) of the flip-chip connecting terminal. Therefore, in the present invention, the thickness of the pre-solder is set to be in the center of the longitudinal direction (longitudinal direction) and the short-side direction (width direction) of the flip-chip connecting terminal, and the non-use is used. A contact step measuring machine determines the difference between the surface of the solder resist and the surface of the solder.

As a second example of the package substrate of the present invention, a via 18 is connected to the bottom surface of the buried circuit 2 including the flip chip connection terminal 26 as shown in FIG. Moreover, the pre-solder is omitted and displayed. In FIG. 5, a through hole 18 is formed in both the bottom surface of the flip chip connection terminal 26 and the bottom surface of the buried circuit 2 which is extended in the longitudinal direction from the flip chip connection terminal 26, but it is also possible only One of them is formed with a through hole 18. That is, in the second example, the through hole 18 is formed in the bottom surface of the flip chip connection terminal 26 buried in the insulating layer 3, and the buried circuit 2 is extended in the longitudinal direction from the flip chip connection terminal 26 The bottom surface, or the bottom surface of the two. By connecting the via hole 18 to the bottom surface in this manner, the flip chip connection terminal 26 or the buried circuit 2 extending from the flip chip connection terminal 26 in the longitudinal direction is fixed to the insulating layer 3 by the via hole 18, so that In the first example, the adhesion between the flip chip connection terminal 26 and the insulating layer 3 can be made stronger.

In the present invention, the through hole refers to a layer connecting the wiring layers provided on the package substrate as a plurality of layers, and for example, a hole for interlayer connection of the wiring layer can be formed by using a laser or the like, and then the hole is formed in the hole. Coating or the like is formed. Further, in order to obtain the connection surface of the bottom surface of the flip chip connection terminal or the bottom surface of the buried circuit from the flip chip connection terminal in the longitudinal direction, it is preferable to apply a film by a so-called filled via. To form a through hole.

A third example of the package substrate of the present invention is as shown in FIG. It is shown that a convex shape 27 is formed in a part of the longitudinal direction of the flip chip connection terminal 26. Further, the pre-solder 19 is omitted and displayed. The convex shape 27 can be formed, for example, by patterning a portion of the embedded circuit into the flip chip connection terminal 26 by forming a plating resist. Further, although not shown, for example, an etching resistor can be formed by forming a part of the side surface and a top surface thereof protruding from the surface of the insulating layer 3, and the protrusion can be maintained by a part of the buried buried circuit. The ground remains but the other portions are etched so as to be flush with the surface of the insulating layer 3. The height of the convex shape 27 is preferably about 3 μm to 8 μm, and the range in which the convex shape 27 is provided is preferably 50% to 100% of the dimension in the short-side direction (width direction) of the flip-chip connecting terminal 26 and is a flip chip connection. The dimension of the terminal 26 in the longitudinal direction (longitudinal direction) is about 10% to 70%. Since the convex shape 27 is formed in a part of the longitudinal direction of the flip-chip connecting terminal 26 as described above, the solder is deposited on the step portion (not shown) of the convex shape 27, so that the surface is flat compared to the case where the surface is flat. The amount of solder disposed on the flip chip connection terminal 26 can be increased. Further, since the convex shape 27 causes the solder of the other portions to concentrate, the solder is aggregated with the convex shape 27 as the center. Therefore, the protruding solder deposit can be formed in the longitudinal direction of the flip chip connection terminal 26. Selected location. Therefore, since the protruding portion on the flip chip connection terminal 26 can be provided corresponding to the bump position of the semiconductor element mounted on the flip chip connection terminal 26, the flip chip connection terminal 26 and the bump of the semiconductor element can be surely Make a connection.

A fourth example of the package substrate of the present invention is as shown in FIG. It is shown that a recessed shape 28 is formed in a part of the longitudinal direction of the flip chip connection terminal 26. Moreover, the pre-solder is omitted and displayed. Although not shown, the recessed shape 28 can be formed, for example, by forming a buried circuit whose top surface is exposed from the surface of the insulating layer 3, and then etching is formed by etching in such a manner that the top surface is exposed. In the buried circuit, a part of the top surface thereof is more recessed than the surface of the insulating layer 3, but the other portions remain as they are. The depth of the recessed shape 28 is preferably about 3 μm to 8 μm, and the range of the recessed shape 28 is preferably 50% to 100% of the dimension in the short-side direction (width direction) of the flip-chip connecting terminal 26 and is a flip-chip connecting terminal. The length of the long side direction (longitudinal direction) of 26 is about 10% to 70%. Since the molten solder is deposited in this portion by forming the recessed shape 28 in this manner, the amount of solder (not shown) disposed on the flip chip connection terminal 26 can be increased. That is, since the recessed shape 28 functions as a container for depositing solder, the solder is deposited in the recessed shape 28, so that solder can be formed on the flip chip connection terminal 26 and the solder is sufficient for forming the solder fillet. of.

As a fifth example of the package substrate of the present invention, as shown in FIG. 3, the front end of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Moreover, the pre-solder is omitted and displayed. When the circuit pattern is formed by etching a metal foil adhered to the surface of the insulating layer 3 as in the prior art, the circuit pattern is a convex circuit 32 (FIG. 1), and the flip chip connection terminal is formed. 26 only its bottom surface will adhere to the insulating layer 3. Moreover, since it is formed by etching, when the circuit pattern formed by the convex circuit 32 is viewed from a cross section, a circuit pattern is generated. On the surface side of the case, the width of the bottom side becomes a finer phenomenon, a so-called undercut. Therefore, if the size of the flip chip connection terminal 26 is made fine, the adhesion area between the bottom surface of the circuit pattern formed by the convex circuit 32 and the insulating layer 3 is reduced, so that the adhesion force with the insulating layer 3 is lowered. There is a possibility of peeling off by applying only a small amount of force when performing flip chip bonding. Therefore, in order to secure the adhesion between the insulating layer 3 and the flip-chip connecting terminal 26, the circuit pattern is fixed from the upper side by coating with the solder resist 4, and the flip-chip connecting terminal 26 is soldered from the solder. The opening 31 of the resist 4 is exposed, and the solder resist 4 is used to fix the both sides of the flip chip connection terminal 26 in the longitudinal direction. However, in this method, since the width of the opening 31 of the solder resist 4 is limited by the resolution limit of the solder resist 4, it is necessary to set the flip chip connection terminal 26 to be larger than the resolution of the solder resist 4. The limit is longer. Moreover, therefore, the wiring freedom of the circuit pattern is also limited. According to the fifth example of the package substrate 1 of the present invention, since the flip chip connection terminal 26 is formed by a buried circuit whose top surface is exposed from the surface of the insulating layer 3, it is possible to ensure the density even if it is fine. Focus on. Therefore, it is not necessary to cover the circuit pattern which is extended on both sides in the longitudinal direction of the flip-chip connecting terminal 26 from above by the solder resist 4, that is, the front end of the flip-chip connecting terminal 26 can be formed. Inside the opening 31 of the solder resist 4. Therefore, since the flip chip connection terminal 26 can be made finer without being limited by the resolution of the solder resist 4, the density can be increased, and the degree of freedom in designing the circuit pattern can be improved.

As a sixth example of the package substrate of the present invention, it can be mentioned in FIG. It is shown that the circuit 2 is embedded in both sides of the flip chip connection terminal 26 in the longitudinal direction or on one side. According to the sixth example of the package substrate of the present invention, as in the fifth example, since the flip chip connection terminal 26 can be made fine without being restricted by the resolution of the solder resist 4, it is possible to achieve further improvement. The density is increased, and the degree of freedom in circuit pattern design can be improved.

As a seventh example of the package substrate of the present invention, as shown in FIG. 8, a part of the flip chip connection terminal 26 is provided with a portion 33 which is expanded in the short-side direction (width direction). The front end of the flip chip connection terminal 26 may be formed in the opening 31 of the solder resist 4. Moreover, the pre-solder is omitted and displayed. Since the flip-chip connection terminal 26 is partially provided with the portion 33 which is expanded in the short-side direction (width direction), the adhesion area with the insulating layer 3 is enlarged, so that the flip-chip connection terminal 26 can be insulated. The adhesion of the layer 3 is further enhanced, and more of the amount of the pre-solder 19 can be ensured, and since the pre-solder 19 of the portion 33 which is expanded in the short-side direction (width direction) is caused by the surface tension A part of the solder is concentrated to form a solder deposit, so that the solder deposit can be stably formed at a selected position.

An example of the semiconductor package of the present invention is as shown in FIG. 9 and the semiconductor element 15 is mounted on the package substrate 1 of the first to seventh examples by flip chip bonding. The underfill 23 is preferably filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 including the flip chip connecting terminal 26 of the semiconductor element mounting package substrate 1. According to this, the bottom filler 23 can be made semi-conductive. The adhesion between the surface of the bump 25 of the body element 15 and the insulating layer 3 provided with the flip chip connection terminal 26 is further enhanced. Thus, a semiconductor package 24 can be provided which is high in density and excellent in reliability.

Hereinafter, an example of a method of manufacturing a package substrate of the present invention will be described with reference to FIGS. 10 to 18.

First, as shown in FIG. 10, a plurality of metal foils 9 in which the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12 are laminated in this order are prepared.

The first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) and is capable of being stripped between the second carrier metal foil 11 and the second carrier metal foil 11 . When the surface of the second carrier metal foil 11 can be protected, the material or thickness is not required. However, from the viewpoint of versatility and handleability, copper foil or aluminum foil is preferable as the material, and the thickness is preferably 1 to 35 μm. . Further, between the first carrier metal foil 10 and the second carrier metal foil 11, a release layer (not shown) for resolving the peel strength between the two is preferably provided as a release layer. In the case where the heating and pressurization when laminating with the insulating resin are performed plural times, the peel strength can be stabilized. In the case of the above-mentioned release layer, a metal oxide layer and an organic agent layer are disclosed in Japanese Laid-Open Patent Publication No. 2003-181970, which is disclosed in Japanese Laid-Open Patent Publication No. 2003-094553. A metal oxide containing Ni and W or a metal oxide of Ni and Mo disclosed in Japanese Laid-Open Patent Publication No. WO2006/013735. Further, when the first carrier metal foil 10 is made between it and the second carrier metal foil 11, In the case of physical peeling, it is preferable that the peeling layer is peeled off while being attached to the side of the first carrier metal foil 10, and does not remain on the surface of the second carrier metal foil 11.

The second carrier metal foil 11 is a seed layer (power supply layer) for supplying a current in order to perform the first pattern plating film 13 on the surface after the first carrier metal foil 10 is peeled off, and is used as the first carrier. The metal foils 10 and between them and the base metal foil 12 can be stripped rationally. As long as it can function as a power supply layer together with the base metal foil 12, the material or thickness is not particularly required. However, from the viewpoint of versatility and handleability, copper foil or aluminum foil is preferable as the material. Use 1~18μm. However, since the outer layer circuit 2 is formed as described later (FIG. 16 (12), (13), (14)), it is removed by etching, so that high precision is formed in order to minimize the variation in the etching amount. The fine circuit is preferably an extremely thin metal foil of 1 to 5 μm. Further, in order to stabilize the peel strength between the first carrier metal foil 10 and the base metal foil 12, it is preferable to provide a peeling layer (not shown) as described above. Further, since the peeling layer functions as a seed layer together with the second carrier metal foil 11 and the base metal foil 12, it is preferable to have conductivity. Further, when the peeling layer is peeled off from the second carrier metal foil 11 and the base metal foil 12, it is preferable to peel off in a state of being adhered to the base metal foil 12 side without remaining in the second carrier metal foil 11 On the surface.

The base metal foil 12 is disposed on the side opposite to the substrate 16 when the multilayer metal foil 9 and the substrate 16 are laminated to form the core substrate 17, and It is assumed that the crop can be peeled off rationally between the second carrier metal foil 11 and the second carrier metal foil 11 . The material and the thickness are not particularly required as long as they are adhered to the substrate 16 when laminated with the substrate 16. However, from the viewpoint of versatility and handleability, copper foil is preferable as the material. Or aluminum foil, as the thickness, is preferably 9 to 70 μm. Further, in order to stabilize the peel strength between the second carrier metal foil 11 and the second carrier metal foil 11, it is preferable to provide a peeling layer (not shown) as described above. Further, when the peeling layer is peeled off from the second carrier metal foil 11 and the base metal foil 12, it is preferable to peel off in a state of being adhered to the base metal foil 12 side, and it is not left in the second carrier metal foil. On the surface of 11 people.

The multilayered metal foil 9 is a multilayer metal foil 9 having three or more metal foils (for example, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12 as described above). Between at least two places (for example, as described above, between the first carrier metal foil 10 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the base metal foil 12) Stripper. When the base material 16 is laminated on the base metal foil 12 side of the multilayered metal foil 9 to form the core substrate 17, a foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10, even if it is adhered to the surface of the first carrier metal foil 10. When such a foreign matter adheres, the first carrier metal foil 10 is peeled off from the second carrier metal foil 11 to form a surface of the second carrier metal foil 11 which is not affected by foreign matter such as resin powder. A high quality metal foil surface can be ensured. Therefore, when the first pattern plating film 13 is used by using the second carrier metal foil 11 as a seed layer, it is possible to suppress the occurrence of defects. Seek improvement in yield.

Next, as shown in Fig. 11 (1), the base metal foil 12 side of the multilayered metal foil 9 is laminated with the substrate 16 to form the core substrate 17. The base material 16 is formed by laminating and integrating the multilayer metal foil 9 to form the core substrate 17. As the base material 16, a user who is generally the insulating layer 3 of the package substrate 1 for semiconductor element mounting can be used. Examples of such a substrate 16 include a glass epoxy, a glass polyimide, and the like. When the core substrate 9 is used as the support substrate when the package substrate 1 is manufactured, the core substrate 17 is used as a support substrate, and the improvement in workability and the prevention of damage during processing are required to improve the yield. Therefore, as the base material 16, it is preferable to provide a reinforcing material such as glass fiber. For example, a prepreg such as an epoxy glass cloth or a polyimide glass cloth may be superposed on the multilayer metal foil 9 and heat may be used. The pressure method is formed by heating and pressurizing and laminating. Since the multilayered metal foil 9 is laminated on both sides of the substrate 16 (the upper and lower sides of FIG. 11 (1)) and the subsequent processes are performed, two processes for manufacturing the package substrate 1 can be performed in one process. Therefore, the number of processes can be reduced. Moreover, since it is possible to form a laminated board which is symmetrically formed on both sides of the core substrate 17, it is possible to suppress the bending, and it is also possible to suppress damage due to workability or hooking in a manufacturing facility or the like.

Next, as shown in Fig. 11 (2), the first carrier metal foil 10 is peelably peeled off between the first carrier metal foil 10 of the multilayered metal foil 9 and the second carrier metal foil 11. On the surface of the first carrier metal foil 10, foreign matter such as a resin powder such as a prepreg which is a material of the substrate 16 may be deposited. Therefore, the first carrier metal foil is used When the circuit is formed in 10, there is a possibility that a defect such as an open circuit or a short circuit occurs in the circuit due to a foreign matter such as a resin powder adhering to the surface, and there is a possibility that the yield is lowered. However, since the first carrier metal foil 10 is peeled off and removed in this manner, the second carrier metal foil 11 to which foreign matter such as resin powder is not adhered can be used to form the circuit. Therefore, it is possible to suppress the occurrence of circuit defects and improve the quality. rate. Moreover, since the first carrier metal foil 10 can be peeled off rationally, the peeling strength can be easily performed by adjusting the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11. At this time, it is preferable that the peeling layer (not shown) between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayered metal foil 9 is transferred to the first carrier metal foil 10 side. As a result, the surface of the second carrier metal foil 11 is exposed on the side of the second carrier metal foil 11 after the first carrier metal foil 10 is peeled off, so that it is performed on the second carrier metal foil 11 in the subsequent process. The formation of the plating resist or the formation of the first pattern plating film 13 is not hindered by the peeling layer.

Here, it is preferable that the multilayer metal foil 9 has a peeling strength between the second carrier metal foil 11 and the base metal foil 12 that is stronger than the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11. Multi-layer metal foil 9. Thereby, when the first carrier metal foil 10 and the second carrier metal foil 11 are peeled off from the substrate, the second carrier metal foil 11 and the base metal foil 12 can be prevented from being simultaneously peeled off. The peeling strength is set to 2 N/m to 50 N/m between the first carrier metal foil 10 and the second carrier metal foil 11 at the initial stage before the heating and pressurization, and the second carrier metal foil 11 is used. Between 10N/m and 70N/m and the base metal foil 12, and The peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11 is smaller than the peel strength between the second carrier metal foil 11 and the base metal foil 12 by 5 N/m to 20 N/m. In the manufacturing process, it is not easy to be peeled off by the treatment, but on the other hand, it is easy to peel off, and it is possible to prevent the second carrier metal foil 11 from being peeled off while peeling off the first carrier metal foil 10, so that workability is good.

The adjustment of the peeling strength is, for example, as shown in JP-A-2003-181970, JP-A-2003-094553, and JP-A-2006-013735, by adjusting the base of the peeling layer. After the thickness of the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) and the plating solution composition or conditions for forming the metal oxide or alloy plating layer to be the release layer, it is possible to adjust the composition or conditions of the plating solution.

Next, as shown in FIG. 11 (3), the first pattern plating film 13 is formed on the second carrier metal foil 11 remaining on the core substrate 17. As described above, since the foreign material such as the resin powder such as the prepreg used in the lamination is not adhered to the surface of the second carrier metal foil 11 (between the first carrier metal foil 10), it is possible to Suppress circuit defects caused by this. The first pattern plating film 13 can be formed by plating on the second carrier metal foil 11 after forming a plating resist (not shown). As the plating resist, a photosensitive resist used in the manufacturing process of the package substrate 1 can be used. As the plating, a copper sulfate plating method used in the manufacturing process of the package substrate 1 can be used.

The multilayer metal foil 9 is preferably a surface of the second carrier metal foil 11 which is previously provided with irregularities having an average thickness (Ra) of 0.3 μm to 1.2 μm. The multilayer metal foil 9 of the first carrier metal foil 10 is laminated on the peeling layer (not shown). By the way, the surface of the second carrier metal foil 11 after the first carrier metal foil 10 and the peeling layer are peeled off together with the peeling layer are provided with irregularities having a predetermined average thickness (Ra) of 0.3 μm to 1.2 μm. Therefore, when the plating resist for the first pattern plating film 13 is formed on the surface of the second carrier metal foil 11 (between the first carrier metal foil 10), the adhesion and the resolution of the plating resist can be improved. It is advantageous for the formation of high-density circuits. Further, since the unevenness is first provided on the surface of the second carrier metal foil 11, after the first carrier metal foil 10 is peeled off, it is not necessary to roughen the surface of the second carrier metal foil 11, so that the process can be performed. The number is reduced.

The surface roughness of the unevenness provided on the surface of the second carrier metal foil 11 is improved from the viewpoint of improving the adhesion or resolution of the plating resist and ensuring the peelability after the first pattern plating film 13 The average roughness (Ra) is from 0.3 μm to 1.2 μm. When the average roughness (Ra) is less than 0.3 μm, there is a tendency that the adhesion of the coating resist is insufficient, and when the average roughness (Ra) is more than 1.2 μm, the coating resist It becomes difficult to follow the surface, and there is a tendency for insufficient adhesion. Further, when the line width/line distance of the coating resist is finer than 15 μm / 15 μm, the average roughness (Ra) is preferably 0.5 μm to 0.9 μm. Here, the average roughness (Ra) means an average thickness (Ra) prescribed by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like. Further, when the second carrier metal foil 11 is a copper foil, the composition of the copper plating when forming the copper foil as the second carrier metal foil 11 is adjusted (package) With additives or the like, or conditions, adjustment of the average roughness (Ra) is possible.

Next, as shown in FIG. 12 (4), the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating film 13 to form a laminate 22. As the insulating layer 3, a user who is generally the insulating layer 3 of the package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin, a polyimide resin, and the like. For example, an epoxy-based or polyimide-based adhesive sheet, an epoxy glass cloth, or a polyimide may be used. A prepreg such as a glass cloth is formed by laminating and integrating heat and pressure using a hot press method or the like. Here, the laminate 22 means that it is laminated on the second carrier metal foil 11 including the first pattern plating film 13 among the states in which the layers are integrated as described above. When the metal foil which becomes the conductor layer 20 is further superposed on the resin which becomes the insulating layer 3, and it fuses at the same time by heating and pressure-combining, it is also including this conductor layer 20. Further, in the case where the interlayer circuit 6 is formed by the conductor layer 20 as will be described later, and the interlayer connection 5 of the connection conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included.

Next, as shown in Figs. 12 (5), (6), interlayer connection holes 21 are formed, and the interlayer connection 5 and the inner layer circuit 6 can be formed. The interlayer connection 5 can be formed, for example, by forming a layer connection hole 21 by using a so-called conformal method, and then plating the interlayer connection hole 21 therein. In this plating film, a thin layer electroless copper plating film can be used as a base plating film, and then an electroless copper plating film, a copper plating, a hole-fill plating film, or the like can be used as a thick layer plating film. In order to thin the thickness of the etched conductor layer 20 to form a fine circuit, it is preferable to form a plating resist after coating the thin layer substrate, and Thick plating is performed by copper plating or hole filling plating. The inner layer circuit 6 can be formed, for example, by performing plating on the interlayer connection hole 21 and then removing unnecessary portions of the conductor layer 20 by etching.

Then, as shown in FIGS. 13(7), (8) and FIGS. 14(9) and (10), the insulating layer 3 and the conductor layer 20 are further formed on the inner layer circuit 6 and the interlayer connection 5, Similarly to the case of Figs. 12 (5) and (6), the inner layer circuit 6, the outer layer circuits 2, 7, and the interlayer connection 5 are formed so as to have a desired number of layers. Further, in the present invention, the inner layer circuit 6 and the outer layer circuits 2, 7 are collectively referred to as a conductor circuit.

Next, as shown in Fig. 15 (11), between the second carrier metal foil 11 of the multilayered metal foil 9 and the base metal foil 12, the laminate 22 and the second carrier metal foil 11 are collectively cropped from the core substrate 17 Rational stripping to separate. At this time, it is preferable that the peeling layer (not shown) between the second carrier metal foil 11 of the multilayered metal foil 9 and the base metal foil 12 is transferred to the base metal foil 12 side. Thereby, since the surface of the second carrier metal foil 11 is exposed on the side of the laminate 22 after the base metal foil 12 is peeled off, the etching of the second carrier metal foil 11 performed in the subsequent process is not peeled off. The layer is hindered.

Next, as shown in FIGS. 16(12) to (14), the etching resist 34 is formed on the second carrier metal foil 11 of the laminate 22 which is separated and separated, and the laminate 22 is etched. In the carrier metal foil 11, the first pattern plating film 13 is exposed on the surface of the insulating layer 3 to form the buried circuit 2, and then the three-dimensional circuit 27 is formed on the first pattern plating film 13 or the insulating layer 3. Also, as shown in FIGS. 17(12) to (14), by being separated The second pattern plating film 14 is formed on the second carrier metal foil 11 of the peeled laminate 22, and an etching resist is formed on the carrier metal foil other than the portion where the second pattern plating film is formed, and etching is performed. The portion of the pattern plating film 14 and the second carrier metal foil 11 other than the portion where the etching resist is formed are removed by etching, and the first pattern plating film 13 is exposed on the surface of the insulating layer 3 to form the buried circuit 2, A stereo circuit 27 is formed on the first pattern plating film 13 or on the insulating layer 3. Further, FIGS. 16(12) to (14) and FIGS. 17(12) to (14) show only the lower portion of the laminate 22 separated as shown in FIG. 15 (11). The flip chip connection terminal can be formed by the buried circuit 2 formed by exposing the first pattern plating film 13 from the insulating layer 3 by the processes of FIGS. 16(12) to (14) or FIGS. 17(12) to (14). The three-dimensional circuit 27 formed on the first pattern plating film on the surface of the laminate may form a bump or a pillar, and the three-dimensional circuit 27 formed on the insulating layer on the surface of the laminate may form a dummy terminal. Thereby, since the side surface of the outer layer circuit 2 is not eroded by the etching when the outer layer circuit 2 is formed, the undercut phenomenon can be formed, so that the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed by the present invention is buried in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides thereof are in close contact with the insulating layer 3, so that even It is a fine circuit that also ensures sufficient adhesion. Further, when an extremely thin copper foil having a thickness of 1 μm to 5 μm is used as the second carrier metal foil 11, since the second carrier metal foil 11 can be removed even with a small amount of etching, it is buried in the insulating layer 3 However, the surface of the outer layer circuit 2 is exposed from the insulating layer 3, and the surface of the outer layer circuit 2 is flat, and it can be ensured by setting it as a wire bonding terminal or a flip chip connection terminal. It is suitable for use as a connection terminal to a semiconductor element. Moreover, since the connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in a plan view, the connection terminal with the semiconductor element can be provided directly above or below the interlayer connection 5. Moreover, it can respond to miniaturization and high density. Further, by forming the three-dimensional circuit 27 at an arbitrary position, it is possible to form a structure of various conductor circuits such as bumps, pillars, and dummy terminals, and by changing the thickness of the second carrier metal foil 11 or the second pattern plating film 14, Since it can be formed in any height, it can respond to the connection form with various semiconductor elements (not shown) or other package board. For example, as shown in FIG. 18, a column body is provided on the first pattern plating film 13 of the package substrate 1 of the present invention to form a pillar, and the connection to the top substrate is performed, even if no cavity is provided. It also becomes a PoP (Stacked Package). Further, in the case where the bumps 25 on the side of the semiconductor element 35 shown in FIG. 18 are in a peripheral arrangement (the bumps 25 are arranged side by side around the semiconductor element 35), the semiconductor element 35 is formed when the flip chip is connected. When the semiconductor element 35 is bent to the side of the semiconductor element mounting package substrate 1, the central portion of the semiconductor element 35 is easily bent and deformed. However, since the dummy terminal is provided first (in FIG. 18, it is a three-dimensional formed on the insulating layer). The circuit 27) can support the lower surface of the semiconductor element 35, so that deformation can be suppressed. Further, if the dummy terminal is formed so as to be connected to the first pattern plating film and the interlayer connection 5, the heat from the semiconductor element 35 can be released. Therefore, reliability can be improved. Moreover, the dummy terminal means that it is electrically independent and does not function as an electronic circuit, although it is formed in FIG. 16 and FIG. The insulating layer may be connected to the first pattern plating or the interlayer connection 5 which is not electrically operated.

Next, the solder resist 4 or the protective plating film 8 can be formed as needed. As the protective plating film 8, a nickel plating film and a gold plating film which are generally used as a protective plating film for a connection terminal of a package substrate are preferable.

As described above, according to the manufacturing method of the package substrate of the present invention, it is possible to form a package substrate which is provided with a flat and fine buried circuit at a position overlapping the interlayer connection, and can be formed to be suitable for wire bonding or pouring. A package substrate on which a wafer is attached. Further, by forming a three-dimensional circuit at an arbitrary position, it is possible to form a package substrate including various metals such as bumps or pillars.

[Examples]

Next, an embodiment of another manufacturing method of the package substrate of the present invention will be described, but the present invention is not limited to the embodiment.

(Example 1)

First, as shown in FIG. 10, the multilayer metal foil 9 in which the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12 are laminated in this order is prepared. The first carrier metal foil 10 used a copper foil of 9 μm, the second carrier metal foil 11 used an ultra-thin copper foil of 3 μm, and the base metal foil 12 used a copper foil of 18 μm. A peeling layer (not shown) is provided on the surface of the base metal foil 12 (between the second carrier metal foil 11) so as to be capable of peeling off the crop. Further, on the surface of the second carrier metal foil 11 ( Concavities and convexities having an average thickness (Ra) of 0.7 μm are provided in advance between the first carrier metal foil 10 and the first carrier metal foil 10 . Further, on the unevenness, that is, a peeling layer (not shown) is provided between the first carrier metal foil 10 and the first carrier metal foil 10 so as to be capable of peeling off the crop. The peeling layer between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is made of Ni 30 g/L and Mo 3.0 g by use. A plating bath having a composition of /L and citric acid of 30 g/L was formed to form a metal oxide layer. Further, the adjustment of the peel strength is performed by adjusting the current to adjust the amount of the metal oxide forming the peeling layer. The peel strength at this time was 47 N/m between the base metal foil 12 and the second carrier metal foil 11, and 29 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. In addition, the rate of change in peel strength after heating and pressurization (after the core substrate 17 is formed by laminating the prepreg of the substrate 16) is about 10% higher than the initial stage.

The production of the multilayered metal foil 9 shown in Fig. 10 is specifically carried out as follows.

(1) As the base metal foil 12, an electrolytic copper foil having a thickness of 18 μm was used, and immersed in 30 g/L of sulfuric acid for 60 seconds, and after acid washing, it was washed with running water for 30 seconds.

(2) using the washed electrolytic copper foil as a cathode, and using a Ti (titanium) plate coated with ruthenium oxide as an anode, and as a plating bath containing Ni (nickel), Mo (molybdenum), and citric acid. In the bath of nickel sulfate 6 hydrate 30g / L, sodium molybdate 2 hydrate 3.0g / L, citrate 3 sodium dihydrate 30g / L, pH 6.0, liquid temperature 30 ° C, the gloss of electrolytic copper foil The surface was electrolytically treated at a current density of 20 A/dm ² for 5 seconds to form a peeling layer (not shown) containing a metal oxide made of nickel and molybdenum.

(3) On the surface after forming a peeling layer (not shown), Ti (Titanium) coated with yttria is applied in a bath of copper sulfate 5 hydrate 200 g/L, sulfuric acid 100 g/L, and liquid temperature 40 ° C. The electrode plate was used as an anode, and was plated at a current density of 4 A/dm ^{2 for} 200 seconds to form a metal layer of the second carrier metal foil 11 having a thickness of 3 μm.

(4) On the surface on which the metal layer to be the second carrier metal foil 11 is formed, the same bath as in the above (2) is subjected to electrolytic treatment at a current density of 10 A/dm ² for 10 seconds to form a nickel-containing molybdenum layer. A release layer of a metal oxide (not shown).

(5) On the surface on which the peeling layer 13 was formed, the same bath as in the above (3) was used, and plating was performed for 600 seconds at a current density of 4 A/dm ² to form a first carrier metal foil 10 having a thickness of 9 μm. The metal layer.

(6) Granular roughened particles are formed on the surface in contact with the substrate 16 by copper sulfate plating, and chromate treatment and decane coupling agent treatment are performed. Further, a chromate treatment is applied to the surface not in contact with the substrate 16.

Next, as shown in Fig. 11 (1), the base metal foil 12 side of the multilayered metal foil 9 is laminated with the substrate 16 to form the core substrate 17. As the base material 16, a prepreg of epoxy glass cloth is used, and the multilayer metal foil 9 is placed on the upper and lower sides of the prepreg, and then heated and pressurized by a hot press method to be integrated.

Next, as shown in Fig. 11 (2), the first carrier gold is placed between the first carrier metal foil 10 of the multilayer metal foil 9 and the second carrier metal foil 11. Is a foil 10 crop rational stripping.

Next, as shown in FIG. 11 (3), the first pattern plating film 13 is formed on the second carrier metal foil 11 remaining on the core substrate 17. The first pattern plating film 13 is formed by forming a photosensitive plating resist on the second carrier metal foil 11 and then plating it with copper sulfate.

Next, as shown in FIG. 12 (4), the insulating layer 3 and the copper foil (12 μm) as the conductor layer 20 are laminated on the second carrier metal foil 11 including the first pattern plating film 13 to form a laminate. twenty two. The insulating layer 3 is formed by laminating and integrating an epoxy-based adhesive sheet by hot pressing and pressurization.

Next, as shown in Figs. 12 (5) and (6), the interlayer connection 5 and the inner layer circuit 6 are formed. The interlayer connection 5 is formed by depositing a layer in the interlayer connection hole 21 after forming the interlayer connection hole 21 by a conformal method. In this plating film, after a thin layer electroless copper plating film is applied as a base plating film, a photosensitive plating resist is formed, and a thick layer plating is performed by copper sulfate plating. Thereafter, the unnecessary portion of the conductor layer 20 is removed by etching to form the inner layer circuit 6.

Next, as shown in FIGS. 13 (7), (8), and FIGS. 14 (9), (10), on the inner layer circuit 6 and the interlayer connection 5, the insulating layer 3 and the conductor layer 20 are further formed and formed. The inner layer circuit 6 and the outer layer circuits 2, 7 and the interlayer connection 5 form a laminate 22 having four conductor layers 20.

Next, as shown in FIG. 15 (11), between the second carrier metal foil 11 of the multilayer metal foil 9 and the base metal foil 12, the laminate 22 and the second layer are formed. The carrier metal foil 11 is separated from the core substrate 17 by crop rational separation.

Next, as shown in FIGS. 16(12) to (14), an etching resist 14 is formed on the second carrier metal foil 11 of the laminated body 22 which is separated and separated, and the second carrier of the laminated body 22 is etched again. In the metal foil 11, the first pattern plating film 13 is exposed on the surface of the insulating layer 3 to form the buried circuit 2, and the three-dimensional circuit 27 is formed on the first pattern plating film 13 or the insulating layer 3. Further, the buried circuit 2 formed by exposing the first pattern plating film 13 from the insulating layer 3 serves as a flip chip connection terminal, and the three-dimensional circuit 27 formed on the first pattern plating film on the surface of the laminate is formed as a bump. The three-dimensional circuit 27 on the insulating layer on the surface of the laminate is used as a dummy terminal.

Next, a photosensitive solder resist is formed, and then, as a protective plating film, an electroless nickel plating film and an electroless gold plating film are formed to form a package substrate.

(Example 2)

The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is 30 g/L by using Ni (nickel). The current in the case where the plating bath of Mo (molybdenum) 3.0 g/L and citric acid 30 g/L was formed to form a metal oxide layer was changed to adjust the amount of the metal oxide forming the peeling layer to be changed. The peel strength at this time was 23 N/m between the base metal foil 12 and the second carrier metal foil 11, and 18 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was produced in the same manner as in Example 1 except for the above.

(Example 3)

The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is achieved by using Ni (nickel) 30 g/L. The current in the case where the plating bath of Mo (molybdenum) 3.0 g/L and citric acid 30 g/L was formed to form a metal oxide layer was changed to adjust the amount of the metal oxide forming the peeling layer to change it. The peel strength at this time was 15 N/m between the base metal foil 12 and the second carrier metal foil 11, and 2 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was produced in the same manner as in Example 1 except for the above.

(Example 4)

The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is achieved by using Ni (nickel) 30 g/L. The current in the case where the plating bath of Mo (molybdenum) 3.0 g/L and citric acid 30 g/L was formed to form a metal oxide layer was changed to adjust the amount of the metal oxide forming the peeling layer to change it. The peel strength at this time was 68 N/m between the base metal foil 12 and the second carrier metal foil 11, and 48 N/m between the second carrier metal foil 11 and the first carrier metal foil 10.

Using the multilayer metal foil 9 prepared above, the process shown in FIGS. 16(12) to (14) of the first embodiment is not performed, and as shown in FIGS. 17(12) to (14), it is separated. Second carrier of the peeled laminate 22 The second pattern plating film 14 is formed on the metal foil 11, and the etching resist 34 is formed on the carrier metal foil other than the portion where the second pattern plating film is formed, and the etching is performed, and then the second pattern plating film 14 is formed and formed. The second carrier metal foil 11 other than the portion having the etching resist is removed by etching, and the first pattern plating film 13 is exposed on the surface of the insulating layer 3 to form the buried circuit 2, and is formed on the first pattern plating film 13 or A stereo circuit 27 is formed on the insulating layer 3. Further, the buried circuit 2 formed by exposing the first pattern plating film 13 from the insulating layer 3 serves as a flip chip connecting terminal, and the three-dimensional circuit 27 formed on the first pattern plating film on the surface of the laminated body is formed as a pillar. The three-dimensional circuit 27 on the insulating layer on the surface of the laminate is used as a dummy terminal. A package substrate was produced in the same manner as in Example 1 except for this process.

(Example 5)

The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is achieved by using Ni (nickel) 30 g/L. The current in the case where the plating bath of Mo (molybdenum) 3.0 g/L and citric acid 30 g/L was formed to form a metal oxide layer was changed to adjust the amount of the metal oxide forming the peeling layer to change it. The peel strength at this time was 43 N/m between the base metal foil 12 and the second carrier metal foil 11, and 28 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was produced in the same manner as in Example 4 except for the above.

(Example 6)

The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is achieved by using Ni (nickel) 30 g/L. The current in the case where the plating bath of Mo (molybdenum) 3.0 g/L and citric acid 30 g/L was formed to form a metal oxide layer was changed to adjust the amount of the metal oxide forming the peeling layer to change it. The peel strength at this time was 22 N/m between the base metal foil 12 and the second carrier metal foil 11, and 4 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was produced in the same manner as in Example 4 except for the above.

In Table 1, in the first to sixth embodiments, the final state of the outer layer circuit 2 formed in the insulating layer 3, the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11, and the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11 are shown. The peeling strength between the second carrier metal foil 11 and the base metal foil 12, and the presence or absence of peeling of the carrier metal foil during the treatment. In any of the first to sixth embodiments, the fine outer layer circuit 2 having a line width/line pitch of about 10 μm/10 μm can be formed (○ in the table 1 indicates that there is no undercut phenomenon). Further, as a result of observing the cross section, no undercut occurred in either of them. Further, as a result of the observation of the cross section, since the second carrier metal foil 11 is made of an ultra-thin copper foil of 3 μm, it is uniformly removed by a small amount of etching, and the unevenness of the surface of the outer layer circuit 2 is flat. Further, none of the examples 1 to 6 is between the first carrier metal foil 10 and the second carrier metal foil 11 or the second carrier metal foil 11 due to the treatment in the manufacturing process. The case of peeling off from the base metal foil 12 (○ in Table 1 indicates no peeling). Again, in the first When the carrier metal foil 10 and the second carrier metal foil 11 are peeled off, there is no peeling between the second carrier metal foil 11 and the base metal foil 12.

As shown in FIG. 18, the buried circuit 2 of the package substrate (FIG. 17 (14)) fabricated in Embodiment 4 is crimped to the bump 25 of the semiconductor element 35, and flip-chip is soldered (not shown). Wafer connection. The bumps 25 of the semiconductor element 35 are arranged in the periphery. However, since the surface of the lower surface of the semiconductor element 35 is supported by the three-dimensional circuit 27 as a dummy terminal, no deflection occurs in the semiconductor element 35.

The initial peel strength (N/m) before heating and pressurization (before the prepreg of the substrate 16 is laminated to form the core substrate 17) was measured, and a multilayer metal foil cut to a width of 10 mm was produced. For the sample, Tensilon RTM-100 (trade name "Tensilon", registered trademark of ORIENTEC Co., Ltd.) was used, and the first carrier metal foil was first oriented at room temperature (25 ° C) according to the 90 degree peeling method of JIS Z 0237. The peeling was measured at a speed of 300 mm per minute in a 90-degree direction, and then the second carrier metal foil was peeled off at a speed of 300 mm per minute in a direction of 90 degrees and measured. Moreover, after heating and pressurization (will become the prepreg of the substrate 16 The peel strength of the core substrate 17 after lamination was also measured in the same manner as the initial peel strength, and the rate of change with respect to the initial stage was taken out. In addition, when the multilayer metal foil 9 and the epoxy glass cloth prepreg which is the base material 16 are laminated to form the core substrate 17, the heating and pressurizing conditions are performed by a vacuum pressing method and the pressure is 3 MPa, and the temperature is 175 ° C. Hold time 1.5 hr (hours).

Hereinafter, the present invention will be specifically described by way of examples, but the invention is not limited thereto.

(Example 7)

A package substrate including a flip chip terminal having a buried circuit was produced in the same manner as in the first embodiment. Here, an opening is provided in the solder resist formed on the package substrate, and a buried circuit having a line width/line pitch of 20 μm/20 μm (pitch 40 μm) and being a flip chip connection terminal is disposed in the opening. . The dimension of the flip chip connection terminal defined by the opening of the solder resist in the longitudinal direction (the length of the flip chip connection terminal) is about 100 μm.

Next, a pre-solder is formed by printing a solder paste on a buried circuit that becomes a flip chip connection terminal and reflowing it. For the solder paste for pre-solder, the Sn (tin)-Ag (silver)-Cu (copper)-based ECOSOLDER M705 (manufactured by Senju Metal Industry Co., Ltd., trade name ECOSOLDER is registered) is used for reflow soldering. In other words, it was carried out using an infrared reflow device at a peak temperature of 260 °C.

Next, cutting processing is performed to the package size. This cut-off seal As shown in FIG. 2, the substrate is provided with an insulating layer 3; a buried circuit 2 is provided so that the top surface is exposed on the surface of the insulating layer 3; and the solder resist 4 is disposed on the insulating layer. 3 and on the buried circuit 2; the buried circuit 2 disposed in the opening 31 of the solder resist 4 forms a flip chip connection terminal 26. Further, the thickness of the pre-solder 19 covering the flip-chip connecting terminal 26 is 3 to 5 μm. Here, the thickness of the solder is HISOMET (manufactured by UNION Optics Co., Ltd., trade name, HISOMET is a registered trademark) which is a non-contact step measuring machine, and the solder resist and the flip chip connection terminal are measured before and after the pre-solder 19 is formed. The step difference between 26 was measured.

As shown in FIG. 9, after the package substrate 1 is manufactured, the semiconductor element 15 is mounted by flip chip bonding. The flip chip connection is such that the flip chip connection terminal 26 on the package substrate 1 and the bump 25 of the semiconductor element 15 (formed on the copper pillar with Sn (tin) - 3.0 mass % Ag (silver) - 0.5 mass After the %Cu (copper) solder was placed at a position with a pitch of 40 μm and a height of 25 μm, the flip chip bonding was performed using an ultrasonic flip chip bonding machine SH-50MP (ALTECS Co., Ltd., product name). The pressing conditions of the flip chip connection were maintained at 230 ° C while ultrasonic waves were used in combination, and held for 4 seconds in a state where 50 μg of the bumps were pressed. Thereafter, the underfill material 23 is filled between the surface of the bump 25 formed of the semiconductor element 15 and the insulating layer 3 including the flip chip connection terminal 26 of the package substrate 1, thereby obtaining the semiconductor package 24.

(Example 8)

The thickness of the pre-solder covering the flip chip connection terminals is 7 to 10 μm. Otherwise, the tenth circuit board and the semiconductor package were obtained in the same manner as in the seventh embodiment.

(Example 9)

The thickness of the pre-solder covering the flip chip connection terminals is 17 to 20 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in the seventh embodiment.

[Comparative Example 1]

The thickness of the pre-solder covering the flip chip connection terminals is 1 to 2 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in the seventh embodiment.

[Reference Example 1]

The thickness of the pre-solder covering the flip chip connection terminals is 25 to 28 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in the seventh embodiment.

(Embodiment 10)

In the same manner as in the seventh embodiment, a pre-solder was formed on the buried circuit which was a flip chip connection terminal. Here, as shown in FIG. 5, the solder resist 4 is provided with an opening 31 in which the buried circuit 2 serving as the flip chip connection terminal 26 is disposed. Also, the via 18 is connected to the flip chip including The bottom surface of the buried circuit 2 is connected to the terminal 26. Thereafter, in the same manner as in the seventh embodiment, a package substrate and a semiconductor package were formed.

(Example 11)

In the same manner as in the fourth embodiment, as shown in Figs. 17 (12) to (14), the second pattern plating film 14 is formed on the second carrier metal foil 11, and the flip chip connection terminal of the buried circuit is formed. A portion of the portion forms a convex shape (a three-dimensional circuit). A solder resist is formed and a nickel/gold plating film (a nickel plating film and a gold plating film thereon) as a protective plating film is formed. Here, as shown in FIG. 6, the solder resist 4 is provided with an opening 31 in which the buried circuit 2 serving as the flip chip connection terminal 26 is disposed. Further, a convex shape 27 is formed in a part of the longitudinal direction of the flip chip connection terminal 26, and the height of the convex shape 27 is about 5 μm. The range of the convex shape 27 is 100% of the dimension of the flip chip connection terminal 26 in the short-side direction and is about 30% of the dimension of the flip chip connection terminal 26 in the longitudinal direction. After that, a package substrate and a semiconductor package were formed in the same manner as in the seventh embodiment.

(Embodiment 12)

In the same manner as in the first embodiment, a package substrate including a flip chip terminal having a buried circuit was fabricated. Thereafter, an etching resist is formed, and the buried circuit is exposed on the top surface, and a part of the top surface thereof is more recessed than the surface of the insulating layer, and the other portions are etched as they are, thereby forming a depressed shape. Thereafter, a solder resist is formed, and a nickel/gold plating film (a nickel plating film and a gold plating film thereon) as a protective plating film is formed. Here, as shown in FIG. An opening 31 is provided in the solder resist 4, and a buried circuit 2 serving as a flip chip connection terminal 26 is disposed in the opening 31. Further, a recessed shape 28 is formed in a part of the longitudinal direction of the flip chip connection terminal 26, and the depth of the recessed shape 28 is about 5 μm. The range of the recessed shape 28 is 100% of the dimension in the short-side direction of the flip-chip connecting terminal 26 and about 30% of the dimension in the longitudinal direction of the flip-chip connecting terminal 26. After that, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment.

(Example 13)

In the same manner as in the seventh embodiment, a package substrate including a flip chip terminal having a buried circuit was fabricated. Here, as shown in FIG. 3, the solder resist 4 is provided with an opening 31 in which the buried circuit 2 serving as the flip chip connection terminal 26 is disposed. Further, the front end of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. After that, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment.

(Example 14)

In the same manner as in the seventh embodiment, a package substrate including a flip chip terminal having a buried circuit was fabricated. Here, as shown in FIG. 4, the solder resist 4 is provided with an opening 31 in which the buried circuit 2 serving as the flip chip connection terminal 26 is disposed. Further, the buried circuit 2 is provided on both sides in the longitudinal direction of the flip chip connection terminal 26 or on one side. After that, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment.

(Example 15)

In the same manner as in the seventh embodiment, a package substrate including a flip chip terminal having a buried circuit was fabricated. Here, as shown in FIG. 8, the solder resist 4 is provided with an opening 31 in which the buried circuit 2 serving as the flip chip connection terminal 26 is disposed. Further, a part of the flip chip connection terminal 26 in the longitudinal direction is formed with a portion 33 that is expanded in the short-side direction (width direction). That is, the flip chip connection terminal 26 is formed with a portion 33 which is partially expanded in the short-side direction (width direction). After that, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment.

[Comparative Example 2]

In the same manner as in the seventh embodiment, a package substrate including a flip chip terminal having a buried circuit was fabricated. Here, as shown in FIG. 16 (14), on the opposite side of the surface of the buried circuit 2 on which the flip chip connection terminal is disposed, the same configuration as that shown in FIG. 1 is provided and the convex circuit is disposed. The resulting circuit pattern (outer layer circuit 7).

Next, a solder resist is formed on the circuit pattern (outer layer circuit 7) formed by the bump circuit, and a nickel/gold plating film (a nickel plating film and a gold plating film thereon) as a protective plating film is formed. Here, an opening is provided in the solder resist, and a circuit pattern formed by a bump circuit having a line width/line pitch of 20 μm/20 μm (40 μm pitch) and being a flip chip connection terminal is disposed in the opening.

Then, by being a flip-chip connection terminal and by a convex circuit On the circuit pattern (outer layer circuit 7), the solder paste is printed and reflowed to form a pre-solder. For the solder paste for pre-solder, the Sn (tin)-Ag (silver)-Cu (copper)-based ECOSOLDER M705 (manufactured by Senju Metal Industry Co., Ltd., trade name ECOSOLDER is registered) is used for reflow soldering. In other words, it was carried out using an infrared reflow device at a peak temperature of 260 °C.

Next, cutting processing is performed to the package size. The package substrate is as shown in FIG. 1 and is provided with: an insulating layer 3; a circuit pattern disposed on the surface of the insulating layer 3 and formed by the convex circuit 32; and the solder resist 4 being disposed in the insulating layer On the layer 3 and on the circuit pattern formed by the bump circuit 32, the circuit pattern formed in the opening 31 of the solder resist 4 and formed by the bump circuit 32 forms the flip chip connection terminal 26. Further, the thickness of the pre-solder 19 covering the flip-chip connecting terminal 26 is 3 to 5 μm. Thereafter, a semiconductor package was obtained in the same manner as in the seventh embodiment.

[Comparative Example 3]

The thickness of the pre-solder covering the flip chip connection terminals is 17 to 20 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Comparative Example 3.

In Table 2, the results of examining the cross-sectional shape of the flip-chip connecting terminal, the thickness of the solder, and the presence or absence of solder bridging were shown for the package substrates of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3. Moreover, the results of investigating the state of the solder fillet were shown for the semiconductor packages of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3.

As a result of observing the cross-sectional shape of the flip-chip connecting terminal, in the seventh to fifteenth embodiments, the side surface and the bottom surface of the flip-chip connecting terminal were buried in the insulating layer to be closely adhered, and the cross-sectional shape was slightly rectangular and was not found. The end is the phenomenon. On the other hand, in Comparative Examples 2 and 3, since the bump circuit was formed, only the bottom surface of the flip chip connection terminal was in close contact with the insulating layer. Further, an undercut phenomenon was observed in the cross-sectional shape of the flip chip connection terminal, and the width at the narrowest portion was less than half the width with respect to the top width (the width on the surface side).

As a result of measurement of the thickness of the solder, in Examples 7 to 15, the thickness of the solder was 3 to 20 μm, and as a result of the solder bridging, no solder bridging occurred in the range of the thickness of the solder. On the other hand, in Comparative Example 1, the solder thickness was as thin as 1 to 2 μm, and solder bridging did not occur. in In Reference Example 1, the thickness of the solder was as thick as 25 to 28 μm, and solder bridging occurred between adjacent flip chip connection terminals. In Comparative Example 3, the thickness of the solder was 17 to 20 μm, but since it was a convex circuit, the solder was wound around the side surface of the flip chip connection terminal to cause solder bridging.

As a result of the confirmation of the solder fillet of the semiconductor package, in Examples 7 to 15, Reference Example 1 and Comparative Example 3, the solder fillet formed between the bumps of the semiconductor element and the bump of the solder in the semiconductor element And both of the flip chip connection terminals of the package substrate are wet spread and in good condition. On the other hand, in Comparative Examples 1 and 2, in the bump of the semiconductor element or the part of the flip-chip connection terminal of the package substrate, the solder spread was insufficient, and the formation of the solder fillet was not sufficient.

The cross-sectional shape of the flip chip connection terminal was observed by making a microsection and observing the cross section with a metallographic microscope. The thickness of the solder on the flip chip connection terminal is determined by using HISOMET (manufactured by UNION Optics Co., Ltd., trade name. HISOMET registered trademark) which is a non-contact step measuring machine, before and after the formation of the pre-solder. Determined by the step difference between the terminals connected to the flip chip. The presence or absence of solder bridging and the state of the solder fillet were confirmed by a 10-fold observation using a solid microscope.

1‧‧‧Package substrate or package substrate for semiconductor device mounting or 10th circuit substrate

2‧‧‧Outer circuit or buried circuit

3‧‧‧Insulation

4‧‧‧ solder resist

5‧‧‧Interlayer connection

6‧‧‧ Inner layer circuit

7‧‧‧Outer circuit

8‧‧‧Protective coating

9‧‧‧Multilayer metal foil

10‧‧‧1st carrier metal foil

11‧‧‧2nd carrier metal foil

12‧‧‧Base metal foil

13‧‧‧1st pattern coating

14‧‧‧2nd pattern coating

15‧‧‧Semiconductor components

16‧‧‧Substrate

17‧‧‧ core substrate

18‧‧‧through hole

19‧‧‧Pre-solder

20‧‧‧Conductor layer

21‧‧‧Interlayer connection holes

22‧‧‧Layered

23‧‧‧Bottom filler

24‧‧‧Semiconductor package

25‧‧‧ (on the side of the semiconductor component) bump

26‧‧‧Flip chip connection terminal

27‧‧‧ convex shape or stereo circuit

28‧‧‧ concave shape

29‧‧‧ Sealing material

31‧‧‧ (solder resist) opening

32‧‧‧ convex circuit

33‧‧‧The part that was expanded in the short-side direction

34‧‧‧etching resist

35‧‧‧Semiconductor components

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a (a) plan view, (b) A-A' sectional view, and (c) B-B' sectional view of a vicinity of a flip chip connection terminal of a conventional package substrate.

2 is a view of the flip chip connection terminal of the package substrate of the present invention (a) plan view, (b) A-A' sectional view, and (c) B-B' sectional view.

Figure 3 is a (a) plan view and (b) A-A' cross-sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Fig. 4 is a (a) plan view, (b) A-A' sectional view, and (c) B-B' sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Figure 5 is a (a) plan view and (b) A-A' cross-sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Figure 6 is a (a) plan view and (b) A-A' cross-sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Figure 7 is a (a) plan view and (b) A-A' cross-sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Fig. 8 is a (a) plan view, (b) A-A' sectional view, and (c) B-B' sectional view of the vicinity of the flip chip connection terminal of the package substrate of the present invention.

Figure 9 is a cross-sectional view of the vicinity of a packaged flip chip connection terminal of the present invention.

Figure 10 is a cross-sectional view of a multilayer metal foil used in the present invention.

Fig. 11 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 12 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 13 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 14 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 15 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 16 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 17 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.

Fig. 18 is a cross-sectional view showing a semiconductor package produced by using the method of manufacturing a package substrate of the present invention.

2‧‧‧Outer circuit or buried circuit

3‧‧‧Insulation

4‧‧‧ solder resist

8‧‧‧Protective coating

19‧‧‧Pre-solder

26‧‧‧Flip chip connection terminal

31‧‧‧ (solder resist) opening

Claims (12)

A method for producing a package substrate for mounting a semiconductor element, comprising: preparing a first carrier metal foil; and providing a second carrier metal foil having a rough surface having an average thickness of 0.3 to 1.2 μm on the surface and a second carrier metal foil; a process of forming a core substrate by laminating a plurality of metal foils of the base metal foil of the back surface in this order, and laminating the base metal foil side of the multilayer metal foil with the substrate; the first carrier metal foil of the multilayer metal foil and a process for rationally stripping the first carrier metal foil between the second carrier metal foils; a process of applying the first pattern plating film on the surface of the second carrier metal foil of the core substrate; and a step of including the first pattern plating film a process of forming a laminate by forming an insulating layer, a conductor circuit and a layer connection on the surface of the carrier metal foil; and forming the laminate between the second carrier metal foil of the multilayer metal foil and the base metal foil a process in which the carrier metal foil is separated from the core substrate by rational stripping; and an etching resist is formed on the second carrier metal foil of the peeled laminate, and etching is performed. The first pattern plating film is exposed from the insulating layer on the surface of the laminate to form a buried circuit, or a process of forming a three-dimensional circuit on the first pattern plating film on the surface of the laminate, or insulation on the surface of the laminate A process of forming a three-dimensional circuit on the layer or a process of forming a recessed shape on the first pattern plating film on the surface of the laminate. A method for producing a package substrate for mounting a semiconductor element, comprising: preparing a first carrier metal foil; and providing a second carrier metal foil having a rough surface having an average thickness of 0.3 to 1.2 μm on the surface and a second carrier metal foil; a process of forming a core substrate by laminating a plurality of metal foils of the base metal foil of the back surface in this order, and laminating the base metal foil side of the multilayer metal foil with the substrate; the first carrier metal foil of the multilayer metal foil and a process for rationally stripping the first carrier metal foil between the second carrier metal foils; a process of applying the first pattern plating film on the surface of the second carrier metal foil of the core substrate; and a step of including the first pattern plating film a process of forming a laminate by forming an insulating layer, a conductor circuit and a layer connection on the surface of the carrier metal foil; and forming the laminate between the second carrier metal foil of the multilayer metal foil and the base metal foil a process in which the carrier metal foil is separated from the core substrate by rational stripping; and the second pattern metal foil is subjected to the second pattern metal foil on the peeled laminate; and the second pattern coating process is performed; An etching resist is formed on a portion of the bulk metal foil other than the second pattern plating portion, and etching is performed to etch the portion where the second pattern is applied and the portion where the etching resist has been formed. The second carrier metal foil is removed, and the first pattern plating film is exposed from the insulating layer on the surface of the laminate to form a buried circuit, or Forming a three-dimensional circuit on the first pattern plating film on the surface of the laminate body, or forming a three-dimensional circuit on the insulating layer on the surface of the laminate body, or forming a concave shape on the first pattern plating film on the surface of the laminate body Process. The method for producing a package substrate for mounting a semiconductor device according to the first aspect of the invention, wherein the insulator, the conductor circuit and the interlayer are formed on the second carrier metal foil including the first pattern plating film. a process for forming a laminate; and a process of separating the laminate and the second carrier metal foil from the core substrate by rational separation between the second carrier metal foil and the base metal foil of the multilayer metal foil; Between the two processes, there is a process of forming an insulating layer and a conductor circuit of a desired number of layers. The method for producing a package substrate for mounting a semiconductor device according to the first or second aspect of the invention, wherein the first pattern plating film is formed by exposing the insulating layer on the surface of the laminate to form a buried circuit. The flip chip connection terminal is formed in a process of forming a three-dimensional circuit on the first pattern plating film on the surface of the laminate, forming a pillar or forming a convex shape in a portion of the longitudinal direction of the flip chip connection terminal, in the surface of the laminate In the process of forming a three-dimensional circuit on the insulating layer, a dummy terminal is formed. A semiconductor element mounting package substrate manufactured by the method for manufacturing a semiconductor element mounting package substrate according to the first or second aspect of the invention, which is provided with the following: Floor; a buried circuit disposed such that a top surface thereof is exposed on a surface of the insulating layer; and a solder resist disposed on the insulating layer and the buried circuit; wherein the buried circuit is disposed in the A flip chip connection terminal is formed in the opening of the solder resist, and the flip chip connection terminal is covered with a pre-solder having a thickness of 3 μm or more. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein the through hole is connected to a bottom surface of the buried circuit in which the flip chip connection terminal is formed. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a convex shape. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a recessed shape. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein the tip end of the flip chip connection terminal is disposed in the opening of the solder resist. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein the buried circuit is provided with an extended portion on both sides or one side in the longitudinal direction of the flip chip connection terminal. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein a part of the flip chip connection terminal is expanded in the short-side direction. In a semiconductor package, a bump of a semiconductor element is mounted on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to the fifth aspect of the invention.