TWI579963B - Semiconductor device structure and method of fabricating same - Google Patents

Description

Semiconductor element structure and method of manufacturing same

The present invention relates to a semiconductor device structure and a method of fabricating the same, and more particularly to a semiconductor device having an interconnect structure and a method of fabricating the same.

The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of various electronic components such as transistors, diodes, resistors and capacitors. For the most part, improving the integration density is achieved by continuously reducing the minimum body size, which increases the number of components in a particular area. As the demand for smaller electronic devices continues to increase in the near future, there is an increasing demand for miniaturization or more innovative semiconductor die packaging technology.

As semiconductor technology evolves, wafer level wafer size packaging (WLCSP) structures are also an effective alternative to reducing the physical size of semiconductor components. In a wafer level wafer size package (WLCSP) structure, active devices such as transistors and the like are formed on the upper surface of the substrate in a wafer level wafer size package (WLCSP) structure.

The current WLCSP process consists of a two-layer polyimide layer and a redistribution layer. RDL) and an under bump metallization (UBM) consist of four mask structures, and it is a high cost structure. In addition, the large grain structure of wafer level wafer size packages is not protected by solder bumps.

In one embodiment, a structure includes: a passivation layer over the substrate; a dielectric layer over the passivation layer; and a post-passivation interconnect structure over the dielectric layer, and the post-passivation interconnect structure extends through Passing through the dielectric layer and electrically connecting to the conductive pad. The foregoing structure further includes a bump located above the post-passivation interconnect structure, and the bump is electrically connected to the post-passivation interconnect structure; the molding layer is located above the post-passivation interconnect structure; and the protective layer is located at the mold Above the plastic layer.

In another embodiment, a structure includes: a conductive pad disposed on a substrate; a passivation layer positioned over the substrate; and the passivation layer having an opening over the conductive pad; and a post passivation interconnect (PPI) a structure above the passivation layer and electrically connected to the conductive pad. The foregoing structure further includes a molding layer positioned over the post-passivation interconnect structure; and a protective layer over the molding layer.

In still another embodiment, a method includes: providing a substrate, wherein the substrate has a conductive pad disposed thereon; forming a passivation layer over the substrate; and the passivation layer has an opening over at least a portion of the conductive pad; forming a dielectric layer is over the passivation layer; and a post-passivation interconnect structure is formed over the dielectric layer, and the post-passivation interconnect structure extends through the dielectric layer and is electrically connected to the conductive layer Electric pad. The foregoing method further includes: forming a bump over the post-passivation interconnect structure, and the bump is electrically connected to the post-passivation interconnect structure; forming a molding layer over the post-passivation interconnect structure; and forming a protective layer on the mold Above the plastic layer.

100‧‧‧Semiconductor components

101‧‧‧Substrate

103‧‧‧ components

105‧‧‧ Inner dielectric layer

107‧‧‧Under metal layer

109‧‧‧First interconnect structure

111‧‧‧Upper metal layer

113‧‧‧Second interconnect structure

115‧‧‧ Passivation layer

117‧‧‧Electrical mat

119‧‧‧ Post Passivation Interconnect (PPI) Structure

121‧‧‧First dielectric layer

123‧‧‧Barrier

125‧‧‧Flexible wire

127‧‧‧Bumps

201‧‧‧Liquid Molding Mixture (LMC) Materials

203‧‧‧Release film

205‧‧‧Metal sheet

401‧‧‧Molding layer

403‧‧‧ angle

501‧‧‧film

601‧‧ ‧ protective layer

701‧‧‧film

703‧‧‧UV adhesive layer

705‧‧‧ grassroots

801‧‧‧protection layer

901‧‧‧film

903‧‧‧First polymer layer

905‧‧‧UV stripping layer

907‧‧‧UV adhesive layer

1001‧‧‧Protective layer

1101‧‧‧film

1103‧‧‧UV adhesive layer

1105‧‧‧First polymer layer

1107‧‧‧UV stripping layer

1109‧‧‧Second polymer layer

1201‧‧‧Protective layer

1301‧‧‧Steps

1303‧‧‧Steps

1305‧‧‧Steps

1307‧‧‧Steps

1309‧‧‧Steps

1311‧‧‧Steps

The embodiments of the present invention can be best understood from the following detailed description and appended claims. It is emphasized that, in accordance with standard practice practices in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion.

1-12 are cross-sectional views showing various intermediate stages of forming a semiconductor component having a wafer size package structure, in accordance with some embodiments.

Figure 13 is a flow chart showing a method of fabricating a semiconductor device having a wafer size package structure, in accordance with some embodiments.

It should be understood that the following disclosure provides various embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are just examples and are not intended to be limiting. Furthermore, the description that one of the following first features is formed over a second feature may include embodiments in which the first and second features are formed in direct contact, and other features may be included between the first and second features, The first and second features may be made in direct contact. In addition, the present disclosure may use repeated reference symbols and/or words in the various examples. These repeated symbols or words are not used for the sake of simplicity and clarity. To define the relationship between various embodiments and/or the structures.

In addition, spatial relative terms, such as "lower", "lower", "upper", etc., are used to describe the relative relationship of an element or feature to other elements or features in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device can be otherwise positioned (e.g., rotated 90 degrees or other orientation), and the spatially relative descriptions used herein can also be interpreted accordingly.

This summary is directed to the embodiments described in the specific context. A structure of a semiconductor element having a wafer size package structure and a manufacturing step thereof. However, embodiments of the present invention are also applicable to various semiconductor elements. Hereinafter, various embodiments will be described in detail with reference to the drawings.

1-12 are cross-sectional views showing various intermediate stages of forming a semiconductor component having a wafer size package structure, in accordance with some embodiments. First, referring to FIG. 1, the semiconductor device 100 includes a substrate 101 which may be made of tantalum, niobium, tantalum carbide or the like. Alternatively, the substrate 101 may be a silicon-on-insulator (SOI) substrate. The germanium insulator substrate may comprise a layer of a semiconductor material (e.g., germanium, germanium, and the like) formed over the insulator layer (e.g., buried oxide or the like), and the insulating layer is formed in the germanium substrate. In addition, other useful substrates include multilayer substrates, gradient substrates, composite pointing substrates, or other similar substrates.

The substrate 101 may further comprise a plurality of elements 103, which are represented in Figure 1 as a single transistor. However, component 103 can include a variety of active and passive components such as transistors, diodes, capacitors, resistors, inductors And other analogs, and the active and passive components can be used to create the desired structural or functional requirements of the substrate 101. Element 103 can be formed on or in substrate 101 or in a covered dielectric layer by any suitable method. It will be understood by those skilled in the art that the above examples are merely illustrative of the embodiments and are not intended to limit the disclosure.

An interlayer dielectric layer (ILD) 105 is formed on the upper surface of the substrate 101 and the element 103 for isolating the element 103 from the subsequently formed metal layer. An inner dielectric layer 105 is formed over the substrate 101 and the component 103 for isolating the component 103 from the subsequently formed metal layer. The inner dielectric layer 105 may comprise cerium oxide, a low-k dielectric material (a material having a lower dielectric constant than cerium oxide), for example: cerium oxynitride, phosphosilicate glass (PSG), bismuth boron silicate glass. (borophosphosilicate glass, BPSG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiO _x C _y , spin-on glass, spin-on polymer, carbonium Materials, or compounds, mixtures, compositions or the like, and deposited by suitable methods, such as spin coating, chemical vapor deposition (CVD) plasma-assisted chemical vapor deposition (plasma-enhanced CVD) , PECVD) or other similar methods. The above materials of porosity can also be used. These materials and processes are given as examples, and other materials or processes may also be used. It should be noted that those of ordinary skill in the art will appreciate that the inner dielectric layer 105 may further comprise a plurality of dielectric layers.

Further referring to FIG. 1, the lower metal layer 107 and the upper metal layer 111 is formed over the inner dielectric layer 105. The lower metal layer 107 can include a first interconnect structure 109. Likewise, the upper metal layer 111 can include the second interconnect structure 113. The first interconnect structure 109 and the second interconnect structure 113 are formed using a conductive material such as copper, silver, gold, tungsten, aluminum, combinations thereof, alloys thereof, or other similar conductive materials. The first interconnect structure 109 and the second interconnect structure 113 can be formed using any suitable technique (eg, deposition, damascene, and the like). For illustrative purposes, the first interconnect structure 109 and the second interconnect structure 113 shown in FIG. 1 are a single conductive line. In other embodiments, the first interconnect structure 109 and the second interconnect structure 113 may include a plurality of conductive lines and via holes, and may have a structure conforming to the design specifications of the semiconductor device 100. Generally, one or more inner metal dielectric layers and associated metal layers are used to interconnect each of the elements 103 in the substrate 101 to form a functional circuit and further provide a connection to an external circuit.

It should be noted that the first metal layer 107 and the upper metal layer 111 are shown in FIG. It will be understood by those of ordinary skill in the art that one or more inner metal dielectric layers (not shown) and associated metal layers (not shown) may be formed between the lower metal layer 107 and the upper metal layer 111. In particular, the layers between the lower metal layer 107 and the upper metal layer 111 may be formed using a dielectric (for example, very low K dielectric material) or an alternative layer of a conductive material (for example, copper).

A passivation layer 115 is formed on the upper surface of the upper metal layer 111. In some embodiments, the passivation layer 115 may comprise one or more layers of cerium oxide, undoped silicon glass (USG), tantalum nitride (SiN), cerium oxynitride (SiON), phosphoric acid phosphite glass. (PSG), polybenzoxazole (polybenzoxazole, PBO), benzocyclobutene (BCB), a polymer such as polyimine, a compound thereof, a mixture thereof, a composition thereof or the like, and deposited by a suitable method, for example, spin coating Cloth, chemical vapor deposition (CVD) and plasma assisted chemical vapor deposition (PECVD) and other similar methods.

With further reference to FIG. 1, an opening may be formed in the passivation layer 115. This opening is for accommodating the conductive pad 117 in the passivation layer 115. In particular, the conductive pads 117 provide a conductive via between the second interconnect structure 113 and the post passivation interconnect (PPI) structure 119 in the semiconductor device 100. The conductive pads 117 can be formed using a conductive material such as copper, copper alloy, aluminum, silver, gold, any combination thereof, and/or multilayer structures. The conductive pads 117 can be formed by a suitable method such as chemical vapor deposition, sputtering, electroplating, and the like.

The first dielectric layer 121 is formed on the upper surface of the passivation layer 115. The first dielectric layer 121 can be formed using an epoxy resin, a polyimide, and the like. Additionally, the first dielectric layer 121 may be formed of a suitable polymeric dielectric material, such as polybenzoxazole (PBO) and the like. The first dielectric layer 121 can be formed by any suitable method, such as chemical vapor deposition, spin coating, and/or the like.

As shown in FIG. 1, a post-passivation interconnect structure 119 is formed over the first dielectric layer 121. A portion of the post passivation interconnect structure 119 can extend through the first dielectric layer 121 to electrically connect to the conductive pads 117. The post passivation interconnect structure 119 can include a barrier layer 123 and a conductive line 125 overlying the barrier layer 123. The post passivation interconnect structure 119 connects the conductive pads 117 of the input/output terminals of the semiconductor device 100. In particular, the post passivation structure 119 provides a conductive path between An interconnection structure in the metal layer (for example, the second interconnection structure 113 located in the upper metal layer 111) is interposed between the input/output terminals of the semiconductor element 100. In some embodiments, the barrier layer 123 can be formed using, for example, chemical vapor deposition, atomic layer deposition (ALD), other similar methods, or a combination thereof. The barrier layer 123 may comprise a nitride or an oxynitride such as titanium nitride, a titanium oxynitride compound, tantalum nitride, an oxynitride compound, tungsten nitride, cerium oxide, the like, or a combination thereof. The conductive line 125 may be formed on the barrier layer 123 by a method such as an electro-chemical plating process, a chemical vapor deposition, an atomic layer deposition, or a physical vapor deposition (PVD). ), other similar methods or a combination thereof. In some embodiments, the conductive lines 125 can comprise copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

As shown in FIG. 1, the bumps 127 are disposed over the conductive lines 125. In some embodiments, the bumps 127 can be solder balls and can be formed using any suitable material, such as, for example, SAC405. SAC405 contains 95.5% tin, 4% silver and 0.5% copper. In some embodiments, a reflow process can be applied to the lower half of the bump 127 to bond the bump 127 to the conductive line 125.

A special advantage of placing the bumps 127 on the conductive lines 125 is that the bumps 127 are directly bonded to the conductive lines 125 to reduce the fabrication cost of the wafer level wafer size package. For example, in a conventional fabrication process, in order to place the bumps on the under bump metallization (UBM) structure, four masks may be formed during the fabrication of the post-passivation interconnect structure 119 in accordance with some embodiments. Cover layer. Direct combination by using the aforementioned Techniques, the mask layer used to form the under bump metal layer structure can be retained. Further, the result is that the manufacturing cost and reliability of the wafer level wafer size package can be improved.

Referring to FIG. 2, a liquid molding compound (LMC) material 201 is deposited over the semiconductor device 100. In some embodiments, the liquid molding mixture material 201 can comprise, for example, a vermiculite mixed epoxy or the like. According to some embodiments, the release film 203 can be used to press the liquid molding mixture material 201. The release film 203 may be formed of a soft material such as, for example, Ethylene Tetrafluoroethylene (ETFE). In some embodiments, the release film 203 can be applied to the metal plate 205.

Referring to Fig. 3, when the metal plate 205 is pressed, a part of the bump is pressed into the release film 203. In addition to this, the release film 203 can push the partial liquid molding mixture material 201 away from the upper surface of the semiconductor element 100, with the result that the lower surface of the release film 203 can be lower than the upper end of the bump 127. Further, the liquid molding compound mixed material 201 can be applied to a curing process. This curing process can be used to cure the liquid molding mixture material 201 to form a molding layer over the semiconductor component 100.

Referring to FIG. 4, the release film 203 over the semiconductor element 100 is removed to expose the molding layer 401 and the bumps 127. In some embodiments, the upper surface of the bump 127 may have a thin layer of residue of the liquid molding mixture material (not shown). For example, the residue of the liquid molding mixture material on the upper surface of the bump 127 can be removed by a suitable etching technique, such as a wet or plasma etching process. The partially retained molding layer 401 is lower than the bump 127 The top surface. As shown in Fig. 4, the bumps 127 are partially buried in the molding layer 401. The upper surface of the molding layer 401 is nearly flat except that there may be a bevel near the bumps 127. The flat portion of the molding layer 401 is formed to a thickness of between about 40 and 150 microns. The bevel of the molding layer 401 may form an angle 403 with the upper surface. In some embodiments, the angle 403 can range between about 30 and 70 degrees.

A feature advantage of having the molding layer 401 is that the molding layer 401 can serve as a protective layer for the bumps 127 and other portions of the semiconductor component 100 to protect them from heat, vibration, moisture, and corrosion. In addition to this, the molding layer 401 can also prevent the bumps 127 from cracking in the reliability test, such as a thermal cycle test. Further, the molding layer 401 can help reduce mechanical or thermal stress during the fabrication of the semiconductor component 100.

In some embodiments, protecting the semiconductor component 100 still requires a protective layer other than the molding layer 401. For example, the molding layer 401 can have voids (not shown) that pass water or other contaminants through the post-passivation interconnect structure 119, which can cause, for example, corrosion damage and result in a nearby post-passivation interconnect layer structure. Short circuit between. In some embodiments, the molding layer 401 can have voids having an average size of about 15 microns. In some embodiments, the molding layer 401 can have voids having an average size of about 40 microns. The semiconductor component 100 may not pass a reliability test, such as a Pressure Cooker Test (PCT) that simulates a severe temperature and humidity environment. In some embodiments, the semiconductor component 100 is immersed in a steam pot test at 121 ° C for 168 hours, relative humidity of 100% and 2 atmospheres. In a more detailed description below, a protective film may be formed over the molding layer to seal the voids of the molding layer 401. The semiconductor component 100 is protected from harsh environmental effects.

In a more detailed description below, a protective film is formed over the molding layer 401. In some embodiments, a film is applied over molding layer 401 and bumps 127. This film is then removed and the residue is left over the molding layer 401 to form a protective layer. In some embodiments, the protective layer can fill the voids of the molding layer 401 and can prevent water or other contaminants from passing through the molding layer 401 to the post-passivation interconnect structure 119. The film may be coated with one or more layers, or one or more configurations, and may comprise a non-conductive material such as a polymer, resin, insulator, or the like. In some embodiments, the film can be of the ultraviolet light type. The ultraviolet light type film may further comprise an ultraviolet light release adhesive layer. In general, when the ultraviolet light-peeling adhesive is exposed to ultraviolet light, its adhesive strength is lowered, so that the film can be easily removed, for example, by peeling it off from the semiconductor element 100.

In other embodiments, the film can be of a non-ultraviolet light type. For example, in some embodiments, the film comprises a layer of thermoplastic polymer. The non-UV type film can be applied over the semiconductor element 100 by a high temperature (60 ° C to 80 ° C) process to soften the thermoplastic polymer layer. When the temperature is lowered to room temperature, the film can be firmly attached over the semiconductor element 100. In some embodiments, the film 501 can be a backside thinned tape (ultraviolet or non-UV type) that can be used to protect the semiconductor component 100 from grinding debris during substrate thinning. The advantage of using a film comprising a backside thinned tape is that the same film can be used for the wafer thinning process and the step of forming a protective layer. Combining the above fabrication process can reduce the cost of semiconductor fabrication.

Referring first to Figures 5 and 6, which are drawn in accordance with some embodiments A first method of forming a protective layer is shown, and FIG. 5 illustrates a film 501, such as a thermoplastic polymer, coated over the semiconductor component 100 using, for example, a roller (not shown). For film 501, the roller can provide a pressure of between about 0.3 megapascals (MPa) and about 0.5 megapascals (MPa), and a temperature of between about 30 ° C and about 100 ° C. In some embodiments, as shown in FIG. 5, the film 501 can have a sufficient thickness to completely cover the bumps 127.

Referring to Fig. 6, for example, the film 501 located on the film plastic layer 401 is peeled off to remove a portion of the film on the semiconductor element 100 (see Fig. 5). In some embodiments, the residue left by film 501 comprises a thermoplastic polymer disposed on film plastic layer 401 and bumps 127. The residue of the film 501 seals the void of the film plastic layer 401 to form a protective layer 601 above the film plastic layer 401. The protective layer 601 protects the film plastic layer 401 and protects the layers below it from environmental effects such as moisture.

In some embodiments, the plasma cleaning process is selectively applied to the bumps 127 to remove residual material from all of the films 501 located on the upper surface of the bumps 127 (see Figure 5). The plasma cleaning process also removes a portion of the upper surface of the protective layer 601. In one embodiment, the plasma cleaning process is performed in an inert gas environment, such as nitrogen, argon, or the like, using oxygen plasma or other similar process. In some embodiments, the protective layer 601 comprises a thermoplastic polymer and can form a thickness of between about 0.5 microns and about 50 microns.

Referring to Figures 7 and 8, a second method of forming a protective layer is illustrated in accordance with some embodiments. With further reference to FIG. 7, film 701 comprises a UV adhesive layer 703 having a thickness of about 40 microns and a base layer 705 having a thickness of about 50 microns above the UV adhesive layer 703. In some embodiments, thin The film 701 may further comprise an optional resin layer (not shown) having a thickness of about 350 microns between the ultraviolet adhesive layer 703 and the base layer 705. The base layer 705 may comprise a polymeric material such as polyester fibers, polypropylene (PP), polyethylene terephthalate (PET), and the like.

For example, the film 701 can be coated over the semiconductor component 100 using rollers (not shown). For film 701, the rollers can provide a pressure of between about 0.3 MPa to about 0.5 MPa and a temperature of between about 30 ° C and about 100 ° C. The foregoing film 701 can be pressed into the void of the molding layer 401, and the ultraviolet adhesive of the ultraviolet adhesive layer 703 can fill the void of the molding layer 401. As shown in FIG. 7, the film 701 may have a sufficient thickness to completely cover the bumps 127.

Referring to FIG. 8, for example, after exposing the film 701 to ultraviolet radiation, the film 701 located on the film plastic layer 401 and the bump 127 is peeled off to remove a portion of the film 701 on the semiconductor device 100 (see section 7). Figure). In some embodiments, the film 701 remains as a residue, comprising an ultraviolet gel material of the UV adhesive layer 703 on the molding layer 401 and the bumps 127. The film 701 can leave a larger amount of residue on the molding layer 401 than on the bumps 127 because the adhesion strength of the ultraviolet adhesive layer 703 to the molding layer 401 is much greater than the adhesion of the ultraviolet adhesive layer 703 to the bumps 127. strength. As shown in Fig. 8, the residue of the film 701 seals the void of the film plastic layer 401 to form a protective layer 801 above the film plastic layer 401. The protective layer 801 protects the film plastic layer 401 and protects the layers below it from environmental effects such as moisture.

In some embodiments, the plasma cleaning process is selectively applied to the bumps 127 to remove residual material from all of the films 701. The plasma cleaning process also removes a portion of the upper surface of the protective layer 801. In one embodiment, the plasma cleaning process is performed in an inert gas environment, such as nitrogen, argon, or the like, using oxygen plasma or other similar process. In some embodiments, the protective layer 801 comprises an ultraviolet light gel and can form a thickness of between about 0.5 microns and about 50 microns.

Referring to Figures 9, 10, a third method of forming a protective layer is illustrated in accordance with some embodiments. Referring further to FIG. 9, the film 901 can include an ultraviolet light release layer 905 between the first polymer layer 903 and the second polymer layer 907. The ultraviolet light release layer 905 may comprise a material similar to the ultraviolet light adhesive layer 703 described in the aforementioned seventh embodiment. In some embodiments, the first polymer layer 903 is a thermoplastic polymer material, and the second polymer layer 907 is a polymer material such as polyester fiber, polypropylene (PP), polyethylene terephthalate. Polyethylene terephthalate (PET), and other analogs.

For example, the film 901 can be coated over the semiconductor component 100 using a roller (not shown). For film 901, the roller can provide a pressure of between about 0.3 megapascals (MPa) and about 0.5 megapascals (MPa), and a temperature of between about 30 ° C and about 100 ° C. The foregoing film 901 can be pressed into the void of the molding layer 401, and the thermoplastic material of the first polymer layer 903 can fill the void of the molding layer 401. As shown in Fig. 9, the film 901 may have a sufficient thickness to completely cover the bumps 127. In some embodiments, as shown in FIG. 9, the first polymer layer 903 is not present in the bump 127 and the ultraviolet light release layer 905. Meanwhile, the upper surface of the bump 127 may be in contact with the ultraviolet light release layer 905.

Referring to FIG. 10, for example, after exposing the film 901 to ultraviolet radiation, the second polymer layer 907 located on the first polymer layer 903 and the bumps 127 is peeled off to remove the film 901 on the semiconductor device 100. The second polymer layer 907 (see Figure 9). As shown in FIG. 10, the first polymer layer 903 left by the film 901 forms a protective layer 1001 over the molding layer 401. The protective layer 1001 protects the film plastic layer 401 and protects the layers below it from environmental effects such as moisture.

In some embodiments, the plasma cleaning process is selectively applied to bumps 127 to remove residual material from all of the film 901, such as the material of the ultraviolet light release layer 905 and the material of the first polymer layer 903. The plasma cleaning process also removes a portion of the upper surface of the protective layer 1001. Thus, for materials lost by the plasma cleaning process, the first polymer layer 903 in the film 901 can provide an initial thickness sufficient to compensate for the aforementioned loss of material. In one embodiment, the plasma cleaning process is performed in an inert gas environment, such as nitrogen, argon, or the like, using oxygen plasma or other similar process. In some embodiments, the multilayer structure of the film 901 as described in the above-mentioned FIG. 9 can provide a protective layer 1001 of a better thickness control over the molding layer 401. In some embodiments, the protective layer 1001 comprises a thermoplastic polymer and can form a thickness of between about 0.5 microns and about 50 microns.

Referring to Figures 11 and 12, a fourth method of forming a protective layer is illustrated in accordance with some embodiments. Referring further to FIG. 11, the film 1101 may include an ultraviolet adhesive layer 1103, a first polymer layer 1105 over the ultraviolet adhesive layer 1103, and an ultraviolet light release layer over the first polymer layer 1105. 1107, and a second polymer layer 1109 above the ultraviolet light release layer 1107. The ultraviolet light release layer 1107 may comprise a material similar to the ultraviolet light adhesive layer 703 described in the aforementioned seventh embodiment. In some embodiments, the first polymer layer 1105 and the second polymer layer 1109 may comprise polyester fibers, polypropylene (PP), polyethylene terephthalate (PET), and Other analogues.

For example, the film 1101 can be coated over the semiconductor component 100 using a roller (not shown). For film 1101, the roller can provide a pressure of between about 0.3 MPa to about 0.5 MPa and a temperature of between about 30 ° C and about 100 ° C. The foregoing film 1101 can be pressed into the void of the molding layer 401, and the ultraviolet adhesive of the ultraviolet adhesive layer 1103 can fill the void of the molding layer 401. As shown in FIG. 11, the film 1101 may have a sufficient thickness to completely cover the bumps 127. In some embodiments, as shown in FIG. 11, the ultraviolet adhesive layer 1103 and the first polymer layer 1105 are not present between the bump 127 and the ultraviolet light release layer 1107, and the upper surface of the bump 127 can be The ultraviolet light release layer 1107 is in contact.

Referring to FIG. 12, for example, after the film 1101 is exposed to ultraviolet radiation and the ultraviolet light release layer 1107 is cured, the second polymer layer 1109 located on the first polymer layer 1105 and the bumps 127 is peeled off to be removed. In addition to the second polymer layer 1109 in the film 1101 on the semiconductor component 100 (see Figure 11). As shown in FIG. 12, the ultraviolet adhesive layer 1103 and the first polymer layer 1105 left by the film 1101 form a protective layer 1201 over the molding layer 401. The protective layer 1201 protects the film plastic layer 401 and protects the layers below it from environmental effects such as moisture.

The plasma cleaning process is selectively applied to the bumps 127 to remove residual material of all of the thin films 1101, such as the material of the ultraviolet adhesive layer 1103, the material of the ultraviolet light release layer 1107, and the first polymer layer 1105. The plasma cleaning process can also remove portions of the upper surface of the protective layer 1201. Thus, for materials lost by the plasma cleaning process, the first polymer layer 1105 in the film 1101 can provide an initial thickness sufficient to compensate for the aforementioned loss of material. In one embodiment, the plasma cleaning process is performed in an inert gas environment, such as nitrogen, argon, or the like, using oxygen plasma or other similar process. In some embodiments, the multilayer structure of the film 1101 as described in the aforementioned FIG. 11 can provide a protective layer 1201 of a better thickness control over the molding layer 401. In some embodiments, the protective layer 1201 comprises a UV adhesive layer 1103 and a first polymer layer 1105 and can form a thickness of between about 0.5 microns and about 50 microns.

Figure 13 is a flow chart showing a method of fabricating a semiconductor device having a wafer size package structure, in accordance with some embodiments. The method begins in step 1301, in which a post-passivation interconnect structure (PPI) is formed over a semiconductor device substrate (see the description of FIG. 1 above). At step 1303, a bump is formed over the post-passivation interconnect structure (see the description of FIG. 1 above). At step 1305, a liquid molding mixture material (LMC) is applied over the post-passivation interconnect structure and over the bumps (see description of Figure 2 above). Subsequently, a pressing process and a curing process of the liquid molding mixture material are performed to form a molding layer over the post-passivation interconnect structure (refer to the description of Figures 2-4 above). At step 1307, the film is applied over the molding layer and the bumps using rollers (see the description of Figures 5, 7, 9, and 11 above). At step 1309, the mold layer will be located. And removing the film or part of the film above the bump to form a protective layer on the film material remaining on the molding layer (refer to the description of Figures 6, 8, 10, and 12 above). Finally, in step 1311, plasma cleaning is performed to remove the remaining film material on the upper surface of the bump (see the description of Figures 6, 8, 10, and 12 above).

The features of some embodiments have been summarized above, so that those skilled in the art can better understand the detailed description. It will be appreciated by those of ordinary skill in the art that the present invention can be readily utilized as a basis for the same purpose and/or implementation of the same advantages in the embodiments described herein. It is also to be understood by those skilled in the art that such equivalents are not to be Spirit and scope.

100‧‧‧Semiconductor components

101‧‧‧Substrate

103‧‧‧ components

105‧‧‧ Inner dielectric layer

107‧‧‧Under metal layer

109‧‧‧First interconnect structure

111‧‧‧Upper metal layer

113‧‧‧Second interconnect structure

115‧‧‧ Passivation layer

117‧‧‧Electrical mat

119‧‧‧ Post Passivation Interconnect (PPI) Structure

121‧‧‧First dielectric layer

123‧‧‧Barrier

125‧‧‧Flexible wire

127‧‧‧Bumps

401‧‧‧Molding layer

601‧‧ ‧ protective layer

Claims (9)

A semiconductor device structure comprising: a passivation layer over a substrate; a dielectric layer over the passivation layer; a post passivation interconnect structure over the dielectric layer, and the post passivation interconnect The structure extends through the dielectric layer and is electrically connected to a conductive pad; a bump is located above the back passivation interconnect structure, and the bump directly contacts and electrically connects the post passivation interconnect structure; a molding layer over the post passivation interconnect structure; and a protective layer over the molding layer. A semiconductor device structure comprising: a conductive pad disposed on a substrate; a passivation layer over the substrate; and the passivation layer having an opening over the conductive pad; a post passivation interconnect structure located in the passivation Above the layer, and electrically connected to the conductive pad; a bump above the back passivation interconnect structure, and the bump directly contacts and electrically connects the post passivation interconnect structure; a molding layer is located Above the passivation interconnect structure; and a protective layer over the mold layer. The structure of claim 2, further comprising a dielectric layer between the passivation layer and the post passivation interconnect structure. The structure of claim 2, wherein the bump extends through the molding layer and the protective layer. The structure of claim 1 or 2, wherein the protective layer comprises an ultraviolet glue, a thermoplastic polymer layer or a combination thereof. A method of fabricating a semiconductor device, comprising: providing a substrate having a conductive pad disposed thereon; forming a passivation layer over the substrate, and the passivation layer has an opening at least one of the conductive pads a dielectric layer is formed over the passivation layer; a post-passivation interconnect structure is formed over the dielectric layer, and the post-passivation interconnect structure extends through the dielectric layer and is electrically connected To the conductive pad; forming a bump above the passivation interconnect structure, and the bump is electrically connected to the post passivation interconnect structure; forming a molding layer over the post passivation interconnect structure, wherein Forming the molding layer over the post passivation interconnect structure comprises: coating a liquid molding mixture material over the post passivation interconnect structure and the bump; pressing the liquid molding mixture material until the liquid a surface of the molding mixture material having a surface lower than the upper surface of the bump; curing the liquid molding mixture material to form the molding layer; and performing plasma cleaning to remove the liquid molding on the bump The residue polymer material; and A protective layer is formed over the molding layer. The method of claim 6, wherein the step of forming the protective layer comprises: coating a film over the molding layer and the bump, and the film comprises an ultraviolet glue layer; exposing the film to ultraviolet rays Radiating; removing the film over the molding layer and the bump, wherein a residue of the film is over the molding layer to form the protective layer over the molding layer, and The residue comprises a portion of the UV adhesive layer; and plasma cleaning is performed to remove the residue of the film on the bump. The method of claim 6, wherein the step of forming the protective layer comprises: coating a film over the molding layer and the bump, and the film comprises a thermoplastic polymer layer; a plastic layer and the film over the bump, wherein a residue of the film is over the molding layer to form a protective layer over the molding layer, and the residue comprises a portion of the thermoplastic polymer a layer; and performing a plasma cleaning to remove the residue of the film on the bump. The method of claim 6, wherein the step of forming the protective layer comprises: coating a film over the molding layer and the bump, and the film comprises: a first polymer layer, an ultraviolet light a release layer, above the first polymer layer, and a second polymer layer above the ultraviolet release layer; exposing the film to ultraviolet radiation; removing the molding layer and the protrusion The ultraviolet light release layer and the second polymer layer above the block, wherein the first polymer layer forms the protective layer over the molding layer; and plasma cleaning to remove the bump This residue of the film.