TWI574153B - Method for reducing use of dram in ssd and the ssd using the same - Google Patents

Description

Method for reducing DRAM usage in solid state hard disks and using the method Solid state hard drive

The present invention relates to a method for reducing the use of DRAM (Dynamic Random Access Memory), and more particularly to a method for reducing the use of DRAM in a solid state hard disk and a solid state hard disk using the same.

Recently, flash memory is widely used for storing digital data, and has many applications: flash memory chips can be assembled into solid-state hard disks, as a main component of a notebook computer, or as a portable storage device, such as A flash drive; a single flash memory chip can also be packaged to form a micro SD memory card that can be inserted into a smart phone for recording data. Taking a solid-state hard disk as an example, a solid-state hard disk has the advantages of shockproof, small size, low heat dissipation, and fast read and write compared to a conventional hard disk. Although traditional hard drives have a higher bit cost ratio than solid state drives, the difference is shrinking. Solid-state hard drives are replacing traditional hard drives and become the mainstream of storage devices.

In solid state drives or other similar storage devices, mapping tables are used to achieve read/write characteristics. Usually, the mapping table is very large, whole or The sub-map is used to perform read or write tasks. Therefore, it is actually necessary to store an entire or partial mapping table into a DRAM module to quickly respond to read/write instructions. The entire mapping table is stored in the flash memory unit (page or block) of the solid state drive before the DRAM module initializes the download of the entire or partial mapping table. Solid state hard disk controllers are usually designed and manufactured together with DRAM modules. The storage capacity of DRAM modules is about 1/1000 of that of all flash memory in solid state drives. For example, if the capacity of the solid state drive is 512 GB, then the DRAM module of the solid state drive controller should be no less than 512 MB. In the past, the capacity of solid-state hard disks was not large, and the DRAM modules required were not large. The cost of DRAM modules is not significant. However, as the capacity of solid state hard disks increases rapidly, the cost of DRAM modules becomes a problem.

The present invention can provide a solution to the aforementioned problems.

This paragraph of text extracts and compiles certain features of the present invention. Other features will be revealed in subsequent paragraphs. The intention is to cover various modifications and similar arrangements in the spirit and scope of the appended claims.

In order to solve the foregoing problems, the present invention discloses a method for reducing the use of DRAM in a solid state hard disk, the method comprising the steps of: A. providing a reference table in a DRAM module of a solid state hard disk, wherein the reference table has a solid state hard disk a physical address of a plurality of subgroups of a mapping table in a non-volatile memory unit, wherein the mapping table has mapping data, and each mapping data is used to map a logical address to a non-volatile memory of the solid state hard disk a corresponding physical address of the body unit; Each subgroup contains a portion of all mapping data; B. provides a logical corresponding physical address table in the DRAM module of the solid state hard disk, wherein the logical corresponding physical address table stores a plurality of logical addresses and DRAM modules a physical address, wherein each physical address of the DRAM module corresponds to a logical address and points to a subgroup of mapping data having a corresponding logical address; C. receives a command from the host of the solid state hard disk, For accessing a target logical address of the non-volatile memory unit; D. confirming whether a physical address of the DRAM module corresponding to the target logical address is stored in the logical corresponding entity address table; If the result of step D is yes, the mapping data in the subgroup is used to execute the command, or if the result of step D is no, a corresponding subgroup of the mapping material containing the target logical address is passed through the reference table. Copying from the mapping table to the DRAM module to execute the command; and F. adding a target entity address of the DRAM module to the logical corresponding entity address table, the mapping data storage of the target logical address On the target Address, so that the target logical addresses correspond to the target entity can address.

The method may further include a step E1 before the step F: E1. When the logical corresponding physical address is expressed to the maximum storage capacity, the target logical address having the lowest priority among all the target logical addresses is from the logical corresponding entity. Removed from the address table. The priority is set by the hit rate of the sorted temporary data access, the recent access record in order, or the random weighting of the sort.

The method may further include a step B1 after the step B: B1. providing a subgroup address to the logical address table in the DRAM module of the solid state hard disk, The subgroup address to logical address table is a mapping data storage logical address of the corresponding subgroup and a physical address of the DRAM module. If the command is a write, the method further includes a step E2 before the step F: E2. programmatically corresponding data corresponding to the physical address in the non-volatile memory unit according to the sub-group address to the logical address table .

Preferably, the non-volatile memory unit is a flash memory chip in the solid state hard disk. The flash memory chip can be a NAND flash memory chip, a NOR flash memory chip, or a charge capture flash memory chip.

In accordance with the present invention, a solid state hard disk using the above method is further disclosed. The solid state hard disk includes: a plurality of non-volatile memory cells; a DRAM module; and a controller for creating a reference table in the DRAM module, wherein the reference table has the non-volatile memory a physical address of a plurality of subgroups of a mapping table, wherein the mapping table has mapping data, and each mapping data is used to map a logical address to a corresponding physical address of the non-volatile memory unit; The subgroup includes a portion of all mapping data; creating a logical corresponding physical address table in the DRAM module, wherein the logical corresponding physical address table stores a plurality of logical addresses and physical addresses of the DRAM module, wherein the DRAM module Each physical address of the group corresponds to a logical address and points to a subgroup of mapping data storing the corresponding logical address; receiving a command from the host of the solid state hard disk for the non-volatile memory unit Accessing a target logical address; confirming whether a physical address of the DRAM module corresponding to the target logical address is stored in the logical corresponding physical address table; if the result is confirmed If yes, the mapping data in the subgroup is used to execute the command; if the confirmation result is no, a corresponding subgroup including the mapping material of the target logical address is copied from the mapping table to the DRAM module through the reference table. In the group, to execute the command; and adding a target entity address of the DRAM module to the logical corresponding entity address table, the mapping data of the target logical address is stored in the target entity address, so that the target logic The address can correspond to the target entity address.

Preferably, the controller may further remove the target logical address having the lowest priority among all the target logical addresses from the logical corresponding entity address table when the logical corresponding physical address is expressed to the maximum storage capacity. The priority may be set by the hit rate of sorting temporary data accesses, sequentially arranging the most recent access records, or sorting the weights arbitrarily. The controller may be further configured to create a subgroup address to a logical address table to the DRAM module, wherein the subgroup address to the logical address table is a mapping data storage logical address and a DRAM module of the corresponding subgroup The physical address of the group. If the command is a write, the controller is further configured to program the data corresponding to the corresponding physical address in the non-volatile memory unit according to the sub-group address to the logical address table.

Preferably, the non-volatile memory unit can be a flash memory chip in the solid state hard disk. The flash memory chip can be a NAND flash memory chip, a NOR flash memory chip, or a charge capture flash memory chip.

Compared with the conventional solid state hard disk, the method and the solid state hard disk architecture provided by the present invention do not have to copy the entire mapping table from the flash memory chip to the DRAM module of the solid state hard disk. Therefore, the capacity requirements of DRAM can be reduced.

10‧‧‧ Solid State Drive

100‧‧‧ Controller

20‧‧‧Host

200‧‧‧DRAM Module

202‧‧‧ storage space

204‧‧‧reference table

206‧‧‧Logical Correspondence Address Table

208‧‧‧Subgroup Address to Logical Address Table

301‧‧‧First flash memory chip

302‧‧‧Second flash memory chip

303‧‧‧ Third flash memory chip

304‧‧‧fourth flash memory chip

305‧‧‧ fifth flash memory chip

306‧‧‧ sixth flash memory chip

307‧‧‧ seventh flash memory chip

308‧‧‧ eighth flash memory chip

Figure 1 is a block diagram of a solid state hard disk in accordance with the present invention.

Figure 2 shows an example of a DRAM module data structure.

Figure 3 is a flow chart showing the steps of the method of the present invention.

The invention will be more specifically described by reference to the following embodiments.

Referring to Fig. 1, there is shown an embodiment of a solid state hard disk 10 having characteristics for reducing DRAM use in accordance with the present invention. The solid state drive 10 is used to store data for access (write and read). Therefore, the solid state hard disk 10 can have a plurality of non-volatile memory cells. The number of non-volatile memory cells is determined by the capacity of the solid state hard disk 10, and the storage capacity of each non-volatile memory cell is not limited. In fact, the non-volatile memory unit can be a flash memory chip. Preferably, the flash memory chip may be a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip, which is not limited in the present invention.

In this embodiment, the solid state hard disk 10 includes eight flash memory chips (a first flash memory chip 301, a second flash memory chip 302, a third flash memory chip 303, a fourth flash memory chip 304, a fifth flash memory chip 305, a sixth flash memory chip 306, a seventh flash memory chip 307, and An eighth flash memory chip 308), a DRAM module 200 and a controller 100. The controller 100 has many functions. According to the present invention, the main function is to create a reference table 204 in the DRAM module 200 (refer to the table 204 having the physical addresses of a plurality of subgroups of a mapping table in the flash memory chips; the mapping table has mapping data, Each mapping data is used to map a logical address to a corresponding physical address of the flash memory chip; each subgroup contains a portion of all mapping data, and a logical corresponding physical address table 206 is created in the DRAM module. Group 200 (the logical corresponding physical address table stores a plurality of logical addresses and physical addresses of the DRAM module 200; each physical address of the DRAM module 200 corresponds to a logical address and points to a map for storing a corresponding logical address In a subgroup of data, a command is received from a host 20 of the solid state hard disk 10 for accessing a target logical address of the flash memory chip to confirm whether it corresponds to a target logical address. A physical address of the DRAM module 200 is stored in the logical corresponding entity address table 206. If the confirmation result is yes, the mapping data in the subgroup is used to execute the command, and if the confirmation result is no, the target logic is included. A corresponding subgroup of the mapping data of the address is copied from the mapping table to the DRAM module 200 via the reference table 204 to execute the command, and a target entity address of the DRAM module 200 is added to the logical corresponding entity address table. 206, the mapping data of the target logical address is stored in the target entity address, so that the target logical address can correspond to the target physical address, when the logical correspondence When the physical address is expressed to the maximum storage capacity, the lowest priority among all the target logical addresses (the priority can be set by the hit rate of the sorted temporary data access, the latest access record is sequentially arranged, or the sort is randomly given the weight) The target logical address is removed from the logical corresponding entity address table 206, and a subgroup address is created into the logical address table 208 in the DRAM module 200 (the subgroup address to the logical address table 208 is the corresponding sub The mapping data storage logical address of the group and the physical address of the DRAM module 200) and if the command is written, according to the sub-group address to the logical address table 208, the corresponding corresponding flash memory chips are programmed. Information on the physical address. A method of reducing the amount of use of the DRAM module 200 in the solid state hard disk 10 is basically implemented by the controller 100. Therefore, the operation of the controller 100 and the solid state hard disk 10 (function of use) will be described in detail in a different method.

Please refer to FIG. 3, which is a flow chart of the steps of the method provided by the present invention. The first step is to provide the reference table 204 in the DRAM module 200 of the solid state hard disk 10 (S01). It is clear that the reference table 204 must be created because there is no data left in the DRAM module 200 just after booting. Referring to the physical addresses of the plurality of subgroups of the mapping table in the flash memory chip of the solid state hard disk 10, the mapping table is used to map the logical address to the corresponding physical bit of the flash memory chip of the solid state hard disk 10. The address is quite large. Therefore, the mapping table is usually broken up into a number of subgroups and stored in a number of addresses (the physical address of the flash memory chip). The mapping table has mapping data, and each mapping data is used to map a logical address. a corresponding physical address to a non-volatile memory unit of the solid state hard disk; A subgroup contains a portion of all mapping data. For a better understanding of this, please see Figure 2. Figure 2 shows an example of the data structure of the DRAM module 200. Reference table 204 has two blocks. One of the physical addresses of the mapping table in the solid state hard disk 10 flash memory chip is recorded (block 0 of the eighth flash memory chip 308, block 0 of the eighth flash memory chip 308, page 2, Block 0 of the eighth flash memory chip 308, block 1 of the eighth flash memory chip 308, and block 1 of the eighth flash memory chip 308 (page 2), and the other indicates The logical address of each subgroup mapping data. For example, "1-10" refers to logical address 1 to logical address 10 of the mapping material of a first subgroup. The block 0 page 2 of the eighth flash memory chip 308 stores the logical address 1 of the mapped data to the logical address 10. Of course, the arrangement of the reference table 204 may have a plurality of logical addresses in a subgroup, or only one logical address in each subgroup, which is not limited by the present invention.

Next, the logical corresponding physical address table 206 is provided in the DRAM module 200 of the solid state hard disk 10 (S02). The logical corresponding physical address table 206 stores a plurality of logical addresses and physical addresses of the DRAM module 200. In FIG. 2, a logical address 1 corresponds to a physical address of 0x80000001, and a logical address 12 corresponds to a physical address of 0x80000002. The 0x80000001 of the DRAM module 200 records the logical address 1 of the mapped data. The 0x80000002 of the DRAM module 200 records the logical address 12 of the mapping material. Logical address 1 belongs to the first subgroup, and logical address 12 belongs to a second subgroup of the mapping table. Each physical address of the DRAM module 200 corresponds to a logical address and points to a subgroup of mapping data having a corresponding logical address. A storage space 202 includes a DRAM module 200 referenced by a logical corresponding physical address table 206. The physical address and used to temporarily store the mapping data. At this time, the storage space 202 has the mapping material 1 (MD1) and the mapping material 2 (MD2), and the mapping material 3 displayed in bold italics will be provided later. Similarly, the logically corresponding physical address table 206 needs to be created because it does not exist when the DRAM module 200 is powered.

The third step is to receive a command from the host 20 of the solid state drive 10 for accessing a target logical address of the non-volatile memory chip (S03). Access refers to writing and reading. For some steps, write and read are considered the same, and the differences are noted in the operational examples. The mapping material of the target logical address can be found in the logical corresponding entity address table 206, such as 0x80000001 and 0x80000002. The mapping material of the target logical address may not remain in the logical corresponding entity address table 206. If a target logical address, 23, is to be accessed because it is not in the logical corresponding entity address table 206, further steps are performed. Therefore, it must be confirmed whether the DRAM module 200 physical address corresponding to the target logical address is stored in the logical corresponding entity address table 206 (S04). If the result of step S04 is YES, it is only necessary to use the mapping material in the subgroup to execute the command (S05). If the result of the step S04 is NO, a corresponding subgroup of the mapping material including the target logical address is copied from the reference table 204 to the DRAM module 200 via the reference table 204 to execute the command (S06). That is, the mapping table referenced by the reference table 204 functions to find the physical address of the flash memory chip of the solid state hard disk 10 corresponding to the target logical address. According to the reference table 204, the physical address of the flash memory chip of the solid state hard disk 10 is the block 0 page 3 of the eighth flash memory chip 308. In order to access the target logic The address, 23, the controller 100 copies the mapping material 3 (MD3) to the storage space 202. Finally, if copying is performed, a target entity address of the DRAM module 200 is added to the logical corresponding entity address table 206, and the mapping data of the target logical address is stored in the target entity address for future target logical address. Can correspond to the target entity address (S07).

Step S07 is for updating the logical corresponding entity address table 206 to the target logical address with the new mapping data, and the target logical address is not in the logical corresponding entity address table 206 before the command is received. In this embodiment, the physical address of the module 200 and the corresponding logical address of the logical corresponding physical address table 206 have three groups. Although there may be more groups in other embodiments, the number is not limited. This method requires further steps when the logical corresponding entity address table 206 reaches the maximum storage capacity but continues to receive commands to access the new target logical address. In other embodiments, when the logically corresponding physical address table 206 reaches the maximum storage capacity, the target logical address with the lowest priority among all of the target logical addresses is removed from the logical corresponding physical address table 206. This step can be added before step S07. That is to say, the least used or least important target logical address should be removed from the logical corresponding entity address table 206 by priority. For example, the priority can be set by the hit rate of the sorted temporary data access (the target logical address of the temporary data with the minimum hit rate removed), or the most recent access record can be sorted in order (the least accessed is removed). The target logical address of the temporary data is set. Even, the priority can be determined by the weight of the random logical address assigned to each target.

As noted above, in accordance with the present invention, access can include both write and read. If the command is a write command, a further step is required after step S02: providing the subgroup address to the logical address table 208 in the DRAM module 200 of the solid state drive 10. The sub-group address to logical address table 208 is a mapping data storage logical address of the corresponding sub-group and a physical address of the DRAM module 200. As shown in FIG. 2, the subgroup address to logical address table 208 originally stores logical address 1 and logical address 12, and mapping data of subgroup 1 and subgroup 2 (MD1 and MD2). At this time, the new logical address 3 and the physical address of the DRAM module 200 of the corresponding subgroup 3 are added to the subgroup address to the logical address table 208. The function of the subgroup address to logical address table 208 is to speed up the programming of the data to the flash memory chip. Stylization may be a separate step prior to step S07: the material that is programmed to correspond to the corresponding physical address of the flash memory chip is in accordance with the subgroup address to logical address table 204. For example, if the contents of logical address 23 are changed, the changed data will be programmed to a new physical address, block 0, page 0 to page 3 of third flash memory chip 303. The previous physical address used to store the original material can be block 15, page 0 through page 3 of the third flash memory chip 303. The correct physical address of the new data is always tracked and recorded by the mapping table.

Compared with the conventional solid state hard disk, the method and the solid state hard disk architecture provided by the present invention do not have to copy the entire mapping table from the flash memory chip to the DRAM module of the solid state hard disk. Therefore, the capacity requirements of DRAM can be reduced. The cost of solid state drives can also be reduced. At the same time, because of the use of reference table 204 and flash flash With the increase in I/O capability of the memory chip, the speed of the physical address of the data required to locate the access command does not go too far with the speed of using the DRAM module.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (14)

A method for reducing the use of a DRAM (Dynamic Random Access Memory) in a solid state hard disk includes the steps of: A. providing a reference table in a DRAM module of a solid state hard disk, wherein the reference table has a non-volatile solid state hard disk a physical address of a plurality of subgroups of a mapping table in a memory unit, wherein the mapping table has mapping data, and each mapping data is used to map a logical address to a non-volatile memory unit of the solid state hard disk Corresponding physical address; each sub-group includes a part of all mapping data; B. providing a logical corresponding physical address table in the DRAM module of the solid-state hard disk, wherein the logical corresponding physical address table stores a plurality of logical bits And a physical address of the DRAM module, wherein each physical address of the DRAM module corresponds to a logical address and points to a subgroup of mapping data having a corresponding logical address; C. receives a command, the command is from a solid state a host of the hard disk for accessing a target logical address of the non-volatile memory unit; D. confirming whether a physical address of the DRAM module corresponding to the target logical address is stored in the logic In the physical address table; E. If the result of step D is yes, use the mapping data in the subgroup to execute the command, or if the result of step D is no, the mapping data of the target logical address will be included. A corresponding subgroup is copied from the mapping table to the DRAM module via the reference table to execute the command; and F. adding a target entity address of the DRAM module to the logical corresponding entity address table, the mapping data of the target logical address is stored in the target entity address, so that the target logical address can correspond to the target Physical address. The method of claim 1, further comprising a step E1 before step F: E1. when the logical corresponding physical address is expressed to the maximum storage capacity, the lowest priority among all the target logical addresses is obtained. The target logical address is removed from the logical corresponding physical address table. The method of claim 2, wherein the priority is set by a hit ratio of the sorted temporary data access, a recent access record, or a random order weight. The method of claim 1, further comprising a step B1 after step B: B1. providing a subgroup address to a logical address table in the DRAM module of the solid state hard disk, wherein the subgroup The address-to-logical address table is the mapping data storage logical address of the corresponding sub-group and the physical address of the DRAM module. The method of claim 4, wherein if the command is a write, the method further comprises a step E2 before the step F: E2. according to the subgroup address to the logical address table, the stylized corresponding Information on the corresponding physical address in a non-volatile memory unit. The method of claim 1, wherein the non-volatile memory unit is a flash memory chip in the solid state hard disk. The method of claim 6, wherein the flash memory crystal The chip is a NAND flash memory chip, a NOR flash memory chip, or a charge capture flash memory chip. A solid state hard disk comprising: a plurality of non-volatile memory cells; a DRAM module; and a controller for creating a reference table in the DRAM module, wherein the reference table has the non-volatile memory a physical address of a plurality of subgroups of a mapping table, wherein the mapping table has mapping data, and each mapping data is used to map a logical address to a corresponding physical address of the non-volatile memory unit; The subgroup includes a portion of all mapping data; creating a logical corresponding physical address table in the DRAM module, wherein the logical corresponding physical address table stores a plurality of logical addresses and physical addresses of the DRAM module, wherein the DRAM module Each physical address of the group corresponds to a logical address and points to a subgroup of mapping data storing the corresponding logical address; receiving a command from the host of the solid state hard disk for the non-volatile memory unit Accessing a target logical address; confirming whether a physical address of the DRAM module corresponding to the target logical address is stored in the logical corresponding physical address table; if the confirmation result is yes, And mapping data of the sub-group to execute the command; If the result of the verification is no, a corresponding subgroup of the mapping data including the target logical address is copied from the mapping table to the DRAM module via the reference table to execute the command; and one of the DRAM modules is added. The target entity address is in the logical corresponding entity address table, and the mapping data of the target logical address is stored in the target entity address, so that the target logical address can correspond to the target entity address. The solid state hard disk according to claim 8, wherein the controller further uses the lowest priority target logical address of all the target logical addresses when the logical corresponding physical address is expressed to the maximum storage capacity. This logic is removed from the physical address table. The solid state hard disk of claim 9, wherein the priority is set by a hit rate of sorting temporary data accesses, sequentially arranging recent access records, or arbitrarily granting weights. The solid state hard disk of claim 8, wherein the controller is further configured to create a subgroup address to a logical address table to the DRAM module, wherein the subgroup address to the logical address table The logical address and the physical address of the DRAM module are stored for the mapping data of the corresponding subgroup. The solid state hard disk according to claim 11, wherein if the command is written, the controller is further configured to program the corresponding non-volatile memory unit according to the sub-group address to the logical address table. The data corresponding to the physical address. A solid state hard disk as described in claim 8 wherein the non-volatile The memory unit is a flash memory chip in the solid state hard disk. The solid state hard disk of claim 13, wherein the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip.