TWI552313B - Method of simultaneously manufacturing semiconductor devices in cell region and peripheral region - Google Patents

Description

Method of simultaneously fabricating semiconductor elements of a cell region and a peripheral region

This invention relates to a semiconductor process, and more particularly to a method of simultaneously fabricating semiconductor elements in a cell region and a peripheral region.

With the development of semiconductor components to the generation of nanometers, there are more and more difficulties, such as the line width reduction, line density increase, etc., in the pattern accuracy and process control have a severe test.

For example, when fabricating a gate structure, the gate oxide layer is generally used as an etch stop layer. Moreover, the etching process usually first considers whether the component profile is consistent with the design, so when the cell region is fabricated simultaneously with the peripheral region, the risk of damage to the gate oxide layer is often increased due to over-etching.

In addition, as transistor gate lengths are reduced, the easiest way to increase circuit speed is to reduce the gate oxide thickness; or the wafer requires a triple gate oxide to compromise component performance and circuit consumption. However, these peripherals The extremely thin oxide layer in the zone is also at risk of being damaged during the process.

The present invention provides a method of simultaneously fabricating semiconductor elements of a cell region and a peripheral region, which can reduce the risk of oxide damage in the peripheral region.

A method of simultaneously fabricating a semiconductor component of a cell region and a peripheral region of the present invention includes providing a substrate having at least one cell region and at least one peripheral region. A gate oxide layer, a first conductor structure layer, an inter-gate dielectric layer and a second conductor structure layer are sequentially formed on the substrate. A mask structure is formed on the second conductor structure layer, and the mask structure is used as an etching mask to remove the second conductor structure layer of the cell region and the peripheral region, and the inter-gate dielectric layer is used as an etch stop layer. Forming a first protective layer covering the inter-gate dielectric layer in the peripheral region, exposing the inter-gate dielectric layer of the cell region, and etching the exposed inter-gate dielectric layer and the first conductive structural layer in the cell region, and The gate oxide layer acts as an etch stop layer. An ion implantation process is then performed to form source and drain electrodes in the substrate of the cell region. The first protective layer is removed, and a second protective layer covering the gate oxide layer, the first conductor structure layer, the inter-gate dielectric layer and the second conductor structure layer is formed in the cell region, and the inter-gate dielectric layer of the peripheral region is exposed. The gate oxide layer is used as an etch stop layer to etch the exposed inter-gate dielectric layer and the first conductor structure layer in the peripheral region.

In an embodiment of the invention, the step of forming the mask structure includes forming a cap layer on the second conductor structure layer, and forming a first pattern mask layer and a layer on the cap layer of the cell region and the peripheral region, respectively. Two pattern cover layer.

In an embodiment of the invention, the cell region and the peripheral region are removed The step of the two-conductor structure layer includes etching the cap layer by using the first and second pattern mask layers as an etching mask to transfer the patterns of the first and second pattern mask layers to the cap layer, and then using the cap layer As an etching mask, the second conductor structure layer is etched.

In an embodiment of the invention, after etching the second conductive structure layer, the first and second pattern mask layers are further removed.

In an embodiment of the invention, the step of forming the first and second pattern mask layers comprises first forming a first material layer on the cap layer in a comprehensive manner, and forming a uniform distribution on the first material layer of the cell region. The plurality of spacer masks remove a portion of the spacer mask, and the unremoved spacer mask becomes the first pattern mask layer. A second material layer is formed on the substrate in a comprehensive manner and covers the spacer mask, and the second pattern mask layer is formed on the second material layer of the cell region and the peripheral region.

In an embodiment of the invention, before removing the second conductor structure layer of the unit cell region and the peripheral region, the method further comprises: etching the second material layer by using the second pattern mask layer as an etching mask to make the second pattern Transferring the pattern of the mask layer to the second material layer and exposing the first pattern mask layer, and etching the first material layer by using the first pattern mask layer and the second pattern mask layer as an etching mask to make the first The pattern mask layer and the pattern of the second material layer are transferred to the first material layer and expose the second conductor structure layer.

In an embodiment of the invention, the material of the cap layer is, for example, yttrium oxide, tantalum nitride or polysilicon; the material of the first material layer is, for example, polysilicon; the material of the spacer mask, such as tantalum nitride, hafnium oxide or polysilicon; The material of the two material layers is, for example, photoresist or spin-on carbon.

In an embodiment of the invention, the substrate may further include at least one capacitor Area.

In an embodiment of the invention, the mask structure can be formed simultaneously in the capacitor region, and when the second conductor structure layer of the cell region and the peripheral region is removed, part of the second conductor structure layer of the capacitor region is simultaneously removed. Two conductor layers positioned above the first conductor structure layer are formed to expose the inter-gate dielectric layer between the two conductor layers.

In an embodiment of the invention, the step of forming the first protective layer includes simultaneously covering the exposed inter-gate dielectric layer in the capacitor region.

In an embodiment of the invention, the step of forming the second protective layer includes simultaneously covering the inter-gate dielectric layer between the two conductor layers.

In an embodiment of the invention, the mask structure can be formed simultaneously in the capacitor region, and when the second conductor structure layer of the peripheral region of the cell region is removed, part of the second conductor structure layer of the capacitor region is simultaneously removed. A conductor layer is formed on the first conductor structure layer.

In an embodiment of the invention, after etching the inter-gate dielectric layer and the first conductor structure layer exposed in the peripheral region, the second protective layer may be removed and a third protective layer is formed on the substrate. The third protective layer has an opening over the one of the conductor layers exposing the capacitor region, and then etches the structure exposed from the opening, and uses the inter-gate dielectric layer as an etch stop layer.

In an embodiment of the invention, the edge of the cell region includes a word line extraction region, and after etching the inter-gate dielectric layer and the first conductor structure layer in the peripheral region, the second layer may be removed. a protective layer and sidewalls of the plurality of stacked structures formed by the first conductor structure layer, the inter-gate dielectric layer and the second conductor structure layer on the substrate Forming an isolation spacer thereon, and then forming a third protective layer on the substrate, the third protective layer having a connection between the first opening above the conductor layer exposing the capacitor region and the stacked structure of the exposed word line extraction region The upper second opening, in turn, etches the structure exposed from the first and second openings and uses the inter-gate dielectric layer as an etch stop layer.

Based on the above, the present invention can accurately control the etching amount of the gate oxide layer in the peripheral region by separately performing the etching step in the cell region and the peripheral region, thereby reducing the risk of oxide layer damage in the peripheral region. In addition, if the capacitor area is fabricated, it can be integrated with the cell area process to reduce a mask process.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧cell area

20‧‧‧The surrounding area

30‧‧‧ capacitor area

40‧‧‧ character line extraction area

100‧‧‧Base

102‧‧‧ gate oxide

104‧‧‧First conductor structure

106‧‧‧Interruptor dielectric layer

108‧‧‧Second conductor structure

110‧‧‧Component isolation structure

112‧‧‧ cover

114‧‧‧First material layer

116, 200‧‧‧ sacrificial layer

118a, 118b, 202‧‧ ‧ clearance wall curtain

120‧‧‧Light resistance

122‧‧‧Second material layer

124, 204‧‧‧ second pattern cover layer

126, 206‧‧‧ first protective layer

128‧‧‧Ion implantation process

130‧‧‧Source and bungee

132, 208‧‧‧ second protective layer

210, 302‧‧‧ third protective layer

212, 304, 306‧‧‧ openings

300‧‧‧Isolation spacer

1A to 1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device in which a cell region and a peripheral region are simultaneously formed in accordance with a first embodiment of the present invention.

2A to 2H-2 are schematic cross-sectional views showing a manufacturing process of a semiconductor device in which a cell region and a peripheral region are simultaneously formed in accordance with a second embodiment of the present invention.

3A-1 to 3C are cross-sectional views showing another manufacturing process of Fig. 2F following the second embodiment.

1A to 1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device in which a cell region and a peripheral region are simultaneously formed in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided, and the substrate 100 has a cell region 10 and a peripheral region 20. There is also a capacitor region 30 in the substrate 100 of the present embodiment. Although there is only one of the cell region 10, the peripheral region 20, and the capacitor region 30 in the drawing, the present invention is not limited thereto. Then, a gate oxide layer 102, a first conductor structure layer 104, an inter-gate dielectric layer 106, and a second conductor structure layer 108 are sequentially formed on the substrate 100. The first conductor structure layer 104 is, for example, a single layer or a double layer structure composed of tungsten, aluminum, copper, polysilicon or other suitable material. The inter-gate dielectric layer 106 is, for example, an ONO layer, a high dielectric material, or other suitable dielectric layer. The second conductor structure layer 108 is, for example, a single layer or a double layer structure composed of an epitaxial layer, a polysilicon layer, a metal layer or the like. In this embodiment, after the formation of the first conductor structure layer 104 in the peripheral region 20 and the capacitor region 30, the fabrication of the device isolation structure 110 (such as STI) is performed first, and then the dielectric layer 106 and the gate dielectric layer are further formed. Two conductor structure layer 108.

Then, referring to FIG. 1B, in order to form a mask structure on the second conductor structure layer 108, the pattern mask required for etching can be formed by a general process, or the following steps can be performed in conjunction with semiconductor components of the nano generation. First, a cap layer 112 may be formed on the second conductor structure layer 108, wherein the cap layer 112 is, for example, a hafnium oxide layer, a tantalum nitride layer, or a polysilicon layer. Then, different pattern mask layers are respectively formed on the cap layer 112 of the cell region 10 and the peripheral region 20, so that the first material layer 114 can be formed on the cap layer 112 in a comprehensive manner, wherein the first material layer 114 is formed. The material has a large etching selectivity ratio with the material of the cap layer 112 to facilitate the etching process in subsequent stages. This is done so that when the cap layer 112 is a hafnium oxide layer, the first material layer 114 may be selected from materials such as polysilicon. Then, a plurality of sacrificial layers 116 uniformly distributed are formed on the first material layer 114 of the cell region 10 by a first mask process. In this embodiment, the selection gates belonging to the dense region in the cell region 10 in the original mask data are first removed, and the same line width and the same are added in the removed region and the open region adjacent to the dense region. A plurality of dummy patterns of the pitch to form a modified reticle material. Since the modified reticle is added with a dummy pattern in the open area, when the sacrificial layer 116 is defined by the modified reticle, the line width of the conventional line adjacent to the peripheral area 20 can be prevented from being affected. And the problem of poor uniformity of key dimensions. In this way, the word line of the semiconductor component such as the memory can be made to have better critical dimension uniformity without changing the number of masks.

Next, referring to FIG. 1C, spacer masks 118a and 118b are formed on the sidewalls of the sacrificial layer 116, wherein the spacer masks 118a and 118b are made of a material such as tantalum nitride, hafnium oxide or polysilicon. In the present embodiment, the spacer mask 118a corresponds to the line within the cell region 10, and the spacer mask 118b is a dummy pattern for improving the uniformity of critical dimensions.

Then, referring to FIG. 1D, a mask structure such as a photoresist 120 is formed on the substrate 100 by a second mask process, and completely covers the peripheral region 20 and the capacitor region 30. Since the spacer masks 118a and 118b are formed not only on the long side of the sacrificial layer 116 but also on the short side of the sacrificial layer 116, the spacer mask 118b (i.e., dummy pattern) is removed for the etching mask by the photoresist 120. At the same time, the spacer mask 118a on the short side of the sacrificial layer 116 can be simultaneously removed.

Subsequently, referring to FIG. 1E, after removing the photoresist 120 and removing the sacrificial layer 116, the unremoved spacer mask 118a becomes the first pattern mask layer. Next, a second material layer 122 is formed on the substrate 100 in a comprehensive manner and covers the spacer mask 118a, wherein the material of the second material layer 122 is, for example, photoresist or spin on carbon. Subsequently, a second pattern mask layer 124 is formed on the cell region 10, the peripheral region 20, and the second material layer 122 of the capacitor region 30 by a third mask process, which may vary depending on the pattern to be formed in each region.

Then, the second pattern mask layer 124 in FIG. 1E can be used as an etching mask to etch the second material layer 122 to transfer the pattern of the second pattern mask layer 124 to the second material layer 122 and expose the first pattern. The mask layer (ie, the spacer mask 118a). If the second pattern mask layer 124 is covered over the first pattern mask layer, the spacer mask 118a is not exposed after this etching step.

Subsequently, referring to FIG. 1F, after the first material layer 114 and the cap layer 112 are etched by using the spacer mask 118a and the second pattern mask layer 124 of FIG. 1E as an etching mask, the spacer mask 118a and The pattern of the second material layer 122 is transferred to the first material layer 114 and the cap layer 112, and the second conductor structure layer 108 is exposed. Then, using the etched cap layer 112 as an etch mask, the second conductor structure layer 108 is etched away, and the inter-gate dielectric layer 106 is used as an etch stop layer. After etching the second conductor structure layer 108, the structure above the cap layer 112 can be completely removed. In this embodiment, after removing a portion of the second conductor structure layer 108 of the capacitor region 30, two conductor layers positioned above the first conductor structure layer 104 can be formed to expose the inter-gate dielectric layer between the two conductor layers. 106.

Next, referring to FIG. 1G, a first protective layer 126 covering the inter-gate dielectric layer 106 is formed in the peripheral region 20 and the capacitor region 30 by using a fourth mask process, and the inter-gate dielectric layer 106 of the cell region 10 is exposed. . Thereafter, the inter-gate dielectric layer 106 and the first conductor structure layer 104 exposed in the cell region 10 are etched using the gate oxide layer 102 as an etch stop layer. Because the peripheral region 20 is covered by the first protective layer 126 during the etching process, the internal inter-gate dielectric layer 106 and the first conductive structural layer 104 are not removed at the same time, so the process is etched together with the conventional one. In comparison, the risk of damage to the gate oxide layer 102 can be greatly reduced. The substrate 100 can then be subjected to an ion implantation process 128 to form source and drain electrodes 130 in the substrate 100 of the cell region 10. Although only the arrows representing the ion implantation process 128 are shown in the cell region 10 in this figure, it is understood that the general ion implantation process is performed on the entire substrate 100. In addition, the first protective layer 126 is removed even before the ion implantation process 128 is performed because the peripheral region 20 and the implanted region within the capacitor region 30 are not removed in subsequent steps, nor are they themselves The implanted dose affects, and thus the first protective layer 126 can be removed prior to the ion implantation process 128.

Then, referring to FIG. 1H, after removing the first protective layer (126 of FIG. 1G), a second protective layer 132 covering all structures is formed in the cell region 10 by using a fifth mask process, and the gate of the peripheral region 20 is exposed. Inter-dielectric layer 106. At this time, the second protective layer 132 may also cover the inter-gate dielectric layer 106 between the two conductor layers (ie, 108) in the capacitor region 30. Then, the gate inter-gate dielectric layer 106 and the first conductor structure layer 104 are exposed in the peripheral region 20 with the gate oxide layer 102 as an etch stop layer. At this time, it is also possible that the peripheral isolation region 20 and the element isolation structure 110 in the capacitor region 30 are exposed. Was removed together.

In addition, the second protective layer 132 may be removed after the step of FIG. 1H, and subsequent processes are performed.

2A to 2H-2 are schematic cross-sectional views showing a manufacturing process of a semiconductor device in which a cell region and a peripheral region are simultaneously formed in accordance with a second embodiment of the present invention. The first step of the second embodiment is the same as that of Fig. 1A of the first embodiment, and therefore will not be described again, and the second embodiment uses the same reference numerals as the first embodiment to denote the same or similar members.

Referring to FIG. 2A, after the step of FIG. 1A is completed, in order to form a mask structure on the second conductor structure layer 108, a cap layer 112 and a first material layer 114 are first formed on the second conductor structure layer 108. Then, a plurality of sacrificial layers 200 are formed on the first material layer 114 of the cell region 10 by a first mask process. The material selection of the cap layer 112 and the first material layer 114 can be referred to the previous embodiment.

2B-1 and 2B-2, wherein FIG. 2B-1 is a top view, and FIG. 2B-2 is a II-II' line segment of FIG. 2B-1. A spacer mask 202 is formed on the sidewall of the sacrificial layer 200, wherein the material of the spacer mask 202 is, for example, tantalum nitride, hafnium oxide or polysilicon. In addition, a WL pick-up region 40 having an edge of the cell region 10 is shown in FIG. 2B-1, and the device isolation structure 110 is under the inter-gate dielectric layer 106 in this region, instead of the first A conductor structure layer 104.

Next, please refer to FIG. 2C-1 and FIG. 2C-2, wherein FIG. 2C-1 is a top view, and FIG. 2C-2 is a II-II' line segment of FIG. 2C-1. First, the sacrificial layer 200 is removed, only the spacer mask 202 is left, and then the second material layer 122 is formed on the substrate 100 and covered. Covering the spacer mask 202, and then forming a second pattern mask layer 204 on the second material layer 122 using a second mask process, which differs from FIG. 1E of the first embodiment in a second in the capacitor region 30. The pattern of the mask layer 204 is patterned.

Thereafter, please refer to FIG. 2D-1 and FIG. 2D-2, wherein FIG. 2D-1 is a top view, and FIG. 2D-2 is a II-II' line segment of FIG. 2D-1. Using the second pattern mask layer 204 of FIG. 2C-1 as an etch mask, the second material layer 122 is etched, and the pattern of the second pattern mask layer 204 is transferred to the second material layer 122 and the spacer mask is exposed. After 202, the first material layer 114 and the cap layer 112 are etched by using the spacer mask 202 and the second pattern mask layer 204 as an etch mask until the second conductor structure layer 108 is exposed. Then, using the etched cap layer 112 as an etch mask, the second conductor structure layer 108 is etched away, and the inter-gate dielectric layer 106 is used as an etch stop layer. After etching the second conductor structure layer 108, the structure above the cap layer 112 can be completely removed. In the present embodiment, a portion of the second conductor structure layer 108 of the capacitor region 30 is removed to form a single conductor layer on the first conductor structure layer 104.

Next, referring to FIG. 2E, a first protective layer 206 covering the inter-gate dielectric layer 106 is formed in the peripheral region 20 and the capacitor region 30 by using a third mask process, and the inter-gate dielectric layer 106 of the cell region 10 is exposed. . Then, the gate inter-gate dielectric layer 106 and the first conductor structure layer 104 are exposed in the cell region 10 with the gate oxide layer 102 as an etch stop layer. The substrate 100 can then be subjected to an ion implantation process 128 to form source and drain electrodes 130 in the substrate 100 of the cell region 10. In the figure, although the first protective layer 206 covers the peripheral region 20 and the capacitor region 30 when the ion implantation process 128 is performed, the present invention is not limited thereto. Even before the ion implantation process 128 is performed A protective layer 206 is removed because the peripheral region 20 and the implanted region within the capacitor region 30 are removed in subsequent steps and do not affect the operation and performance of the semiconductor device. Therefore, the first protective layer 206 can be removed prior to the ion implantation process 128.

Then, referring to FIG. 2F, the first protective layer 206 of FIG. 2E may be removed after the ion implantation process 128, and a second protective layer 208 covering all structures may be formed in the cell region 10 by using a fourth mask process. The inter-gate dielectric layer 106 in the peripheral region 20 and the capacitor region 30 is exposed. Then, the gate inter-gate dielectric layer 106 and the first conductor structure layer 104 are exposed in the peripheral region 20 with the gate oxide layer 102 as an etch stop layer. At this time, the peripheral isolation region 20 and the element isolation structure 110 in the capacitor region 30 are also removed together if exposed.

2G-1 and 2G-2, wherein FIG. 2G-1 is a top view, and FIG. 2G-2 is a II-II' line segment of FIG. 2G-1. After removing the second protective layer 208, a third protective layer 210 is additionally formed on the substrate 100 by a fifth mask process. The third protective layer 210 has an opening 212 above the second conductive structure layer 108 exposing the capacitor region 30. . Also, since the previously formed spacer mask (see 202 of FIG. 2C-1) is formed not only on the long side of the sacrificial layer 200 but also on the short side of the sacrificial layer 200, a portion of the second conductor structure layer 108 is formed. The short side portions are connected, so the third protective layer 210 may further include an opening that exposes the cap layer 112 in the word line extraction region 40.

2H-1 and 2H-2, wherein FIG. 2H-1 is a cross-sectional view of the regions 10, 20, and 30, and FIG. 2H-2 is a cross-sectional view of the region 40. After the third protective layer 210 is used as an etch mask, the structure exposed from the opening 212 is removed, and after the inter-gate dielectric layer 106 is used as an etch stop layer, the second conductor structure in the capacitor region 30 Layer 108 will become two conductor layers, and the second conductor structure layer 108 connected within word line extraction region 40 will also be separated.

3A to 3C are cross-sectional views showing another manufacturing process of Fig. 2F following the second embodiment.

3A-1 and 3A-2, wherein FIG. 3A-1 is a top view, and FIG. 3A-2 is a II-II' line segment of FIG. 3A-1. After removing the second protective layer (208 of FIG. 2F), a plurality of stacked structures composed of the first conductor structure layer 104, the inter-gate dielectric layer 106, the second conductor structure layer 108, and the cap layer 112 on the substrate 100 An isolation spacer 300 is formed on the sidewall.

3B-1 and 3B-2, wherein FIG. 3B-1 is a top view, and FIG. 3B-2 is a II-II' line segment of FIG. 3B-1. A third protective layer 302 is formed on the substrate 100 by a fifth mask process. The third protective layer 302 has a first opening 304 and an exposed word line extraction region over the second conductor structure layer 108 exposing the capacitor region 30. The second conductor structure layer 108 in 40 is connected to the second opening 306 above the portion.

Referring to FIG. 3C, the third protective layer 302 of FIG. 3B-1 is used as an etch mask to etch the structures exposed from the first and second openings 304 and 306, and is terminated by the inter-gate dielectric layer 106 as an etch. After the layer, the second conductor structure layer in capacitor region 30 becomes two conductor layers exposing the inter-gate dielectric layer 106 between the two conductor layers. At the same time, the second conductor structure layer 108 connected in the word line extraction region 40 is also cut. Since the second opening 306 is originally an existing reticle for fabricating the semiconductor component, the first opening 304 can be integrated therewith, omitting an additional reticle process.

In summary, the present invention can accurately control the etching amount of the gate oxide layer in the peripheral region by separately performing the etching step in the cell region and the peripheral region, thereby reducing the risk of oxide damage in the peripheral region. Moreover, it can be integrated with the process of the cell region to reduce the mask process. In addition, the etching mask is produced by the method of the embodiment, and has an effect of improving the uniformity of the critical dimensions.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧cell area

20‧‧‧The surrounding area

30‧‧‧ capacitor area

100‧‧‧Base

102‧‧‧ gate oxide

104‧‧‧First conductor structure

106‧‧‧Interruptor dielectric layer

108‧‧‧Second conductor structure

110‧‧‧Component isolation structure

112‧‧‧ cover

126‧‧‧ first protective layer

128‧‧‧Ion implantation process

130‧‧‧Source and bungee

Claims (14)

A method for simultaneously fabricating semiconductor elements of a cell region and a peripheral region, comprising: providing a substrate having at least one cell region and at least one peripheral region; forming a gate oxide layer and a first conductor structure layer sequentially on the substrate a gate dielectric layer and a second conductor structure layer; forming a mask structure on the second conductor structure layer; using the mask structure as an etching mask to remove the cell region and the second conductor of the peripheral region Forming a layer, and using the inter-gate dielectric layer as an etch stop layer; forming a first protective layer covering the inter-gate dielectric layer in the peripheral region, and exposing the inter-gate dielectric layer of the cell region; etching the The inter-gate dielectric layer and the first conductor structure layer are exposed in the cell region, and the gate oxide layer is used as an etch stop layer; an ion implantation process is performed to form a source in the substrate of the cell region And removing the first protective layer; forming a second protective layer covering the gate oxide layer, the first conductor structure layer, the inter-gate dielectric layer and the second conductor structure layer in the cell region, and Exposing the inter-gate dielectric layer of the peripheral region; Engraved dielectric layer and the first conductor structure between the gate layer exposed within the peripheral zone, and in that the gate oxide layer as an etch stop layer. The method of claim 1, wherein the mask structure is formed The step of forming a cap layer on the second conductor structure layer; and forming a first pattern mask layer and a second pattern mask layer on the cell region and the cap layer of the peripheral region, respectively. The method of claim 2, wherein the removing the unit cell region and the second conductor structure layer of the peripheral region comprises: using the first pattern mask layer and the second pattern mask layer as Etching the mask, etching the cap layer to transfer the pattern of the first pattern mask layer and the second pattern mask layer to the cap layer; and etching the second conductor structure by using the cap layer as an etching mask Floor. The method of claim 3, wherein after etching the second conductor structure layer, further comprising removing the first pattern mask layer and the second pattern mask layer. The method of claim 2, wherein the forming the first pattern mask layer and the second pattern mask layer comprises: forming a first material layer on the cover layer in a comprehensive manner; Forming a plurality of spacer masks uniformly distributed on the first material layer of the cell region; removing portions of the spacer masks, and the spacer masks that are not removed become the first pattern mask layer Forming a second material layer on the substrate and covering the spacer masks; The second pattern mask layer is formed on the cell region and the second material layer of the peripheral region. The method of claim 5, wherein the removing the unit cell region and the second conductor structure layer of the peripheral region further comprises: etching the second by using the second pattern mask layer as an etching mask a material layer to transfer a pattern of the second pattern mask layer to the second material layer and exposing the first pattern mask layer; and using the first pattern mask layer and the second pattern mask layer as an etch The mask etches the first material layer to transfer the pattern of the first pattern mask layer and the second material layer to the first material layer and expose the second conductor structure layer. The method of claim 5, wherein the material of the cap layer comprises ruthenium oxide, tantalum nitride or polysilicon; the material of the first material layer comprises polysilicon; the spacers The material includes tantalum nitride, tantalum oxide or polycrystalline germanium; the material of the second material layer includes photoresist or spin-on carbon. The method of claim 1, wherein the substrate further comprises at least one capacitor region. The method of claim 8, wherein the forming the mask structure comprises simultaneously forming the mask structure in the capacitor region; and removing the unit cell region and the second conductor structure layer of the peripheral region The step includes simultaneously removing a portion of the second conductor structure layer of the capacitor region to form two conductor layers positioned above the first conductor structure layer, thereby exposing the gate between the two conductor layers Inter-dielectric layer. The method of claim 9, wherein the step of forming the first protective layer comprises simultaneously covering the inter-gate dielectric layer exposed within the capacitor region. The method of claim 9, wherein the step of forming the second protective layer comprises simultaneously covering the inter-gate dielectric layer between the two conductor layers. The method of claim 8, wherein the forming the mask structure comprises simultaneously forming the mask structure in the capacitor region; and removing the unit cell region and the second conductor structure layer of the peripheral region The step includes simultaneously removing a portion of the second conductor structure layer of the capacitor region to form a conductor layer positioned on the first conductor structure layer. The method of claim 12, wherein after etching the inter-gate dielectric layer and the first conductor structure layer exposed in the peripheral region, the method further comprises: removing the second protective layer; on the substrate Forming a third protective layer having an opening over the one conductor layer exposing the capacitor region; and etching a structure exposed from the opening, and using the inter-gate dielectric layer as an etch stop layer. The method of claim 12, wherein the edge of the unit cell region has a word line extraction region, and after etching the inter-gate dielectric layer and the first conductor structure layer exposed in the peripheral region, The method further includes: removing the second protective layer; Forming a plurality of isolation spacers on a sidewall of the plurality of stacked structures formed by the first conductor structure layer, the inter-gate dielectric layer and the second conductor structure layer on the substrate; forming a third protection on the substrate a third protective layer having a second opening over the first opening above the one conductor layer exposing the capacitor region and a connection portion between the stacked structures exposing the word line extraction region; and etching from the first An opening and a structure exposed in the second opening, and the inter-gate dielectric layer is used as an etch stop layer.