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TWI493671B - 具有支撐體的封裝基板及其製法、具有支撐體的封裝結構及其製法 - Google Patents

具有支撐體的封裝基板及其製法、具有支撐體的封裝結構及其製法 Download PDF

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Publication number
TWI493671B
TWI493671B TW101134448A TW101134448A TWI493671B TW I493671 B TWI493671 B TW I493671B TW 101134448 A TW101134448 A TW 101134448A TW 101134448 A TW101134448 A TW 101134448A TW I493671 B TWI493671 B TW I493671B
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TW
Taiwan
Prior art keywords
layer
disposed
electrical contact
contact pad
core layer
Prior art date
Application number
TW101134448A
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English (en)
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TW201314853A (zh
Inventor
Yuan Liang Lo
Wen Lung Lai
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Unimicron Technology Corp
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Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW101134448A priority Critical patent/TWI493671B/zh
Publication of TW201314853A publication Critical patent/TW201314853A/zh
Application granted granted Critical
Publication of TWI493671B publication Critical patent/TWI493671B/zh

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    • H—ELECTRICITY
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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Description

具有支撐體的封裝基板及其製法、具有支撐體的封裝結構及其製法
　　本發明係有關一種半導體封裝基板，尤指一種具有支撐體的封裝基板及其製法、與具有支撐體的封裝結構及其製法。
　　隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化（miniaturization）的封裝需求，係朝降低承載晶片之封裝基板的厚度發展。目前用於承載晶片之封裝基板可分為硬質材與軟質材，一般用於球閘陣列封裝（Ball Grid Array, BGA）之封裝基板係多選擇硬質材。
　　請參閱第1A至1D圖，係為習知雙層線路之封裝基板1a之製法之剖面示意圖。
　　如第1A圖所示，首先，提供一具有相對之第一表面13a與第二表面13b之芯層13，該芯層13之第一與第二表面13a,13b上分別具有銅層11a,11b。
　　如第1B圖所示，於該芯層13之第二表面13b上以雷射形成複數貫穿孔130，以令該第一表面13a之銅層11a外露於該些貫穿孔130。
　　如第1C圖所示，圖案化該銅層11a,11b，利用導電層10進行電鍍銅材，以於該芯層13之第一及第二表面13a,13b上分別形成第一及第二線路層12,14，且於該些貫穿孔130中形成導電通孔140以電性連接該第一及第二線路層12,14，又該第一及第二線路層12,14分別具有複數第一及第二電性接觸墊120,141。
　　如第1D圖所示，於該芯層13之第一及第二表面13a,13b上分別形成絕緣保護層15，且部分絕緣保護層15填滿該導電通孔140。該絕緣保護層15分別具有複數開孔150，以令該些第一及第二電性接觸墊120,141對應外露於各該開孔150，以製成該封裝基板1a。接著，於該些第一及第二電性接觸墊120,141之外露表面上分別形成表面處理層15a。
　　於後續製程中，如第1E圖所示，係於該絕緣保護層15上承載晶片17並藉由導線170電性連接該第二電性接觸墊141，再形成封裝膠體18以包覆該晶片17，且於該些第一電性接觸墊120上結合焊球19，以製成封裝結構1。為了符合微小化與可靠度之需求，於目前製程技術中，該芯層13之厚度可縮小至60μm。
　　惟，隨著微小化之需求增加，厚度為60μm之芯層13已無法滿足封裝件之微小化需求，但若使該芯層13之厚度小於60μm，該封裝基板1a之總板厚R將小於130μm，導致生產作業性不佳，例如：該封裝基板1a於各製程作業站中移動時容易卡板，而不利於生產，又即使能夠生產，在運送或封裝時也容易因厚度太薄而彎翹或破裂，導致無法使用或產品不良。
　　再者，為了有利於製作細間距線路，該銅層11a,11b的厚度薄至接近3μm，導致容易被雷射打穿。而為了避免雷射打穿該第一表面13a之銅層11a，通常會將雷射能量調小，以增加雷射擊發次數，卻因而造成製程時間延長，導致成本提高。
　　又，於習知封裝基板1a之製法中，因該貫穿孔130之深度過深，故不僅於製作該導電通孔140時，會造成電鍍銅性不佳，而產生包孔現象，且於該絕緣保護層15填入該導電通孔140時易有氣孔(void)現象。
　　因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明係揭露一種具有支撐體的封裝基板，係於其一側增設包含銅箔基板與強化板之支撐體，其中，該強化板具有結合該銅箔基板之銅層的介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層。
　　本發明復提供一種具有支撐體的封裝基板之製法，係包括：提供兩以其銅層相互疊置之銅箔基板；於該兩銅箔基板上結合強化板，該強化板具有包覆該兩銅箔基板以固定該兩銅箔基板之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層；於該第二金屬剝離層上形成複數第一電性接觸墊；於該第二金屬剝離層與該些第一電性接觸墊上形成具有相對之第一與第二表面之芯層，令該些第一電性接觸墊嵌埋於該芯層之第一表面；於該芯層之第二表面上形成具有複數第二電性接觸墊之線路層，且於該芯層中形成導電盲孔以電性連接該些第一電性接觸墊與線路層；於該芯層之第二表面與線路層上形成絕緣保護層，且令該些第二電性接觸墊外露於該絕緣保護層；沿該兩銅箔基板之側邊進行切割，令該兩銅箔基板相互疊置之銅層自動分開，以分離出兩封裝基板。
　　前述之具有支撐體的封裝基板及其製法中，該第一金屬剝離層係以物理方式結合該第二金屬剝離層。
　　前述之具有支撐體的封裝基板及其製法中，該芯層係為介電材。
　　前述之具有支撐體的封裝基板及其製法，可包括於該第二電性接觸墊之外露表面上形成表面處理層。
　　本發明又提供一種具有支撐體的封裝結構及其製法，係於前述封裝基板之絕緣保護層上設置晶片，且形成包覆該晶片之封裝膠體。
　　前述之具有支撐體的封裝結構及其製法中，該封裝基板可具有複數封裝單元，以用於切單製程，且該第一電性接觸墊之表面高度可低於該芯層之第一表面高度。
　　另外，前述之具有支撐體的封裝結構及其製法中，該晶片可電性連接該些第二電性接觸墊。
　　由上可知，本發明之具有支撐體的封裝基板及其製法與封裝結構及其製法，係藉由在該封裝基板上結合如銅箔基板與強化板之支撐體，不僅可使該芯層之厚度小於130μm，且可增加封裝基板之強度，以避免於運送時或封裝時因太薄而彎翹或破裂。
　　再者，於封裝後再移除該銅箔基板與強化板，此時之封裝基板之厚度係小於130μm，故相較於習知技術，可降低封裝結構之整體厚度，因而同時滿足產品微小化與可靠度之需求。
　　此外，相較於習知技術，本發明可直接以該第二金屬剝離層為導電途徑來電鍍，而無需於芯層上額外形成電鍍導線，故可簡化整體製程。
　　又，藉由在該封裝基板上結合銅箔基板與強化板，即使該芯層兩表面的銅箔之厚度太薄，於雷射製程時，因為底下還有第一金屬剝離層與第二金屬剝離層，而能有效將雷射的能量分散，所以仍不會打穿該第一電性接觸墊。故相較於習知技術，本發明可以較大雷射能量進行，以減少雷射擊發次數，因而有效減少製程時間，以降低成本。
　　另外，因該芯層之厚度可為超薄，故該導電盲孔之孔深極短，因而不會造成電鍍銅性不佳之問題，可避免產生包孔現象。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“側邊”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
　　請參閱第2A至2F圖，係為本發明之具有支撐體2b的封裝基板2之製法之剖視示意圖。
　　如第2A圖所示，首先，提供兩銅箔基板（Copper clad laminate, CCL）20與兩強化板21，各該銅箔基板20係具有絕緣層200及設於該絕緣層200相對兩側之銅層201,202，該兩銅箔基板20以其中一銅層201相互疊置，且各該強化板21具有介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212。
　　於本實施例中，該絕緣層200之材質可例如為雙順丁烯二酸醯亞胺/三氮阱（Bismaleimide triazine，簡稱BT），該絕緣層200之厚度可例如為100μm，該銅層201,202之厚度可例如為12um。
　　接著，於該兩銅箔基板20上分別壓合該強化板21之介電層210，令該兩介電層210合為一體以包覆該兩銅箔基板20，而固定該兩銅箔基板20，俾形成支撐體2b。
　　於本實施例中，該介電層210之厚度可例如為100um，該介電層210之材質可例如為預浸材（prepreg，簡稱PP）。再者，該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212，且該物理方式係為卡合、靜電、吸附、或黏著物等，亦即該第一金屬剝離層211與第二金屬剝離層212之間並無需藉蝕刻分離。又該第一金屬剝離層211與第二金屬剝離層212係為銅材，且兩者之厚度可為18μm及3μm。另外，有關銅箔基板之種類繁多，且為業界所熟知，故不再贅述。
　　如第2B圖所示，以該第二金屬剝離層212為導電途徑，於該第二金屬剝離層212上形成複數第一電性接觸墊22。
　　如第2C圖所示，於該第二金屬剝離層212與該些第一電性接觸墊22上形成芯層23，且該芯層23具有相對之第一表面23a與第二表面23b，令該些第一電性接觸墊22嵌埋於該芯層23之第一表面23a。
　　接著，於該芯層23之第二表面23b上形成具有複數第二電性接觸墊241之線路層24，且於該芯層23中形成複數導電盲孔240以電性連接該些第一電性接觸墊22與線路層24。
　　於本實施例中，該芯層23係為介電材，且有關線路製程之種類繁多，並無特別限制，故不詳述。
　　如第2D圖所示，於該芯層23之第二表面23b與線路層24上形成絕緣保護層25，該絕緣保護層25具有複數開孔250，以令該些第二電性接觸墊241對應外露於各該開孔250，以製成線路結構26。
　　接著，以該第二金屬剝離層212為導電途徑，於該開孔250中之第二電性接觸墊241上形成表面處理層25a。於本實施例中，形成該表面處理層25a之材質係為鎳/金(Ni/Au)、鎳鈀金(Ni/Pd/Au)或金等選擇，且其形成方式可為化鍍或電鍍等方式，若以化鍍方式形成，則該表面處理層25a之材質係為化鎳/金(Ni/Au)、化鎳鈀金(Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG)或直接浸金(Direct Immersion Gold, DIG)，或者，併用化鍍與電鍍方式，即以該第二金屬剝離層212為導電途徑，形成例如電鍍鎳/化鍍鈀/電鍍金的該表面處理層25a。
　　如第2E及2F圖所示，沿該兩銅箔基板20之側邊進行切割，如第2D圖所示之切割線L，令該兩銅箔基板20相互疊置之銅層201自動分開，以分離出上、下側之封裝基板2。
　　於本實施例中，上、下側均可取得複數個封裝基板2，且各該封裝基板2係具有複數封裝單元2a，以供後續封裝製程大批次量產使用，又該封裝基板2減去該銅箔基板20之厚度d與該強化板21之厚度y的所剩厚度（即該線路結構26之厚度h）係小於130μm。
　　再者，藉由疊置兩銅箔基板20，可同時製作兩批板量，以提升產能。
　　另外，如第2F’圖所示，於第2D圖之製程中，該絕緣保護層25具有一開孔250’，以令該些第二電性接觸墊241對應外露於該開孔250’。接著，於該第二電性接觸墊241上形成表面處理層25a，之後再進行第2E及2F圖之製程。
　　本發明復提供一種具有支撐體2b的封裝基板2，係包括：於相對兩側具有銅層201,202之銅箔基板20、設於該銅箔基板20之其中一銅層202上之強化板21、設於該強化板21上之第一電性接觸墊22、設於該強化板21與第一電性接觸墊22上之芯層23、設於該芯層23上之線路層24、以及設於該芯層23與線路層24上之絕緣保護層25。
　　所述之支撐體2b係包含該銅箔基板20與該強化板21。
　　所述之銅箔基板20之種類繁多，並無特別限制。
　　所述之強化板21具有結合該銅層202之介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212；於本實施例中，該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212。
　　所述之第一電性接觸墊22設於該第二金屬剝離層212上。
　　所述之芯層23係具有相對之第一表面23a與第二表面23b，以令該芯層23之第一表面23a結合該第二金屬剝離層212並嵌埋該第一電性接觸墊22；於本實施例中，該芯層23係為介電材。
　　所述之線路層24係設於該芯層23之第二表面23b上，且具有複數第二電性接觸墊241，又具有設於該芯層23中之導電盲孔240以電性連接該第一電性接觸墊22。
　　所述之絕緣保護層25係設於該芯層23之第二表面23b與該線路層24上，且該絕緣保護層25具有至少一開孔250,250’，以令該些第二電性接觸墊241外露於該開孔250,250’，俾供表面處理層25a形成於該開孔250,250’中之第二電性接觸墊241上。
　　由本發明之具有支撐體2b的封裝基板2之製法可知，一般欲製作厚度小於130μm之基板時，需重新配置新製程設備，因而增加製作成本。本發明之線路結構26之厚度h雖小於130μm，但藉由該銅箔基板20之厚度d與該強化板21之厚度y，以於製作該封裝基板2時，其整體厚度可大於或等於130μm，故可使用原先封裝基板製程所用之設備，因而不會增加製作成本。
　　再者，於封裝製程之前，該封裝基板2具有該銅箔基板20與該強化板21，以提升整體封裝基板2之強度，故相較於習知技術，本發明封裝基板2於運送時不會彎翹或破裂。
　　又，本發明之芯層23之厚度超薄（例如小於60μm），但藉由該銅箔基板20與該強化板21之設計，於形成該導電盲孔240前之雷射製程時，不會打穿該該第一電性接觸墊22，故可以較大雷射能量進行，以減少打發次數，因而有效減少製程時間，以降低成本。
　　另外，因該芯層23之厚度超薄，故該導電盲孔240之孔深極短，因而不會造成電鍍銅性不佳之問題，可避免產生包孔現象，且因該導電盲孔240之孔深極短，故可電鍍填滿銅，而無需將該絕緣保護層25填入該導電通孔240中，以避免氣孔(void)現象。
　　請參閱第3A及3A’圖，係為本發明之具有支撐體2b的封裝結構3a,3a’之剖視示意圖。
　　如第3A圖所示，接續第2F圖之製程，進行封裝製程，係於該線路結構26之絕緣保護層25上設置晶片27，且令該些第二電性接觸墊241作為打線墊，以藉由複數導線270電性連接該晶片27；接著，於該絕緣保護層25上形成封裝膠體28，以包覆該晶片27與導線270，俾形成具有支撐體2b的封裝結構3a。
　　再者，如第3A’圖所示，接續第2F’圖之製程，係令該些第二電性接觸墊241作為覆晶墊，且於該些第二電性接觸墊241上藉由導電凸塊270’設置並電性連接晶片27’；接著，於該芯層23與該晶片27’之間（或該開孔250’中）形成底膠28’以包覆該些導電凸塊270’。之後，於該絕緣保護層25上形成封裝膠體28，以包覆該晶片27’，俾形成另一種具有支撐體2b的封裝結構3a’。
　　另外，有關該第二電性接觸墊241與晶片之電性連接方式繁多，並不限於上述，特此述明。
　　請參閱第3B至3D圖，係可依需求，應用具有支撐體2b的封裝結構3a,3a’之後續製法之剖視示意圖。於本實施例係以第3A圖之封裝結構3a作說明。
　　如第3B圖所示，分離該第一金屬剝離層211與第二金屬剝離層212，以移除該銅箔基板20、該介電層210與第一金屬剝離層211，而外露出該第二金屬剝離層212。
　　於本實施例中，因該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212，故分離該第一金屬剝離層211與第二金屬剝離層212時，僅需以如剝離之物理方式進行分離。
　　如第3C圖所示，藉由蝕刻方式移除該第二金屬剝離層212，以外露出該芯層23之第一表面23a。
　　於本實施例中，一併蝕刻移除該第一電性接觸墊22’之部分表面，使該第一電性接觸墊22’之表面高度低於該芯層23之第一表面23a高度，因而可使該芯層23作為防焊層，而無需於該芯層23之第一表面23a上再製作絕緣保護層。
　　如第3D圖所示，沿各該封裝單元2a進行切割，如第3C圖所示之切割線S，以取得複數個另一型態之封裝結構3，且於該第一電性接觸墊22’上結合焊球29。
　　由應用具有支撐體2b的封裝結構3a之後續製法可知，因先於該絕緣保護層25上進行封裝製程，再移除該銅箔基板20與該強化板21，故藉由該線路結構26的厚度h係小於60μm，可有效降低該另一型態之封裝結構3之整體厚度。因此，相較於習知技術，本發明可依需求使該線路結構26之厚度小於60μm，以滿足微小化之需求。
　　再者，該封裝基板2具有該銅箔基板20與該強化板21，以提升整體封裝基板2之強度，故相較於習知技術，本發明封裝基板2於封裝時不會彎翹或破裂。
　　又，藉由該封裝基板2之厚度超薄，可具有電性信號傳遞路徑短、佈線密度增加、接腳數增加等優點。
　　本發明復提供一種具有支撐體2b的封裝結構3a,3a’，係包括：具有相對之第一表面23a與第二表面23b之芯層23、嵌埋且外露於該芯層23之第一表面23a之第一電性接觸墊22、設於該芯層23之第一表面23a上之支撐體2b、設於該芯層23之第二表面23b上之線路層24、設於該芯層23之第二表面23b與線路層24上之絕緣保護層25、設置於該絕緣保護層25上之晶片27,27’、以及設於該絕緣保護層25上之封裝膠體28。
　　所述之芯層23係為介電材。
　　所述之支撐體2b係包含絕緣層200、設於該絕緣層200相對兩側之銅層201,202、設於該其中一銅層202上之介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212。
　　所述之第一電性接觸墊22復結合該第二金屬剝離層212，且當移除該支撐體2b後，可於該第一電性接觸墊22’上結合焊球29。
　　所述之線路層24係具有複數設於該芯層23之第二表面23b上之第二電性接觸墊241、及設於該芯層23中以電性連接該第一電性接觸墊22之導電盲孔240。
　　所述之絕緣保護層25係設於該芯層23之第二表面23b與該線路層24上，且該絕緣保護層25具有至少一開孔250,250’，以令該些第二電性接觸墊241外露於該開孔250,250’，俾供表面處理層25a形成於該開孔250,250’中之第二電性接觸墊241上。
　　所述之晶片27,27’係藉由導線270或導電凸塊270’電性連接該些第二電性接觸墊241。
　　所述之封裝膠體28係包覆該晶片27,27’與導線270。另外，可於該芯層23與該晶片27’之間形成底膠28’以包覆該些導電凸塊270’。
　　綜上所述，本發明係藉由在該封裝基板上結合一包括銅箔基板與強化板的支撐體，不僅可使該芯層之厚度小於130μm，且可增加封裝基板之強度，以避免生產作業性不佳。
　　再者，於封裝後再移除該銅箔基板與強化板，故相較於習知技術，本發明因線路結構之厚度係小於130μm而可降低封裝結構之整體厚度，以同時滿足產品微小化與可靠度之需求。
　　此外，相較於習知技術，本發明可直接以該第二金屬剝離層為導電途徑來電鍍，而無需於芯層上額外形成電鍍導線，故可簡化整體製程。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,3,3a,3a’．．．封裝結構
1a,2．．．封裝基板
10．．．導電層
11a,11b,201,202．．．銅層
12．．．第一線路層
120,22,22’．．．第一電性接觸墊
13,23．．．芯層
13a,23a．．．第一表面
13b,23b．．．第二表面
130．．．貫穿孔
14．．．第二線路層
140．．．導電通孔
141,241．．．第二電性接觸墊
15,25．．．絕緣保護層
150,250,250’．．．開孔
15a,25a．．．表面處理層
17,27,27’．．．晶片
170,270．．．導線
18,28．．．封裝膠體
19,29．．．焊球
2a．．．封裝單元
2b．．．支撐體
20．．．銅箔基板
200．．．絕緣層
21．．．強化板
210．．．介電層
211．．．第一金屬剝離層
212．．．第二金屬剝離層
24．．．線路層
240．．．導電盲孔
26．．．線路結構
270’．．．導電凸塊
28’．．．底膠
d,y,h,R．．．厚度
L,S．．．切割線
　　第1A至1E圖係為習知封裝基板及封裝結構之製法的剖視示意圖；
　　第2A至2F圖係為本發明之具有支撐體的封裝基板之製法的剖視示意圖；其中，第2F’圖係為第2F圖之另一實施例；
　　第3A圖係為本發明之具有支撐體的封裝結構的剖視示意圖；其中，第3A’圖係為第3A圖之另一實施例；以及
　　第3B至3D圖係為本發明之應用具有支撐體的封裝結構之後續製法的剖視示意圖。
2．．．封裝基板
2a．．．封裝單元
2b．．．支撐體
20．．．銅箔基板
200．．．絕緣層
201,202．．．銅層
21．．．強化板
210．．．介電層
211．．．第一金屬剝離層
212．．．第二金屬剝離層
22．．．第一電性接觸墊
23．．．芯層
23a．．．第一表面
23b．．．第二表面
24．．．線路層
240．．．導電盲孔
241．．．第二電性接觸墊
25．．．絕緣保護層
250．．．開孔
25a．．．表面處理層
d,y,h．．．厚度

Claims (11)

  1. 一種具有支撐體的封裝基板，係包括：
    　　支撐體，係包含絕緣層、設於該絕緣層相對兩側之銅層、設於該其中一銅層上之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層；
    　　第一電性接觸墊，係設於該第二金屬剝離層上；
    　　芯層，係設於該第二金屬剝離層與該第一電性接觸墊上，且該芯層具有相對之第一表面與第二表面，令該第一電性接觸墊嵌埋於該芯層之第一表面；
    　　線路層，係設於該芯層之第二表面上，且具有設於該芯層中之導電盲孔以電性連接該第一電性接觸墊，又該線路層具有複數第二電性接觸墊；以及
    　　絕緣保護層，係設於該芯層之第二表面與該線路層上，且具有開孔，以令該些第二電性接觸墊外露於該絕緣保護層之開孔。
  2. 如申請專利範圍第1項所述之具有支撐體的封裝基板，復包括形成於該開孔中之第二電性接觸墊上之表面處理層。
  3. 一種具有支撐體的封裝結構，係包括：
    　　支撐體，係包含絕緣層、設於該絕緣層相對兩側之銅層、設於該其中一銅層上之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層；
    　　第一電性接觸墊，係設於該第二金屬剝離層上；
    　　芯層，係設於該第二金屬剝離層與該第一電性接觸墊上，且該芯層具有相對之第一表面與第二表面，令該第一電性接觸墊嵌埋於該芯層之第一表面；
    　　線路層，係設於該芯層之第二表面上，且具有設於該芯層中之導電盲孔以電性連接該第一電性接觸墊，又該線路層具有複數第二電性接觸墊；
    　　絕緣保護層，係設於該芯層之第二表面與線路層上，且具有開孔，以令該些第二電性接觸墊外露於該絕緣保護層之開孔；
    　　晶片，係設置於該絕緣保護層上，且電性連接該些第二電性接觸墊；以及
    　　封裝膠體，係設於該絕緣保護層上，以包覆該晶片。
  4. 如申請專利範圍第3項所述之具有支撐體的封裝結構，復包括形成於該開孔中之第二電性接觸墊上之表面處理層。
  5. 一種具有支撐體的封裝基板之製法，係包括：
    　　提供兩銅箔基板，各該銅箔基板係具有絕緣層及設於該絕緣層相對兩側之銅層，該兩銅箔基板以其銅層相互疊置；
    　　於該兩銅箔基板上結合強化板以形成支撐體，該強化板具有包覆該兩銅箔基板以固定該兩銅箔基板之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層；
    　　於該第二金屬剝離層上形成複數第一電性接觸墊；
    　　於該第二金屬剝離層與該些第一電性接觸墊上形成芯層，且該芯層具有相對之第一表面與第二表面，令該些第一電性接觸墊嵌埋於該芯層之第一表面；
    　　於該芯層之第二表面上形成線路層，且於該芯層中形成導電盲孔以電性連接該些第一電性接觸墊與線路層，又該線路層具有複數第二電性接觸墊；
    　　於該芯層之第二表面與線路層上形成絕緣保護層，並於該絕緣保護層中形成有開孔，且令該些第二電性接觸墊外露於該絕緣保護層之開孔；
    　　沿該兩銅箔基板之側邊進行切割，令該兩銅箔基板相互疊置之銅層自動分開，以分離出兩具有該支撐體的封裝基板。
  6. 如申請專利範圍第5項所述之具有支撐體的封裝基板之製法，其中，該第一金屬剝離層係以物理方式結合該第二金屬剝離層。
  7. 如申請專利範圍第5項所述之具有支撐體的封裝基板之製法，復包括於形成該絕緣保護層之開孔之後，於該開孔中之第二電性接觸墊上形成表面處理層。
  8. 一種具有支撐體的封裝結構之製法，係包括：
    　　提供一封裝基板，該封裝基板係包含支撐體及設於該支撐體上之線路結構，該支撐體係具有絕緣層、設於該絕緣層相對兩側之銅層、設於該其中一銅層上之介電層、設於該介電層上之第一金屬剝離層及設於該第一金屬剝離層上之第二金屬剝離層，且該線路結構結合於該第二金屬剝離層上；
    　　於該線路結構上設置晶片；以及
    　　於該線路結構上形成封裝膠體，以包覆該晶片。
  9. 如申請專利範圍第8項所述之封裝結構之製法，其中，該線路結構係包含：
    　　第一電性接觸墊，係設於該第二金屬剝離層上；
    　　芯層，係設於該第二金屬剝離層與該第一電性接觸墊上，且該芯層具有相對之第一表面與第二表面，令該第一電性接觸墊嵌埋於該芯層之第一表面；
    　　線路層，係設於該芯層之第二表面上，且具有設於該芯層中之導電盲孔以電性連接該第一電性接觸墊，又該線路層具有複數第二電性接觸墊；以及
    　　絕緣保護層，係設於該芯層之第二表面與線路層上，且具有開孔，以令該第二電性接觸墊外露於該絕緣保護層之開孔，並令該些第二電性接觸墊電性連接該晶片。
  10. 如申請專利範圍第9項所述之具有支撐體的封裝結構之製法，復包括於該開孔中的第二電性接觸墊上形成表面處理層。
  11. 如申請專利範圍第8項所述之具有支撐體的封裝結構之製法，其中，該封裝基板係具有複數封裝單元，以用於切單製程。
TW101134448A 2011-09-30 2012-09-20 具有支撐體的封裝基板及其製法、具有支撐體的封裝結構及其製法 TWI493671B (zh)

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916422B2 (en) * 2013-03-15 2014-12-23 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
CN204014250U (zh) * 2014-05-16 2014-12-10 奥特斯(中国)有限公司 用于生产电子元件的连接系统的半成品
JP6358887B2 (ja) * 2014-07-31 2018-07-18 新光電気工業株式会社 支持体、配線基板及びその製造方法、半導体パッケージの製造方法
TWI570816B (zh) * 2014-09-26 2017-02-11 矽品精密工業股份有限公司 封裝結構及其製法
TWI585923B (zh) * 2014-10-03 2017-06-01 矽品精密工業股份有限公司 封裝基板、封裝結構及其製法
US9502344B2 (en) * 2014-10-06 2016-11-22 Viagan Ltd. Wafer level packaging of electronic device
TWI563577B (en) * 2014-10-09 2016-12-21 Phoenix Pioneer Technology Co Ltd Package structure and method of manufacture
TWI558286B (zh) * 2014-10-28 2016-11-11 恆勁科技股份有限公司 封裝結構及其製法
TWI550744B (zh) * 2014-12-04 2016-09-21 矽品精密工業股份有限公司 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法
JP2016213283A (ja) * 2015-05-01 2016-12-15 ソニー株式会社 製造方法、および貫通電極付配線基板
TWI632647B (zh) * 2016-01-18 2018-08-11 矽品精密工業股份有限公司 封裝製程及其所用之封裝基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1829420A (zh) * 2005-03-02 2006-09-06 三星电机株式会社 其中具有嵌入式电容器的印刷电路板及其制造方法
TW200845319A (en) * 2007-03-09 2008-11-16 Casio Computer Co Ltd Semiconductor device having semiconductor structure bodies on upper and lower surfaces thereof, and method of manufacturing the same
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877940A (en) * 1993-12-02 1999-03-02 Teledyne Industries Inc. Fabrication multilayer combined rigid/flex printed circuit board
US5505321A (en) * 1994-12-05 1996-04-09 Teledyne Industries, Inc. Fabrication multilayer combined rigid/flex printed circuit board
KR100302652B1 (ko) * 1998-09-11 2001-11-30 구자홍 플렉시블인쇄회로기판의제조방법및그방법으로생산한플렉시블인쇄회로기판
KR100333627B1 (ko) * 2000-04-11 2002-04-22 구자홍 다층 인쇄회로기판 및 그 제조방법
TW490820B (en) * 2000-10-04 2002-06-11 Advanced Semiconductor Eng Heat dissipation enhanced ball grid array package
KR100432715B1 (ko) * 2001-07-18 2004-05-24 엘지전자 주식회사 방열부재를 갖는 인쇄회로기판 및 그 제조방법
CN1224305C (zh) * 2001-10-31 2005-10-19 新光电气工业株式会社 半导体器件用多层电路基板的制造方法
CN100475004C (zh) 2003-05-23 2009-04-01 富士通株式会社 布线板制造方法
JP4541763B2 (ja) 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
TWI229920B (en) * 2004-04-12 2005-03-21 Phoenix Prec Technology Corp Electrical connection structure of embedded chip and method for fabricating the same
KR20060026130A (ko) * 2004-09-18 2006-03-23 삼성전기주식회사 칩패키지를 실장한 인쇄회로기판 및 그 제조방법
KR100688768B1 (ko) * 2004-12-30 2007-03-02 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조 방법
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
JP2007335698A (ja) 2006-06-16 2007-12-27 Fujitsu Ltd 配線基板の製造方法
US7750488B2 (en) * 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US9018667B2 (en) * 2008-03-25 2015-04-28 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and dual adhesives
US8207052B2 (en) * 2009-01-16 2012-06-26 Globalfoundries Singapore Pte. Ltd. Method to prevent corrosion of bond pad structure
TWI387027B (zh) * 2009-02-16 2013-02-21 Advanced Semiconductor Eng 無核心封裝基板及其製造方法
TWI390692B (zh) 2009-06-23 2013-03-21 Unimicron Technology Corp 封裝基板與其製法暨基材
JP5573429B2 (ja) * 2009-08-10 2014-08-20 住友ベークライト株式会社 無電解ニッケル−パラジウム−金めっき方法、めっき処理物、プリント配線板、インターポーザ、および半導体装置
US8805132B2 (en) * 2010-12-08 2014-08-12 International Business Machines Corporation Integrated circuit package connected to a data transmission medium

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1829420A (zh) * 2005-03-02 2006-09-06 三星电机株式会社 其中具有嵌入式电容器的印刷电路板及其制造方法
TW200845319A (en) * 2007-03-09 2008-11-16 Casio Computer Co Ltd Semiconductor device having semiconductor structure bodies on upper and lower surfaces thereof, and method of manufacturing the same
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same

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