TWI455148B - Integrated device for accessing multi-port input read/write event - Google Patents

Description

Integrated device for accessing multiple input and read and write events

The present invention relates to an integrated device, and more particularly to an integrated device for accessing multiple input and write events using a static random access memory (SRAM).

Static Random Access Memory (SRAM) is often used as a cache memory because of its high read/write speed, no need to perform refresh operations, increased CPU and GPU processing efficiency, and good anti-noise capability. use. With the advancement of the integrated circuit process and the development of materials science, the operating frequency and computing power of the integrated circuit are rapidly increased. Appropriately increasing the SRAM helps to reduce the number of times the CPU accesses the data, and the system generates heat reduction.

As shown in FIG. 1, a conventional system on a chip or a display driver IC often uses a dual-slice SRAM 2 for a processor, such as a microcontroller (Microcontroller Unit) 1, to perform reading and writing of data. . Because the number of double-stroke SRAM word lines and the number of bit lines are twice that of SRAM, and the number of transistors is more than that of SRAM, it has the disadvantages of complicated circuit and large occupied area.

Therefore, there is also a method as shown in Fig. 2, which uses the 單埠SRAM 3 plus a timing control circuit 4 to provide the microcontroller 1 for reading and writing data. The timing control circuit 4 outputs the read/write event that arrives first among A埠 or B埠 to the SRAM 3 to perform reading and writing, and suspends the input of another read/write event that arrives until the SRAM 3 is completed. After the read and write events are reached, the post-arrival read and write events are input and output to 單埠 SRAM 3. In this way, the timing of the timing control circuit 4 must be synchronized with the operating speed of the 單埠SRAM 3, and the microcontroller 1 must wait for the SRAM 3 to complete a read/write event before inputting the next read/write event into the timing control circuit. 4, and finally caused the overall speed of the system to decline.

As mentioned above, the traditional use of double-turn SRAM will result in an excessively large footprint, while the use of 單埠SRAM and timing control circuitry will result in a system speed drop.

In view of the above problems, the present invention provides an integrated device for accessing multiple input and write events, including: a SRAM; and an event queue connected to the SRAM having a plurality of inputs埠And a plurality of serial event storages for storing a read/write event for the SRAM received through the input ports.

In the integrated device for accessing a plurality of input and read and write events according to the present invention, the event queue further has an event execution unit connected between the plurality of serially connected event memories and the top SRAM. According to the execution speed of the 單埠SRAM, the data of the read/write event stored in the event storage is controlled to move to the 單埠SRAM.

Specifically, the event execution unit notifies the event execution unit of the previous stage of the event execution unit to output the next read and write event to be executed to the event execution unit when the read/write event is completed by the event SRAM. .

In an integrated device for accessing a plurality of input and read and write events according to the present invention, one of the plurality of event storages of the plurality of serially connected event storages does not store a read/write event With vacancies, it will pass The event storage of the previous stage outputs a read and write event stored to one of the non-first level event stores.

In the integrated device for accessing a plurality of input and write events according to the present invention, the event queue further has an event dispatcher having the plurality of inputs for inputting the plurality of read and write events; An output buffer sequentially outputs the plurality of read and write events to the plurality of serial event storages;

In the integrated device for accessing a plurality of input and write events according to the present invention, the event queue further has an event trigger for triggering the input that can be input first in the event dispatcher according to the read/write event. .

In the integrated device for accessing a plurality of input and read and write events according to the present invention, the event dispatcher further includes a priority processing logic circuit for setting a read/write event that is preferentially executed.

In the integrated device for accessing a plurality of input and write events according to the present invention, the event execution unit further controls an output distributor to determine that an output of the UI SRAM is transmitted through the complex output of the output distributor. An output in the output is output.

As described above, the present invention provides an architecture consisting of a 單埠SRAM and an event queue, while solving the problem of large area using a double 埠SRAM and a system speed reduction using a 單埠SRAM and a timing control circuit.

The above and other objects, features and advantages of the present invention will become more <

Figure 3 shows the architecture of the present invention using a 單埠SRAM and event queue for the microcontroller to read and write data. As shown in Figure 3, 單埠SRAM 3 There is an event queue 5 between the microcontroller 1 and the timing control circuit 4 of the prior art.

Figure 4 is a diagram showing the detailed architecture of the event queue 5 of the present invention. As shown in FIG. 4, the event queue 5 has an event dispatcher 51, an event trigger 52, a plurality of event stores 53a, 53b (four in the case of FIG. 4), and an event execution unit 54. A read/write event will arrive at the SRAM 3 via the event dispatcher 51, the event store 53a, the event store 53b, and the event execution unit 54 in sequence.

The event distributor 51 comprises two inputs 埠 DIN A, DIN B. The event trigger 52 includes two input control terminals CTL A, CTL B, which triggers the input of the event dispatcher 51 according to the read/write event, and can input the read/write event first. Therefore, the event dispatcher 51 sequentially outputs the read and write events of the two inputs 埠 DIN A, DIN B to the event storage 53a.

The event storage 53a can store a read/write event, including a shift end shift and a vacant end empty (not shown), and further includes a memory unit (not shown) to determine whether the event storage 53a has a vacancy. If there is a space, the read/write event is allowed to enter, and the input port of the event store 53a is closed. When the event store 53b of the next stage has a space, the read/write event is input to the event store 53b of the next stage and the user is set. With a vacancy, the input to open event store 53a allows for new read and write event inputs. The structure and function of the event storage 53b are the same as those of the event storage 53a, and the description thereof will not be repeated.

Therefore, in particular, when a read/write event output from the event dispatcher 51 is input to the event store 53a, if the event store 53b does not store a read/write event and has a vacancy, the event store 53b passes through the vacancy side. The empty output signal (for example, a high level signal) to the shift terminal shift of the event storage 53a notifies the event storage 53a to move the input read/write event to the event storage 53b; if the event storage 53b stores the read/write event In the case where there is no vacancy, the event storage 53b transmits a signal (for example, a low level signal) to the shift terminal shift of the event storage 53a through the empty end, and notifies the event storage 53a to store the input read/write event. The read/write event output by the event storage 53b is input to the event execution unit 54, and the output event storage 53b has a vacancy.

The event execution unit 54 includes a slot end empty, an output control end output control, and an execution end exec. The event execution unit 54 outputs the read/write event input from the event storage 53b to the input 埠DIN of the 單埠SRAM 3, and outputs a control signal to the control terminal CTL of the 單埠SRAM 3 to perform reading and writing. The event execution unit 54 controls whether the event storage 53b of the previous stage performs data movement according to the execution speed of the 單埠SRAM 3. Specifically, when the action terminal ACT of the 單埠SRAM 3 informs the execution end of the 單埠SRAM 3 that the read and write operations of the exec 單埠SRAM 3 are completed, the event execution unit 54 outputs a signal through the empty terminal (for example, a high level signal). ) to the shift terminal shift of the event storage 53b, the notification event storage 53b moves the input read/write event to the event execution unit 54. The event execution unit 54 further has a function of controlling the output of the output distributor 6. The event execution unit 54 outputs an output control signal to the output control terminal output control of the output distributor 6 through the output control terminal to determine the output of the SRAM 3. The output signal of the output enters the output of the output distributor 6 and is output by which of the two output ports.

With the above architecture, when a plurality of read and write events are input to the event queue 5, the read and write events are stored in the event storages 53a, 53b connected in series, so that only one event storage 53a (or 53b) has a space, micro The controller 1 can input all the read and write events of the double input into the event queue 5 without stopping to wait for the SRAM 3 to complete the read and write operations. The system processing speed can therefore be improved.

Further, in terms of the occupied area, the occupied area of the 單埠SRAM 3 is about 70% of the occupied area of the double 埠SRAM 2, and the use event 伫5 is only increased by about 10%, so the present invention uses 單埠The SRAM 3 has the advantage of having an area reduction compared to the event queue 5 conventionally using the double-turn SRAM 2.

In addition to using the 單埠SRAM and event queues to simulate dual-access SRAM in an event-driven manner, the present invention can also increase the number of event stores in the event queue to simulate a multi-access file register (file). Register). Furthermore, the present invention can also add a priority processing logic circuit to the event dispatcher to set the read and write events that cannot be waited for. Having thus described the preferred embodiments, the above embodiments are merely illustrative of the invention, and the scope of the invention is defined by the scope of the claims.

1‧‧‧Microcontroller

2‧‧‧Double SRAM

3‧‧‧單埠SRAM

4‧‧‧Sequence Control Circuit

5‧‧‧ event queue

51‧‧‧Event distributor

52‧‧‧ event trigger

53a, 53b‧‧‧ event storage

54‧‧‧Event Execution Unit

6‧‧‧Output distributor

DIN, DIN A, DINB‧‧‧ input埠

CTL, CTL A, CTL B‧‧‧ control terminal

Shift‧‧‧ shifting end

Empty‧‧‧vacancy

Exec‧‧‧executive

Output‧‧‧output

Output control‧‧‧output control terminal

ACT‧‧‧ action side

CTL‧‧‧ control terminal

Figure 1 shows the architecture that traditionally uses dual-turn SRAMs for microcontrollers to read and write data.

Figure 2 shows the architecture that traditionally uses 單埠SRAM for microcontrollers to read and write data.

Figure 3 shows the use of 單埠SRAM and event queues for the present invention. The controller performs the structure of reading and writing data.

Figure 4 is a diagram showing the detailed architecture of the event queue of the present invention.

3‧‧‧單埠SRAM

5‧‧‧ event queue

51‧‧‧Event distributor

52‧‧‧ event trigger

53a, 53b‧‧‧ event storage

54‧‧‧Event Execution Unit

6‧‧‧Output distributor

DIN, DIN A, DINB‧‧‧ input埠

CTL, CTL A, CTL B‧‧‧ control terminal

Shift‧‧‧ shifting end

Empty‧‧‧vacancy

Exec‧‧‧executive

Output‧‧‧output

Output control‧‧‧output control terminal

ACT‧‧‧ action side

Claims (7)

An integrated device for accessing a plurality of input and write events, comprising: a static random access memory (SRAM); and an event queue connected to the 單埠SRAM, having a plurality of input ports and a plurality of event storages connected in series, the event storages respectively storing a read/write event received by the input ports for the top SRAM, wherein the event queue has an event execution unit And connecting to the plurality of serially connected event storages and the 單埠SRAM, according to the execution speed of the 單埠SRAM, controlling the data of the read/write event stored in the event storage to move to the 單埠SRAM . The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event execution unit notifies the event execution unit before the read/write event is completed by the event SRAM. The event store outputs the next read and write event to be executed to the event execution unit. An integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein one of the plurality of event storages of the plurality of serially connected event stores is not the first level If there is no hang-up event for storing a read/write event, the event storage of the previous level is notified to output a read/write event stored to one of the event stores of the non-first level. The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event queue further has an event dispatcher having: the plurality of input ports for inputting And a plurality of read and write events; and an output buffer, sequentially outputting the plurality of read and write events to the A plurality of concatenated event stores. The integrated device for accessing a plurality of input and read and write events, as described in claim 4, wherein the event queue further has an event trigger, and the event dispatcher is triggered according to the read/write event. Enter the input 先 first. The integrated device for accessing a plurality of input and read and write events, as described in claim 4, wherein the event dispatcher further includes a priority processing logic circuit for setting a read/write event that is preferentially executed. The integrated device for accessing a plurality of input and read and write events, as described in claim 1, wherein the event execution unit further controls an output distributor to determine that an output of the UI SRAM is transmitted through the output. An output 埠 of the complex output 埠 of the splitter is output.