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TWI323826B - The manufacturing process of the combine of optical lens and chip - Google Patents

The manufacturing process of the combine of optical lens and chip Download PDF

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Publication number
TWI323826B
TWI323826B TW095142246A TW95142246A TWI323826B TW I323826 B TWI323826 B TW I323826B TW 095142246 A TW095142246 A TW 095142246A TW 95142246 A TW95142246 A TW 95142246A TW I323826 B TWI323826 B TW I323826B
Authority
TW
Taiwan
Prior art keywords
wafer
optical lens
bonding process
optical
image
Prior art date
Application number
TW095142246A
Other languages
English (en)
Other versions
TW200821740A (en
Inventor
Chang Chao-Chi
Original Assignee
Ether Precision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ether Precision Inc filed Critical Ether Precision Inc
Priority to TW095142246A priority Critical patent/TWI323826B/zh
Priority to US11/640,249 priority patent/US20080115880A1/en
Priority to US11/925,742 priority patent/US8013289B2/en
Publication of TW200821740A publication Critical patent/TW200821740A/zh
Application granted granted Critical
Publication of TWI323826B publication Critical patent/TWI323826B/zh
Priority to US13/219,589 priority patent/US8134118B2/en

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B7/00—Mountings, adjusting means, or light-tight connections, for optical elements
    • G02B7/02—Mountings, adjusting means, or light-tight connections, for optical elements for lenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Lens Barrels (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

1323826 九、發明說明： 【發明所屬之技術領域】 本發明係與光學鏡頭有關，更詳而言之是指一種 光學鏡頭與晶片結合製程者。 【先前技術】 按，如圖一所示，習知影像擷取單元1大體上係 由一光學鏡頭2與一影像感測元件（image sensor) 3 所構成，光學鏡頭2係固定於影像感測元件3上，包 含有若干鏡片4、一鏡筒（barrel)5與一鏡座 (holder)6,光學鏡頭2 —般係利用黏膠黏固於影像感 測元件3上，使影像感測元件3可位於焦深範圍内。 目前所知習知影像感測元件之封裝技術有以下若干方 式：利用晶片直接連接基板（chip on boad, COB)，以 及目前較為業界採用之捲帶封裝（tape carrier _ package, TCP)、玻璃覆晶（chip on glass, COG)及中華 民國發明公告第234237號「影像感測元件及其封裝方 法」、第228284號「影像感測元件之封裝結構及其晶 圓級封裝方法」等專利案所示之技術。前揭COB、TCP、 COG或專利前案等封裝方式，技術改良之重點多係針 對可簡化製程、降低製作成本，不過，即使封裝製程 略有簡化，效果仍不臻理想。 其次，習知影像擷取單元之組裝方式係將光學鏡 1323826 : 頭——對應黏接於封裝完成後之影像感測元件上，組 裝甚為費時。 【發明内容】 本發明之主要目的即在提供一種可解決前揭缺失 之光學鏡頭與晶片結合製程，其可一次產出多數影像 擷取單元，可有效簡化組裝製程、降低製作成本，甚 具經濟效益。 本發明之另一目的在於提供一種可解決前揭缺失 之光學鏡頭與晶片結合製程，其可確保影像感測元件 之潔淨及產品良率者。 緣是，為達成前述之目的，本發明係提供一種光 學鏡頭與晶片結合製程，包含有以下步驟提供晶圓： 該晶圓之上表面設有複數影像感測晶片；連接光學鏡 頭：於各該影像感測晶片上同時對應設置一光學鏡 • 頭，用以於該晶圓上形成複數影像擷取單元；分解晶 圓：以將各該影像感測晶片分離之方式分解晶圓’用 以可一次產出多數影像擷取單元。 【實施方式】 以下，茲舉本發明若干較佳實施例，並配合圖式 做進一步之詳細說明如後，其中： 請參閱圖二至圖四所示，本發明一較佳實施例之 1323826 【主要元件符號說明】 本發明： 光學鏡頭與晶片結合製程10 晶圓12 影像感測晶片14 光學鏡頭16 影像擷取單元18 光學鏡頭陣列組20 •提供晶圓100 連接光學鏡頭110 分解晶圓120 習知： 影像擷取單元1 光學鏡頭2 • 影像感測元件3

Claims (1)

  1. 十、申請專利範圍： 年，月Ί日修(更)正替換頁 1. 種光學鏡碩與晶片結合製程 驟： 提供晶圓：該晶圓夕L + τ 曰N之上表面設有複數影像感測晶 片； 連接光學鏡頭：係利用將具有多數光學鏡頭之一 光學鏡頭陣列組對應設置於晶圓上，而使個別光學鏡 頭同時設於各影像威測a y u ί/琢A列日日片上’用以於該晶圓上形成 複數影像擷取單元； /刀解曰日圓·以將各該影像感測晶片分離之方式分 解晶圓，用以可—次產出多數影像擷取單元。 2. 如申請專利範圍第丨項所述之光學鏡頭與晶片 結合製程’其中，分解晶圓之步驟中，係利用切割之 方式分解晶圓。 3. 如申請專利範圍第ί項所述之光學鏡頭與晶片 結合製程，其中，提供晶圓之步驟中，各該影像感測 晶片係石夕晶片。 4. 如申凊專利範圍第ί項所述之光學鏡頭與晶片 結合製程’其中該光學鏡頭陣列組係利用習知微電鑄 (LIGA )技術製作多數連接之鏡筒後再組裝鏡片而 成。 5. 如申請專利範圍第ί項所述之光學鏡頭與晶片 结合製程’其中該光學鏡頭陣列組係利用習知化學蝕 1323826 钟年1月7日修{更)正替換頁j 刻（Chemical etching)技術製作多數連接之鏡筒支再 組裝鏡片而成。 6.如申請專利範圍第1項所述之光學鏡頭與晶片 結合裝程其中，分解晶圓之步驟中，亦同時分解光 學鏡頭陣列組。
TW095142246A 2006-11-15 2006-11-15 The manufacturing process of the combine of optical lens and chip TWI323826B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW095142246A TWI323826B (en) 2006-11-15 2006-11-15 The manufacturing process of the combine of optical lens and chip
US11/640,249 US20080115880A1 (en) 2006-11-15 2006-12-18 Manufacturing process of the combining of optical lens and sensor chips
US11/925,742 US8013289B2 (en) 2006-11-15 2007-10-26 Lens array block for image capturing unit and methods of fabrication
US13/219,589 US8134118B2 (en) 2006-11-15 2011-08-26 Image capture unit and methods of fabricating a lens array block utilizing electrolysis

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095142246A TWI323826B (en) 2006-11-15 2006-11-15 The manufacturing process of the combine of optical lens and chip

Publications (2)

Publication Number Publication Date
TW200821740A TW200821740A (en) 2008-05-16
TWI323826B true TWI323826B (en) 2010-04-21

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TW095142246A TWI323826B (en) 2006-11-15 2006-11-15 The manufacturing process of the combine of optical lens and chip

Country Status (2)

Country Link
US (1) US20080115880A1 (zh)
TW (1) TWI323826B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8090250B2 (en) 2009-06-23 2012-01-03 Ether Precision, Inc. Imaging device with focus offset compensation
US8203791B2 (en) 2008-08-15 2012-06-19 Ether Precision, Inc. Image capturing unit and lens assembly

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8013289B2 (en) 2006-11-15 2011-09-06 Ether Precision, Inc. Lens array block for image capturing unit and methods of fabrication
US9100501B2 (en) * 2007-02-12 2015-08-04 Qualcomm Incorporated Methods and systems for performing authentication and authorization in a user-device environment

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US5952778A (en) * 1997-03-18 1999-09-14 International Business Machines Corporation Encapsulated organic light emitting device
JP3290375B2 (ja) * 1997-05-12 2002-06-10 松下電器産業株式会社 有機電界発光素子
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8203791B2 (en) 2008-08-15 2012-06-19 Ether Precision, Inc. Image capturing unit and lens assembly
US8090250B2 (en) 2009-06-23 2012-01-03 Ether Precision, Inc. Imaging device with focus offset compensation

Also Published As

Publication number Publication date
TW200821740A (en) 2008-05-16
US20080115880A1 (en) 2008-05-22

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