TWI232472B - Metal-insulator-metal (MIM) capacitor and fabrication method for making the same - Google Patents

Abstract

A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.

Description

1232472 V. Description of the invention [Technical Field] The present invention relates to a metal-insulator-metal (hereinafter referred to as M I μ) capacitor structure, especially a M having a high capacitance density. IM capacitor structure and its manufacturing method. [Prior art 1 Capacitive elements are often used as integrated electronic circuits in integrated circuits such as radio frequency IC (r a d i 〇 f r e q u e n c y i n t e g r a t e d circuits, RF I C) or single crystal microwave ic (m 0nol ithi c microwave integrated circuits, MMIC). Common capacitor structures include metal-oxide-semiconductor (MOS) capacitors, P-N junction capacitors, and M I M capacitors. Among them, M I M capacitors can provide better electrical properties than M0S capacitors and P-N junction capacitors in some applications. This is because M0S capacitors and P-N junction capacitors are limited by their own structure. The problem is that a depleted layer (de ρ 1 eti ο η 1 ayer) is generated in the semiconductor electrode during operation, which causes its frequency characteristics to be limited. In comparison, MIMO capacitors can provide better frequency and temperature characteristics. In addition, MIM capacitors can be formed at the metal interconnect stage, which also reduces the difficulty or complexity of integrating with the CMOS front-end process. Structurally, the MIM capacitor includes a capacitor insulation layer, such as a pecVD dielectric layer, which is disposed between the lower electrode and the upper electrode. Μ I Μ capacitors often require

Page 7 1232472 V. Description of the invention (2) One '-one-one-one must occupy a considerable area of the wafer. In order to increase the circuit to reduce the cost, the MIM capacitor must be developed towards a high capacitance density (capac ^ a ^ ce density) in order to increase the circuit density. A past method to reduce the thickness of the PECVD dielectric layer (td) goes against increasing the capacitance density / (\ Gk / td). However, this method has limited effectiveness. This is due to the fact that the low dielectric layer thickness (t d) creates new problems, such as high leakage current and poor RF tangent coefficient loss. Another method to increase the capacitance density of MIM capacitors is to use a high dielectric constant capacitor dielectric layer. For example, U.S. Patent No. 6 2 32 197 discloses a MIM capacitor and its function to improve a mixecj mode capacitor in a logic circuit. Among them, the lower electrode of the capacitor is polycrystalline silicon (Polycide) / 'The upper electrode of the capacitor is metal. The capacitor dielectric layer may be silicon oxide, nitride nitride, hydroxide hydroxide (S i 0 N), or an oxide group (t a n t a 1 u m ο X i d e). Among them, silicon oxide, silicon nitride, and silicon hydroxide can be low-pressure chemical vapor deposition (LPCVD) > plasma enhanced chemical vapor deposition (p 1 asmaenhancedchemica 1 vapor deposition 'PECVD), or It is formed by high-density plasma chemical vapor deposition (high-density plasma CVD, HDPCVD). The thickness of the capacitor dielectric layer is between about 100 and 500 angstroms. U.S. Patent No. 6 4 5 9 1 17 discloses a M I M capacitor with a high quality factor (Q f a c t 〇 r). The capacitor dielectric layer is made of silicon hydroxide (Si ON). Compared with silicon oxide, silicon hydroxide has a relatively high dielectric constant. 1232472 V. Explanation of the invention (3) Constant. U.S. Patent No. 6 4 6 8 8 5 8 discloses a method for forming a capacitor structure of M I M, which uses platinum (ρ 1 atinum) as the material of the capacitor upper and lower electrodes, and uses a dielectric constant material such as T a 205, B a T i 0 3 as the valley dielectric layer. Ta 20 5 and BaTi 03 are both deposited by chemical vapor deposition to a thickness of about 50 to 200 angstroms. However, the aforementioned conventional method of changing the material of the capacitor is relatively expensive. Therefore, the industry still needs a new MI capacitor structure and manufacturing method that can save costs and increase the capacitance density of MI capacitors. [Content] Therefore, the main object of the present invention is to provide an improved MEMS capacitor structure and a manufacturing method thereof. The main object of the present invention is to provide a MIMO capacitor structure capable of doubling the unit capacitance value and a manufacturing method thereof. According to a preferred embodiment of the present invention, the present invention provides a metal-insulator-metal (MI) capacitor including a first metal layer; a first capacitor dielectric layer disposed on the first metal layer; a second A metal layer is stacked on the first capacitor dielectric layer, wherein the first metal layer, the first capacitor dielectric layer, and the second metal layer constitute a capacitor structure; a second capacitor 1232472 5. Description of the invention ( 4) a dielectric layer disposed on the second metal layer; and a third metal layer stacked on the second capacitor dielectric layer, wherein the second metal layer, the second capacitor dielectric layer and the The third metal layer constitutes an upper capacitor structure; wherein the first metal layer and the third metal layer are electrically connected to a first capacitor terminal of the M I M capacitor, and the second metal layer is electrically connected to the M I M capacitor Second Capacitor End The present invention also proposes a method for manufacturing a metal-insulator-metal (MI) capacitor, which includes providing a substrate; and forming a first metal layer and a first capacitor dielectric layer in this order on the substrate. , The second metal layer, the second capacitor dielectric layer, Three metal layers and a cap layer; etching the cap layer, the third metal layer, and the second capacitor dielectric: a rabbit layer, the second metal layer, and the first capacitor dielectric layer until the & first metal is exposed Layer to form an upper capacitor structure composed of the third metal layer, the second capacitor dielectric layer and the second metal layer; a part of the upper capacitor structure is covered with a photoresist, and the photoresist It is defined that the first metal layer is about to form an electrode plate shape pattern of a capacitor structure; the first metal layer and the cap layer, the third metal layer and the second capacitor dielectric layer which are not covered by the photoresist are etched ; And removing the photoresist. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to limit the present invention.

Page 10 1232472 V. Description of the invention (5) [Performance method] Please refer to Fig. 1. Fig. 1 is a schematic diagram of another aspect of the structure of the capacitor in the preferred embodiment of the present invention. In the present invention, the IM capacitor structure 10 includes a first metal layer 1 2 ′. According to a preferred embodiment of the present invention, the first metal layer 12 may be a second metal layer (M eta 1 3 ) Or a fourth layer of metal (μ eta 1 4), but is not limited thereto, and the first metal layer 12 may be disposed on a bottom layer 100, such as an inter-metal dielectric (IMD). The second metal layer 14 is disposed on the first metal layer 12 and is electrically insulated from the first H layer 12 by a first capacitive dielectric layer 13. The third metal layer 6 is disposed above the second metal layer 14 and is electrically insulated from the second metal layer 14 through a second capacitor dielectric layer 15. The third metal layer 16 is covered with a cap layer 22, which may be made of silicon nitride or silicon oxide. The above M IM capacitor structure 10 is disposed in a metal interlayer dielectric layer 120 deposited on a bottom layer 1000. The first metal layer 1 2 of the above MI capacitor structure 10, the first capacitor dielectric layer 13 and the second metal layer 14 constitute a first capacitor (C1), and the second metal layer 14 and the second capacitor layer The electrical layer 15 and the third metal layer 16 constitute a second capacitor (C2). The first metal layer 12 of the above MI capacitor structure 10 is electrically connected to the first terminal line (firsttermina 1) 4 2 through a metal via (ν ia) 3 1 passing through the interlayer dielectric layer 1 2 0, The second metal layer 1 4 is electrically connected to the second terminal 4 4 through a metal via (via) 3 2 passing through the interlayer dielectric layer 1 2 0, and the third metal layer 1 6 Through a metal interlayer dielectric layer 1 2 0 and

1232472 V. Description of the invention (6) —------------ Cap iayer 2 2 on the metal layer 16 2 via 3 ^ The first terminal line ( firsttermina 1) 4 2 Electrical connection. In other words, in the present invention, the first gold exhibition layer 12 and the third gold lip layer 16 are connected to each other to form the first metal layer 12 and the third metal layer 16 above and below the second metal layer 1 4 The sandwiched structure resembles a sandwich.

Referring to FIG. 2 to FIG. 11, the present invention also provides a method for making M! M electric and structure in FIG. First, as shown in FIG. 2, a substrate (not shown) is provided. The substrate has a bottom layer 100 (for example, a metal dielectric layer (IMD)). Next, a first metal layer 12, a first capacitor dielectric layer 13, a second metal layer 14 and a second capacitor dielectric layer 15, a third metal layer 16 and a cap layer are formed on the bottom surface of the bottom surface. In a preferred embodiment of the present invention, the first gold lip layer 12 is a three-layer metal wire (Metal 3) with a thickness of about 500 angstroms. However, those skilled in the art should understand that the present invention does not Limited to this. The second metal layer 14 and the metal layer 16 may be made of metal such as titanium / titanium nitride (Ti / T) with a thickness of about 100 angstroms, but are not limited thereto. The cap layer 22 according to the present invention Σ "The preferred embodiment is composed of silicon nitride, but in other embodiments, oxidation = can also be used. According to a preferred embodiment of the present invention, the first electrical input layer 13 and the second capacitor dielectric layer 15 is a PECVD dielectric layer. Among them, the first capacitive dielectric layer 13 and the second capacitive dielectric layer 15 may also be constructed and constructed of a suitable capacitive dielectric material. Display, and then using yellow light and etching process, the first capacitor dielectric

Page 121232 V. Description of the invention (7) The stacked film structure composed of the electrical layer 13, the second metal layer 14, the second, the capacitor dielectric layer 15, the third metal layer 16 and the cap layer 22 is defined as The desired capacitor structure is 50. The etching stops on the first metal layer 12 after the first capacitor dielectric layer 13 is etched. As shown in FIG. 4, it is next on the capacitor structure 50 formed by the first capacitor dielectric layer 1 3, the second metal layer 14, the second capacitor dielectric layer 15, the third metal layer 16, and the cap layer 22, and A photoresist layer is formed on the first metal layer 12 and exposed and developed to form photoresist masks 60 a and 60 b. The photoresist mask 60 a is used to define the pattern of the first metal layer 12 And size, and it also covers a part of the capacitor structure 50, as shown in FIG. 5, which shows the shape of the photoresist mask 60a in FIG. 4 and its upper capacitor structure 50 (FIG. 5 only indicates the top cover layer) 22). The photoresist mask 60b defines other circuits of the third layer of metal (m e t a 1 3). As shown in FIG. 6, the photoresist masks 60a and 60b are used as etching masks, and a metal etching process is performed to etch the first metal layer 12 not masked by the photoresist masks 60a and 60b. The lower capacitor structure 70 and the lead 210 are formed. The lower capacitor structure 70 and the previously formed upper capacitor structure 50 form a sandwich-stacked capacitor structure 10. Please refer to Fig. 7. Fig. 7 is a schematic elevation view of the capacitor structure shown in Fig. 6 rotated by 90 degrees at 10 degrees. As shown in FIG. 7, the capacitor structure 50 on the portion not covered by the photoresist mask 60 a also uses the third metal layer 16 and the cap layer 22 as an etching buffer layer in the above-mentioned etching process of the metal wire. Etched to the second capacitor

Page 13 1232472 V. Description of the invention (8) The electric layer 15 makes the area of the second metal layer 14 smaller than that of the first metal layer 12 and the area of the third metal layer 16 smaller than that of the second metal layer 1 of 4 area. In other embodiments, the etching may etch through the second capacitive dielectric layer 15 and etch to the second metal layer 14. As shown in FIG. 8 and FIG. 9, FIG. 9 is a schematic elevation view of the capacitor structure 10 rotated by 90 degrees in FIG. 1 20, and then a plurality of metal vias 31, 32, 33, and 31 are formed in the metal interlayer dielectric layer 120, wherein the metal via 31 is electrically connected to the first metal 膺 12 and the metal via 32 is electrically connected to the second The metal layer 14 and the metal vias 33 are electrically connected to the third metal layer 16 through the top cover layer 22, and the metal vias 3 1 0 are electrically connected to the wires 2 1 0. Finally, as shown in Figure 10 and Figure Η--, Figure 11 is also a schematic diagram of the elevation of the capacitor structure shown in Figure 10 rotated by 90 degrees by 10, and then the fourth layer is performed on the interlayer dielectric layer 120. The definition of metal (Metal 4) = a first terminal conductor 42 and a second terminal conductor 44 are formed above the capacitor structure 10, and a wire 41 is formed in the metal via 310, which is electrically connected to the wire 2 10. The first metal layer 2 and the third metal layer 6 of the capacitor structure 10 are electrically connected to the first terminal conductor 4 2 through the metal vias 31 and 33, and the second metal layer 14 of the capacitor structure ο The second terminal conductor 44 is electrically connected through the metal via 32. The above are only the preferred embodiments of the present invention.

1232472 V. Description of the invention (9) Equal changes and modifications made within the scope of the invention shall fall within the scope of the invention patent.

Page 15 1232472 Brief description of the diagrams Brief description of the diagrams Figure 1 is a schematic cross-sectional view of the capacitor structure of the IM capacitor in the preferred embodiment of the present invention. FIG. 2 to FIG. 11 are cross-sectional views illustrating a method for fabricating the capacitor of FIG. 1 by the present invention. Explanation of symbols of the drawings 10 Capacitor structure 12 First metal layer 13 First capacitor dielectric layer 14 Second metal layer 15 Second capacitor dielectric layer 16 Third metal layer 22 Cap layer 31, 32, 3 3 Metal guide 42 First terminal conductor 4 4 Second terminal conductor 50 Capacitor structure 60a, b Resistive shield 70 Capacitance structure 100 Bottom layer 121 Interlayer dielectric layer 210 Conductor 310 Metal via 410 Conductor

Page 16

Claims (1)

1232472 6. Scope of patent application 1. A metal-insulator-metal (ΜIM) capacitor comprising: a first metal layer; a first capacitor dielectric layer provided on the first metal layer; a second A metal layer is stacked on the first capacitor dielectric layer, wherein the first metal layer, the first capacitor dielectric layer and the second metal layer form a capacitor structure; a second capacitor dielectric layer is provided on On the second metal layer; and a third metal layer stacked on the second capacitor dielectric layer, wherein the second metal layer, the second capacitor dielectric layer and the third metal layer constitute an upper capacitor Structure; wherein the first metal layer and the third metal layer are electrically connected to a first capacitor terminal of the MI capacitor, and the second metal layer is electrically connected to a second capacitor terminal of the MI capacitor. 2. The MI capacitor as described in item 1 of the scope of the patent application, wherein the area of the second metal layer is smaller than the area of the first metal layer. 3. The MIM capacitor as described in item 1 of the scope of patent application, wherein the area of the third metal layer is smaller than the area of the second metal layer. 4. The MI capacitor as described in item 1 of the patent application scope, wherein the first capacitor dielectric layer is a PECVD dielectric layer. 5. The M IM capacitor as described in item 1 of the patent application scope, wherein the second capacitor Page 17 1232472 6. Scope of patent application The capacitive dielectric layer is a PECVD dielectric layer. 6. The MI capacitor according to item 1 of the scope of the patent application, wherein the thickness of the second metal layer is smaller than the thickness of the first metal layer. 7. The MIM capacitor as described in item 6 of the scope of the patent application, wherein the thickness of the second metal layer is about 1000 angstroms. 8. The M IM capacitor as described in item 6 of the patent application scope, wherein the second metal layer comprises titanium. 9. A method for manufacturing a metal-insulator-metal (MIM) capacitor, comprising: providing a substrate; sequentially forming a first metal layer, a first capacitor dielectric layer, and a second metal layer on the substrate. , A second capacitor dielectric layer, a third metal layer, and a cap layer; etching the cap layer, the third metal layer, the second capacitor dielectric layer, the second metal layer, and the first capacitor dielectric layer Until the first metal layer is exposed, thereby forming an upper capacitor structure composed of the third metal layer, the second capacitor dielectric layer and the second metal layer; a portion of the upper capacitor is covered with a photoresist Structure, and the photoresist defines that the first metal layer is about to form an electrode plate shape pattern of a capacitor structure; the first metal layer and the top cover layer, the Page 18 1232472 6. Scope of patent application The third metal layer and the second capacitor dielectric layer; and removing the photoresist. 10. The method for manufacturing a capacitor as described in item 9 of the scope of patent application, wherein the thickness of the second metal layer is smaller than the thickness of the first metal layer. 1 1. The method for manufacturing a capacitor as described in item 10 of the scope of the patent application, wherein the thickness of the second metal layer is about 1000 angstroms, and the thickness of the first metal layer is about 50,000. Aye. 1 2. The method for manufacturing a MI capacitor as described in item 9 of the scope of the patent application, wherein the first and second capacitor dielectric layers are PECVD dielectric layers. Page 19