TW202042359A - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes flexible substrate, a plurality of leads, a chip and a plurality of bumps. The flexible substrate has a chip bonding area. The leads are disposed on the flexible substrate and include a plurality of first leads and a plurality of second leads. The first leads and the second leads are arranged alternately along a first side of the chip bonding area. The chip is located in the chip bonding area with an active surface of the chip facing the flexible substrate. The bumps are disposed on the active surface of the chip and include a plurality of first bumps and a plurality of second bumps adjacent to a first edge of the active surface. The first bumps are bonded to the first leads, the second bumps are bonded to the second leads, and a width of one of the first bumps bonded to one of the first leads is the same as a width of one of the second leads adjacent thereto.

Description

Thin film flip chip package structure

The present invention relates to a packaging structure, and more particularly to a thin-film-on-chip packaging structure.

The chip on film (COF) package structure is a common package type of the driver chip of the liquid crystal display. With the increase in the number of bumps on the wafer, the increase in the number of pins, and the shrinking of the pin pitch, the layout of bumps and pins is increasingly restricted.

As far as the current size design of the bump and the pin is concerned, the width of the bump is designed to be greater than the width of the pin to ensure that the bump and the pin are connected to each other to maintain a sufficient joint area. Under the trend of Fine Pitch, the spacing between adjacent bumps will be reduced accordingly. Once machine accuracy errors or pin offsets occur, the existing spacing between adjacent bumps may be difficult Provide enough safety space or buffer space, so that the risk of bumps overlapping adjacent pins is greatly increased.

The invention provides a thin film flip chip packaging structure, which helps reduce the risk of bumps overlapping adjacent pins.

The chip-on-film package structure of the present invention includes a flexible substrate, a plurality of pins, a chip, and a plurality of bumps. The flexible substrate has a wafer bonding area. The wafer bonding area has opposite first and second sides. These pins are arranged on the flexible substrate. These pins include multiple first pins and multiple second pins. The first pins and the second pins are alternately arranged along the first side edge, and extend from the chip bonding area through the first side edge. The wafer is located in the wafer bonding area. The chip has an active surface, the active surface has opposite first and second edges, and the active surface faces the flexible substrate. The first edge is adjacent to the first side of the wafer bonding area, and the second edge is adjacent to the second side of the wafer bonding area. These bumps are arranged on the active surface of the chip. The bumps include a plurality of first bumps and a plurality of second bumps adjacent to the first edge. The first bumps are connected to the first pins, the second bumps are connected to the second pins, and the width of the first bump connected to one of the first pins is the same as that of the adjacent second pin. The widths of the pins are equal.

In an embodiment of the present invention, in the above-mentioned chip-on-film package structure in a direction parallel to the first edge, the second bumps and the first bumps are arranged alternately. The second bumps are closer to the center of the wafer than the first bumps, and the ends of the second pins are closer to the center of the die bonding area than the ends of the first pins.

In an embodiment of the present invention, the width of each of the above-mentioned second bumps is greater than the width of the correspondingly joined second pin.

In an embodiment of the present invention, the width of the first bump equal to the width of the adjacent second pin is less than or equal to the width of the first pin that is correspondingly joined.

In an embodiment of the present invention, the ratio of the width of the first bump equal to the width of the adjacent second pin to the width of the correspondingly joined first pin is between 0.8 and 1.

In an embodiment of the present invention, a second pin is provided between any two adjacent first pins or a first pin is provided between any two adjacent second pins.

In an embodiment of the present invention, the width direction of the adjacent first bumps and the width direction of the second pins are parallel to the first edge of the chip.

In an embodiment of the present invention, the aforementioned pins include a plurality of third pins. The third pins are arranged along the second side edge and extend from the chip bonding area through the second side edge. The bumps include a plurality of third bumps adjacent to the second edge, and the third bumps are connected to the third pins.

In an embodiment of the present invention, the above-mentioned thin film flip chip package structure further includes a solder mask layer. The solder mask is located on the flexible substrate and partially covers these pins. The solder mask has an opening to expose the wafer bonding area.

In an embodiment of the present invention, the above-mentioned chip-on-film packaging structure further includes a packaging compound. The encapsulant is filled at least between the chip and the flexible substrate.

Based on the above, the film-on-chip package structure of the present invention is designed to design the width of a part of the multiple bumps to be equal to the width of the adjacent pins. Under the premise of not affecting the lead spacing, the bumps and the adjacent The spacing between the pins can be increased. Once machine accuracy errors or pin offsets occur, there is enough space between the bumps and adjacent pins as a safe space or buffer space, which helps to reduce the bumps overlapping adjacent pins. Risks to improve the process yield and product reliability of the film-on-chip package structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is an enlarged schematic diagram of area A of FIG. 1A. Fig. 1C is a schematic cross-sectional view of Fig. 1B along the section line B-B'. In order to clearly show the connection relationship between the pins 120, the chip 130 and the bumps 140, the chip 130 and the solder mask 150 of FIG. 1A are presented by a perspective drawing method, and the packaging gel 160 is omitted.

1A to 1C, in this embodiment, the film-on-chip package structure 100 includes a flexible substrate 110, a plurality of pins 120, a chip 130, and a plurality of bumps 140. The flexible substrate 110 It can be made of polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), carbonate (polycarbonate, PC) or other suitable flexibility Made of materials. On the other hand, the flexible substrate 110 is used to carry the pins 120, wherein the flexible substrate 110 has a chip bonding area 112, and the chip bonding area 112 has a first side 112a and a second side 112b opposite to each other. .

Specifically, the pins 120 are disposed on the flexible substrate 110, and the pins 120 include a plurality of first pins 122 and a plurality of second pins 124, wherein the first pins 122 and the second pins 124 The two pins 124 are arranged alternately along the first side 112 a and extend from the chip bonding area 112 through the first side 112 a. That is, at least one second pin 124 is provided between any two adjacent first pins 122, or at least one first pin 122 is provided between any two adjacent second pins 124. In addition, the first pins 122 and the second pins 124 respectively have a section inside the wafer bonding area 112 and another section outside the wafer bonding area 112.

On the other hand, the length of each second pin 124 in the wafer bonding area 112 is longer than the length of each first pin 122 in the wafer bonding area 112. That is, the end 124a of each second pin 124 is closer to the center C of the wafer bonding area 112 than the end 122a of each first pin 122, or the end 124a of each second pin 124 is closer to the center C of the wafer bonding area 112 than the end 122a of each first pin 122. The end 122 a of the pin 122 is far away from the first side 112 a of the die bonding area 112. The chip 130 is located in the chip bonding area 112. The chip 130 has an active surface 130a. The chip 130 has its active surface 130a facing the flexible substrate 110 and is bonded to the chip bonding area through the bumps 140 provided on the active surface 130a. 112 of these pins 120 within.

Furthermore, the active surface 130a of the chip 130 has a first edge E1 and a second edge E2 opposite to each other. The first edge E1 is adjacent to the first side 112a of the chip bonding area 112, and the second edge E2 is adjacent to the chip bonding area 112. The second side 112b. The first edge E1 and the second edge E2 may be the long sides of the wafer 130, wherein the bumps 140 include a plurality of first bumps 142 and a plurality of second bumps 144 adjacent to the first edge E1. These first bumps 142 is connected to the first pins 122, and the second bumps 144 are connected to the second pins 124. Furthermore, in the direction D parallel to the first edge E1, the second bumps 144 and the first bumps 142 are arranged alternately, and the second bumps 144 are closer to the chip 130 than the first bumps 142. The central C. For example, in the direction D parallel to the first edge E1, the second bumps 144 are aligned with each other, the first bumps 142 are aligned with each other, and any second bump 144 is staggered at any first edge. Bump 142.

Based on the above-mentioned layout of bumps 140 and pins 120, the film-on-chip package structure 100 can meet the design requirements of high pin count, high bump count and fine pitch.

In this embodiment, the width 142W of the first bump 142 joined to one of the first pins 122 is equal to the width 124W of the adjacent second pin 124, and the adjacent first bump 142 is The width direction of the second pin 124 may be parallel to the first edge E1 of the wafer 130. Therefore, the adjacent first bump 142 and the second pin 124 maintain a relatively large distance. Once the machine accuracy error or pin offset occurs, the adjacent first bump 142 and the second pin 124 Enough spacing between the leads 124 is used as a safety space or buffer space, thus helping to reduce the risk of the first bump 142 overlapping the adjacent second lead 124, thereby improving the process yield and the thin film flip chip packaging structure 100 The reliability of the product.

For example, the width 142W of the first bump 142 and the width 124W of the second pin 124 may be 8 micrometers (micrometer, µm), but the invention is not limited thereto. On the other hand, the width 144W of each second bump 144 may be greater than the width 124W of the corresponding second pin 124 to be joined, so as to provide a better joining effect. For example, the width 144W of the second bump 144 may be 13 μm to 15 μm, but the present invention is not limited thereto. Since the width 144W of the second bumps 144 is designed to be greater than the width 124W of the second pins 124, if the pin offset occurs when the chip 130 is bonded to the pins 120, the second bumps 144 and the second pins A sufficient bonding area can still be maintained between the 124, so that a good bonding strength between the bump and the pin is maintained, and the degree of deviation of the pin and the bump when abutting is further suppressed.

In this embodiment, the width 142W of each first bump 142 and the width 122W of the correspondingly joined first pin 122 may be the same. In other words, the width 122W of each first pin 122 and the width 124W of the adjacent second pin 124 may be the same, for example, 8 microns, but the invention is not limited to this.

In this embodiment, the pins 122 may also include a plurality of third pins 126, and the bumps 140 include a plurality of third bumps 146 adjacent to the second edge E2. The third pins 126 may be arranged along the second side 112b and extend from the chip bonding area 112 through the second side 112b, wherein the third bumps 146 are bonded to the third pins 126 . On the other hand, in order to protect the pins 120 and prevent the pins 120 from being damaged or contaminated by foreign objects causing pin bridging, the thin film flip chip package structure 100 may further include a solder mask 150, wherein the solder mask 150 is located on the flexible On the substrate 110, these pins 120 are partially covered. The solder mask layer 150 exposes the chip bonding area 112. Further, the solder mask layer 150 has an opening 152, and the chip bonding area 112 is substantially defined by the opening 152 of the solder mask layer 150.

In addition, in order to protect the electrical contacts of the bumps 140 and the pins 120, and avoid the intrusion of moisture and pollution, the film-on-chip packaging structure 100 may further include a packaging compound 160, wherein the packaging compound 160 is at least filled in the chip 130 and flexible Between the substrates 110 and can further cover the periphery of the opening 152 of the solder mask 150 and the side surface of the chip 130.

FIG. 1D is a schematic partial top view of a chip on film package structure according to an embodiment of the invention. FIG. 1E is a schematic partial top view of a chip on film package structure of the prior art. In particular, the dotted pins in FIG. 1D are used to indicate the positions of the second pins 124 after they are offset, and the dotted pins in FIG. 1E are used to indicate that the second pins 1241 are offset. s position.

For example, if the width 142W of the first bump 142 is 8 microns, the width 144W of the second bump 144 is 13 microns, and the distance between the center of the first bump 142 and the center of the second bump 144 is 16 microns , The interval S1 between the first bump 142 and the second bump 144 is 5.5 microns, as shown in FIG. 1D. On the other hand, if the width W1 of the first bump 1421 and the width W2 of the second bump 1441 are both 13 μm, and the distance between the center of the first bump 1421 and the center of the second bump 1441 is 16 μm, then The interval S2 between the first bump 1421 and the second bump 1441 is 3 microns, as shown in FIG. 1E.

Continuing the above, the interval S1 (for example, 5.5 microns) between the first bump 142 and the second bump 144 is much larger than the interval S2 (for example, 3 microns) between the first bump 1421 and the second bump 1441. When the two pins 1241 are offset, the second pin 1241 is easily overlapped with the first bump 1421 adjacent thereto. Compared with this, since the interval S1 between the first bump 142 and the second bump 144 of this embodiment is relatively large, even if the second pin 124 is offset, the second pin 124 and the adjacent first There is still enough buffer space between the bumps 142, which helps prevent the second pin 124 from overlapping with the adjacent first bump 142.

2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention. Please refer to FIG. 2, the chip-on-film package structure 100a of this embodiment is similar to the chip-on-film package structure 100 of the above-mentioned embodiment, but the difference lies in: in the chip-on-film package structure 100a, the width of each first pin 122 122W is greater than the width 142W of the first bump 142 that is correspondingly joined. More specifically, the ratio of the width 142W of the first bump 142 to the width 122W of the first pin 122 to be joined may be between 0.8 and 1, that is, the width 142W of the first bump 142 is 8 for example. In the case of micrometers, the width 122W of the first pin 122 is, for example, between 8 micrometers and 10 micrometers, but the invention is not limited thereto. Since the width 122W of the first pins 122 is designed to be greater than the width 144W of the first bumps 142, if the chip 130 is bonded to the pins 120, if there is a pin offset, the first bumps 142 and the first pins 122 It can still maintain a sufficient bonding area between the bumps and the pins to maintain a good bonding strength.

In summary, the thin film flip chip package structure of the present invention designs the width of the first bump to be equal to the width of the adjacent second pin, and the first bump and the phase The distance between adjacent second pins can be increased. Once machine accuracy errors or pin offsets occur, there is enough space between the first bump and the adjacent second pin as a safe space or buffer space, which helps to reduce the first bump The risk of connecting the adjacent second pin is to improve the process yield and the product reliability of the film-on-chip package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b: Thin film flip chip package structure 110: Flexible substrate 112: wafer bonding area 112a: first side 112b: second side 120: pin 122, 1221: first pin 122a, 124a: end 122W: width of the first pin 124, 1241: second pin 124W: the width of the second pin 126: third pin 130: chip 130a: active side 140: bump 142, 1421: first bump 142W, W1: the width of the first bump 144, 1441: second bump 144W, W2: the width of the second bump 146: third bump 150: solder mask 160: Encapsulation colloid A: area C: Central D: direction E1: First edge E2: second edge

FIG. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is an enlarged schematic diagram of area A of FIG. 1A. Fig. 1C is a schematic cross-sectional view of Fig. 1B along the section line B-B'. FIG. 1D is a schematic partial top view of a chip on film package structure according to an embodiment of the invention. FIG. 1E is a schematic partial top view of a chip on film package structure of the prior art. 2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention.

110: Flexible substrate

112: wafer bonding area

112a: first side

120: pin

122: first pin

122W: width of the first pin

124: second pin

124W: the width of the second pin

130: chip

140: bump

142: The first bump

142W: the width of the first bump

144: second bump

144W: the width of the second bump

A: area

E1: First edge

Claims (10)

A film-on-chip packaging structure includes: The flexible substrate has a chip bonding area, and the chip bonding area has a first side and a second side opposite to each other; A plurality of pins are arranged on the flexible substrate, wherein the pins include a plurality of first pins and a plurality of second pins, and the first pins and the second pins are along The first side edges are staggered and extend from the chip bonding area through the first side edge; A chip is located in the chip bonding area, the chip has an active surface, the active surface has a first edge and a second edge opposite, and the active surface faces the flexible substrate, wherein the first edge is adjacent to the chip bonding The first side of the area, the second edge is adjacent to the second side of the wafer bonding area; and A plurality of bumps are disposed on the active surface of the chip, wherein the bumps include a plurality of first bumps and a plurality of second bumps adjacent to the first edge, and the first bumps are bonded to the The first pins, the second bumps are joined to the second pins, and the width of a first bump joined to one of the first pins is adjacent to the second The widths of the pins are equal. In the thin-film-on-chip package structure described in claim 1, wherein in a direction parallel to the first edge, the second bumps and the first bumps are staggered, and the second bumps The block is closer to the center of the chip than the first bumps, and the ends of the second pins are closer to the center of the bonding area of the chip than the ends of the first pins. In the chip-on-film package structure described in claim 1, wherein the width of each of the second bumps is greater than the width of the correspondingly bonded second pin. As claimed in the first item of the patent application, the width of the first bump that is equal to the width of the adjacent second pin is less than or equal to the width of the corresponding first pin width. The chip-on-film package structure according to claim 4, wherein the width of the first bump that is equal to the width of the adjacent second pin and the width of the first pin that is correspondingly joined The ratio of is between 0.8 and 1. As described in the first item of the scope of patent application, the thin film flip chip package structure, wherein a second pin is provided between any two adjacent first pins or a second pin is provided between any two adjacent second pins There is this first pin. According to the first aspect of the patent application, the width direction of the first bump and the width direction of the second pin are parallel to the first edge of the chip. In the thin film flip chip package structure described in claim 1, wherein the pins include a plurality of third pins, and the third pins are arranged along the second side edge and extend from the die bonding area The inside extends out through the second side edge, the bumps include a plurality of third bumps adjacent to the second edge, and the third bumps are connected to the third pins. As described in the first item of the patent application, the film-on-chip package structure further includes a solder mask layer on the flexible substrate and partially covering the pins. The solder mask layer has an opening to expose the chip bonding Area. As described in the first item of the patent application, the film-on-chip packaging structure further includes a packaging glue filled at least between the chip and the flexible substrate.

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