201112337 六、發明說明： 【發明所屬之技術領域】 本發明一般而言是關於半導體裝置或者積體電路，更 詳而言的，是關於高功率裝置。 參考前案 【先前技術】 側向雙擴散電晶體（Lateral Double-Diffused (LD) transistor)已於高電壓應用中獲得廣泛採用。對於高效能 的側向雙擴散電晶體而言，當電晶體導通時，期望具有低 >及極至源極（drain-~to-source)導通電阻（on-resistance ; Rdsd以最小化其功率散逸’並且期望具有高崩潰電壓 (breakdown voltage)以最大化其電壓耐受力（v〇ltage capabi 1 ity)。為了達到低没極至源極導通電阻，該高側向 雙擴散電晶體的通道應盡可能越短越好。 當製程技術演進至深次微米（例如：超過〇 35#m)# 常大型積體電路（VLSI)時，期望將高壓（HV)側向雙擴散電 晶體與低壓⑽電晶體製造於相同基板上。—般而言，用 於形成如互補式金屬氧化物半導體（_)的低壓裝置的製 程是用=形成高壓裝置。然而，f知的⑽s製程並不相容 於形成尚壓電晶體。舉例而言，製程覆蓋問題使得用以定 義該通道長度的高麼通道_以對準（alignment)。製程覆 蓋中的製程變異需要很大的製程窗a(prQcesswind〇w)。 形成短通道長度以達到餘極至源極導通 電阻（RdSon)變付困難。具去 H ’所用的薄閘極電極妨礙其本 94920 3 201112337 身作為硬遮罩（hard mask)，使得形成該通道阱的製程控制 進一步惡化。 由先前的討論可知，本發明期望提供形成有短通道長 度的可靠高壓裝置，以具有低汲極至源極導通電阻（RdSon)。 【發明内容】 本發明提供一種形成裝置的方法。該方法包含設置製 備有主動裝置區域（active device region)的基板。該主 動裝置區域包含閘極堆疊（gate stack)的閘極堆疊層，該 閘極堆疊層於閘極介電層上至少包括有閘極電極層。對應 於該閘極的第一遮罩設置於該基板上。該基板經圖案化， 以至少去除未經該第一遮罩保護的頂部閘極堆疊層的部 分。第二遮罩亦設置於該基板上，該第二遮罩具有開口， 該開口曝露出一部分之該第一遮罩與該頂部閘極堆疊層。 .通道阱藉由透過該開口與閘極堆疊層將離子注入該基板而 形成。 於另一實施例中，揭露了另一個形成裝置的方法。該 方法包含設置製備有主動裝置區域的基板。該主動裝置區 域於該主動裝置區域與閘極堆疊的閘極堆疊層的第一部分 中包含有經掺雜的漂移牌（doped dr i f t we 11)。該等閘極 堆疊層於該基板的表面上的閘極介電層上至少包含有閘極 電極層。對應於該閘極的第一遮罩設置於該基板上。該基 板經圖案化，以至少去除未經該第一遮罩保護的頂部閘極 堆疊層的部分。第二遮罩亦設置於該基板上，該第二遮罩 具有開口，該開口曝露出一部分之該第一遮罩與該頂部閘 4 94920 201112337 極堆疊層。通道阱藉由透過該開口與閘極堆疊層將離子注 入該基板而形成。 ；* 於再一實施例中，提供了一種裝置。該裝置包含製備 有主動裝置區域的基板。該主動裝置區域包含閘極堆疊， 該閘極堆疊於閘極介電層上具有閘極電極層。至少該閘極 電極層利用硬遮罩進行圖案化。該裝置亦包含經摻雜的通 道阱，其係置於該基板中而鄰近該閘極的第一邊緣。該閘 極的第一邊緣在該閘極下的通道阱的通道邊緣與該通道阱 重叠。該閘極的第一邊緣與該通道邊緣定義該裝置的有效 通道長度。該裝置亦包含鄰近該閘極的第二邊緣的經摻雜 的漂移阱。 .配合參照以下說明書與附加圖式，本發明上述這些或 其他目的與本發明說明書中所揭露的優點與特徵將變得清 楚明瞭。再者，可暸解到本說明書中所描述的各種實施例 的特徵並非獨立的，而能夠以各種組合或排列而存在。 【實施方式】 本發明的實施例一般而言是關於半導體裝置或積體電 路。更詳而言的，一些實施例是關於高功率裝置。舉例而 言，高.功率裝置包含側向雙擴散電晶體，如金屬氧化物電 晶體（M0S)。可採用該等高功率裝置作為切換電壓整流器 (switching voltage regulator)，以作為功率管理的應 用。該等側向雙擴散電晶體能夠輕易地被整合入裝置或積 體電路。該等裝置或積體電路可結合至例如消費性電子產 品中或與消費性電子產品共同使用，更具體而言，可應用 5 94920 201112337 於如行動電爷、正& °干板電腦以及個人數位助理（PDA)的可攜式 洎賈性產品。 •立第1圖顯不裝置的實施例的一部分1〇〇。如圖所示， 雜包含基板1〇1。嫩可包括痛。該基板 敍式绍祕/ p型摻雜物（p-typedopant)。亦可使用如矽 邑緣體上覆發⑽）的㈣或者其他類型的夷板 …該基板可製備有第-與第二區域110與 中’：第一區域包括低細)裝置區域，同時該： ;二、=括向壓(HV)裝置區域。該等區域可為其他類型 1置區域或者可設置額外的裝置區域。舉例而言^ ^錢化物(dual gate oxide; _裝置而形成門】 氧化物區域。該等雙閘極氧化物裳置可甲極 、、先。又或者，該等雙閘極氧化物裴置可僅包含高壓區、’、 於一個實施例中，該第一區域包括第—鱼-二域 ，動子區域㈣VeSUb_regl〇n)U2與116。該第一 一類型是互補的類型，形成互補類型的裝置。舉例一 該互補類型的裝置包括互補金屬氧化物半導體（二°與 置。形成非互補或其他類型的裝置亦是有用的。 放 該第一類型主動子區域包括例如n型主動子區域， =二類型主動子區域包括ρ型主動區域。該第—類型= ::區域包括經第二類型摻雜的請：該第二類 子區域包括經第一類型摻雜的阱124。舉存丨而_ J旳吕，該第一201112337 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to semiconductor devices or integrated circuits, and more particularly to high power devices. Reference [Prior Art] Lateral Double-Diffused (LD) transistors have been widely used in high voltage applications. For high performance lateral double diffused transistors, it is desirable to have low > and drain-to-source on-resistance (on-resistance; Rdsd to minimize its power when the transistor is turned on) Dissipating 'and expecting a high breakdown voltage to maximize its voltage withstand. In order to achieve low dipole to source on resistance, the channel of the high lateral double diffused transistor It should be as short as possible. When process technology evolves to deep sub-micron (eg, over 〇35#m)# often large integrated circuits (VLSI), high voltage (HV) lateral double diffused transistors and low voltages are expected. (10) The transistor is fabricated on the same substrate. In general, the process for forming a low voltage device such as a complementary metal oxide semiconductor (-) is to form a high voltage device with =. However, the (10)s process is incompatible. For example, the process coverage problem is such that the channel used to define the length of the channel is aligned. The process variation in the process coverage requires a large process window a (prQcesswind〇w Short-form The length of the track is difficult to reach the balance-to-source on-resistance (RdSon). The thin gate electrode used to remove H' prevents the body from being used as a hard mask to form the channel well. Process control is further aggravated. As will be appreciated from the foregoing discussion, the present invention contemplates providing a reliable high voltage device formed with a short channel length to have a low drain to source on resistance (RdSon). SUMMARY OF THE INVENTION The present invention provides a device for forming a device. The method includes disposing a substrate prepared with an active device region, the active device region including a gate stack of a gate stack, the gate stack layer being at least on the gate dielectric layer A gate electrode layer is included. A first mask corresponding to the gate is disposed on the substrate. The substrate is patterned to remove at least a portion of the top gate stack layer that is not protected by the first mask. The second mask is also disposed on the substrate, the second mask has an opening exposing a portion of the first mask and the top gate stack layer. Forming ions into the substrate through the opening and the gate stack layer. In another embodiment, another method of forming a device is disclosed. The method includes disposing a substrate on which an active device region is prepared. The first portion of the gate stack of the active device region and the gate stack includes doped dr ift we 11 which are stacked on the surface of the substrate. The gate electrode layer is included at least. The first mask corresponding to the gate is disposed on the substrate. The substrate is patterned to remove at least a portion of the top gate stack layer that is not protected by the first mask. The second mask is also disposed on the substrate, and the second mask has an opening exposing a portion of the first mask and the top gate 4 94920 201112337 pole stack layer. The channel well is formed by implanting ions into the substrate through the opening and the gate stack layer. ;* In yet another embodiment, a device is provided. The device comprises a substrate on which an active device region is prepared. The active device region includes a gate stack having a gate electrode layer stacked on the gate dielectric layer. At least the gate electrode layer is patterned using a hard mask. The device also includes a doped channel well disposed in the substrate adjacent the first edge of the gate. The first edge of the gate overlaps the channel well at the channel edge of the channel well under the gate. The first edge of the gate and the edge of the channel define the effective channel length of the device. The device also includes a doped drift well adjacent the second edge of the gate. The above and other objects and features of the present invention will become apparent from the description and appended claims. Moreover, it will be appreciated that the features of the various embodiments described in this specification are not independent, but can be present in various combinations or permutations. [Embodiment] Embodiments of the present invention generally relate to a semiconductor device or an integrated circuit. More specifically, some embodiments relate to high power devices. For example, a high power device includes a lateral double diffused transistor, such as a metal oxide transistor (M0S). These high power devices can be employed as switching voltage regulators for power management applications. The lateral double diffusing transistors can be easily integrated into the device or integrated circuit. The devices or integrated circuits can be incorporated into, for example, or used in conjunction with consumer electronics, and more specifically, 5 94920 201112337 can be applied to mobile computers, positive & A portable assistant for digital assistants (PDAs). • Part 1 of the embodiment of the first embodiment of the device is shown. As shown in the figure, the impurity includes the substrate 1〇1. Tenderness can include pain. The substrate is described as a p-typedopant. It is also possible to use (four) or other types of slabs such as smear (10) on the rim (the substrate can be prepared with the first and second regions 110 and the middle: the first region includes a low-fine device), and : ; 2, = bracketed pressure (HV) device area. These areas may be other type 1 zones or additional device areas may be provided. For example, ^ dual gate oxide ( _ device to form a gate) oxide region. These double gate oxides can be placed in the front, or first, the double gate oxide device It may comprise only a high pressure zone, 'in one embodiment, the first zone comprises a first fish-two domain, a mover zone (four) VeSUb_regl〇n) U2 and 116. The first type is a complementary type that forms a complementary type of device. For example, the complementary type of device includes a complementary metal oxide semiconductor (two-phase and two-phase. It is also useful to form a non-complementary or other type of device. The first type of active sub-region includes, for example, an n-type active sub-region, = two The type active sub-region includes a p-type active region. The first-type = :: region includes a second type doped: the second-type sub-region includes a first type doped well 124. J旳吕, the first
類型主動子區域包括p型摻雜阱，而該第二類型主動品 域包括η型摻雜阱。亦可使用其他組構的主動子區H 94920 6 201112337 型摻雜物可包含硼（B)、銦（In)或兩者的組合，同時n型摻 雜物可包含磷（Ρ)、砷（As)、銻（sb)或三者的纟且合。 第一類型的電晶體140設置於該第一_型主動子區域 中，而 而第二類蜇的電晶體150設置於該第二_型主動子區 域中。舉例而言，η型電晶體設置於具有P型摻雜拼的η 型主動子區域中，同時ρ型電晶體設置於具有η型推雜拼 的Ρ型主動子區域中。於一個實施例中，該等電晶體是M〇s 場效電晶體（M0SFET)。亦可使用其他類型的電晶體。 例如，電晶體包括閘極，該閘極於閘極介電材料142 上具有閘極電極144。該閘極電極包括例如多晶石夕 (polysilicon)。亦可使用如多晶石夕化物或金屬石夕化物等其 他類型的閘極電極材料。藉由將所欲的金屬斑夕b : 、 两珥多晶矽反應 可形成多晶石夕化物或者金屬石夕化物。可使用如 ,.,,、 , 録、欽或鎳 (mckel)等各種類型的金屬。亦可使用其他_型的間 極材料。再者，該閘極電極可摻雜有摻雜 Φ -fcs； _L a I , 4參雜該問極 =可取決於製程技術。例如，該閘極電極可摻 ^電晶體類型㈣雜物類型。亦可使用其他摻雜物類型 摻雜該閘極電極。該閘極介電材料可為矽氧化物(silic⑽ 二de)。亦可使用其他類型的閘極電.極或閘極介電材料。 2極電極材料與閘極介電材料可取決於製程技術。舉例 而吕’鈷矽化物閘極電極可用於η 1〇 」用於0.18微米與0.13微米製 牙王技術’同時鎳矽化物可用於〇 1 叩彳政米製程技術。亦可使 八他、'且構的閘極電極與閑極介電材料 該閘極的側壁可設置有側劈八 _ 巧叫土刀隔件148。該等側壁分 94920 7 201112337 隔件可包括如夕氧化物、石夕II化物或者兩者的組合的介電 材料。亦可使用其他類型的材料於該等側壁分隔件。 擴散區域146鄰近該閘極。該等擴散區域可作為該電 晶體的源極與汲極。可設置延伸擴散區域147。該等延伸 擴散區域可為淺擴散區域，於該等分隔件下方延伸。該第 一類型電晶體的擴散區域（包含該等延伸擴散區域）摻雜有 第一類型摻雜物，而該第二類型電晶體的擴散區域摻雜有 第二類型摻雜物。舉例而言，P型擴散區域係針對P型電 晶體而設置，而η型擴散區域係針對η型電晶體而設置。 該等擴散區域的深度與摻雜物濃度可例如取決於應用方式 (如電壓需求）。 該高壓區域包含高壓主動區域165。於一個實施例中， 該高壓主動區域包括第一類型主動區域。舉例而言，該高 壓主動區域包括η型主動區域。亦可設置ρ型高壓主動區 域。再者，可瞭解到，為了簡化起見該高壓區域僅描續 個主動區域，而該高壓區域可包含高壓主動區域或子區 域。舉例而言，該等高壓主動子區域可為用於互補類型高 壓裝置的互補類型高壓子區域。 設置如淺溝槽隔離（STI)區域的隔離區域180，以隔離 該等區域中的低壓與南壓區域以及該等區域内的主動子區 域。亦可使用其他類型的隔離區域。 於一個實施例中，該第一類型高壓主動區域至少包括 第一與第二部分。該第一部分包括第二類型高壓通道（或本 體）阱135，而該第二部分包括第一類型高壓漂移阱136。 8 94920 201112337 該高壓漂移阱可定義高壓裝置的類型。舉例而言，p型高 壓主動區域可具有η型高壓通道阱與p型高壓漂移阱。於 一個實施例中，第三或中間部分將該通道與漂移阱分隔 開。於其他實施例中，該第一與第二部分是相鄰接的部分。 舉例而言，該高壓通道與高壓漂移阱互相接觸。 深阱132可設置於該高壓主動區域中，.包圍該高壓通 道與漂移阱。一般而言，該深阱包括第一類型的摻雜物或 暑與該高壓裝置類型相同的摻雜物。該深阱可用以將該漂 移阱與該基板隔離。舉例而言，Ρ型裝置將具有η型深阱。 於一些情況下，該深阱可選擇性存在或者該深阱可包括該 第二類型或者與該高壓裝置類型相反類型的摻雜物。舉例 而言，於η型高壓裝置之情形中，該深阱可為ρ型或η型 深阱。所選擇的深阱的不同類型可取決於基板的類型。一 般而言，經ρ型摻雜的基板是用於製造裝置。當使用ρ型 基板時，可選擇該η型深阱。這是因為η型漂移阱已不同 於該ρ型基板。對於η型基板而言，ρ型深阱可用以將該 通道阱與該基板隔離。亦可使用其他組構的深阱。 如圖所示，第一類型高壓裝置設置於該第一類型高壓 主動區域中。於一個實施例中，該第一類型高壓裝置包括 側向雙擴散（LD)裝置，如LDM0S裝置。該高壓裝置包括具 有第一與第二邊緣179a至b或者多個側壁的閘極。 該閘極於高壓閘極介電材料172上包含有高壓閘極電 極174。該高壓閘極電極可包括多晶矽。亦可使用如多晶 矽化物或者金屬矽化物等其他類型的高壓閘極電極材料。 9 94920 201112337 可使用如鈷、鈦或鎳等各種 型的高壓閘極電極材料。再 Ί亦可使用其他類 物。例如，該向壓間極電極可捧雜有與該電晶體類型相同 的摻雜物類型。亦可使用換雜有其他摻雜物的高壓閘極電 極。該南壓閘極介電材料可切氧化物。亦可使用其他類 型的南壓閘極介電材料。 於一個實施例中’該高壓閘極電極材料與高壓閘極介 電材料可取決於CMOS製程及/或技術。於一個實施例中， 該高壓閘極電極材料與高壓閘極介電材料可取決於用於低 壓裝置的CMOS製程及/或技術。舉例而言，録石夕化物閘極 電極可用於0. 18與0· 13微米的製程技術，同時錄石夕化物 可用於0. 0 9微米製程技術。亦可使用其他組構的閘極電極 與閘極介電材料。 該閘極的側壁可設置有侧壁分隔件178。該等側壁分 隔件可包括如矽氧化物、矽氮化物或者兩者的組合的介電 材料。亦可使用其他類型的材料於該等側壁分隔件。 於一個實施例中，該高壓閘極（如閘極電極）、閘極介 電材料與分隔件的各種閘極元件具有與該低壓區域中的低 壓裝.置相同類型的材料。如此一來，提升了形成高壓與低 壓裝置的製程可相容性。 該高壓閘極與該高壓主動區域的第一及第二部分中的 通道和漂移阱部分重叠。漂移隔離區域180a可設置於該高 壓裝置的高壓側的漂移阱136内。該漂移隔離區域180a能 夠改善該高壓裝置因高電壓所造成的崩潰電壓。舉例而 10 94920 201112337 言，該漂移隔離區域特別用以承受超過大約ίο伏特的高電 壓應用。如圖所示，該漂移隔離區域180a置於該閘極下方 的漂移阱136中。亦可將該漂移阱置於其他位置，如部分 位於該閘極下方。 . 第一類型汲極擴散區域176b設置於該漂移隔離區域 18 0 a與隔離區域18 0之間，將該南壓主動區域與該向壓區 域中其他子主動區域隔離。第一類型的源極擴散區域176a 設置於該第一類型高壓主動區域的通道阱135中。可設置 源極延伸區域.177，其延伸於該高壓閘極的通道側（channe 1 s i d e)的分隔件下方。該第一類型源極與汲極擴散區域例如 包括用於p型高壓主動區域的p型擴散區域。亦可設置用 於η型高壓主動區域的η型擴散區域。取決於應用方式， 可選擇該等擴散區域的摻雜物深度與濃度。於一個實施例 中，擴散區域的摻雜物深度與濃度可相同於低壓裝置的摻 雜物深度與濃度。亦可使用其他摻雜物深度與濃度。 第二類型本體接觸區域171可設置於該高壓主動區域 的第一部分中。如圖所示，該第二類型本體接觸區域171 介於該源極擴散區域176a與該隔離區域180之間。該第二 類型本體接觸區域包括第二類型摻雜物。於一個實施例 中，該本體接觸區域的摻雜物深度與濃度可相同於該低壓 裝置的擴散區域。亦可使用其他摻雜物深度與濃度。該本 體接觸區域171提供電性耦合至該通道阱135。 該通道阱135的邊緣133延伸於該閘極的源極側 (source side)的閘極下面。該邊緣133可稱作為該通道阱 11 94920 201112337 的通道邊緣。該通道阱135的通道邊緣與該源極側的閘極 的第一邊緣179a定義了該高壓電晶體的通道，該通道具有 有效通道長度L。 於一個實施例中，該有效通道長度藉由離子注入（ion implantation)所控制，且自我對準（self_aligned)至該閘 極邊緣。舉例而言，利用注入遮罩（implant mask)透過該 閘極電極或者硬遮罩與該閘極電極注入摻雜物離子。於一 個實施例中，亦使用該注入遮罩以圖案化該高壓閘極的通 道邊緣。該有效通道長度可藉由所選定以滿足臨限電壓 (threshold voltage)與崩潰電壓需求的通道或本體注入 條件進行控制。舉例而言，可藉由降低傾斜角度 、注入能 量或者劑量等而得到較短的有效通道長度。 利用經自我對準至該注入的閘極邊緣的通道阱，可避 免製程覆蓋問題。能夠達到具有非常低的汲極至源極導通 電阻的非常短之有效通道長度，使得高電流能夠通過小面 積。此對於0. 35微米以下，如〇. 25微米、0· 18微米與0. 13 微米的製程技術特別有用。 具有降低的功率散逸的功率管理應用之較小面積需求 係能夠増進效能同時降低成本。 於一個實施例中，該有效通道長度L小於0. 4微米。 於另一實施例中，該有效通道長度小於.0. 3微米。於又一 實施例中，該有效通道長度小於〇. 25微米。例如，取決於 應用方式，亦可使用其他有效通道長度。 第2a至2g圖顯示用於形成裝置或積體電路1〇〇的製 12 94920 201112337 程的實施例的剖面圖。參照第2a圖，設置有基板101。該 基板可包括如經輕微p型掺雜的基板的矽基板。亦可使用 其他類型的基板，包含經η型摻雜的基板、矽鍺或絕緣體 上覆矽（SOI) 〇 如圖所示，第一與第二裝置區域11〇與16〇定義於該 基板上。該第一區域例如包括低壓裝置區域，同時該第二 區域包括高壓裝置區域。可設置其他類型的裝置區域或者 額外的裝置區域。又或者’蹿裝置可僅包含高壓區域。 該低壓裝置區域110可定義有第一與第二類型主動子 區域112與116。於一個實施例中，該第一與第二類型主 動子區域是互補類型的主動子區域，以形成如CM〇s裝置的 互補裝置。亦可形成非互褚或其他類型的裝置。 至於該高壓裝置區域16〇，高壓主動區域165係定義 於其中。於一個實施例中，該高壓主動區域165可為第一 或第二類型高壓主動區域。雖然僅描繪一個高壓主動區 域’.但是可瞭解到該高壓裝置區域可包含額外的高壓主動 區域或子區域1等高壓主動子區域可為互補的多個高壓 主動子區域。 该基板亦製備有多個隔離區域18〇，以將該等裝置區 域與其他主動裝置子區域分隔開。於―個實施例中，該; 隔離區域180包括多個淺溝槽隔離（STI)。可採用各種習知 製程以形成該等淺溝槽隔離區域。舉例而言，可利知 姓刻與遮罩技術來姓刻該基板，以形成多個溝槽，接著以 如石夕氧化㈣介騎料充料_。可實魏學機械研 94920 13 201112337 磨_)以去除_的介電材料’並且提供平坦的基板頂部 表面（substrate top surface)。亦可使用其他製程 料’以形成該等淺溝槽隔離。 =第2b射，形成有用於該裝置區域的主動區域的推 =(4 _呢11)。於一個實施例中，經第一類型摻雜的 阱m形成於該第二類型高麼主動 二類型摻雜的阱122形 a 千而''，工第 112巾。與h 成於該第—類型高壓主動子區域 而^^ 〜型換賴形成於該p型主動子區域中， /雜牌形成於該n型主動子區域卜 於該高壓主動區域 分。舉例而士 “165巾’至少包含第一與第二部 分對應於界㈣I P分對應於沒極部分，而該第二部 部分以將= 些實施例中，設置有第三或中間 第一與第二部分分隔開。又或者，該第-與第 -相，接的部分，而沒有中間部分。 的沒極部136形成於該高壓主動區域 漂移二例如為該高壓裝置的漂移醉。該 壓主動區域“二域相同的類型。於第一類型高 n^^月/肀，該漂移阱包括第一類型。舉例而言， ㈣壓主動區域所設置。 牌lir 可選擇性地設置於該漂移 至古m壯該’示移淺溝槽隔離區域置於該漂移阱中，以改 改善該高壓裝置二1舉:而言，該漂移淺溝槽隔離區域 談严務汽 '塞 朋/貝可罪度（breakdown re 1 i abi 1 i ty)。 "你〜’槽隔離區域可與其他淺溝槽隔離區域於同時形 14 94920 201112337 成。 深高壓阱132可設置於該高壓主動區域165中。如圖 所示，談深高壓阱132形成於整個高壓主動區域165中， 並且包圍該高壓主動區域165的第一與第二部分。該深高 壓阱具有與該漂移阱和該高壓主動區域相反的類型。於第 一類型高壓主動區域之情形中，該深阱包括第二類型。舉 例而言，p型深阱為η型高壓主動區域所設置。 各種阱的摻雜物深度與濃度皆可取決於例如應用方 式。舉例而言，較高電壓的應用方式可能需要較低的摻雜 物摻雜濃度與較深的阱深度。於一個實施例中，該深阱132 的深度大約3微米，具有大約5E16cm_3的摻雜物濃度。對 於漂移阱136而言，可能需要大約1. 5微米的深度，具有 大約5E17cnf3的摻雜物濃度。其他摻雜物深度與濃度亦可 用於該等阱。 如上所述，該等淺溝槽隔離區域形成於各種摻雜阱形 成之前。亦可使用如於形成各種掺雜阱後形成該等淺溝槽 隔離區域的其他製程方案摻雜阱。 可藉由離子注入形成摻雜阱。P型摻雜物可包含硼 (B)、BF2(硼與氟化合）、銦（In)或者三者的組合，同時η 型摻雜物可包含磷（Ρ)、砷（As)、銻（Sb)或三者的組合。一 般而言，第一與第二類型的主動區域是於個別製程中選擇 性地形成。舉例而言，該等η型區域可注入有η型摻雜物， 同時注入遮罩防止ρ型區域的摻雜。 於一個實施例中，該高壓區域的阱與該等低壓區域係 15 94920 201112337 分開形成。舉例而言，可首先形成t亥等低 該等高壓阱。亦可在形成該等低壓 -乂开，接著形成 阱。不同類型的低壓阱可形成於個別丨^呈1j形成該等高壓 的高壓阱亦可形成於個別製程中。舉= = 而不同類型 中的第一類型與第二類型阱於個別而°該低壓區域 >广 主入製程中形士' 地，該咼壓區域中不同類型的阱亦θ 々成。同樣 成。 〜於個別注入製程中形 可藉由單一注入製程或多道注入_ 。' 多道注入製程中，可於不同能量斤’私形成摻雜阱。於 矛王度注入換雜私 所欲的摻雜分佈（doping prof i ip、 ’以達到 ^ ° $ 手 、、士 實施高溫驅進（drive-in)製程以造'入製程’ 可採用單一注入製程以例如形成多個=雜::。 深啡而言’可以大約6E12cm、穆雜物濃度對？型 的能量程度注入磷，接著於大約11〇〇七進行 '約2〇〇〇Kev 亦可使用單-注入製程以形成其他類型的：兩小時驅進。 道注入製程形成多個阱。舉例而言；可藉由多亦可利用多 形成低壓阱。 日夕道注入製程 於第2c ϋ巾’該基板上形成有間極之各種居。 實施例中，該基板上形成有閘極介電層。診於一個 詹可包括石夕氧化物。亦可使用其他種類^的介電極介電 化梦)。又或者，可使用高k、低k或者介電材料=氡氣 對於1.8V閘極電壓電晶體而言，該閘極介電層。物。 可為大約30 *(A)。亦可使用其他厚*。該厚度的厚度 閘極電壓應用方式。舉例而言，較高的閘極取决於 可能i:迤 16 9的2〇 201112337 較厚的閘極介電層。於一個實施例中，該閘極介電層是藉 由熱氧化（thermal oxidation)而形成。亦可使用如化學氣 相沈積（CVD)的其他製程技術以形成該閘極介電層。 閘極電極層244沈積於該閘極介電層242上。於一個 實施例中，該閘極電極層包括多晶矽（p〇lysilic〇n ; P〇ly)。該閘極電極層244可形成為非晶層（amorph〇us)或 結晶層。對於非晶的沈積層，可實施接下來的處理以結晶 該沈積層。亦可使用其他類型的閘極電極材料。舉例而言， 可接著處理該多晶矽，以形成多晶矽化物或金屬閘極。該 閘極電極層的厚度可能為大約2〇〇〇埃以）或更低。於另一 實施例中，該閘極電極層妁厚度為大約25〇〇埃或更低。於 又一貫施例中，該閘極電極層的厚度為大約4〇〇〇埃或更. 低。舉例而言，於多晶矽化物閘極的實施例中，該多晶矽 可為大約2000埃，同時鎢為大約2000埃。亦可使用其他 厚度。可使用各.種製程技術以形成該閘極電極層。舉例而 吕，可藉由CVD沈積多晶矽，同時可藉由濺鍍 沈積金屬。取決於材料，亦可使用其他製程技術。 參照第2d圖，遮罩層288形成於該基板上，覆蓋該閘 極電極層。於-個實施财’該料層包括光阻。該遮罩 如所欲般進行圖案化。為了圖案化該遮罩層，可採用微影 技術（Ph〇t〇lith〇graphy)。舉例而言，該遮罩可透過微影 遮罩而選擇性地曝露於曝光源（exp〇sure s〇urce)。取決於 是否使用正或反光阻，可藉由顯影將經曝露或未經曝露的 部分去除。為了增進微影解析度（lith〇graphic 94920 17 201112337 resolution)，可於該遮罩層下設置ARC層（未顯示）。 該遮罩層288經圖案化以形成開口 289，以曝露該閘 極電極層244之一部分。於一個實施例中，該開口對應於 用於通道阱注入的開口。舉例而言，該遮罩層作為該通道 阱注入遮罩。可利用該遮罩層圖案化該ARC層。接下來圖 案化該ARC層亦為有用者。 於第2e圖中，以摻雜物注入該基板，以形成通道阱 135。於一個實施例中，注入有與該高壓主動區域的類型相 反的摻雜物。舉例而言，將p型摻雜物注入該η型高壓主 動區域的ρ型深阱。於一個實施例中，該等摻雜物以某角 度進行注入，以形成自該閘極電源至該通道阱的邊緣的通 道。該注入角度0可介於大約1至45度的範圍。亦可使 用其他注入角度。取決於應用方式的需求，可變化注入的 條件。舉例而言，劑量與能量可經選擇，以達到所欲的有 效通道長度。 於一個實施例中，該通道阱藉由多道注入所形成。舉 例而言，該通道胖可藉由至少兩道傾斜與旋轉注入（rot ate implant)而形成。於一個實施例中，該注入包括四方注入 (quad implant)。四方注入包括4道傾斜角度注入（ti 1 ted angled implant)，每一個傾斜角度注入皆轉動達一旋轉角 度（rotation angle)。舉例而言，可利用四方注入於大約 30度的傾斜角度以大約45度的旋轉角度以大約2E13cnT2 劑量的硼於大約130KeV的能量程度形成ρ型通道阱。亦可 使用其他傾斜角度、旋轉角度、劑量及能量程度。舉例而 18 94920 201112337 言’四方注入可包括大約7度的傾斜角度以大約45度的旋 轉角度以大約2E13cm'2劑量的硼於大約i5〇KeV的能量程 ；'· 度。 r 在形成該通道摻雜阱135之後，去除該閘極電極層244 的經曝露部分，如第2f圖所示。於一個實施例中，實施如 反應離子姓刻（RIE)的非等向性钮刻（anis〇tr〇pic etch)， 以去除該閘極電择層的經曝露部分。於一個實施例中，去 除該閘極電極層的經曝露部分形成高壓閘極的第一邊緣。 於一個實施例中，該第一邊緣對應於該高壓閘極的源極 側。如圖所示’該閘極介電層242可作為蝕刻該閘極電極 層的蝕刻停止層fetch stop)。由於該閘極介電層可作為用 於接下來離子注入的注入遮罩，以保護該基板免於注入損 傷（implant damage)，因此留下該閘極介電層是有利的。 又或者，可去除該閘極介電層的經曝露部分。去除該閘極 介電層242以曝露出該基板亦為有用者。在蝕刻該閘極電 極層之後，去除該遮罩層288。 如上所述，於一個實施例中，該注入遮罩可作為通道 阱注入遮罩’·以及作為用於圖案化該高壓閘極的第一邊緣 (例如：源極側）的遮罩。利用相同遮罩以形成該通道阱與 該閘極的源極側，該通道自我對準至該閘極邊緣。如此一 來’使得該南壓裝置的通道長度經良好控制，以產生非常 短的有效通道長度，以降低汲極至源極導通電阻效能。於 —個實施例中，該有效通道長度L短於〇. 4微米。於另一 實施例中，該有效通道長度L短於〇. 3微米❶於又一實施 94920 19 201112337 例中，該有效通道長度L·短於〇. 25微米。 參照第2gffi，另一遮罩層獅形成於 且經圖案化。該遮罩層經圖案化以曝露出：’並 欲去除的部分，並保護對應於該等低=層244 八。無加二_ 斗 &展置的閘極的部 刀舉幻而5，該遮罩可作為閘極遮罩。此外， 288b保護該高壓區域的源極部分以及該高壓裝置°的門 .該閘極電極層244的經曝露部分經去除成低^愈古 壓裝置的閘極。 成該低I與问 -之開極之後，製程繼續形成如第1圖所描 程例如包含藉由離子注入形成延伸區域 形成分隔件148與m以及擴散區域146與176。 不同類型的延伸與擴散區域可形成於不同的製程中。舉例 而:，Π型擴散區域形成於一個注入製程中，而p型擴散 ^域形成於另-製程中。再者，可個別地形成不同裝置區 域的擴散與延伸區域。在形成有該等擴散區域之後，可形 成石夕化物間極與接點（⑽㈣。舉例而言，該基板1〇1上 &積有=的孟屬’且該金屬經反應以形成石夕化物接點與 間極。該等接點與閘極可形成於相同或不同的製程中。去 除未經反應的金屬。可形成前金屬（pre-metal)與層間 Unblevel)介電層’其中形成有接點與内連接 ㈣erx。磁t)。可藉由如雙鑲嵌技術（-Η腿赚 Μη〇_)形成額外的内連接階層。最終可實施純化 (passivation)、切持 、 鬼（dicing)、組合與測試，以完成該積 體電路。 94920 20 201112337 形成裝置100的製程的替代實施例顯示於第3a至3g 圖中。參照第3a圖，顯示經局部處理的裝置。該經局部處 理的裝置類似於第2c圖甲所示者。硬遮罩咖形成於該開 極電極層244上。該硬遮罩例如包括石夕氧化物。於—個實 施例中、’該硬遮罩388藉由CVD而形成。該硬遮罩的厚度 二大約為40奈米。亦可使用其他材料、技術或者厚度。舉 1昭Γ更遮罩可由石夕氧化物或其他類型的材料形成。 上。第3b圖，軟遮罩287(如光阻）形成於該硬遮罩388 盆可作^微影技術圖案化該軟遮罩，以形成開口 289， 該硬遮it注入遮罩。就層可設置於該軟遮罩287與 刻（RIE)而轉換H更H遮罩的圖案藉由例如反應離子姓 之後，去除兮浐例中，如第3c圖所示，在圖案化該硬遮罩 摻雜阱135。=遮罩層。以摻雜物注入該基板以形成通道 的類型相反的換個只施例中，注入有與該高壓主動區域 高壓主動區物。舉例而言，將P型摻雜物注入η型 型深牌。 於一個實施 以 $可 自該閘極邊緣至=，該等摻雜物於某角度進行注入， 介於大約丨 該通道阱的邊緣形成通道。注入角度0 1 ^ 45 於 例而言 =施例中，該通道牌藉由多=二形成 用方式的需求，。亦可使用其他的注入角度。取決於應 量與能量可經、琴可變化注入的條件。舉例而言，角度、劑 一個會=擇，以達到所欲的有效通道長度 該通道阱可 舉 藉由至少兩道傾斜與旋轉注入而形 94920 21 201112337 成。於一個實施例中，該注入包括四方注入。四方注入包 括4道傾斜角度注入，每一道注入皆轉動達一旋轉角度。 舉例而言，可利用四方注入於大約3 〇度的傾斜角度以大約 45度的旋轉角度以大约2Ei3cnT2劍量的蝴於大約i30KeV 的能量程度形成p型通道阱。亦可使用其他傾斜角度、旋 轉角度、劑里及能量程度。舉例而言，四方注入可包括大 約7度的傾斜角度以大約45度的旋轉角度以大約2Εΐ3(^:2 劑量的硼於大約15〇KeV的能量程度。 如第3d圖所示，於該基板上沈積有另一軟遮罩層287, 覆蓋該硬遮罩層與經曝露的閘極電極層。該軟遮罩藉由微 〜而圖案化。該軟遮罩保護部份對應於該等電晶體閘極的 硬遮罩層388。新的ARC㉟可設置於該軟遮罩287與該硬 遮罩388之間。於第3e圖中，該硬遮罩的經曝露部分經去 除，曝露出部分的閘極電極層。可藉由例如反應離子触刻 (RIE)達到該硬遮罩層的圖案化。該經圖案化的硬遮罩可作 為閘極遮罩。如第3f圖所示，於圖案化該.硬遮罩之後，將 $亥軟遮罩去除。 參照第3g圖’該閘極電極層⑽藉由例如㈣進行圖 案化以於該低壓與高壓區域中形成多個閘極。可藉由例如 反應離子餘刻（RIE)達到該閘極電極層的圖案化。圖案化該 該硬遮罩，縮減其厚度。於_閉 曰後，可藉由例如清潔步驟去除該硬遮罩388。 製程如先前所述般繼續完成該裝置。 … 形成裝置100的製程的另一實施例顯示於第如至紅 94920 22 201112337 圖中。參照第4a圖’顯示經局部處理的裝置。該經局部處 理的裝置類似於第3a圖中所顯示者。 參照第4b圖’軟遮罩層387(如光阻層）形成於該硬遮 罩388上。可於該軟遮罩與該硬遮罩之間設置有ARC層。 §亥軟遮罩經圖案化以曝露出部分的硬遮罩388。該軟遮罩 所剩下的部分對應於該高壓區域16〇中的高壓閘極。可藉 由微影技術達到該軟遮罩的圖案化。於一個實施例中，該 經圖案化的軟遮罩層亦曝露出該低壓區域11()中的硬遮 罩。 如第4c圖所示，該軟遮罩的圖案藉由例如反應離子蝕 刻而轉移至該硬遮罩。該反應離子蝕刻去除硬遮罩經曝露 的部分以曝露出該面壓區域中欲去除的閘極電極層344的 部分。於一個實施例中，去除該硬遮罩時亦曝露出該低壓 區域中的閘極電極層。在圖案化該硬遮罩之後，將該軟遮 罩去除。 於第4d圖中’另一軟遮罩層487(如光阻層）形成於該 基板上。ARC層可設置於該軟遮罩層下。該軟遮單層可藉 由微影技術進行圖案化，以曝露出該低壓區域中欲去除的 閘極電極層344之部分，並保護對應於該等低壓裝置的閘 極的部分。舉例而言，該經圖案化的軟遮罩可作為用於該 低壓區域的閘極遮罩。將該教遮罩層自該高壓區域去除。 於第4e圖中’該閘極電極層經圖案化。於一個實施例 中，該低壓區域中的閘極電極層利用該軟遮罩進行圖案 化’同時將該硬遮罩使用於該高壓區域中。使用軟遮罩有 94920 23 201112337 利於形成該低壓區域中具關鍵尺寸（critical dimension) 的閘極。 參照第4f圖，另一軟遮罩層487b(如光阻層）形成於 該基板上。ARC層可設置於該軟遮罩層下。該軟遮罩層可 藉由微影技術進行圖案化，以形成開口 489。該經圖案化 的軟遮罩層可作為通道注入遮罩。 如第4g圖中所示，該基板注入有摻雜物以形成通道摻 雜阱135。於一個實施例中，注入有與談高壓主動區域相 反類型的摻雜物。舉例而言，p型摻雜物經注入進入η型 高壓主動區域的ρ型深阱。. 於一個貪施例中，該等摻雜物於某角度進行注入，以 自該閘極邊緣至該通道阱的邊緣形成通道。該注入角度Θ 可介於大約1至45度。亦可使用其他的注入角度。取決於 應用方式的需求，可變化注入的條件。舉例而言，角度、 劑量與能量可經選擇，以達到所欲的有效通道長度。 於一個實施例中，該通道阱藉由多道注入所形成。舉 例而言，該通道牌可藉由至少兩道傾斜與旋轉注入而形 成。於一個實施例中，該注入包括四方注入。四方注入包 括4道傾斜角度注入，每一個傾斜角度注入皆轉動達一旋 轉角度。舉例而言，可利用四方注入於大約30度的傾斜角 度以大約45度的旋轉角度以大約2E13cnT2劑量的硼於大約 130KeV的能量程度形成ρ型通道阱。亦可使用其他傾斜角 度、旋轉角度、劑量及能量程度。舉例而言，四方注入可 包括大約45度的傾斜角度以大約45度的旋轉角度以大約 24 94920 201112337 2E13cnT2劑量的硼於大約15〇KeV的能量程度。 於一個實施例中，在去除該通道阱之後，該 與硬遮罩經去I舉例而言，首先去除該〜遮罩，接 去㈣硬遮罩。於一些實施例中，保留該硬遮罩。在形成 該等閘極之後，該製程如先前所述般繼續完成該裝置。 形成裝置100的製程的替代實施例顯示於第5a至5 圖中。參照第5a ®，顯示經局部處理的裝置。該經局2 理的裝置類似於第4c圖中所示者。 处 如第5b圖所示’軟遮罩層587(如光随層）形成於該基 並。ARC層可設置於該閘極軟遮罩層下。.該軟遮罩層可 =微影技術進行圖案化，以曝露出該高壓區域，並 置免於被處理。如第5c圖所描綠，該高壓區域 :閘極電極藉由例如反應離子仙進行圖案化，以利用 作為閘極遮罩形成該閘極。在圖案化該高壓區域 中的閘極電極之後，該軟遮罩經去除。 一 ”第5d n軟遮罩層587b(如光阻）形成於今 2=ARC層可設置於該軟遮罩層下。該軟遮罩層_ 軟遮罩層可作為通道注人遮罩。 抓圖案化的 如第5e圖所示’該基板注入有摻 ㈣。於-個實施例中，注入 類型的摻雜物。舉例而言，p型摻雜 ：£域相反 壓主動區域的㈣深牌。 U入進入η型高 於一個實施例中，該等摻雜物於某角度進行注入，以 94920 25 201112337The type active sub-region includes a p-type doped well, and the second type active region includes an n-type doped well. Other substructure active sub-regions H 94920 6 201112337 type dopants may also comprise boron (B), indium (In) or a combination of both, while the n-type dopant may comprise phosphorus (germanium), arsenic ( As), 锑 (sb) or the combination of the three. A first type of transistor 140 is disposed in the first _ type active sub-region, and a second type of NMOS transistor 150 is disposed in the second _-type active sub-region. For example, the n-type transistor is disposed in the n-type active sub-region having the P-type doping, and the p-type transistor is disposed in the 主动-type active sub-region having the n-type push-stack. In one embodiment, the transistors are M〇s field effect transistors (MOSFETs). Other types of transistors can also be used. For example, the transistor includes a gate having a gate electrode 144 on the gate dielectric material 142. The gate electrode includes, for example, polysilicon. Other types of gate electrode materials such as polycrystalline lithite or metal lithium may also be used. The polycrystalline lithiate or the metal cerium compound can be formed by reacting the desired metal b: and the two polycrystalline germanium. Various types of metals such as , ., , , , chin, or nickel (mckel) can be used. Other _ type interlayer materials can also be used. Furthermore, the gate electrode may be doped with a doping Φ -fcs; _L a I , 4 may be dependent on the process technique. For example, the gate electrode can be doped with a transistor type (4) type of debris. The gate electrode can also be doped with other dopant types. The gate dielectric material can be a tantalum oxide (silic (10) two de). Other types of gate or gate dielectric materials can also be used. The 2-pole electrode material and the gate dielectric material may depend on the process technology. For example, Lu's cobalt-telluride gate electrode can be used for η 1〇" for 0.18 micron and 0.13 micron denture technology' while nickel telluride can be used for 〇 1 叩彳 米 制 process technology. It is also possible to make the gate electrode and the idle electrode dielectric material of the octagonal structure. The side wall of the gate electrode can be provided with a side 劈 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The sidewalls 94920 7 201112337 spacers may comprise a dielectric material such as a cerium oxide, a stellite compound or a combination of the two. Other types of materials can also be used for the sidewall spacers. Diffusion region 146 is adjacent to the gate. These diffusion regions serve as the source and drain of the transistor. An extended diffusion region 147 can be provided. The extended diffusion regions may be shallow diffusion regions extending below the spacers. The diffusion regions of the first type of transistor (including the extended diffusion regions) are doped with a first type of dopant, and the diffusion regions of the second type of transistor are doped with a second type of dopant. For example, the P-type diffusion region is provided for the P-type transistor, and the n-type diffusion region is provided for the n-type transistor. The depth and dopant concentration of the diffusion regions may depend, for example, on the mode of application (e.g., voltage requirements). The high pressure region includes a high pressure active region 165. In one embodiment, the high voltage active region comprises a first type of active region. For example, the high voltage active region includes an n-type active region. A p-type high-voltage active area can also be set. Furthermore, it will be appreciated that for simplicity, the high voltage region only depicts the active region, and the high voltage region may comprise a high voltage active region or sub-region. For example, the high voltage active sub-regions can be complementary type high voltage sub-regions for complementary type high voltage devices. Isolation regions 180, such as shallow trench isolation (STI) regions, are provided to isolate the low and south voltage regions in the regions and the active sub-regions within the regions. Other types of isolated areas can also be used. In one embodiment, the first type of high voltage active region includes at least first and second portions. The first portion includes a second type of high voltage channel (or body) well 135 and the second portion includes a first type of high voltage drift well 136. 8 94920 201112337 This high voltage drift trap defines the type of high voltage device. For example, the p-type high voltage active region can have an n-type high voltage channel well and a p-type high voltage drift well. In one embodiment, the third or intermediate portion separates the channel from the drift trap. In other embodiments, the first and second portions are adjacent portions. For example, the high voltage channel and the high voltage drift well are in contact with each other. A deep well 132 can be disposed in the high voltage active region to surround the high voltage channel and the drift trap. In general, the deep well includes a dopant of the first type or a dopant of the same type as the high voltage device. The deep well can be used to isolate the drift well from the substrate. For example, a Ρ-type device would have an n-type deep well. In some cases, the deep well may be selectively present or the deep well may comprise a dopant of the second type or of a type opposite to the high voltage device type. For example, in the case of an n-type high voltage device, the deep well can be a p-type or an n-type deep well. The different types of deep wells selected may depend on the type of substrate. In general, a p-type doped substrate is used in a manufacturing apparatus. When a p-type substrate is used, the n-type deep well can be selected. This is because the n-type drift well is different from the p-type substrate. For an n-type substrate, a p-type deep well can be used to isolate the channel well from the substrate. Other configurations of deep wells can also be used. As shown, a first type of high voltage device is disposed in the first type of high voltage active region. In one embodiment, the first type of high voltage device comprises a lateral double diffused (LD) device, such as an LDMOS device. The high voltage device includes a gate having first and second edges 179a-b or a plurality of sidewalls. The gate includes a high voltage gate electrode 174 on the high voltage gate dielectric material 172. The high voltage gate electrode can include polysilicon. Other types of high voltage gate electrode materials such as polycrystalline telluride or metal telluride can also be used. 9 94920 201112337 Various types of high voltage gate electrode materials such as cobalt, titanium or nickel can be used. Other types can be used. For example, the inter-electrode electrode can be doped with the same dopant type as the transistor. High voltage gate electrodes with other dopants can also be used. The south gate dielectric material can cut oxides. Other types of south-voltage gate dielectric materials can also be used. In one embodiment, the high voltage gate electrode material and high voltage gate dielectric material may depend on the CMOS process and/or technology. In one embodiment, the high voltage gate electrode material and high voltage gate dielectric material may depend on the CMOS process and/or technology used for the low voltage device. For example, the magnetite gate electrode can be used for the process technology of 0.18 and 0·13 micrometers, and the magnetite compound can be used for the 0. 0 9 micrometer process technology. Other configurations of gate electrodes and gate dielectric materials can also be used. The sidewall of the gate may be provided with a sidewall spacer 178. The sidewall spacers may comprise a dielectric material such as tantalum oxide, tantalum nitride or a combination of the two. Other types of materials can also be used for the sidewall spacers. In one embodiment, the high voltage gate (e.g., gate electrode), the gate dielectric material, and the various gate elements of the spacer have the same type of material as the low voltage package in the low voltage region. As a result, the process compatibility of the high pressure and low pressure devices is improved. The high voltage gate overlaps the channel and drift well portions of the first and second portions of the high voltage active region. The drift isolation region 180a may be disposed in the drift well 136 on the high voltage side of the high voltage device. The drift isolation region 180a can improve the breakdown voltage of the high voltage device due to high voltage. For example, 10 94920 201112337 stated that the drift isolation region is particularly designed to withstand high voltage applications in excess of approximately ίο volts. As shown, the drift isolation region 180a is placed in the drift well 136 below the gate. The drift trap can also be placed in other locations, such as partially below the gate. A first type of drain diffusion region 176b is disposed between the drift isolation region 18a and the isolation region 18o, and isolates the southvoltage active region from other sub-active regions in the nip region. A first type of source diffusion region 176a is disposed in the channel well 135 of the first type of high voltage active region. A source extension region .177 can be provided which extends below the spacer side of the channel side of the high voltage gate (channe 1 s i d e). The first type of source and drain diffusion regions include, for example, p-type diffusion regions for p-type high voltage active regions. An n-type diffusion region for the n-type high-voltage active region may also be provided. The dopant depth and concentration of the diffusion regions can be selected depending on the mode of application. In one embodiment, the dopant region has a dopant depth and concentration that is the same as the dopant depth and concentration of the low voltage device. Other dopant depths and concentrations can also be used. A second type of body contact region 171 can be disposed in the first portion of the high voltage active region. As shown, the second type of body contact region 171 is interposed between the source diffusion region 176a and the isolation region 180. The second type of body contact region includes a second type of dopant. In one embodiment, the body contact region may have a dopant depth and concentration that is the same as the diffusion region of the low voltage device. Other dopant depths and concentrations can also be used. The body contact region 171 provides electrical coupling to the channel well 135. The edge 133 of the channel well 135 extends below the gate of the source side of the gate. This edge 133 can be referred to as the channel edge of the channel well 11 94920 201112337. The channel edge of the channel well 135 and the first edge 179a of the source side gate define a channel of the high voltage transistor having an effective channel length L. In one embodiment, the effective channel length is controlled by ion implantation and self-aligned to the gate edge. For example, an implant mask is used to implant dopant ions through the gate electrode or the hard mask and the gate electrode. In one embodiment, the implant mask is also used to pattern the channel edges of the high voltage gate. The effective channel length can be controlled by channel or body injection conditions selected to meet the threshold voltage and breakdown voltage requirements. For example, a shorter effective channel length can be obtained by reducing the tilt angle, the injected energy or the dose, and the like. Process coverage problems can be avoided by using a channel well that is self-aligned to the gate edge of the implant. A very short effective channel length with very low buck-to-source on-resistance can be achieved, allowing high currents to pass through small areas. This is particularly useful for process technologies below 0.35 microns, such as 〇. 25 microns, 0. 18 microns, and 0.13 microns. Smaller area requirements for power management applications with reduced power dissipation are able to achieve performance while reducing cost. 4微米。 In one embodiment, the effective channel length L is less than 0. 4 microns. 5微米。 In another embodiment, the effective channel length is less than .0. 3 microns. In another embodiment, the effective channel length is less than 0.25 microns. For example, depending on the application, other valid channel lengths can also be used. Figures 2a through 2g show cross-sectional views of an embodiment of a process for forming a device or integrated circuit 1 94 12 94920 201112337. Referring to Fig. 2a, a substrate 101 is provided. The substrate may comprise a germanium substrate such as a substrate that is slightly p-doped. Other types of substrates may also be used, including an n-type doped substrate, germanium or insulator overlying germanium (SOI). As shown, the first and second device regions 11 and 16 are defined on the substrate. . The first region includes, for example, a low voltage device region while the second region includes a high voltage device region. Other types of device areas or additional device areas can be set. Alternatively, the '蹿 device may only contain high pressure regions. The low voltage device region 110 can define first and second types of active sub-regions 112 and 116. In one embodiment, the first and second types of active sub-regions are complementary types of active sub-regions to form complementary devices such as CM〇s devices. Non-mutual or other types of devices may also be formed. As for the high voltage device region 16 〇, the high voltage active region 165 is defined therein. In one embodiment, the high voltage active region 165 can be a first or second type of high voltage active region. Although only one high voltage active region is depicted. It is understood that the high voltage device region may include additional high voltage active regions or sub-regions 1 such as high voltage active sub-regions may be complementary multiple high voltage active sub-regions. The substrate is also prepared with a plurality of isolation regions 18〇 to separate the device regions from other active device sub-regions. In one embodiment, the isolation region 180 includes a plurality of shallow trench isolations (STIs). Various conventional processes can be employed to form the shallow trench isolation regions. For example, it may be known that the surname and the masking technique are used to name the substrate to form a plurality of trenches, followed by, for example, a radiant charge. It can be used to remove the dielectric material and provide a flat substrate top surface. Other process materials can also be used to form such shallow trench isolations. = 2b shot, with push = (4 _ 11) for the active area of the device area. In one embodiment, the first type doped well m is formed in the second type of high active two type doped wells 122 shaped a thousand and ''. And h is formed in the first-type high-voltage active sub-region and the ^^-type-replacement is formed in the p-type active sub-region, and the /no-brand is formed in the n-type active sub-region in the high-voltage active region. For example, the "165 towel" includes at least the first and second portions corresponding to the boundary (four) I P points corresponding to the non-polar portion, and the second portion is to be = in some embodiments, the third or intermediate first The second portion is spaced apart. Alternatively, the first and the first phase, the connected portion, and the intermediate portion are formed. The non-polar portion 136 is formed in the high-voltage active region drift 2, for example, the drift of the high-voltage device. Press the active area "the same type of two domains. The first type is high n^^month/肀, and the drift trap includes the first type. For example, (4) the pressure active area is set. The card lir can be selectively disposed in the drift to the floating trench isolation region to be placed in the drift trap to improve the high voltage device: the drift shallow trench isolation region Talk about Yan Wu's breakdown of 1 abi 1 i ty. "You~'s slot isolation area can be combined with other shallow trench isolation areas at the same time 14 94920 201112337. A deep high voltage well 132 can be disposed in the high voltage active region 165. As shown, the deep high voltage well 132 is formed throughout the high voltage active region 165 and surrounds the first and second portions of the high voltage active region 165. The deep high voltage well has a type opposite to the drift well and the high voltage active region. In the case of the first type of high voltage active region, the deep well includes a second type. For example, a p-type deep well is provided for the n-type high voltage active region. The dopant depth and concentration of the various wells may depend, for example, on the application. For example, higher voltage applications may require lower dopant doping concentrations and deeper well depths. In one embodiment, the deep well 132 has a depth of about 3 microns and a dopant concentration of about 5E16 cm-3. For the drift well 136, a depth of about 1.5 microns may be required with a dopant concentration of about 5E17cnf3. Other dopant depths and concentrations can also be used for the wells. As described above, the shallow trench isolation regions are formed before the formation of various doped wells. Other process schemes such as forming shallow trench isolation regions after forming various doped wells may also be used to dope wells. The doped well can be formed by ion implantation. The P-type dopant may comprise boron (B), BF2 (boron and fluoride), indium (In) or a combination of the three, while the n-type dopant may comprise phosphorus (arsenic), arsenic (As), antimony ( Sb) or a combination of the three. In general, the first and second types of active regions are selectively formed in individual processes. For example, the n-type regions may be implanted with an n-type dopant while implanting a mask to prevent doping of the p-type region. In one embodiment, the well of the high voltage region is formed separately from the low pressure region 15 94920 201112337. For example, the high voltage wells such as thai can be formed first. It is also possible to form such low voltages - cleaving, followed by formation of a well. Different types of low voltage wells can be formed in individual processes to form such high voltage high voltage wells or can be formed in individual processes. The == and the different types of the first type and the second type of the well are in the lower part of the low-pressure area > the main-in process of the shape of the 'land, the different types of wells in the rolling area are also θ. Same as. ~ In a separate injection process, the shape can be injected by a single injection process or multiple channels. In the multi-pass injection process, doped wells can be formed in different energies. Injecting the doping distribution into the spear king (doping prof i ip, 'to achieve ^ ° $ hand, and implement the high-speed drive-in process to make the 'in process' can use a single injection The process is, for example, formed into a plurality of = miscellaneous:: In the case of dark brown, 'approximately 6E12 cm, the impurity concentration can be implanted with phosphorus to the energy level of the type, and then about 'about 2〇〇〇Kev can be performed at about 11〇〇7 A single-injection process is used to form other types: two-hour drive. The gate implant process forms multiple wells. For example, multiple low-pressure wells can be formed by multiple applications. The day-injection process is applied to the 2c wipes. A plurality of interlayers are formed on the substrate. In the embodiment, a gate dielectric layer is formed on the substrate. The diagnosis may include a shixi oxide. Other types of dielectric electrodes may be used to mediate the dream. . Alternatively, high k, low k or dielectric material = helium may be used. For a 1.8V gate voltage transistor, the gate dielectric layer. Things. Can be about 30 * (A). Other thicknesses* can also be used. The thickness of the thickness gate voltage application. For example, the higher gate depends on the 2:201112337 thicker gate dielectric layer that may be i:迤16 9 . In one embodiment, the gate dielectric layer is formed by thermal oxidation. Other process techniques such as chemical vapor deposition (CVD) may also be used to form the gate dielectric layer. A gate electrode layer 244 is deposited over the gate dielectric layer 242. In one embodiment, the gate electrode layer comprises polycrystalline germanium (p〇lysilic〇n; P〇ly). The gate electrode layer 244 may be formed as an amorphous layer or a crystalline layer. For an amorphous deposited layer, a subsequent treatment can be performed to crystallize the deposited layer. Other types of gate electrode materials can also be used. For example, the polysilicon can be subsequently processed to form a polycrystalline germanide or metal gate. The thickness of the gate electrode layer may be about 2 Å or less. In another embodiment, the gate electrode layer has a thickness of about 25 angstroms or less. In still another embodiment, the gate electrode layer has a thickness of about 4 angstroms or less. For example, in an embodiment of a polysilicon telluride gate, the polysilicon can be about 2000 angstroms while tungsten is about 2000 angstroms. Other thicknesses can also be used. Various process techniques can be used to form the gate electrode layer. For example, polycrystalline germanium can be deposited by CVD while depositing metal by sputtering. Other process technologies can also be used depending on the material. Referring to Fig. 2d, a mask layer 288 is formed on the substrate to cover the gate electrode layer. The material layer includes a photoresist. The mask is patterned as desired. In order to pattern the mask layer, a lithography technique (Ph〇t〇lith〇graphy) can be employed. For example, the mask can be selectively exposed to an exposure source (exp〇sure s〇urce) through a lithographic mask. The exposed or unexposed portions can be removed by development depending on whether positive or negative photoresist is used. In order to improve the lithography resolution (lith 〇 graphic 94920 17 201112337 resolution), an ARC layer (not shown) may be disposed under the mask layer. The mask layer 288 is patterned to form openings 289 to expose a portion of the gate electrode layer 244. In one embodiment, the opening corresponds to an opening for channel well injection. For example, the mask layer acts as a fill mask for the channel well. The ARC layer can be patterned using the mask layer. The subsequent mapping of the ARC layer is also useful. In Figure 2e, the substrate is implanted with dopants to form channel wells 135. In one embodiment, dopants are implanted opposite the type of the high voltage active region. For example, a p-type dopant is implanted into the p-type deep well of the n-type high voltage active region. In one embodiment, the dopants are implanted at an angle to form a channel from the gate supply to the edge of the channel well. The injection angle 0 can range from about 1 to 45 degrees. Other injection angles can also be used. The conditions of the injection can be varied depending on the needs of the application. For example, the dose and energy can be selected to achieve the desired effective channel length. In one embodiment, the channel well is formed by multiple implants. For example, the channel fat can be formed by at least two tilt and rot ate implants. In one embodiment, the implant comprises a quad implant. The square injection includes four ti 1 ted angled implants, each of which is rotated by a rotation angle. For example, a p-type channel well can be formed with a tetragonal injection at an angle of inclination of about 30 degrees at a rotation angle of about 45 degrees with an energy of about 2E13cnT2 of boron at an energy level of about 130 KeV. Other tilt angles, rotation angles, doses, and energy levels can also be used. For example, 18 94920 201112337 The 'square injection' may include an angle of inclination of about 7 degrees at a rotation angle of about 45 degrees with an energy of about 2E13 cm'2 of boron at an energy range of about i5 〇 KeV; r After forming the channel doped well 135, the exposed portion of the gate electrode layer 244 is removed, as shown in Figure 2f. In one embodiment, an anisotropic etch is performed, such as Reactive Ion (RIE), to remove the exposed portion of the gate electrode layer. In one embodiment, the exposed portion of the gate electrode layer is removed to form a first edge of the high voltage gate. In one embodiment, the first edge corresponds to the source side of the high voltage gate. As shown, the gate dielectric layer 242 can serve as an etch stop for etching the gate electrode layer. Since the gate dielectric layer can serve as an implantation mask for subsequent ion implantation to protect the substrate from implant damage, it is advantageous to leave the gate dielectric layer. Still alternatively, the exposed portion of the gate dielectric layer can be removed. It is also useful to remove the gate dielectric layer 242 to expose the substrate. The mask layer 288 is removed after etching the gate electrode layer. As noted above, in one embodiment, the implant mask can act as a channel well implant mask' and as a mask for patterning the first edge (e.g., source side) of the high voltage gate. The same mask is utilized to form the channel well and the source side of the gate, the channel self-aligning to the gate edge. In this way, the channel length of the south voltage device is well controlled to produce a very short effective channel length to reduce the drain-to-source on-resistance performance. In one embodiment, the effective channel length L is shorter than 〇. 4 microns. In another embodiment, the effective channel length L is shorter than 〇. 3 microns. In yet another embodiment, 94920 19 201112337, the effective channel length L· is shorter than 〇. 25 microns. Referring to the 2gffi, another mask layer lion is formed and patterned. The mask layer is patterned to expose: & the portion to be removed and to protect corresponding to the lower = layer 244 VIII. There is no addition of two _ buckets & the poles of the displayed poles are magical and 5, the mask can be used as a gate mask. In addition, 288b protects the source portion of the high voltage region and the gate of the high voltage device. The exposed portion of the gate electrode layer 244 is removed to the gate of the low voltage device. After the low I and Q-open, the process continues to form the spacers 148 and m and the diffusion regions 146 and 176, as depicted in Figure 1, for example, by forming an extension region by ion implantation. Different types of extension and diffusion regions can be formed in different processes. For example, the Π-type diffusion region is formed in an implantation process, and the p-type diffusion domain is formed in another process. Furthermore, the diffusion and extension regions of different device regions can be formed individually. After the formation of the diffusion regions, the inter-electrode interpole and the junction ((10) (4) can be formed. For example, the substrate 1〇1 & has a genus of genus and the metal reacts to form a stone eve a junction between the junction and the gate. The junction and the gate can be formed in the same or different processes. The unreacted metal can be removed. A pre-metal and interlayer Unblevel dielectric layer can be formed. There are contacts and inner connections (four) erx. Magnetic t). Additional inner join levels can be formed by, for example, dual damascene techniques (-Η 赚 〇 〇 〇 )). Finally, the passivation, the cut, the dicing, the combination and the test can be performed to complete the integrated circuit. 94920 20 201112337 An alternative embodiment of the process for forming device 100 is shown in Figures 3a through 3g. Referring to Figure 3a, a partially processed device is shown. The locally treated device is similar to that shown in Figure 2c. A hard mask is formed on the open electrode layer 244. The hard mask includes, for example, a stone oxide. In one embodiment, the hard mask 388 is formed by CVD. The thickness of the hard mask is about 40 nm. Other materials, techniques or thicknesses can also be used. A 1 Γ 遮 mask can be formed from Shi Xi oxide or other types of materials. on. In Fig. 3b, a soft mask 287 (e.g., photoresist) is formed in the hard mask 388. The soft mask can be patterned by lithography to form an opening 289 which is implanted into the mask. The layer may be disposed on the soft mask 287 and engraved (RIE) to convert the pattern of the H-H mask by, for example, after the reactive ion last name, in the example, as shown in FIG. 3c, the hard is patterned. The mask is doped with a well 135. = mask layer. In another embodiment in which dopants are implanted into the substrate to form channels, the high voltage active region is implanted with the high voltage active region. For example, a P-type dopant is implanted into an n-type deep card. In one implementation, from the gate edge to the =, the dopants are implanted at an angle to form a channel at approximately the edge of the channel well. The injection angle is 0 1 ^ 45. For example, in the example, the channel card is formed by the method of multiple = two. Other injection angles can also be used. It depends on the conditions under which the amount and energy can be changed and the pulse can be injected. For example, the angle, the agent will be selected to achieve the desired effective channel length. The channel well can be formed by at least two tilt and spin injections 94920 21 201112337. In one embodiment, the implant includes a tetragonal implant. The square injection includes four oblique angle injections, each of which is rotated by a rotation angle. For example, a p-channel well can be formed using a square injection at an angle of inclination of about 3 degrees at a rotation angle of about 45 degrees with an energy of about 2Ei3cnT2 of about i30KeV. Other tilt angles, rotation angles, agent levels, and energy levels can also be used. For example, the tetragonal implant can include an angle of inclination of about 7 degrees at a rotation angle of about 45 degrees with an energy level of about 2 Εΐ 3 (^: 2 doses of boron at about 15 〇 KeV. As shown in Figure 3d, on the substrate A soft mask layer 287 is deposited over the hard mask layer and the exposed gate electrode layer. The soft mask is patterned by micro-. The soft mask protection portion corresponds to the power a hard mask layer 388 of the crystal gate. A new ARC 35 can be disposed between the soft mask 287 and the hard mask 388. In Figure 3e, the exposed portion of the hard mask is removed, exposing portions The gate electrode layer can be patterned by, for example, reactive ion lithography (RIE). The patterned hard mask can be used as a gate mask. As shown in Fig. 3f, After patterning the hard mask, the $Hao soft mask is removed. Referring to FIG. 3g, the gate electrode layer (10) is patterned by, for example, (d) to form a plurality of gates in the low voltage and high voltage regions. Patterning of the gate electrode layer is achieved by, for example, reactive ion enrichment (RIE). The hard mask is patterned, The thickness of the hard mask 388 can be removed by, for example, a cleaning step. The process continues as described above. [Another embodiment of the process for forming the device 100 is shown in the Red 94920 22 201112337 In the figure, a partially processed device is shown with reference to Figure 4a. The locally processed device is similar to that shown in Figure 3a. Referring to Figure 4b, 'soft mask layer 387 (such as a photoresist layer) Formed on the hard mask 388. An ARC layer may be disposed between the soft mask and the hard mask. The soft mask is patterned to expose a portion of the hard mask 388. The soft mask The remaining portion corresponds to the high voltage gate in the high voltage region 16A. The patterning of the soft mask can be achieved by lithography. In one embodiment, the patterned soft mask layer is also exposed. a hard mask in the low voltage region 11(). As shown in Fig. 4c, the pattern of the soft mask is transferred to the hard mask by, for example, reactive ion etching. The reactive ion etching removes the hard mask and is exposed. Portion to expose the gate electrode layer 344 to be removed in the area of the face pressure In one embodiment, the gate electrode layer in the low voltage region is also exposed when the hard mask is removed. After the hard mask is patterned, the soft mask is removed. In FIG. 4d, 'another A soft mask layer 487 (such as a photoresist layer) is formed on the substrate. The ARC layer can be disposed under the soft mask layer. The soft mask layer can be patterned by lithography to expose the low voltage. a portion of the gate electrode layer 344 to be removed in the region and protecting portions of the gate corresponding to the low voltage devices. For example, the patterned soft mask can serve as a gate shield for the low voltage region. The mask layer is removed from the high voltage region. In FIG. 4e, the gate electrode layer is patterned. In one embodiment, the gate electrode layer in the low voltage region is performed using the soft mask. Patterning 'The hard mask is used simultaneously in this high pressure region. The use of a soft mask has 94920 23 201112337 which facilitates the formation of gates with critical dimensions in this low voltage region. Referring to Fig. 4f, another soft mask layer 487b (e.g., a photoresist layer) is formed on the substrate. The ARC layer can be disposed under the soft mask layer. The soft mask layer can be patterned by lithography to form openings 489. The patterned soft mask layer can be used as a channel implant mask. As shown in Figure 4g, the substrate is implanted with dopants to form channel doped wells 135. In one embodiment, a dopant of the opposite type to the high voltage active region is implanted. For example, a p-type dopant is implanted into a p-type deep well of an n-type high voltage active region. In a greedy embodiment, the dopants are implanted at an angle to form a channel from the edge of the gate to the edge of the channel well. The injection angle Θ can be between about 1 and 45 degrees. Other injection angles can also be used. The conditions of the injection can be varied depending on the needs of the application. For example, the angle, dose, and energy can be selected to achieve the desired effective channel length. In one embodiment, the channel well is formed by multiple implants. For example, the channel card can be formed by at least two oblique and rotational injections. In one embodiment, the implant includes a tetragonal implant. The square injection includes four oblique angle injections, each of which is rotated to a rotation angle. For example, a p-channel implant can be formed at a tilt angle of about 30 degrees using a tetragonal angle of rotation at an angle of about 45 degrees to form a p-channel well with a dose of about 2E13cnT2 of boron at an energy level of about 130 KeV. Other tilt angles, rotation angles, doses, and energy levels can also be used. For example, the tetragonal implant can include an angle of inclination of about 45 degrees at a rotational angle of about 45 degrees with a dose of about 24 94920 201112337 2E13cnT2 of boron at an energy level of about 15 〇 KeV. In one embodiment, after removing the channel well, the hard mask is removed, for example, by first removing the ~-mask and then removing the (four) hard mask. In some embodiments, the hard mask is retained. After forming the gates, the process continues to complete the apparatus as previously described. An alternate embodiment of the process of forming device 100 is shown in Figures 5a through 5. Refer to Section 5a ® for a partially treated device. The device is similar to that shown in Figure 4c. As shown in Fig. 5b, a 'soft mask layer 587 (e.g., a light layer) is formed on the base. The ARC layer can be disposed under the gate soft mask layer. The soft mask layer can be patterned by lithography to expose the high pressure area and protected from being processed. As shown in Fig. 5c, the high voltage region: the gate electrode is patterned by, for example, a reactive ion to form the gate using the gate mask. After the gate electrode in the high voltage region is patterned, the soft mask is removed. A "5d n soft mask layer 587b (such as a photoresist) is formed on the current 2 = ARC layer can be disposed under the soft mask layer. The soft mask layer _ soft mask layer can be used as a channel to cover the mask. Patterned as shown in Figure 5e, 'the substrate is implanted with (4). In one embodiment, implant type dopants. For example, p-type doping: (4) deep card of the opposite domain active region The U-input into the n-type is higher than in one embodiment, the dopants are implanted at an angle to 94920 25 201112337
成。於一個實施例中，該注入包括四方注入。 色轉注入而形 。四方注入包 括4道傾斜角度注入，每一個傾斜角度注入皆轉動達一旋 轉角度。舉例而言，可利用四方注入於大約3〇度的傾斜角 度以大約45度的旋轉角度以大約2E13cm-2劑量的硼於大約 130KeV的能量程度形成P型通道阱。亦可使用其他傾斜角 度、旋轉角度、劑量及能量程度。舉例而言，四方注入可 包括大約45度的傾斜角度以大約45度的旋轉角度以大約 2E13cm_2劑量的硼於大約150KeV的能量程度。 參照第5f圖，軟遮罩層587c的其他層（如光阻）形成 於該基板上。ARC層可設置於該軟遮覃層下。該軟遮罩層 可藉由微影技術進行圖案化，以曝露出該低壓區域中的欲 去除的閘極電極層344的部分。此外，保留該軟遮罩層於 該高壓區域中，以保護該高壓區域免於被處理。如第5g圖 中所描繪’該經曝露的閘極電極層344的部分經去除，以 形成該低壓裝置的閘極。 類似第4a至4g圖所示的實施例’該等低壓閘極利用 軟遮罩進行圖案化，同時以硬遮罩圖案化該高壓閘極。在 形成該等低壓閘極之後，該軟遮罩經去除，接著去除該等 26 94920 201112337 高壓閘極上的硬遮罩。於一些實施例中，可保留該硬遮罩。 該製程如先前所述般繼續完成該裝置。 本發明可以其他特定形式進行體現，而不悖離本發明 的精神與基本特性。因此，前述的實施例皆為例示，而非 限制本發明。本發明的精神是由附加的申請專利範圍所指 出，並非由所前述實施例所指出，且所有來自該等申請專 利範圍的意義與等效範圍内的所有變化皆涵蓋於申請專利 範圍中。 【圖式簡單說明】 於附加圖式中，類似的參考編號一般而言是參照不同 圖式中的相同零件。再者，該等附加圖式無須依正確比例 繪製，且一般而言是為了強調並且描繪本發明的原理。於 以下說明書内容中，本發明的各種實施例是參考下列附加 圖式進行描述，其中： 第1圖是顯示裝置的實施例； 第2a至2g圖是顯示用於形成裝置的製程的實施例； 第3a至3g圖是顯示用於形成裝置的製程的替代實施 例； 第4a至4g圖是顯示用於形成裝置的製程的另一實施 例；以及 第5a至5g圖是顯示用於形成裝置的製程的另一實施 例。 【主要元件符號說明】 100 裝置或積體電路 101 基板 27 94920 201112337 110 裝置區域 112 主動子區域 116 主動子區域 122 阱 124 阱 132 深阱 133 邊緣 135 通道阱 136 阱 140 電晶體 142 閘極介電材料 144 閘極電極 146 .擴散區域 148 分隔件. 150 電晶體 160 裝置區域 165 南壓主動區域 171 本體接觸區域 172 高壓閘極介電材料 174 高壓閘極電極 176a 源極擴散區域 176b 汲極擴散區域 178 側壁分隔件 179a 邊緣 179b 邊緣 180 隔離區域 180a 漂移淺溝槽隔離區域 242 閘極介電層 244 閘極電極層 287 軟遮罩 288 遮罩層 288b 遮罩層 289 開口 344 閘極電極層 387 軟遮罩 388 硬遮罩 487b 軟遮罩 587 軟遮罩. 587b 軟遮罩 587 c 軟遮罩 589 開口 28 94920to make. In one embodiment, the implant includes a tetragonal implant. Color is injected into shape. The square injection includes four oblique angle injections, each of which is rotated to a rotation angle. For example, a P-channel well can be formed with a tetragonal injection at an angle of inclination of about 3 degrees at a rotation angle of about 45 degrees with a dose of about 2E13 cm-2 of boron at an energy level of about 130 KeV. Other tilt angles, rotation angles, doses, and energy levels can also be used. For example, the tetragonal implant can include an angle of inclination of about 45 degrees at a rotational angle of about 45 degrees with a dose of boron of about 2E13 cm_2 at an energy level of about 150 KeV. Referring to Figure 5f, other layers of soft mask layer 587c, such as photoresist, are formed on the substrate. The ARC layer can be disposed under the soft concealer layer. The soft mask layer can be patterned by lithography to expose portions of the gate electrode layer 344 to be removed in the low voltage region. Additionally, the soft mask layer is retained in the high voltage region to protect the high voltage region from being processed. A portion of the exposed gate electrode layer 344 is removed as depicted in Figure 5g to form the gate of the low voltage device. Embodiments like the one shown in Figures 4a through 4g' are designed to be patterned with a soft mask while patterning the high voltage gate with a hard mask. After forming the low voltage gates, the soft mask is removed, and then the hard mask on the high voltage gates of the 26 94920 201112337 is removed. In some embodiments, the hard mask can be retained. The process continues with the device as previously described. The present invention may be embodied in other specific forms without departing from the spirit and scope of the invention. Accordingly, the foregoing embodiments are illustrative and not restrictive. The spirit of the invention is defined by the scope of the appended claims, and is not intended to be limited by the scope of the appended claims. [Simple description of the drawings] In the additional drawings, like reference numerals generally refer to the same parts in the different drawings. Furthermore, the additional figures are not necessarily drawn to the right scale, and are generally intended to emphasize and depict the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following additional drawings, wherein: FIG. 1 is an embodiment of a display device; and FIGS. 2a to 2g are diagrams showing an embodiment of a process for forming a device; Figures 3a through 3g are alternate embodiments showing a process for forming a device; Figures 4a through 4g are another embodiment showing a process for forming a device; and Figures 5a through 5g are for showing a device for forming a device Another embodiment of the process. [Main component symbol description] 100 device or integrated circuit 101 substrate 27 94920 201112337 110 device region 112 active sub-region 116 active sub-region 122 well 124 well 132 deep well 133 edge 135 channel well 136 well 140 transistor 142 gate dielectric Material 144 Gate electrode 146. Diffusion region 148 Separator. 150 Transistor 160 Device region 165 South voltage active region 171 Body contact region 172 High voltage gate dielectric material 174 High voltage gate electrode 176a Source diffusion region 176b Bump diffusion region 178 sidewall spacer 179a edge 179b edge 180 isolation region 180a drift shallow trench isolation region 242 gate dielectric layer 244 gate electrode layer 287 soft mask 288 mask layer 288b mask layer 289 opening 344 gate electrode layer 387 soft Mask 388 hard mask 487b soft mask 587 soft mask. 587b soft mask 587 c soft mask 589 opening 28 94920