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TW200941658A - Semiconductor device with enhanced heat dissipation effect - Google Patents

Semiconductor device with enhanced heat dissipation effect Download PDF

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Publication number
TW200941658A
TW200941658A TW097128205A TW97128205A TW200941658A TW 200941658 A TW200941658 A TW 200941658A TW 097128205 A TW097128205 A TW 097128205A TW 97128205 A TW97128205 A TW 97128205A TW 200941658 A TW200941658 A TW 200941658A
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TW
Taiwan
Prior art keywords
semiconductor device
heat dissipation
region
pin
insulating layer
Prior art date
Application number
TW097128205A
Other languages
Chinese (zh)
Inventor
zhen-zhong Chen
jia-zhong Wang
wen-qiang Lin
Original Assignee
Bridge Semiconductor Corp
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Publication of TW200941658A publication Critical patent/TW200941658A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor device with enhanced heat dissipation effect, which includes a semiconductor using an integrated metal substrate as base. The integrated metal substrate includes etched circuit, dielectric material, thick copper chip-holding heat dissipation bond-pad, and a plurality of electrical pin bond-pads. The features of the semiconductor device is that the chips can be bonded with the thick copper chip-holding heat dissipation bond-pad directly so as to provide a superior heat dissipation structure during the operation of the chip. Moreover, since the integrated metal substrate of the semiconductor device has dielectric material, the etched circuit can be supported and independent from the electrical pins bond-pads so that the degree of design freedom is increased, and the wiring of finer and thinner circuit is allowable for enhancing the wire-winding in the connection of electric elements. Moreover, since the circuit is supported by the dielectric material, the solder mask layer can be formed on the top of circuit so that the soldered element can be placed on sturdily. By this way, the semiconductor device with enhanced heat dissipation effect disclosed in this invention is capable of improving the problems associated with the conventional plastic substrate, such as poor heat dissipation effect, insufficient wire-winding capability of lead frame, and poor electrical conductivity because of the lack of the function of placing soldered elements.

Description

200941658 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具散熱增益之半導體裝置，尤 指一種可改善傳統封裝塑膠基板散熱差、導線架繞線能 力不足以及因無放置焊接元件功能而導致電性不佳等 問題之半導體裝置。 【先前技術】 隨著半導體技術之不斷提昇，半導體裝置所承載之 °晶片亦趨向高度整合化以提供電子產品所欲之運作速 度及功能，然此同時晶片運作所產生之熱量亦相對地增 加。以往在傳統上係以導線架進行封裝，上述使用導線 架雖可獲得良好之散熱效果，唯其無精細線路之佈線能 力。至於另一解決方案係使用塑膠基板以獲得良好之繞 線能力，然塑膠基板封裝其主體係為塑膠材質，因此散 熱性差。 在一般半導體裝置之製作上，傳統之散熱路徑係由 晶片、黏合膠、基板至基板下方之導熱銲球而傳遞至外 界，不僅散熱路甚長，且散熱效率亦往往不足，為解決 此散熱效率問題，一般在傳統半導體裝置結構上常貼淪 一導熱性佳之金屬材料製成之散熱片（stiffener)，使晶 片產生之熱量得傳遞至散熱片而散逸。而採用此種散熱 m構之半導體裝置已在美國專利公開公報第6906414 號中揭露出來。如2 3圖所示，係顯示該揭露之半導體 裝置之封裝結構。該揭露之半導體裝置4大致上係包括 200941658 一基板41、黏合於該基板4!上之晶片42、 該晶片42之散熱以3、以及用於包覆該基板41 : 散熱片4 3之封谬體44。該散熱片4 3之基縣具有-凹陷部4 3 1及-相對凸出部4 2，可使該晶片4 2產生之熱量藉由該散熱片4 3之凹 陷部4 3 ：1傳遞至凸出部4 3 2而散逸至該半 置4::然：，由於此種封裝結構其散熱片43與基板200941658 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having heat dissipation gain, and more particularly to a method for improving heat dissipation of a conventional packaged plastic substrate, insufficient wire winding capability, and no soldering component A semiconductor device that functions to cause problems such as poor electrical properties. [Prior Art] As the semiconductor technology continues to increase, the wafers carried by the semiconductor devices tend to be highly integrated to provide the desired speed and function of the electronic products, while the heat generated by the wafer operation is relatively increased. In the past, it was conventionally packaged with a lead frame, and the use of the lead frame described above can achieve a good heat dissipation effect, but it has no wiring capability for fine lines. As for the other solution, the plastic substrate is used to obtain a good winding capability, and the plastic substrate is packaged in a plastic system, so that the heat dissipation is poor. In the fabrication of a general semiconductor device, the conventional heat dissipation path is transmitted from the wafer, the adhesive, and the substrate to the heat conductive solder balls under the substrate, and the heat dissipation path is not long, and the heat dissipation efficiency is often insufficient. The problem is that a conventional semiconductor device structure is often attached with a heat sink made of a metal material having good thermal conductivity, so that the heat generated by the wafer is transmitted to the heat sink and dissipated. A semiconductor device using such a heat dissipating structure has been disclosed in U.S. Patent Publication No. 6906414. As shown in Fig. 3, the package structure of the disclosed semiconductor device is shown. The disclosed semiconductor device 4 generally includes a substrate 41 of 200941658, a wafer 42 bonded to the substrate 4, a heat dissipation of the wafer 42, and a cover for covering the substrate 41: a heat sink 43 Body 44. The base of the heat sink 43 has a recessed portion 433 and a relatively protruding portion 42, so that the heat generated by the wafer 4 2 can be transferred to the convex portion by the recessed portion 4 3 : 1 of the heat sink 43 The outlet 4 3 2 is dissipated to the half 4:: However, due to the package structure, the heat sink 43 and the substrate

❹ 片4二:：之結構，意即該裝置4之基板4 1與散熱 片4 3係兩種不同製程所完成之結構，因此在配置—基 板後另必須設置-散熱片結構’不僅得花費另—製程成 :二巧其製程時間亦得延長，故此項技術實不符合 業界大置夏產之考量。 有鑑於此，纟國專利公開公報第6541832號係揭露 一種具有散熱片之半導體裝置，如第24圖所示，該半 導體裝置5上之晶片5 !係與其散熱片5 2貼合藉此 使該明片5 1產生之熱量得直接傳遞至該散熱片5 2 而散逸。然而，此種封裝結構雖能結合基板與散熱片之 功能而達成散熱之目的，唯其整體結構不僅繞線不佳， 無法達成精細線路之製作’並且亦無接地功能，當該半 導體，置於運作時，由於無接地之配置，因此易造成結 構穩疋性不佳，而使電性效率不彰之缺點。 另外，美國專利公開公報第6528882號係揭露一種 從挖洞達成散熱之半導體裝置。如第2 5圖所示，其係 顯示該揭露之半導體裝置之封裝結構。該揭露之半導體 裝置6大致上係、包括—基板6 i、黏合於該基板6工上 200941658 之晶片6 2、以及用於包覆該基板6 1及該晶片6 2之 封膠體6 3。其中該基板6 1係包括一金屬核心層6 1 1、一配置於該金屬核心層6 1 1上表面6 11a之第 一圖形線路層6 1 2、一配置於該金屬核心層6 1 1下 表面6 lib之第二圖形線路層6 13、一配置於該第 一圖形線路層6 1 2與該金屬核心層6 1 1間之第一 絕緣層6 1 4、以及一配置於該第二圖形線路層6 1 3 與該金屬核心層6 1 1間之第二絕緣層6 1 5。利用在 © 該第二圖形線路層613與該第二絕緣層615以雷 射鑽孔鑽出複數個盲孔6 4，並顯露出該金屬核心層6 1 1之下表面6 1 lb，再進一步充填一導熱材料6 5 形成一散熱球6 6，使該散熱球6 6與設置於該第二圖 形線路層6 1 3下方球墊6 7上之錫球6 8於同一層 次’如是使產生之熱可從該晶片6 2通過該金屬核心層 6 1 1後能再直接地轉移通過該些散熱球6 6，藉此提 供晶片一個極短之熱擴散路徑。然而，此種封裝結構雖 ®能達成散熱之目的’唯其在處理製程上係於整體結構完 成後’需再另外製作雷射盲孔及充填導熱材料始得以獲 付此具散熱改良之裝置，因此以該項技術欲改良結構散 熱之同時’亦具有得另外花費雷射鑽孔等製程之成本及 其時間之缺點，同樣係費時費力且費工。故，一般習用 者係無法符合使用者於實際使用時之所需。 【發明内容】 本發明之主要目的係在於，克服習知技藝所遭遇之 200941658 上述問題並提供一種可使散熱效果增益、佈線能力較佳 以及含放置焊接元件功能而使整體結構穩定以提供良 好之電性效率之半導體裝置。 本發明之次要目的係在於’提供一種以一整合型金 屬基板為基礎且具散熱增益之半導體裝置。該整合型金 屬基板包括蝕刻線路、介電材料、厚鋼置晶散熱接墊以 及複數個電性接腳接墊。 本發明之另一目的係在於，有別於傳統塑膠基板封 ❹裝有限散熱月匕力之缺點，本半導體裝置係可使晶片能與 厚銅置晶散熱接墊直接結合，以提供晶片運作時良好之 散熱結構；另外，有別於傳統導線架半導體封裝有限繞 線能力之缺點，本半導體裝置内之整合型金屬基板由於 具有介電材料，可使蝕刻線路獲得支撐而獨立於電性接 腳接墊之外，因此可提高設計自由度並容許較精細線路 之佈線以強化電子元件相連時所需之繞線。同時，亦由 於線路具有介電材料之支撐’可使防焊層能形成於線路 ❹之上以便穩妥地放置焊接元件。 為達以上之目的’本發明係一種具散熱增益之半導 體裝置，係至少包括一具完整線路面與完整接腳面之金 屬基板、一半導體晶片及一成型材.料所組成。 於一實施例中，該金屬基板係包含一金屬板材、一 第一絕緣層及一第二絕緣層。其中該金屬板材係包含一 上部及一相對於上部之下部，並且在該金屬板材之上部 係包括一置晶接墊區域及複數個圖案化線路區域，而該 第二絕緣層則設置在該些圖案化線路區域與該置晶接 200941658 墊區域之間，於其中，該些圖案化線路區域係與該置晶 接塾區域及該第二絕緣層在同一層次，且該些圖案化線 路區域及e亥置晶接墊區域之表面接合層係經由一具^ 擇性之電鍍沉積過程所達成；在該金屬板材之下部則係 包括有一與置晶接墊區域相連之電性接墊區域，以及含 才曰疋數目之接腳區域，而該第一絕緣層則設置在該些電 性接墊區域與該些接腳區域之間，於其中，該接腳區域 係與該電性接墊區域及該第一絕緣層在同一層次，且該 0些接腳區域及該電性接墊區域之表面接合層係經由一 具選擇性之電鍍沉積過程所達成；該半導體晶片係含有 複數個輸入/輸出（1/〇)接墊，且該半導體晶片係黏結 5玄金屬基板之置晶接墊區域之表面，並由該些I/O接墊 電性連接至該些圖案化線路區域；以及該成型材料係用 以封裝該半導體晶片以及該金屬基板之上部，於其中， 該成型材料並無連接於該第一絕緣層。 於另實施例中，該金屬基板係包令—金屬板材及 絕緣層。其中该金屬板材係包含一上部及一相對於上 部之下部，並且在該金屬板材之上部係包括一置晶接墊 區域及複數個圖案化線路區域，於其中，該些圖案化線 路區域及該置晶接墊區域之表面接合層係經由一具選 擇性之電鍍沉積過程所達成；在該金屬板材之下部則係 包括有一與置晶接墊區域相連之電性接墊區域，以及含 才曰疋數目之接腳區域，而該絕緣層則設置在該些電性接 墊區域與該些接腳區域之間，於其中，該接腳區域係與 該電性接墊區域及該絕緣層在同一層次，且該些接腳'區 200941658 域及該電性接墊之表面接合層係經由一具選擇性之電 鍍沉積過程所達成；該半導體晶片係含有複數個1/〇接 墊，且該半導體晶片係黏結於該金屬基板之置晶接墊區 域表面，並由該些1/0接墊電性連接至該些圖案化線路 區域；以及該成型材料係用以封裝該半導體晶片及該金 屬基板之上部’於其令，該成型材料係與該些電性揍墊 區域與該些接腳區域間之絕緣層連接。 再於一實施例中，該金屬基板係包含一金屬板材及 〇 一絕緣層。其中該金屬板材係包含一上部及一相對於上 部之下部，並且在該金屬板材之上部係包括一置晶接墊 &域及複.數個圖案化線路區域，而該絕緣層則設置在該 些圖案化線路區域與該置晶接塾區域之間，於其中，該 圖案化線路區域係與該置晶接墊區域及該絕緣層在同 一層次，且該些圖案化線路區域及該置晶接墊區域之表 面接合層係經由一具選擇性之電鍍沉積過程所達成；在 該金屬板材之下部則係包括有一與置晶接墊區域相連 ❹之凸狀電性接墊區域，以及含指定數目之柱狀接腳區 域’於其中’該柱狀接腳區域係相同於該凸狀電性接塾 區域之高度’且該柱狀接腳區域與該，絕緣層係無形成在 同一平面’又該些凸狀電性接墊區域及該柱狀接腳區域 之表面接合層係經由一具選擇性之電鍍沉積過程所達 成；該半導體晶片係含有複數個I/O接墊，且該半導體 晶片係黏結於該金屬基板之置晶接墊區域，並由該些 I/O接墊電性連接至該些圖案化線路區域；以及該成型 材料係用以封裝該半導體晶片以及該金屬基板之上 200941658 部，於其令，該成型材料係與該些圖案化線路區域間之 絕緣層連接。 【實施方式】 ，明參閱『第1圖』所示，係為本發明一較佳實施例 之半導體裝置剖面示意圖。如圖所示··本發明係一種具 散熱增益之半導體裝置，係至少包括一具完整線路面與 完整接腳面之金屬基板10、-半導體晶片11及-成 型材料1 2所組成。 該金屬基板1 〇係包含一金屬板材i 〇工、一第一 絕緣層1 0 2及-第二絕緣層丄Q 3。其中該金屬板材 1 0 1係包3上部1 0 la及一相對於上部之下部1 0 lb’並且在該金屬板材i 〇丄之上部工〇 la係包括 一置晶接墊區域及複數個圖案化線路區域，而該第二絕 緣層1 0 3則設置在該些圖案化線路區域與該置晶接 墊區域之間；在該金屬板材工〇丄之下部丄〇丄b則係 包括有一與置晶接墊區域相連之電性接墊區域，以及含 指定數目之接腳區域’而該第—絕緣層i〇2則設置在 β亥些電性接墊區域與該些接腳區域之間，於其中，該接 腳區域係與該電性接势區域及該第-絕緣層工0 2在 =一層次，且該些圖案化線路區域、置晶接墊區域、電 性接墊區域及接腳區域之表面接合層係經由一具選擇 =電鑛沉積過程所達成，並分別形成圖案化線路接合 ^(^、置晶㈣接合層^^電性接塾接合層丄 ◦ 6以及接腳接合層丄〇 7。 200941658 該半導體晶片1 1係含有複數個輸入/輸出（I/O) 接墊’且該半導體晶片11係黏結該金屬基板10之置 晶接墊區域表面，並由該些I/O接墊電性連接至該些圖 案化線路區域。 該成型材料1 2係用以封裝該半導體晶片1 1以 及該金屬基板1 〇之上部，於其中，該成型材料^ 2並 無連接於該第一絕緣層i 0 2。以上所述，係構成一全 新且具散熱增益之半導體裝置1。 〇 於一實施例中，該金屬板材101係可為銅及其合 金、鋁、合金42、鋼、鎳及其它導熱材料；該金屬板 材1 0 1之厚度係可為〇〇5毫米（mm )〜〇 5毫米 (mm);該圖案化線路接合層i 〇 4、置晶接墊接合層 1 0 5、電性接墊接合層1 〇 6以及接腳接合層丄〇 7 係作為電源端子及/或接地端子，且上 4〜1〇7之材料係可為錄㈤)、〜：)=)〇 錫（Sn)、銀（Ag)及其組合；該些絕緣層丄〇 2、工 © 0 3之材料係可為防焊綠漆、玻璃纖維與環氧樹脂所組 成材料、雙馬來亞酿胺三氮雜苯樹月旨（Bismaleimide Tmzme，BT)及環氧樹脂。 明參閱『第2圖〜第20圖』所示，係分別為本發 明一較佳實施例之半導體裝置（―）剖面剖面示意圖、 =明-較佳實施例之半導體裝置（二）剖面示意圖、 ^明-較佳實施例之半導體裝置（三）剖面示音圖、 ^發明-較佳實施例之半導體裝置（四）剖面示音圖、 本發明一較佳實施例之半導體裝置（五）剖面示意圖、 12 200941658 本發明一較佳實施例之半導體裝置（六）剖面示意圖、 本發明一較佳實施例之半導體裝置（七）剖面示意圖、 本發明一較佳實施例之半導體裝置（八）剖面示意圖、 本發明一較佳實施例之半導體裝置（九）剖面示意圖、 本發明一較佳實施例之半導體裝置（十）剖面示意圖、 本發明一較佳實施例之半導體裝置（十一）剖面示意 圖、本發明一較佳實施例之半導體裝置（十二）剖面示 意圖、本發明一較佳實施例之半導體裝置（十三）剖面 ❹示意圖、本發明一較佳實施例之半導體裝置（十四）剖 面示意圖、本發明一較佳實施例之半導體裝置（十五） 刮面示意圖、本發明一較佳實施例之半導體裝置（十六） 剖面示意圖、本發明一較佳實施例之半導體裝置（十七） 剖面示意圖、本發明一較佳實施例之半導體裝置（十八） 刮面示意圖及本發明一較佳實施例之半導體裝置（十 九）剖面示意圖。如圖所示：本發明於上述第丄圖實施 例中’首先係提供一厚度為〇 12 5mm之銅及其合金作 ❿為該金屬板材101，並分別於該金屬板材1〇1之上 1 0 1 a 以乾膜貼合（Dry Film Lamination )、濕式旋 轉塗佈（Wet Spin Coating)或簾幕塗佈（Curtain c〇ating) 等方式塗佈一高感先性高分子材料之第一阻層2 〇，以 及於該金屬板材1 〇 i之下部丄〇 11?塗佈一高感光性 高分子材料之第二阻層2 1，並在該第二阻層2 i上形 成複數個第一開口 2 2，以顯露其下該金屬板材J 〇工 之下部1 0 lb’而其上部丄0 la之第一阻層2〇則為 完全覆蓋狀。接著對該些第一開口 2 2下方已顯露之銅 13 200941658 部份進行酸性餘刻或驗性钱刻等姓刻方式形成複數個 第一凹槽2 3 ’並以剝離之方式移除該第一、二阻層， 使該金屬板材1 〇 1之下部1 0 lb形成電性接墊區域 及接腳區域，隨後，形成一第一絕緣層1 〇 2於該些第 一凹槽2 3中，並顯露出該些電性接墊區域及接腳區 域，藉此’由該第一絕緣層1 〇 2為該些電性接塾區域 及接腳區域提供電性隔離。並進一步為後續從該金屬板 材1 0 1上部1 〇 1 a形成之細線佈線電路提供機械性 〇支擇。其中，該金屬板材101亦可為鋁、合金42、 鋼、鎳及其它導熱材料。 接著於該金屬板材1 〇 1之上部1 0 la塗佈一高 感光性高分子材料之第三阻層2 4，並於該第三阻層2 4上形成複數個第二開口 2 5，以顯露其下作為置晶接 塑1區域之金屬板材1 0 1上部1 0 la。之後分別於複 數個第二開口 2 5上電鍍一接合層，以形成預作之圖案 化線路接合層1 0 4與置晶接墊接合層1 〇 5，以及於The structure of the film 4:: means that the substrate 4 1 and the heat sink 43 of the device 4 are constructed by two different processes, so that it is necessary to set the heat sink structure after the substrate is disposed. Another - process Cheng: Second skill, its process time has also been extended, so this technology does not meet the industry's consideration of summer production. In view of the above, Japanese Patent Laid-Open Publication No. 6541832 discloses a semiconductor device having a heat sink. As shown in FIG. 24, the wafer 5 on the semiconductor device 5 is bonded to its heat sink 52 to thereby The heat generated by the film 51 is directly transmitted to the heat sink 52 to dissipate. However, although the package structure can combine the functions of the substrate and the heat sink to achieve the purpose of heat dissipation, the overall structure is not only poorly wound, and the fabrication of the fine circuit cannot be achieved, and there is no grounding function. When the semiconductor is placed, In operation, due to the ungrounded configuration, it is easy to cause poor structural stability, and the shortcomings of electrical efficiency are not recognized. In addition, U.S. Patent Publication No. 6,528,882 discloses a semiconductor device that achieves heat dissipation from burrowing. As shown in Fig. 25, it shows the package structure of the disclosed semiconductor device. The disclosed semiconductor device 6 is substantially comprised of a substrate 6 i, a wafer 6 bonded to the substrate 6 200941658, and a sealant 63 for coating the substrate 61 and the wafer 6 2 . The substrate 61 includes a metal core layer 61, a first patterned circuit layer 6 1 disposed on the upper surface 61 11a of the metal core layer 61, and a core layer 6 1 1 disposed under the metal core layer 6 1 1 . a second pattern circuit layer 6 13 of the surface 6 lib, a first insulating layer 6 1 4 disposed between the first pattern circuit layer 6 1 2 and the metal core layer 61 1 , and a second pattern disposed on the second pattern a second insulating layer 615 between the circuit layer 6 1 3 and the metal core layer 61 1 . Using the second pattern circuit layer 613 and the second insulating layer 615, a plurality of blind holes 64 are drilled by laser drilling, and the lower surface 6 1 lb of the metal core layer 6 1 1 is exposed, and then further Filling a heat-conducting material 6 5 to form a heat-dissipating ball 6 6 such that the heat-dissipating ball 6 6 is at the same level as the solder ball 6 8 disposed on the ball pad 6 7 below the second pattern circuit layer 6 1 3 Heat can then be transferred directly from the wafer 62 through the metal core layer 61 to the heat sink balls 6 6 thereby providing a very short thermal diffusion path for the wafer. However, this kind of package structure can achieve the purpose of heat dissipation. 'Only after the completion of the whole structure in the processing process', it is necessary to make another laser blind hole and fill the heat conductive material to obtain the device with heat dissipation improvement. Therefore, in order to improve the heat dissipation of the structure, the technology also has the disadvantages of cost and time of laser drilling and the like, which is time-consuming and labor-intensive. Therefore, the general practitioner cannot meet the needs of the user in actual use. SUMMARY OF THE INVENTION The main object of the present invention is to overcome the above problems encountered in the prior art of 200941658 and to provide a heat dissipation gain, a good wiring capability, and a function of placing a soldering element to stabilize the overall structure to provide good results. Electrically efficient semiconductor device. A secondary object of the present invention is to provide a semiconductor device based on an integrated metal substrate and having a heat dissipation gain. The integrated metal substrate includes an etched line, a dielectric material, a thick steel crystal thermal pad, and a plurality of electrical pin pads. Another object of the present invention is that the semiconductor device can directly combine the wafer with the thick copper crystal cooling pad to provide a wafer operation time, which is different from the conventional plastic substrate package. Good heat dissipation structure; in addition, unlike the shortcomings of the conventional lead frame semiconductor package with limited winding capability, the integrated metal substrate in the semiconductor device has a dielectric material, which enables the etching circuit to be supported independently of the electrical pin. In addition to the pads, design freedom can be increased and wiring of finer lines can be tolerated to enhance the winding required for electronic components to be connected. At the same time, because the line has the support of the dielectric material, the solder resist layer can be formed over the line to securely place the soldering elements. For the purpose of the above, the present invention is a semiconductor device having a heat dissipation gain, which comprises at least a metal substrate having a complete line surface and a complete pin surface, a semiconductor wafer and a molding material. In one embodiment, the metal substrate comprises a metal plate, a first insulating layer and a second insulating layer. Wherein the metal sheet comprises an upper portion and a lower portion opposite to the upper portion, and the upper portion of the metal plate includes a crystal pad region and a plurality of patterned circuit regions, and the second insulating layer is disposed on the metal plate Between the patterned circuit region and the pad region 200941658, wherein the patterned circuit regions are at the same level as the crystal interface region and the second insulating layer, and the patterned circuit regions and The surface bonding layer of the e-mounting pad region is achieved by a selective electroplating deposition process; the lower portion of the metal plate includes an electrical pad region connected to the crystal pad region, and And the first insulating layer is disposed between the electrical pad region and the pin regions, wherein the pin region is connected to the electrical pad region And the first insulating layer is at the same level, and the surface bonding layers of the plurality of pin regions and the electrical pad region are achieved through a selective electroplating deposition process; the semiconductor wafer system comprises a plurality of inputs / output (1/〇) pad, and the semiconductor wafer is bonded to the surface of the crystal pad region of the 5th metal substrate, and electrically connected to the patterned circuit regions by the I/O pads; The molding material is used to encapsulate the semiconductor wafer and the upper portion of the metal substrate, wherein the molding material is not connected to the first insulating layer. In another embodiment, the metal substrate is a metal sheet and an insulating layer. Wherein the metal sheet comprises an upper portion and a lower portion opposite to the upper portion, and the upper portion of the metal plate includes a crystal pad region and a plurality of patterned circuit regions, wherein the patterned circuit regions and the The surface bonding layer of the crystal pad region is achieved by a selective electroplating deposition process; the lower portion of the metal plate includes an electrical pad region connected to the crystal pad region, and a plurality of pin regions, and the insulating layer is disposed between the electrical pad regions and the pin regions, wherein the pin regions are associated with the electrical pad region and the insulating layer The same level, and the surface of the pin 'region 200941658 and the surface bonding layer of the electrical pad are achieved through a selective electroplating deposition process; the semiconductor wafer system comprises a plurality of 1/〇 pads, and the The semiconductor wafer is bonded to the surface of the metal pad region of the metal substrate, and electrically connected to the patterned circuit regions by the 1/0 pads; and the molding material is used to encapsulate the semiconductor crystal The metal substrate and the upper 'order thereon, the molding material with the plurality of hit lines electrically connected to the pad area of the insulating layer between the plurality of pin area. In still another embodiment, the metal substrate comprises a metal plate and an insulating layer. Wherein the metal sheet comprises an upper portion and a lower portion opposite to the upper portion, and the upper portion of the metal sheet includes a crystal pad & field and a plurality of patterned circuit regions, and the insulating layer is disposed at Between the patterned circuit region and the crystal contact region, wherein the patterned circuit region is at the same level as the crystal pad region and the insulating layer, and the patterned circuit regions and the device The surface bonding layer of the pad region is achieved by a selective electroplating deposition process; the lower portion of the metal plate includes a convex electrical pad region connected to the pad region, and a specified number of columnar pin regions 'in which the columnar pin region is the same as the height of the convex electrical interface region' and the columnar pin regions are not formed in the same plane as the insulating layer Further, the convex electrical pad regions and the surface bonding layer of the columnar pin regions are achieved by a selective electroplating deposition process; the semiconductor wafer system includes a plurality of I/O pads, and the semiconductor The chip is bonded to the pad region of the metal substrate, and is electrically connected to the patterned circuit regions by the I/O pads; and the molding material is used for packaging the semiconductor wafer and the metal substrate. In 200941658, Yu Qiling, the molding material is connected to the insulating layer between the patterned circuit regions. [Embodiment] FIG. 1 is a cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention. As shown in the drawing, the present invention is a semiconductor device having heat dissipation gain, comprising at least one metal substrate 10 having a complete line surface and a complete pin surface, a semiconductor wafer 11 and a molding material 12. The metal substrate 1 comprises a metal sheet i, a first insulating layer 102 and a second insulating layer 丄Q3. Wherein the metal sheet 10 1 is the upper portion 10 la of the package 3 and a lower portion 10 1 lb' with respect to the upper portion, and the upper portion of the metal sheet i 包括 includes a crystal pad region and a plurality of patterns. a circuit region, wherein the second insulating layer 103 is disposed between the patterned circuit region and the crystal pad region; and the lower portion of the sheet metal work includes a An electrical pad region connected to the pad region, and a specified number of pin regions ′, and the first insulating layer i〇2 is disposed between the electrical pads region and the pin regions Wherein the pin area and the electrical potential area and the first insulating layer are at a level, and the patterned circuit area, the crystal pad area, the electrical pad area, and The surface bonding layer of the pin region is achieved by a selective=electrodeposition process, and respectively forms a patterned wiring bond (^, a crystal (4) bonding layer, an electrical bonding layer 丄◦ 6 and a pin) Bonding layer 丄〇 7. 200941658 The semiconductor wafer 1 1 system contains a plurality of inputs/outputs ( I/O) a pad 'and the semiconductor wafer 11 is bonded to the surface of the pad region of the metal substrate 10, and electrically connected to the patterned line regions by the I/O pads. 2 is for encapsulating the semiconductor wafer 11 and the upper portion of the metal substrate 1 , wherein the molding material 2 is not connected to the first insulating layer i 0 2 . The heat dissipation gain of the semiconductor device 1. In one embodiment, the metal plate 101 can be copper and its alloy, aluminum, alloy 42, steel, nickel and other heat conductive materials; the thickness of the metal plate 110 can be 〇〇 5 mm (mm) to 〇 5 mm (mm); the patterned wiring bonding layer i 〇 4, the pad bonding layer 105, the electrical pad bonding layer 1 〇 6 and the pin bonding layer 丄〇7 series as the power terminal and / or grounding terminal, and the material of the upper 4~1〇7 can be recorded (5)), ~:) =) tin (Sn), silver (Ag) and combinations thereof; Layer 2, material © 0 3 material can be made of anti-weld green paint, glass fiber and epoxy resin, double malayan Silabenzene purpose tree months (Bismaleimide Tmzme, BT) and an epoxy resin. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing a semiconductor device (-) according to a preferred embodiment of the present invention, and a schematic cross-sectional view of a semiconductor device (2) according to a preferred embodiment. BRIEF DESCRIPTION OF THE DRAWINGS A semiconductor device according to a preferred embodiment (3) a cross-sectional sound map, an invention-preferred embodiment, a semiconductor device (4), a cross-sectional sound map, and a semiconductor device (5) cross-section of a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 12 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention, a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention, and a cross section of a semiconductor device according to a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention, a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention, and a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention. A cross-sectional view of a semiconductor device (12) according to a preferred embodiment of the present invention, and a semiconductor device (13) according to a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention, a semiconductor device according to a preferred embodiment of the present invention, and a semiconductor device according to a preferred embodiment of the present invention. 6) a schematic cross-sectional view, a schematic view of a semiconductor device according to a preferred embodiment of the present invention, a schematic view of a semiconductor device according to a preferred embodiment of the present invention, and a semiconductor device according to a preferred embodiment of the present invention (19) Schematic diagram of the section. As shown in the figure, the present invention first provides a copper having a thickness of 〇12 5 mm and an alloy thereof as the metal plate 101, and respectively on the metal plate 1〇1. 0 1 a First coating of a high-sensitivity polymer material by means of Dry Film Lamination, Wet Spin Coating or Curtain C〇ating a resist layer 2 〇, and a second resist layer 2 1 coated with a high-sensitivity polymer material on the lower portion of the metal sheet 1 〇i, and a plurality of layers formed on the second resist layer 2 i An opening 2 2 is formed to expose the lower portion of the metal sheet J to be 10 lb' and the first resist layer 2 丄 of the upper portion la0 la is completely covered. Then, the portions of the copper 13 200941658 which are exposed under the first openings 2 2 are subjected to an acid residue or an inspective manner to form a plurality of first grooves 2 3 ′ and are removed by peeling off. The first and second resist layers are formed such that the lower portion 10 lb of the metal plate 1 形成1 forms an electrical pad region and a pin region, and then a first insulating layer 1 〇 2 is formed in the first recesses 23 And exposing the electrical pad regions and the pin regions, thereby providing electrical isolation from the first insulating layer 1 〇 2 for the electrical interface regions and the pin regions. Further, mechanical 〇 is further provided for the subsequent thin wire wiring circuit formed from the upper portion 1 〇 1 a of the metal plate 1 0 1 . The metal sheet 101 may also be aluminum, alloy 42, steel, nickel, and other heat conductive materials. Then, a third resist layer 24 of a high-sensitivity polymer material is coated on the upper portion 10 la of the metal plate 1 〇1, and a plurality of second openings 25 are formed on the third resist layer 24 to The upper part of the metal plate 1 0 1 is exposed as a crystallized plastic 1 region. Thereafter, a bonding layer is plated on the plurality of second openings 25 to form a pre-patterned wiring bonding layer 104 and a bonding pad bonding layer 1 〇 5, and

❹ JU s亥金屬板材10 1下部1 0 lb之電性接藝區域及接腳 區域分別形成電性接墊接合層1 0 6及接腳接合層1 0 7 ’並由此以鎳/金為材料之接合層1 〇 4〜1 〇 7 提供電性接合之介面。隨後係剝離該第三阻層，再分別 於該金屬板材1 〇 1之上部1 〇 la及該些接合層10 4、1 〇 5上貼合一高感光性高分子材料之第四阻層2 6 ’以及於該金屬板材1 〇 1之下部1 〇 1 b、該些接 合層1 0 6、1 〇 7及該第一絕緣層1 〇 2上塗佈貼合 一尚感光性高分子材料之第五阻層2 7，並在該第四阻 14 200941658 層2 6上形成複數個第三開σ 2 8，以顯露其下該金 Ο 1之上部i 〇 l a’而其下部丄〇 ^之第五阻 層2 7則為完全覆蓋狀。接著係對該些第三開口 2 ^下 方已顯露之金屬板材1 0 1進行㈣以形成複數個第 二凹槽29,並顯露其下該第一絕緣層1〇2。至:第 係從該金屬板材101之上部1〇la形成細線電路3 〇 ’完成銅板㈣線路之製作。其中，該細線電路3 〇 〇 =該第-絕㈣1G2與該電性接墊區域及該接腳 區域所支撑。 接著，剝離該第四、五阻層，並於複數個第二凹槽 2 9内形成一第二絕緣層工〇 3，再於該細線電路3 〇、該些接合層1 〇 4、1 〇 5及該第二絕緣層！ ◦ 3 表面塗佈—防焊層3 1，並於該防焊層3 1上形成複數 個第四開口 3 2 ’以顯露其下之圖案化線路接合層i 〇 4與置晶接墊接合層1 〇 5。其中，該第二絕緣層】〇 〇 3與該防焊層3 1可為同一材質，並且亦可同時施作。 至此，係構成本發明之整體具有完整線路面與完整接腳 面之金屬板材1 〇 1、第一絕緣層i 〇 2及第二絕緣層 1 0 3等部份之整合型金屬基板1 〇。 接著於該些第四開口 3 2中之圖案化線路接合層 1 0 4與置晶接墊接合層i 〇 5表面先後黏結一被動 元件3 3及一半導體晶片1 1，並對該半導體晶片工工 與該金屬基板1 〇進行打線接合，使該半導體晶片工工 上之I/O接墊與該金屬基板i 〇上之圖案化線路區域電 性連接。最後’再以一成型材料1 2封裝該半導體晶片 200941658 1 l、該圖案化線路區域以及在該金屬基板i 〇上部之 第二絕緣層1 〇 3。至此，完成一具散熱增益之半導體 裝置1(如第1圖所示）。 請參閱『第2 1圖』所示，係本發明另一較佳實施 例之半導體裝置剖面示意圖。如圖所示：在另一較佳實 施例中，相較於前一實施例（即第丄圖所示），本實施 例係將其上部第二絕緣層消除，並將該成型材料直接連 接至下部第一絕緣層。因此，本發明具散熱增益之半導 體裝置係至少包括一具完整線路面與完整接腳面之金 屬基板1 〇、一半導體晶片1 1及一成型材料1 2所組 成。 S亥金屬基板1 0係包含一金屬板材1 〇 1及一絕 緣層1 0 2。其中該金屬板材1 〇 1係包含一上部工〇 1 a及一相對於上部之下部1 〇1 b，並且在該金屬板材 101之上部1〇la係包括一置晶接墊區域及複數個 圖案化線路區域；在該金屬板材1 〇 1之下部1 〇 lb 則係包括有一與置晶接墊區域相連之電性接墊區域，以 及含指定數目之接腳區域，而該絕緣層1 〇 2則設置在 該些電性接墊區域與該些接腳區域之間。於其中，該接 腳區域係與該電性接墊區域及該絕緣層1 〇 2在同一 層次’且該些圖案化線路區域、置晶接墊區域、電性接 墊£域及接腳區域之表面接合層係經由一具選擇性之 電鑛沉積過程所達成，並分別形成圖案化線路接合層1 0 4、置晶接墊接合層1 〇 5、電性接墊接合層1 0 6 以及接腳接合層1 〇 7。 16 200941658 該半導體晶片1 1係含有複數個ι/ο接墊，且該半 導體晶片11係黏結於該金屬基板10之置晶接墊區 域表面，並由該些1/〇接墊電性連接至該些圖案化線路 區域。 該成型材料係用以封裝該半導體晶片1 1以及該 金屬基板1 〇之上部。以上所述，係構成一全新且具散 熱増益之半導體裝置2。 〇 請參閱『第22圖』所示，係本發明再一較佳實施 例之半導體裝置剖面示意圖。如圖所示：於再一較佳實 允例中，相較於前一實施例（即第i圖所示），本實施 例係將其下部第一絕緣層消除，使其下部形成凸狀接 腳。因此，本發明具散熱增益之半導體裝置係至少包括 一具完整線路面與完整接腳面之金屬基板i Q、一半導 體晶片11及一成型材料12所組成。 該金屬基板1〇係包含一金屬板材1〇1及一絕 ❹緣層1〇 3。其中該金屬板材i 0丄係包含一上部工〇 la及一相對於上部之下部工〇 lb，並且在該金屬板材 1〇1之上部1〇la係包括一置晶接墊區域及複數個 圖案化線路區域，而該絕緣層1 〇 3則設置在該些圖案 化線路區域與該置晶接墊區域之間；而在該金屬板材工 〇 1之下部1 0 1 b則係包括有-與置晶接墊區域相連 ^柱狀電性接墊區域，以及含指定數目之凸狀接腳區 域，於其中，該柱狀接腳區域係相同於該凸狀電性接墊 區域之尚度，且該柱狀接腳區域與該絕緣層1 ◦ 3係無 形成在同一平面；該些圖案化線路區域、置晶接墊區 200941658 域、凸狀電性接墊區域及柱狀接腳區域之表面接合層係 經由一具選擇性之電鑛沉積過程所達成，並分別形成圖 案化線路接合層1 〇 4、置晶接墊接合層1 〇 5、凸狀 電性接墊接合層1 〇 8以及柱狀接腳接合層1 〇 9。 該半導體晶片1 1係含有複數個I/O接墊，且該半 導體晶片1 1係黏結於該金屬基板1 〇之置晶接墊區 域表面，並由該些I/O接墊電性連接至該些圖案化線路 區域。 〇 該成型材料1 2係用以封裝該半導體晶片χ 1以 及該金屬基板1 〇之上部。以上所述，係構成一全新且 具散熱增益之半導體裝置3。 由上述可知，本發明係為一種具散熱增益之半導體 裝置，係包括一以整合型金屬基板為基礎之半導體裝 置。該整合型金屬基板包括蝕刻線路、介電材料、厚銅 置晶散熱接墊以及複數個電性接腳接墊。其特色係在 ❹於’有別於傳統塑膠基板封裝有限散熱能力之缺點，本 半導體裝置係可使晶片能與厚銅置晶散熱接墊直接結 合，以提供晶片運作時良好之散熱結構；另外，有別於 傳統導線架半導體封裝有限繞線能力之缺點，本半導體 裝置内之整合型金屬基板由於具有介電材料可使姓刻 ，路獲得支樓而獨立於電性接腳接墊之外，因此可提高 »又自由度並容許較精細線路之佈線以強化電子元件 #連時所&m同時’亦由於線路具有介電材料之 支撐〃防焊n形成於線路之上以便穩妥地放置焊接 元件。 200941658 藉此，本發明具散熱增益之半導體裝置係可有效達 到改善傳統封裝塑膠基板散熱差、導線架繞線能力不足 以及因無放置焊接元件功能而導致電性不佳等問題。 綜上所述，本發明係一種具散熱增益之半導體裝 置，可有效改善習用之種種缺點，利用於厚鋼蝕刻線路 時所選擇性地保留位於置晶位置下方之銅板，可提供置 晶散熱接墊區域，使晶片能與厚銅置晶散熱接墊直接結 ❹合，有效地提供元件散熱之所需，同時並可以其較精細 線路佈線之基板提供電子元件相連時所需之繞線，因此 可有效改善傳統封裝塑膠基板散熱差、導線架 不足以及因無放置焊接元件功能而導致電性不佳等"問 題，進而使本發明之産生能更進步、更實用、更符合使 用者之所須，確已符合發明專利申請之要件，爰依:提 出專利申請。 惟以上所述者，僅為本發明之較佳實施例而已，當 〇不能以此限定本發明實施之範圍；故，凡依本發明申嘈 專利範圍及發明說明書内容所作之簡單的等效變化^ 修飾’皆應仍屬本發明專利涵蓋之範圍内。 、 200941658 【圖式簡單說明】 第1圖’係為本發明一較佳實施例之半導體裝置剖面 示意圖。 第2圖’係本發明一較佳實施例之半導體裝置（一） 剖面示意圖。 第3圖’係本發明一較佳實施例之半導艎裝置（二） 剖面示意圖。 0 第4圖’係本發明一較佳實施例之半導體裝置（三） 剖面示意圖。 第5圖’係本發明一較佳實施例之半導體裝置（四） 剖面示意圖。 第6圖’係本發明一較佳實施例之半導體裝置（五） 剖面示意圖。 第7圖’係本發明一較佳實施例之半導體裝置（六） 剖面示意圖。 ❹ 第8圖’係本發明一較佳實施例之半導體裝置（七） 剖面示意圖。 第9圖’係本發明一較佳實施例之半導體裝置（八） 剖面示意圖。 第1 0圖’係本發明一較佳實施例之半導體裝置（九 )剖面示意圖。 第11圖’係本發明一較佳實施例之半導體裝置（十 )剖面示意圖。 第1 2圖’係本發明一較佳實施例之半導體裝置（十 一）剖面示意圖。 20 200941658 第1 3圖’係本發明一較佳實施例之半導體裝置（十 一） 剖面示意圖。 第1 4圖’係本發明—較佳實施例之半導體裝置（十 二） 剖面示意圖。 第1 5圖’係本發明一較佳實施例之半導體裝置（十 四）剖面示意圖。 第1 6圖’係本發明一較佳實施例之半導體裝置（十 0 五）剖面示意圖。 第1 7圖，係本發明一較佳實施例之半導體裝置（十 六） 剖面示意圖。 第1 8圖，係本發明一較佳實施例之半導體裝置（十 七） 剖面示意圖。 第1 9圖，係本發明—較佳實施例之半導體裝置（十 八） 刮面示意圖。 第2 0圖，係本發明一較佳實施例之半導體裝置（十 ❹ 九）剖面示意圖。 第2 1圖，係本發明另一較佳實施例之半導體裝置剖 面示意圖。 第22圖，係本發明再一較佳實施例之半導體裝置剖 面示意圖。 第2 3圖’係習知之半導體封裝裝置剖面示意圖。 第2 4圖’係另-習知之半導體封裝裝置剖面示意圖 〇 第2 5圖，係再一習知之主道壯处取 之牛導體封裝裝置剖面示意圖。 21 200941658 【主要元件符號說明】 (本發明部分） 半導體裝置1、2、3 金屬基板1 0 金屬板材1 0 1 上部1 ◦ 1 a €) 下部1 0 1 b 第一、二絕緣層1 0 2、1 0 3 圖案化線路接合層1 0 4 置晶接墊接合層1 0 5 電性揍墊接合層1 0 6 接腳接合層1 0 7 ❿ 凸狀電性接墊接合層1 0 8 柱狀接腳接合層1 0 9 半導體晶片1 1 成型材料1 2 第一、二阻層2 0、2 1 第一開口 2 2 第一凹槽2 3 22 200941658 第三阻層2 4 第二開口 2 5 第四、五阻層2 6、2 第三開口 2 8 第二凹槽2 9 細線電路3 0 防焊層3 1 第四開口 3 2 被動元件3 3 (習用部分） 半導體裝置4 基板4 1 晶片4 2 散熱片4 3 凹陷部4 3 1 凸出部4 3 2 封裝膠體4 4 半導體裝置5 200941658 散熱片5 2 半導體裝置6 基板6 1 金屬核心層6 1 1 上、下表面611a、611b 第一、二圖形線路層6 1 2、6 1 3 第一、二絕緣層6 1 4、6 1 5 晶片6 2 封裝膠體6 3 盲孔6 4 導熱材料6 5 散熱球6 6❹ JU s hai metal plate 10 1 lower 10 lb of electrical interface area and pin area respectively form an electrical pad bonding layer 1 0 6 and pin bonding layer 1 0 7 ' and thus nickel / gold The bonding layer 1 〇4~1 〇7 of the material provides an interface for electrical bonding. Subsequently, the third resistive layer is peeled off, and a fourth resistive layer 2 of a highly photosensitive polymer material is attached to the upper portion 1 〇1 of the metal plate 1 〇1 and the bonding layers 10 4 and 1 〇 5 respectively. And a coating of a photosensitive polymer material on the bonding layer 1 0 6 , 1 〇 7 and the first insulating layer 1 〇 2 a fifth resist layer 27, and a plurality of third openings σ 2 8 are formed on the fourth resistor 14 200941658 layer 26 to reveal the lower portion of the metal dome 1 i 〇l a' and the lower portion thereof The fifth resist layer 27 is completely covered. Then, the metal plate 110 which has been exposed under the third opening 2^ is subjected to (4) to form a plurality of second grooves 29, and the first insulating layer 1〇2 is exposed. To: The second system is formed by forming a thin wire circuit 3 〇 ' from the upper portion 1 〇 la of the metal plate 101 to complete the copper plate (four) circuit. The thin wire circuit 3 〇 〇 = the first - (4) 1G2 and the electrical pad region and the pin region are supported. Then, the fourth and fifth resistive layers are peeled off, and a second insulating layer process 3 is formed in the plurality of second recesses 29, and then the thin wire circuit 3, the bonding layers 1 〇 4, 1 〇 5 and the second insulation layer! ◦ 3 surface coating—solderproof layer 3 1 and forming a plurality of fourth openings 3 2 ′ on the solder resist layer 3 1 to expose the patterned wiring bonding layer i 〇 4 and the bonding pad bonding layer 1 〇 5. The second insulating layer 〇 〇 3 and the solder resist layer 31 may be the same material and may be simultaneously applied. Heretofore, the integrated metal substrate 1 of the metal plate 1 〇 1, the first insulating layer i 〇 2 and the second insulating layer 1300 having the complete wiring surface and the complete landing surface as a whole of the present invention is constructed. Then, a passive component 3 3 and a semiconductor wafer 1 1 are bonded to the surface of the patterned wiring bonding layer 104 and the surface of the bonding pad bonding layer i 〇 5 in the fourth opening 3 2 and the semiconductor wafer 1 The metal substrate 1 is wire bonded to electrically connect the I/O pads on the semiconductor wafer to the patterned line regions on the metal substrate i. Finally, the semiconductor wafer 200941658 1 1 is further encapsulated by a molding material 12, the patterned wiring region, and the second insulating layer 1 〇 3 at the upper portion of the metal substrate i. Thus, a semiconductor device 1 having a heat dissipation gain is completed (as shown in Fig. 1). Referring to Fig. 2, there is shown a cross-sectional view of a semiconductor device in accordance with another preferred embodiment of the present invention. As shown in the figure: in another preferred embodiment, compared to the previous embodiment (ie, as shown in the figure), the present embodiment eliminates the upper second insulating layer and directly connects the molding material. To the lower first insulating layer. Therefore, the semiconductor device having heat dissipation gain of the present invention comprises at least a metal substrate 1 having a complete wiring surface and a complete landing surface, a semiconductor wafer 11 and a molding material 12. The S-shaped metal substrate 10 includes a metal plate 1 〇 1 and an insulating layer 102. Wherein the metal sheet 1 〇1 includes an upper work 1 a and a lower portion 1 〇 1 b with respect to the upper portion, and the upper portion of the metal plate 101 includes a crystal pad region and a plurality of patterns. a line region; the lower portion 1 〇 lb of the metal plate 1 包括 1 includes an electrical pad region connected to the crystal pad region, and a specified number of pin regions, and the insulating layer 1 〇 2 Then disposed between the electrical pad regions and the pin regions. Wherein, the pin area is at the same level as the electrical pad region and the insulating layer 1 ' 2 and the patterned circuit region, the crystal pad region, the electrical pad region and the pin region The surface bonding layer is formed by a selective electrodeposition process, and respectively forms a patterned wiring layer 104, a pad bonding layer 1 〇5, an electrical pad bonding layer 106, and Pin joint layer 1 〇7. 16 200941658 The semiconductor wafer 11 includes a plurality of ι/o pads, and the semiconductor wafer 11 is adhered to the surface of the metal pad region of the metal substrate 10, and is electrically connected to the 1/ 〇 pads. The patterned line areas. The molding material is used to encapsulate the semiconductor wafer 11 and the upper portion of the metal substrate 1 . As described above, it constitutes a new and thermally advantageous semiconductor device 2. 〇 Referring to Fig. 22, there is shown a cross-sectional view of a semiconductor device according to still another preferred embodiment of the present invention. As shown in the figure, in a further preferred embodiment, compared with the previous embodiment (ie, as shown in FIG. 19), the first insulating layer is removed from the lower portion of the embodiment, and the lower portion is formed into a convex shape. Pin. Therefore, the semiconductor device with heat dissipation gain of the present invention comprises at least a metal substrate i Q having a complete line surface and a complete pin surface, a half conductor wafer 11 and a molding material 12. The metal substrate 1 comprises a metal plate 1〇1 and an insulating edge layer 1〇3. Wherein the metal sheet i 0丄 comprises an upper part 〇1a and a lower part 〇1b, and the upper part of the metal sheet 1〇1 includes a crystal pad area and a plurality of patterns a line region, and the insulating layer 1 〇 3 is disposed between the patterned circuit region and the crystal pad region; and the lower portion of the sheet metal work 1 1 1 1 b includes - and The crystal pad region is connected to the columnar electrical pad region, and includes a specified number of convex pin regions, wherein the column pin region is the same as the convex electrical pad region. And the columnar pin region and the insulating layer 1 ◦ 3 are not formed in the same plane; the patterned circuit region, the crystal pad region 200941658 domain, the convex electrical pad region and the column pin region The surface bonding layer is formed by a selective electrodeposition process, and respectively forms a patterned wiring bonding layer 1 〇 4, a pad bonding layer 1 〇 5, and a convex electrical pad bonding layer 1 〇 8 And a columnar pin bonding layer 1 〇9. The semiconductor wafer 11 includes a plurality of I/O pads, and the semiconductor wafer 11 is adhered to the surface of the metal pad region of the metal substrate 1 and electrically connected to the I/O pads. The patterned line areas.形成 The molding material 12 is used to encapsulate the semiconductor wafer 1 and the upper portion of the metal substrate 1 . As described above, a new semiconductor device 3 having heat dissipation gain is constructed. As apparent from the above, the present invention is a semiconductor device having heat dissipation gain, and includes a semiconductor device based on an integrated metal substrate. The integrated metal substrate includes an etched line, a dielectric material, a thick copper crystal thermal pad, and a plurality of electrical pin pads. The feature is that it is different from the limited heat dissipation capability of the traditional plastic substrate package. The semiconductor device enables the wafer to be directly combined with the thick copper crystal thermal pad to provide a good heat dissipation structure for the wafer operation; Different from the shortcomings of the traditional lead frame semiconductor package with limited winding capability, the integrated metal substrate in the semiconductor device can be surnamed by having a dielectric material, and the road obtains a branch and is independent of the electrical pin. Therefore, it can improve the degree of freedom and allow the wiring of finer lines to strengthen the electronic components. When the connection is made with the dielectric material, the solder resist n is formed on the line for safe placement. Welding components. In this way, the semiconductor device with heat dissipation gain of the present invention can effectively improve the heat dissipation of the conventional packaged plastic substrate, the insufficient winding capability of the lead frame, and the poor electrical properties due to the function of not placing the soldering component. In summary, the present invention is a semiconductor device with heat dissipation gain, which can effectively improve various disadvantages of the conventional use, and can selectively retain the copper plate under the crystallizing position when the thick steel etching line is used, and can provide the crystal heat dissipation connection. The pad area enables the wafer to be directly bonded to the thick copper-plated heat-dissipating pad, effectively providing the heat dissipation of the component, and at the same time, the substrate of the finer-line wiring can provide the winding required for the electronic component to be connected. The utility model can effectively improve the heat dissipation of the traditional packaged plastic substrate, the shortage of the lead frame, and the problem of poor electrical conductivity due to the function of not placing the soldering component, thereby making the invention more progressive, more practical and more suitable for the user. Must have met the requirements of the invention patent application, and converted: filed a patent application. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent change made by the scope of the invention and the contents of the invention description of the present invention ^ Modifications shall remain within the scope of this invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention. Fig. 2 is a schematic cross-sectional view showing a semiconductor device (a) according to a preferred embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a semi-conductive device (2) according to a preferred embodiment of the present invention. 0 Fig. 4 is a schematic cross-sectional view showing a semiconductor device (3) according to a preferred embodiment of the present invention. Figure 5 is a cross-sectional view showing a semiconductor device (4) according to a preferred embodiment of the present invention. Figure 6 is a cross-sectional view showing a semiconductor device (5) according to a preferred embodiment of the present invention. Figure 7 is a cross-sectional view showing a semiconductor device (6) according to a preferred embodiment of the present invention. Figure 8 is a cross-sectional view showing a semiconductor device (seven) according to a preferred embodiment of the present invention. Figure 9 is a cross-sectional view showing a semiconductor device (VIII) according to a preferred embodiment of the present invention. Fig. 10 is a schematic cross-sectional view showing a semiconductor device (9) according to a preferred embodiment of the present invention. Figure 11 is a cross-sectional view showing a semiconductor device (10) according to a preferred embodiment of the present invention. Fig. 2 is a schematic cross-sectional view showing a semiconductor device (11) according to a preferred embodiment of the present invention. 20 200941658 Fig. 1 3 is a schematic cross-sectional view showing a semiconductor device (11) according to a preferred embodiment of the present invention. Figure 14 is a schematic cross-sectional view of a semiconductor device (12) of the preferred embodiment. Fig. 15 is a schematic cross-sectional view showing a semiconductor device (fourth) according to a preferred embodiment of the present invention. Fig. 16 is a schematic cross-sectional view showing a semiconductor device (105) according to a preferred embodiment of the present invention. Figure 17 is a cross-sectional view showing a semiconductor device (16) according to a preferred embodiment of the present invention. Figure 18 is a cross-sectional view showing a semiconductor device (17) according to a preferred embodiment of the present invention. Fig. 19 is a schematic view showing a scraping surface of a semiconductor device (seventh embodiment) of the present invention. Fig. 20 is a schematic cross-sectional view showing a semiconductor device (10. 9) according to a preferred embodiment of the present invention. Figure 21 is a cross-sectional view showing a semiconductor device in accordance with another preferred embodiment of the present invention. Figure 22 is a cross-sectional view showing a semiconductor device in accordance with still another preferred embodiment of the present invention. Figure 2 is a schematic cross-sectional view of a conventional semiconductor package device. Fig. 24 is a schematic cross-sectional view of a conventional semiconductor package device. Fig. 25 is a schematic cross-sectional view of a conventional cattle conductor package taken from the main point of the prior art. 21 200941658 [Description of main components] (Invention part) Semiconductor device 1, 2, 3 Metal substrate 1 0 Metal plate 1 0 1 Upper 1 ◦ 1 a €) Lower 1 0 1 b First and second insulation layers 1 0 2 , 1 0 3 patterned wiring bonding layer 1 0 4 bonding pad bonding layer 1 0 5 electrical pad bonding layer 1 0 6 pin bonding layer 1 0 7 凸 convex electrical pad bonding layer 1 0 8 column Pin-joining layer 1 0 9 semiconductor wafer 1 1 molding material 1 2 first and second resistance layers 2 0, 2 1 first opening 2 2 first recess 2 3 22 200941658 third resistive layer 2 4 second opening 2 5 fourth and fifth resistive layers 2 6, 2 third opening 2 8 second recess 2 9 thin wire circuit 3 0 solder resist layer 3 1 fourth opening 3 2 passive component 3 3 (conventional part) semiconductor device 4 substrate 4 1 Wafer 4 2 heat sink 4 3 recess 4 3 1 protrusion 4 3 2 encapsulant 4 4 semiconductor device 5 200941658 heat sink 5 2 semiconductor device 6 substrate 6 1 metal core layer 6 1 1 upper and lower surfaces 611a, 611b One or two graphic circuit layers 6 1 2, 6 1 3 First and second insulating layers 6 1 4, 6 1 5 Wafers 6 2 Package colloids 6 3 Blind holes 6 4 Thermally conductive material 6 5 Heat-dissipating balls 6 6

球墊6 7 錫球6 8 24Ball pad 6 7 solder ball 6 8 24

Claims (1)

200941658 十、申請專利範圍： 1 種具散熱增益之半導體裝置，係至少包括一具完 整線路面與完整接腳面之金屬基板、一半導體晶片 及一成型材料所組成，其中·· 該金屬基板係包含一金屬板材、一第一絕緣層 及一第一絕緣層。其中該金屬板材係包含一上部及 相對於上部之下部，並且在該金屬板材之上部係 〇 包括一置晶接墊區域及複數個圖案化線路區域，而 S亥第二絕緣層則設置在該些圖案化線路區域與該 置晶接墊區域之間；在該金屬板材之下部則係包括 有一與置晶接塾區域相連之電性接墊區域，以及含 指定數目之接腳區域，而該第一絕緣層則設置在該 些電性接墊區域與該些接腳區域之間； 該半導體晶片係含有複數個輪入/輸出（I/O) ❹ 接塾’且該半導體晶片係黏結於該金屬基板之置晶 接塾區域表面’並由該些I/O接塾電性連接至該些 圖案化線路區域；以及 該成型材料係用以封裝該半導體晶片以及該 金屬基板之上部。 2 ·依據申請專利範圍第1項所述之具散熱增益之半導 體裝置’其中，該成型材料並無連接於該第一絕緣 層0 25 200941658 3 .依據申請專利範圍第1項所述之具散熱增益之半導 體裝置，其中’該第一、二絕緣層之材料係可為防 焊綠漆、玻璃纖維與環氧樹脂所組成材料、雙馬來 亞醢胺-三氮雜苯樹脂（Bismaleimide Triazine，BT ) 及環氧樹脂。 4 ·依據申凊專利範圍第1項所述之具散熱增益之半導 體裝置’其中’該接腳區域係與該電性接塾區域及 Ο 該第一絕緣層在同一層次。 5 ·依據申凊專利範圍第1項所述之具散熱增益之半導 體裝置’其中，該些圖案化線路區域係與該置晶接 塾Εΐ域及5亥第二絕緣層在同一層次。 6 .依據申請專利範圍第1項所述之具散熱增益之半導 體裝置，其中，該些圖案化線路區域、置晶接墊區 域、電性接墊區域及接腳區域之表面接合層係經由 ® 一具選擇性之電鍍沉積過程所達成。 7 ·依據申請專利範圍第6項所述之具散熱增益之半導 體裝置，其中’該接合層之材料係包括鎳、金、鈀、 錫、銀及其組合。 8 ·依據申請專利範圍第1項所述之具散熱增益之半導 體裝置’其中，該金屬板材係可為銅及其合金、鋁、 合金42、鋼、鎳及其它導熱材料。 9依據申請專利範圍第1項所述之具散熱增益之半導 26 200941658 體裝置，其中，該金屬板材之厚度係可為〇·〇5毫 米（mm)〜0.5毫米（mm)。 1 0 · —種具散熱增益之半導體裝置，係至少包括一具 完整線路面與完整接腳面之金屬基板、一半導體晶 片及一成型材料所組成，其中： 该金屬基板係包含一金屬板材及一絕緣層。其 中5亥金屬板材係包含一上部及一相對於上部之_下 部’並且在該金屬板材之上部係包括一置晶接墊區 域及複數個圖案化線路區域；在該金屬板材之下部 則係包括有一與置晶接墊區域相連之電性接墊區 域，以及含指定數目之接腳區域，而該絕緣層則設 置在該些電性接墊區域與該些接腳區域之間； *亥半導體晶片係含有複數個I/O接整，且該半 導體晶片係黏結於該金屬基板之置晶接墊區域表 面，並由該些I/O接墊電性連接至該些圖案化線路 區域；以及 該成型材料係用以封裝該半導體晶片以及該 金屬基板之上部。 1依射請專利範目第1 C)項所狀具散熱增益之 f導體裝置，其中，該成型材料係與該些電性接墊 區域與該些接腳區域間之絕緣層連接。 2 .依據申請專利範圍第1〇項所述之具散熱增益之 27 200941658 2導體裝置’其中’該絕緣層之材料係可為防焊綠 =、一玻璃纖維與環氧樹騎組成㈣、雙馬來亞酿 胺一鼠雜苯樹脂及環氧樹脂。 13·依據申請專利範圍第10項所述之具散埶增益之 半導體裝置，其中，該接腳區域係與該電二： 域及該絕緣層在同一層次。 〇 14=據中請專利範圍第10項所述之具散熱增益之 體裝置’其中，該些圖案化線路區域、置晶接 墊區域、電性接墊區域及接腳區域之表面接合層係 經由一具選擇性之電鍍沉積過程所達成。 1 5 ·依據+請專利_第1 3項所収純熱增益之 半導體裝置，其中，該接合層之材料係包括鎳、金、 纪、錫、銀及其組合^ ❾16 ·依射請專㈣㈣1 〇項所述之純熱增益之 半導體裝置’其中，該金屬板材係可為銅及其合 金、鋁、合金42、鋼、鎳及其它導熱材料。 1 7 L依據申請專利範圍第1 〇項所述之具散熱增益之 半導體裝置，其中，該金屬板材之厚度係可為0.05 毫米（mm)〜〇.5毫米（mm)。 1 8 · —種具散熱增益之半導體裝置’係至少包括一具 完整線路面與完整接腳面之金屬基板、一半導體晶 片及一成型材料所組成，其中： 28 200941658 該金屬基板係包含一金屬板材及一絕緣層。其 中該金屬板材係包含一上部及一相對於上部之下 部’並且在該金屬板材之上部係包括一置晶接墊區 域及複數個圖案化線路區域，而該絕緣層則設置在 該些圖案化線路區域與該置晶接墊區域之間；在該 金屬板材之下部則係包括有一與置晶接墊區域相 連之凸狀電性接墊區域，以及含指定數目之柱狀接 0 腳區域； 該半導體晶片係含有複數個I/O接墊，且該半 導體晶片係黏結於該金屬基板之置晶接墊區域表 面’並由該些I/O接墊電性連接至該些圖案化線路 區域；以及 該成型材料係用以封裝該半導體晶片以及該 金屬基板之上部。 ❹19·依據申請專利範圍第18項所述之具散熱增益之 半導體裝置，其中，該絕緣層之材料係可為防焊綠 漆、玻璃纖維與環氧樹脂所組成材料、雙馬來亞醯 胺 ''二氣雜本樹脂及環氧樹脂。 20.依據申請專利範圍第i8項所述之具散熱增益之 半導體裝置’其中，該圖案化線路區域係與該置晶 接墊區域及該絕緣層在同一層次。 2 1 .依據申請專利範圍第丄8項所述之具散熱增益之 29 200941658 半導體裝置，其中，該些圖案化線路區域、置晶接 墊區域、凸狀電性接墊區域及柱狀接腳區域之表面 接合層係經由一具選擇性之電鍍沉積過程所達成。 2 2 ·依據申請專利範圍第2 1項所述之具散熱增益之 半導體裝置，其中，該接合層之材料係包括鎳、金、 鈀、錫、銀及其組合。 2 3 ·依據申請專利範圍第j 8項所述之具散熱增益之 半導體裝置’其中，該柱狀接腳區域係相同於該凸 狀電性接墊區域之高度。 2 4 ·依據申請專利範圍第1 8項所述之具散熱增益之 半導體裝置，其中，該柱狀接腳區域及該絕緣層係 無形成在同一平面。 2 5 ·依據申請專利範圍第1 8項所述之具散熱增益之 半導體裝置，其中’該金屬板材係可為銅及其合 金、鋁、合金42、鋼、鎳及其它導熱材料。 2 6 ·依據申請專利範圍第1 8項所述之具散熱增益之 半導體裝置’其中，該金屬板材之厚度係可為0.05 毫米（mm)〜〇·5毫米（mm)。200941658 X. Patent application scope: A semiconductor device with heat dissipation gain is composed of a metal substrate including a complete circuit surface and a complete pin surface, a semiconductor wafer and a molding material, wherein the metal substrate includes a metal plate, a first insulating layer and a first insulating layer. Wherein the metal sheet comprises an upper portion and a lower portion opposite to the upper portion, and the upper portion of the metal sheet includes a crystal pad region and a plurality of patterned wiring regions, and the second insulating layer is disposed on the metal plate. Between the patterned circuit region and the crystal pad region; the lower portion of the metal plate includes an electrical pad region connected to the crystal contact region, and a specified number of pin regions, and the a first insulating layer is disposed between the electrical pad regions and the pin regions; the semiconductor wafer system includes a plurality of wheel input/output (I/O) ports and the semiconductor chip is bonded to The surface of the metal substrate is electrically connected to the patterned wiring regions by the I/O pads; and the molding material is used to encapsulate the semiconductor wafer and the upper portion of the metal substrate. 2: The semiconductor device with heat dissipation gain according to claim 1 of the patent application, wherein the molding material is not connected to the first insulating layer 0 25 200941658 3 . According to claim 1 A semiconductor device of the gain, wherein the material of the first and second insulating layers is a material of solder resist green paint, glass fiber and epoxy resin, and Bismaleimide Triazine (Bismaleimide Triazine, BT) and epoxy resin. 4. The semiconductor device having a heat dissipation gain as described in claim 1 of the patent application, wherein the pin region is at the same level as the electrical interface region and the first insulating layer. 5. The semiconductor device having a heat dissipation gain according to claim 1, wherein the patterned wiring regions are at the same level as the planar wiring region and the fifth insulating layer. 6. The semiconductor device with heat dissipation gain according to claim 1, wherein the surface layer of the patterned wiring region, the pad region, the electrical pad region and the pin region is via a ® A selective electroplating deposition process is achieved. 7. A semiconductor device having heat dissipation gain according to claim 6 wherein the material of the bonding layer comprises nickel, gold, palladium, tin, silver, and combinations thereof. 8. A semiconductor device having heat dissipation gain as described in claim 1 wherein the metal sheet is copper and its alloys, aluminum, alloy 42, steel, nickel, and other thermally conductive materials. 9 The semiconductor device according to claim 1 of claim 1, wherein the thickness of the metal plate is 〇·〇 5 mm (mm) to 0.5 mm (mm). The semiconductor device with heat dissipation gain is composed of a metal substrate including at least one complete circuit surface and a complete pin surface, a semiconductor wafer and a molding material, wherein: the metal substrate comprises a metal plate and a metal plate Insulation. Wherein the 5H metal sheet comprises an upper portion and a lower portion relative to the upper portion and includes a crystal pad region and a plurality of patterned circuit regions on the upper portion of the metal plate; and the lower portion of the metal plate includes An electrical pad region connected to the region of the crystal pad and a specified number of pin regions, and the insulating layer is disposed between the electrical pad regions and the pin regions; The wafer system includes a plurality of I/Os, and the semiconductor wafer is bonded to the surface of the metal pad region of the metal substrate, and electrically connected to the patterned circuit regions by the I/O pads; The molding material is used to encapsulate the semiconductor wafer and the upper portion of the metal substrate. A f-conductor device having a heat dissipation gain according to the first aspect of the patent specification, wherein the molding material is connected to the electrical pad region and the insulating layer between the pin regions. 2. According to the scope of claim 1 of the patent application, the heat dissipation gain is 27 200941658 2 conductor device 'where the material of the insulation layer can be welding green =, a glass fiber and epoxy tree ride (four), double Malayan Amine-Phenylbenzene Resin and Epoxy Resin. 13. The semiconductor device having a divergence gain according to claim 10, wherein the pin region is at the same level as the electrical second: domain and the insulating layer. 〇14=The body device with heat dissipation gain according to Item 10 of the patent scope, wherein the surface layer layer of the patterned circuit region, the crystal pad region, the electrical pad region and the pin region This is achieved through a selective electroplating deposition process. 1 5 · According to the patent device of the pure heat gain received in the patent of §13, wherein the material of the bonding layer includes nickel, gold, gold, tin, silver and a combination thereof. ❾16 · According to the shot, please (4) (4) 1 〇 The pure heat gain semiconductor device of the above description, wherein the metal sheet may be copper and its alloys, aluminum, alloy 42, steel, nickel, and other thermally conductive materials. 1 7 L The semiconductor device having heat dissipation gain according to the first aspect of the patent application, wherein the thickness of the metal plate may be 0.05 mm (mm) to 5.5 mm (mm). 1 8 · A semiconductor device with heat dissipation gain is composed of a metal substrate including a complete line surface and a complete pin surface, a semiconductor wafer and a molding material, wherein: 28 200941658 The metal substrate comprises a metal plate And an insulating layer. Wherein the metal sheet comprises an upper portion and a lower portion relative to the upper portion and includes a crystal pad region and a plurality of patterned circuit regions on the upper portion of the metal plate, and the insulating layer is disposed on the patterning layer Between the line region and the crystal pad region; the lower portion of the metal plate includes a convex electrical pad region connected to the crystal pad region, and a specified number of columnar pin pads; The semiconductor wafer includes a plurality of I/O pads, and the semiconductor wafer is bonded to the surface of the metal pad substrate of the metal substrate and electrically connected to the patterned circuit regions by the I/O pads. And the molding material is used to encapsulate the semiconductor wafer and the upper portion of the metal substrate. ❹19. The semiconductor device with heat dissipation gain according to claim 18, wherein the material of the insulating layer is a material of solder resist green paint, glass fiber and epoxy resin, and bismaleide ''Two gas mixed resin and epoxy resin. 20. The semiconductor device having heat dissipation gain according to claim i8, wherein the patterned wiring region is at the same level as the crystal pad region and the insulating layer. 2 1. The semiconductor device according to claim 29, wherein the patterned circuit region, the crystal pad region, the convex electrical pad region and the column pin The surface bonding layer of the region is achieved via a selective electroplating deposition process. 2 2 . The semiconductor device having heat dissipation gain according to claim 21, wherein the material of the bonding layer comprises nickel, gold, palladium, tin, silver, and combinations thereof. 2 3 . The semiconductor device having a heat dissipation gain according to the invention of claim j. wherein the columnar pin region is the same as the height of the convex electrical pad region. The semiconductor device having heat dissipation gain according to claim 18, wherein the columnar pin region and the insulating layer are not formed on the same plane. 2 5 . The semiconductor device having heat dissipation gain according to claim 18, wherein the metal plate is made of copper and its alloy, aluminum, alloy 42, steel, nickel and other heat conductive materials. 2 6 . The semiconductor device having heat dissipation gain according to claim 18 of the patent application, wherein the thickness of the metal plate may be 0.05 mm (mm) to 5 5 mm (mm).
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8598463B2 (en) 2010-08-05 2013-12-03 Unimicron Technology Corp. Circuit board and manufacturing method thereof
US10340199B2 (en) 2014-11-20 2019-07-02 Mediatek Inc. Packaging substrate with block-type via and semiconductor packages having the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8598463B2 (en) 2010-08-05 2013-12-03 Unimicron Technology Corp. Circuit board and manufacturing method thereof
US10340199B2 (en) 2014-11-20 2019-07-02 Mediatek Inc. Packaging substrate with block-type via and semiconductor packages having the same

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