SU1552391A1 - Reference voltage shapaer for demodulator of phase-manipulated signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the noise immunity. The driver contains a frequency multiplier 1, a narrowband filter 2, a frequency divider 3, a phase shifter 4, a phase keyer 5, a delay line 6, phase detectors 7 and 10, a threshold unit 8, and a trigger 9. The goal is achieved by introducing a phase correction unit 11, a limiting amplifier 12, And 13 and 14 elements and an inverter 15, by which the slow departure of the phase of the reference voltage is avoided and the initial phase of the received signal is determined. 2 Il.

Description

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The invention relates to telecommunications and may find application in data transmission systems.

The purpose of the invention is to increase immunity.

FIG. Figure 1 shows the structural and electrical diagram of the former; in fig. 2 - stress diagrams for his work.

The shaper contains a frequency multiplier 1, a narrow-band filter 2, a frequency divider 3, a phase shifter 4, a phase keyer 5, a delay line 6, a first phase detector 7, a threshold unit 8, a trigger 9, a second phase detector 10, a phase correction unit 11, the amplifier-limiter 12, the first element And 13, the second element And 14 and the inverter 15, and the phase correction unit 11 contains the amplifier-limiter 16, the differentiating element 17, the delay element 18, the element 19, the element OR 20, the inverter 21, the shift register 22, the decoder 23 and the driver 24 pulses.

Shaper works as follows.

Let the signals of a single phase manipulation of the form enter the shaper input (Fig. 2a).

S; (t) umcos (u0t + q 0 + y),

where Um, С0 „- exactly the amplitude and frequency of the signal at the receiving point; tfo is the initial phase of the signal

i 1,2 - random information parameter of the signal.

These signals are fed to the input of frequency multiplier 1, where the phase of the signal is eliminated during the frequency wiping process, then the effect of interference is attenuated in narrowband filter 2. With the help of the divider 3 frequency and the phase shifter 4, a reference oscillation of the type is formed (Fig. 2g)

Son (t) U cos (cOet), which is fed to the inputs of the first phase detector 7 (to the first one directly, and to the second through the delay line 6).

Prior to the occurrence of a jump in the phase of the reference voltage, the phase difference of the voltages at the outputs of the first phase detector 7 is constant and is determined by the delay time of the delay line 6. In my

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15 20 25

thirty

35

40

45

50

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The phenomenon of the appearance of the Fata jump, the phase difference of the voltage at the inputs of the first phase detector 7 also changes abruptly. This triggers the threshold unit 8, the trigger 9 overturns into another state and causes the phase manipulator 5 to change the phase of the reference voltage by 180.

Thus, this part of the driver circuit eliminates rapid changes in the phase of the reference oscillation. However, it cannot eliminate the slow departure of the phase of the reference voltage and does not determine the initial phase of the received signal. These tasks are solved by the phase correlation unit 11 together with the first and second elements 13 and 14, the inverter 15 and the amplifier-limiter 12.

The input information combination is fed to the input of the amplifier-limiter 16, in which the formation of positive pulses of duration 0.5 TC-Tc (Fig. 2b). Pulses with a duration of 0, ЬТС are formed with a positive input wave half-wave and no phase jumps. Formed in the limiter 16, the sequence is fed to the first input of the element And 19

and differentiating element 17, which separates the leading edges of the pulses (Figure 2b). Next, short pulses through the delay element 18 (Fig. 2d) arrive at the second input of the And 19 element. The delay element 18 delays the input sequence of pulses by 3 / 4TC (Fig. 2d).

Thus, the signal at the output of the element And 19 appears when the pulse duration from the output of the amplifier-limiter 16 is greater than or equal to 3/4TC, which corresponds to the time of the phase change in the positive half-wave of the information signal (fig.2d). The signal from the output of the AND element 19 is fed to the input of the shift register 22 and is written to it. The capacity of the register is calculated for the length of the code

combinations that determine the beginning of the reception. From the output of the shift register 22, the signals in the paraple code are allocated to the decoder 23, which selects the given combination from all possible combinations of symbols. The reception signal of the initial combination (Fig. 2e) is fed to the pulse shaper 24, where it is delayed by 1 / 4TG and

converted to a form sufficient for the normal operation of the first and second elements And 13 and 14, to the first inputs of which it enters. The second inputs of these elements are supplied with voltage from the output of amplifier-limiter 12. The circuit is designed so that when 1 pulse coincides with the output of amplifier-limiter 12 (Fig. 2h) with the pulse from the output of the imager 24 pulses, the signal from the output of the first element And 13 (Fig. 2i) goes to the third input of the trigger 9 and sets it to the zero state (Fig. 2k). If the coincidence occurred at the time of zero voltage from the output of the amplifier-limiter 12, then the signal from the output of the second element

Signagg, containing serially connected frequency multiplier, UCP filter, frequency divider Phaser, first phase detector, threshold unit, trigger, phase switch and second phase detector, the output of the phase shifter through the delay line connected to the second input of the first phase detector, input multiplier frequency is connected to the second input of the second phase detector and is the input of the generator, the output of which is the output of the second 15 phase detector, characterized in that, in order to increase the resistance, introduced in series United phase correction unit and the first element And, after 25

This AND 14 arrives at the second input of the Trig-20 Consecutively connected amplifier-ragger 9 and installs it into the unit, the inverter and the second element, And

the second input and output of which is connected respectively to the output of the phase correction unit and the second input of the trigger, the third input of which is connected to the output of the first element And, the second input of which is connected to the output of the amplifier-limiter, the input of which is connected to the output of the phase shifter, the input of the frequency multiplier is connected to the input the correction unit, and the output of the delay line is connected to the second input of the phase manipulator.

condition. Thus, the initial setting of the trigger 9 is set and the initial phase for the manipulator 5 of the phase is determined (FIG. 2L). In accordance with the phase of the reference voltage supplied to the first input of the second phase detector 10 from the output of the phase manipulator 5, the initial information sequences of binary signals (FIG. 2m).

Claims (1)

Invention Formulation Voltage Driver for demodulator phase shift keying Signagg, containing serially connected frequency multiplier, UCP filter, frequency divider Phaser, first phase detector, threshold unit, trigger, phase switch and second phase detector, the output of the phase shifter through the delay line connected to the second input of the first phase detector, input multiplier frequency is connected to the second input of the second phase detector and is the input of the generator, the output of which is the output of the second 5 phase detector, characterized in that, in order to increase ehozaschischennosti, administered serially connected phase correction unit and a first AND gate, posle25 thirty . K / l XXXX  / I s s s s and to t U XX jr four XX XX i II1P Figg P - t 47 / N / y s