SG10202005368UA - Memory device and method of operating the memory device - Google Patents
Memory device and method of operating the memory deviceInfo
- Publication number
- SG10202005368UA SG10202005368UA SG10202005368UA SG10202005368UA SG10202005368UA SG 10202005368U A SG10202005368U A SG 10202005368UA SG 10202005368U A SG10202005368U A SG 10202005368UA SG 10202005368U A SG10202005368U A SG 10202005368UA SG 10202005368U A SG10202005368U A SG 10202005368UA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- operating
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5644—Multilevel memory comprising counting devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190100570A KR20210020697A (en) | 2019-08-16 | 2019-08-16 | Memory device and operating method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202005368UA true SG10202005368UA (en) | 2021-03-30 |
Family
ID=74567435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202005368UA SG10202005368UA (en) | 2019-08-16 | 2020-06-08 | Memory device and method of operating the memory device |
Country Status (4)
Country | Link |
---|---|
US (1) | US11270760B2 (en) |
KR (1) | KR20210020697A (en) |
CN (1) | CN112397126B (en) |
SG (1) | SG10202005368UA (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200141304A (en) * | 2019-06-10 | 2020-12-18 | 에스케이하이닉스 주식회사 | Semiconductor device and operating method of semiconductor device |
KR20210112661A (en) * | 2020-03-05 | 2021-09-15 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof |
US11636897B2 (en) | 2021-03-03 | 2023-04-25 | Sandisk Technologies Llc | Peak current and program time optimization through loop dependent voltage ramp target and timing control |
US11972801B2 (en) | 2022-02-07 | 2024-04-30 | Sandisk Technologies, Llc | Program voltage dependent program source levels |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3836985B2 (en) * | 1998-09-07 | 2006-10-25 | 松下電器産業株式会社 | Semiconductor device |
KR100635205B1 (en) | 2004-11-15 | 2006-10-16 | 에스티마이크로일렉트로닉스 엔.브이. | Method of reading a flash memory device |
KR100729351B1 (en) | 2004-12-31 | 2007-06-15 | 삼성전자주식회사 | Nand flash memory device and program method thereof |
KR100669349B1 (en) * | 2005-12-02 | 2007-01-16 | 삼성전자주식회사 | Flash memory device and read method thereof |
KR100822805B1 (en) * | 2006-10-20 | 2008-04-18 | 삼성전자주식회사 | Flash memory device having multiple speed operation mode |
KR101448851B1 (en) | 2008-02-26 | 2014-10-13 | 삼성전자주식회사 | Programming method of Non-volatile memory device |
KR101575851B1 (en) * | 2009-03-13 | 2015-12-10 | 삼성전자주식회사 | Non-volatile memory device and program method thereof |
JP2011065708A (en) * | 2009-09-16 | 2011-03-31 | Toshiba Corp | Nonvolatile semiconductor memory device |
KR20120121166A (en) * | 2011-04-26 | 2012-11-05 | 에스케이하이닉스 주식회사 | Semiconductor device and operating method thereof |
KR101184539B1 (en) * | 2011-06-28 | 2012-09-19 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method of operating thereof |
KR20130072087A (en) * | 2011-12-21 | 2013-07-01 | 에스케이하이닉스 주식회사 | Nonvolatile memory device, method of fabricating the same, and method of operating the same |
KR101925018B1 (en) * | 2012-06-19 | 2018-12-05 | 삼성전자주식회사 | Non-volatile memory device |
KR101999764B1 (en) * | 2012-08-24 | 2019-07-12 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR20140026115A (en) * | 2012-08-24 | 2014-03-05 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
KR102081757B1 (en) | 2013-06-26 | 2020-02-26 | 삼성전자주식회사 | Nonvolatile memory device and program method thereof |
KR102161737B1 (en) * | 2013-12-02 | 2020-10-05 | 삼성전자주식회사 | Bit line sensing method of semiconduct memory device |
CN103956187B (en) * | 2014-05-12 | 2017-07-18 | 北京兆易创新科技股份有限公司 | A kind of dynamic preliminary filling control circuit and flash-memory storage system |
CN106373615A (en) * | 2015-07-20 | 2017-02-01 | 毛冬冬 | Design of OTP memory with characteristic of regulation of readout speed with bit line load |
KR20180086047A (en) * | 2017-01-20 | 2018-07-30 | 삼성전자주식회사 | A nonvolatile memory device for varying a recovery interval and an operation method thereof |
US11361819B2 (en) * | 2017-12-14 | 2022-06-14 | Advanced Micro Devices, Inc. | Staged bitline precharge |
-
2019
- 2019-08-16 KR KR1020190100570A patent/KR20210020697A/en not_active Application Discontinuation
-
2020
- 2020-04-23 US US16/856,695 patent/US11270760B2/en active Active
- 2020-06-01 CN CN202010486460.5A patent/CN112397126B/en active Active
- 2020-06-08 SG SG10202005368UA patent/SG10202005368UA/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN112397126B (en) | 2024-04-23 |
US11270760B2 (en) | 2022-03-08 |
CN112397126A (en) | 2021-02-23 |
KR20210020697A (en) | 2021-02-24 |
US20210050051A1 (en) | 2021-02-18 |
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