RU2828235C1 - Device for detecting groups of single bits in data units within given boundaries - Google Patents

Abstract

FIELD: data processing devices.

SUBSTANCE: invention relates to data processing devices and can be used to construct functional units for analysing properties of generators of pseudorandom sequences of binary numbers. Device comprises an external N-bit input bus, two decoders, two groups of (N-1)-th OR elements, a group of N AND elements with inverse input 10₁, 10₂, … 10_N, two units for counting units, a first unit for detecting lower limit 5L and a second unit for detecting upper limit 5H, each of which contains a group of N detection units 6₁, 6₂, …, 6_N, N groups 7₁, 7₂, … 7₁ of (N+1-I) OR elements with inverse input of 1st detection units 6₁, first group of (N-1)-th AND elements with inverse inputs 8₂, 8₃, …, 8_N, second group of (N-1)-th AND elements with inverse input 9₂, 9₃, …, 9_N, AND element 13, internal buses of lower BUL and upper BUH boundaries, initial digits of groups of the specified range BLH, lower BL and upper BH boundaries.

EFFECT: enabling detection of groups of single bits in a given range of bits, determination of the number of detected groups and their arrangement in data units.

1 cl, 2 dwg

Description

AREA OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to construct functional units for analyzing the properties of generators of pseudo-random sequences of binary numbers, filtering events, processing signals, images and results of physical experiments.

PRIOR ART

A device for detecting groups of bits is known (RU No. 2780985 C1, IPC G06F 7/74, G06F 7/02, declared 01.12.2021, published 04.10.2022, Bulletin No. 28), contains an external m-bit data input ID, an external m-bit input of a given template IG, a group of external data outputs QB, the first RS start-stop trigger TSS 1, the second D-trigger TR2 delay 2, the counter CTG groups 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, a group of m comparators a group of (m-1) elements AND element OR 9 and element AND 10, and also external inputs of asynchronous reset to zero state CLR, device start START, device stop STOP and clock C, internal 2m-bit data bus BD, internal m-bit buffer data bus IOB, internal coincidence flag FE, external exchange control bus EO, external flag "Buffer full" FF and flag "Buffer empty" FZ are introduced.

The disadvantage of this device is that it identifies at each clock cycle groups of bits that correspond only to a given pattern.

A device for detecting groups of single bits and the maximum group in data blocks is known (RU No. 280039 C1, IPC G06F 7/74, declared 03/09/2023, published 07/17/2023, Bulletin No. 20), comprising an external input data bus IBD, a group of external outputs of the number of groups in the block QB, a group of external outputs of the maximum group QM and a group Q1, Q2, Q3, Q4 of external outputs of the number of single groups in the input sequence, the first groups of AND elements with inverted inputs, a group of AND elements OR element 5, adder group group of registers group of units counting blocks group of elements OR priority encoder 10, the first OB and the second OM output buffers, and also external inputs of the synchronous setting to the zero state IR and clock IC, a group of internal buses B1, B2, B3 and B4, an internal flag FB4, external exchange control buses EO, external flags “Buffer full” FF and “Buffer empty” FZ are introduced.

The disadvantage of this device is that it detects only 1, 2, 3, ≥4 bit groups in 8-bit data blocks.

The closest device of the same purpose to the claimed invention in terms of a set of features is a device for detecting single groups of bits in a binary sequence (RU No. 2763859 C1, IPC G06F7/74, H03K 21/00, declared on 29.04.2021, published on 11.01.2022, Bulletin No. 2), adopted as a prototype, comprises an external data input DI, a group of external data outputs QB, a group of external outputs of the number of groups QG, the first RS start-stop trigger TSS 1, the first bit counter CTB 2, the register of the first bit of the group number RGB 3, the first AND element 4, the first OR element 5 with one inverse input, the second single-bit trigger TR1 6, the second AND element 7 with one inverse input, the second counter of units CTU 8, the lower bound equality block 9, the upper bound equality block 10, the third the lower boundary trigger TRL 11, the fourth upper boundary trigger TRM 12, the third 13 and fourth 14 AND elements with two inverse inputs, the second OR element 15, the output buffer OB 16 and the third counter of the number of groups CTG 17, as well as external inputs of asynchronous setting to zero state CLR, device start START, device stop STOP and clock C, external input buses of the lower boundary GL and upper boundary GM of the range of single bits, external exchange control bus EO, external flag "Buffer full" FF and flag "Buffer empty" FZ are introduced. In this device, groups of single bits of a given dimension are detected within the lower GL and upper GM boundaries of the range.

The disadvantage of this device is its low speed, since the input data is received sequentially, one digit (bit) at each clock cycle.

OBJECTIVE OF THE INVENTION

The objective of the invention is to develop hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments.

When analyzing generators of pseudo-random binary number sequences, the device is designed to identify groups (rows) of consecutive single bits of capacity within specified range boundaries and count the number of such groups.

When processing the results of physical experiments, the device is designed to identify events of a given dimension, determine their number and place them in data blocks.

The technical result of the invention is the expansion of the arsenal of means for the same purpose, in terms of ensuring the possibility of detecting groups of single bits in a given range of bit depth, determining the number of identified groups and their placement in data blocks.

BRIEF DESCRIPTION OF THE ESSENCE OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the device for detecting in data blocks groups of single bits within specified limits contains an external N-bit input data bus ID of data blocks G, external M-bit input buses for setting the lower IL and upper IH limits, where M=]log2 N[ is a larger integer, groups of external outputs of the number of groups of the specified range QLH and is greater than the upper limit QH, initial digits of groups of the specified range QULH and the upper limit QUH, the first 1 and second 2 decoders, the first and the second groups of (N-1) OR elements, a third group of N AND elements with an inverted input first 11 and second 12 units counting units, first lower boundary detection module 5L and second upper boundary detection module 5H, each of which contains a group of N detection units N groups from (N+1-I) OR elements with inverted input of the 1st detection blocks 6 _I , where the first group of (N-1) AND gates with inverted inputs the second group of (N-1)-th AND elements with inverted input and element I 13,

and also internal buses of the lower BUL and upper BUH boundaries, initial digits of groups of a given range BLH, lower BL and upper HH boundaries were introduced,

wherein the bits of the external input buses for setting the lower IL and upper IH boundaries are connected to the address inputs of the first 1 and second 2 decoders, respectively, whose outputs, from the first output to the (N-1)th output, are connected to the first inputs of the corresponding identical (N-1)th OR elements, respectively, of the first and the second groups, the outputs of which are the corresponding bits of the same name, from the first bit to the (N-1)-th bit, the internal buses of the lower BUL and upper BUH boundaries, respectively, whose N-th bits are connected to the N-th outputs of the first 1 and second 2 decoders, respectively, as well as the outputs of the elements in the first groups, starting from the output of the (N-1)th element to the second element, are connected to the second inputs of the corresponding previous OR elements in the first and the second groups, starting from the (N-2)-th element to the first element, and the second inputs of the (N-1)-th elements of the groups are connected to the N-th outputs of the first 1 and second 2 decoders, respectively,

wherein the bits of the external input data bus ID are connected to the first groups of inputs II of the first lower boundary detection module 5L and the second upper boundary detection module 5H, in which the second groups of inputs 12 are connected to the bits of the internal buses of the lower BUL and upper BUH boundaries, respectively,

in addition, in the first module of detection of the lower boundary 5L and the second module of detection of the upper boundary 5H, the digits of the first groups of inputs II in groups of (N+1-I) digits, each of which starts from the 1st digit to the Nth digit connected in the corresponding 1st blocks of 6 _I detection group with second direct inputs of OR elements with inverse input of groups , in which the first inverse inputs are connected to the digits of the second groups of inputs by 12 groups of (N+1-I) digits, each of which starts from the 1st digit to the (N+lI)th digit, while the outputs of the OR elements with the inverse input of the groups detection blocks 6 _I , starting from the second block 6 ₂ to the N-th block 6 _N , are connected to the direct inputs of the same-name elements AND with the inverse inputs of the first group the inverse inputs of which are connected to the digits of the second groups of inputs by 12 groups of J digits, each of which starts from the N-th digit to the second digit, where and the outputs of OR elements with the inverse input of the group the first detection block 61 are connected to the inputs of the AND element 13,

and the outputs of the AND elements with the inverted inputs of the first group connected to the direct inputs of the same-name elements AND with the inverse inputs of the second group which have the first inverted inputs (N-2) of AND elements, starting from the third element to the Nth element connected to the direct inputs of the corresponding previous (N-2) AND elements from the second group starting from the second element up to (N-1)th element and the first inverse input of the second element connected to the output of element AND 13,

in addition, the outputs of all (N-1) AND gates with inverted input from the second group are the corresponding identical (N-1) digits, starting from the second digit to the N-th digit, of the groups of outputs Q of the corresponding modules for detecting the boundaries of the lower 5L and upper 5H, and the first digit of the outputs Q is connected to the output of the corresponding AND element 13,

wherein the output group bits Q of the detection modules of the lower 5L and upper 5H boundaries are the same-name bits of the internal buses of the initial bits of the groups of the lower BL and upper BH boundaries, respectively, and all N bits of the bus of the lower boundary BL are connected to the direct inputs of the same-name AND elements with the inverse input of the third group the outputs of which are the bits of the internal bus of the initial bits of the groups of the given range BLH, which is connected to the same-name bits of the external outputs of the initial bits of the groups of the given range QULH and is connected to the inputs of the first unit counting block 11, the outputs of which are the corresponding bits of the group of external outputs of the number of groups of the given range QLH,

where all N bits of the internal bus of the initial bits of the groups of the upper HV boundary are connected to the inverse inputs of the same-name elements AND with the inverse input of the third group and are also the same-named digits of the external outputs of the initial digits of the groups of the upper limit of QUH and are connected to the inputs of the second unit counting block 12, the outputs of which are the corresponding digits of the group of external outputs of the number of groups greater than the upper limit of QH.

BRIEF DESCRIPTION OF DRAWINGS

Fig. 1 shows the diagram of the proposed device. Fig. 2 shows the timing diagram of the device operation for N=8 bit depth of input blocks.

In Fig. 1 - 2 and in the text the following designations are used:

AND - the AND element,

ВН - internal N-bit bus of initial bits of upper boundary groups,

BL - internal N-bit bus of initial bits of lower boundary groups,

BLH - internal N-bit bus of initial bits of groups of a given range,

BUH - internal N-bit upper boundary bus,

BUL - internal N-bit lower boundary bus,

DC decoder,

G (G1, G2, …, G10) - input N-bit data blocks,

I1, I2 - the first and second groups of inputs of the boundary detection modules,

ID - external N-bit input bus of data blocks G,

IH - external M-bit input bus for setting the upper limit,

where M=]log2 N[ is the larger integer,

IL - external M-bit input bus for setting the lower limit,

H - upper limit of the range,

L - lower limit of the range,

N - the bit depth of the input data block,

OR - OR element,

Q - group of outputs of the boundary detection modules,

QH - group of external outputs of the number of groups is greater than the upper limit,

QLH - group of external outputs of the number of groups of a given range,

QUH - a group of external outputs of the initial digits of the upper boundary groups,

QULH - a group of external outputs of the initial digits of groups of a given range,

1 - first lower boundary decoder,

2 - the second upper boundary decoder,

- the first group of (N-1) OR elements,

- the second group of (N-1) OR elements,

5L - first module of detection of the lower limit,

5H - the second upper limit detection module,

- a group of N detection blocks,

- N groups of (N+1-I) OR elements with inverted input of the 1st detection blocks 6 _I , where 1 = 1, …, N,

- the first group of (N-1) AND elements with inverted inputs,

- the second group of (N-1) AND elements with inverted input,

- the third group of N AND elements with inverted input,

11 - the first block of units counting,

12 - the second block of units counting,

13 - element I.

The proposed device comprises an external N-bit input data bus ID of data blocks G, external M-bit input buses for setting the lower IL and upper IH boundaries, where M=]log2 N[ is a larger integer, groups of external outputs of the number of groups of a given range QLH and greater than the upper boundary QH, initial digits of groups of a given range QULH and the upper boundary QUH, the first 1 and second 2 decoders, the first and the second groups of (N-1) OR elements, a third group of N AND elements with an inverted input first 11 and second 12 units counting units, first lower boundary detection module 5L and second upper boundary detection module 5H, each of which contains a group of N detection units N groups from (N+1-I) OR elements with inverted input of the 1st detection blocks 6 _I , where I = 1, …, N, the first group of (N-1)-th AND elements with inverted inputs the second group of (N-1)-th AND elements with inverted input and element I 13.

Also introduced are internal buses of the lower BUL and upper BUH boundaries, initial digits of groups of a given range BLH, lower BL and upper HH boundaries.

The bits of the external input buses for setting the lower IL and upper SH boundaries are connected to the address inputs of the first 1 and second 2 decoders, respectively, whose outputs, from the first output to the (N-1)th output, are connected to the first inputs of the corresponding identical (N-1)th OR elements, respectively, of the first and the second groups, the outputs of which are the corresponding bits of the same name, from the first bit to the (N-1)th bit, of the internal buses of the lower BUL and upper BUH boundaries, respectively, in which the N-th bits are connected to the N-th outputs of the first 1 and second 2 decoders, respectively.

Outputs of elements in the first and the second groups, starting from the output of the (N-1)th element to the second element, are also connected to the second inputs of the corresponding previous OR elements in the first groups, starting from the (N-2)-th element to the first element. The second inputs of the (N-1)-th elements of the groups are connected to the N-th outputs of the first 1 and second 2 decoders, respectively.

The bits of the external input data bus ID are connected to the first groups of inputs II of the first lower boundary detection module 5L and the second upper boundary detection module 5H, whose second groups of inputs 12 are connected to the bits of the internal buses of the lower BUL and upper BUH boundaries, respectively.

In the first module of detection of the lower boundary 5L and the second module of detection of the upper boundary 5H, the digits of the first groups of inputs I are in groups of (N+1-I) digits, each of which starts from the 1st digit to the Nth digit connected in the corresponding 1st blocks 6i of the group detection with second direct inputs of OR elements with inverse input of groups in which the first inverse inputs are connected to the digits of the second groups of inputs by 12 groups of (N+1-I) digits, each of which starts from the 1st digit to the (N+lI)th digit, while the outputs of the OR elements with the inverse input of the groups detection blocks starting from the second block to N-th block connected to the direct inputs of the same-name elements AND with the inverse inputs of the first group the inverse inputs of which are connected to the digits of the second groups of inputs by 12 groups of J digits, each of which starts from the N-th digit to the second digit, where (J = 1, …, (N-1)), and the outputs of OR elements with the inverse input of the group the first detection block 6 ₁ are connected to the inputs of the AND element 13.

Outputs of AND gates with inverted inputs of the first group connected to the direct inputs of the same-name elements AND with the inverse inputs of the second group which have the first inverted inputs (N-2) of AND elements, starting from the third element to the Nth element connected to the direct inputs of the corresponding previous (N-2) AND elements from the second group starting from the second element up to (N-1)th element and the first inverse input of the second element connected to the output of element AND 13.

Outputs of all (N-1) AND gates with inverted input from the second group are the corresponding identical (N-1) digits, starting from the second digit to the N-th digit, of the groups of outputs Q of the corresponding modules for detecting the boundaries of the lower 5L and upper 5H, and the first digit of the outputs Q is connected to the output of the corresponding AND element 13.

The output group bits Q of the detection modules of the lower 5L and upper 5H boundaries are the same-name bits of the internal buses of the initial bits of the groups of the lower BL and upper BH boundaries, respectively. Moreover, all N bits of the bus of the lower boundary BL are connected to the direct inputs of the same-name elements AND with the inverse input of the third group the outputs of which are the bits of the internal bus of the initial bits of the groups of the given range BLH, which is connected to the same-name bits of the external outputs of the initial bits of the groups of the given range QULH and is connected to the inputs of the first unit counting block 11, the outputs of which are the corresponding bits of the group of external outputs of the number of groups of the given range QLH.

Moreover, all N bits of the internal bus of the initial bits of the groups of the upper HV boundary are connected to the inverse inputs of the same-name elements AND with the inverse input of the third group and are also the same-named digits of the external outputs of the initial digits of the groups of the upper limit of QUH and are connected to the inputs of the second unit counting block 12, the outputs of which are the corresponding digits of the group of external outputs of the number of groups greater than the upper limit of QH.

DETAILED DESCRIPTION OF THE ESSENCE OF THE INVENTION

The operating principle of the proposed device is as follows.

The proposed device allows detecting in N-bit blocks of input data G single groups (rows) containing a number of single bits in a given range from the lower boundary L to the upper boundary H (the groups contain ≥L (L or more) and <H (less) single bits, where L<H, H≤N). In addition, the number of such groups and their location in data blocks, as well as the number of groups containing ≥H (H or more) single bits, are determined.

The input N-bit data blocks G are sequentially fed to the external input data bus ID in each clock cycle. The bit depth of the boundaries of the detected single groups is specified in binary code - the lower limit of the range L on the external input task bus IL, the upper limit of the range H on the external input task bus IH, (the number of bits of which is M =]log2 N [greater integer), which are transmitted to the first 1 and second 2 decoders DC. Then in the first and the second in groups of OR elements, binary codes of the IL and IH boundaries are converted into corresponding unitary L and H-bit single rows, starting from the first bit, which are transmitted to the corresponding internal buses of the lower boundary BUL and the upper boundary BUH, for example, for L=3, the value on the BUL[8-1]=0000 0111 bus is formed with the block bit depth N=8.

In the first 5L and second 5H boundary detection modules, the detection of single groups (rows) containing ≥L and ≥H single bits, respectively, is carried out and the formation of the initial bits of the detected single groups in the current block G on the input data bus ID on the corresponding internal buses BL and BH.

In this case, in groups of N detection blocks respectively in the first 5L and in the second 5H border detection modules, on OR elements with an inverse input of the corresponding groups of the same name masking of the senior bits from the input data bus ID corresponding to the zero bits from the internal buses for specifying the bit depth of the lower boundary BUL and the upper boundary BUH is carried out. In this case, single values are formed at the outputs of the corresponding masked OR elements with an inverse input, and the corresponding values of the bits from the input data bus ID for the specified bit depths of the detected groups of the lower boundary BUL and the upper boundary BUH are transmitted to the outputs of the non-masked OR elements with an inverse input. In this case, in the corresponding detection blocks (N+1-I) discharge groups are allocated, where

Next, on the AND elements 13 and in the first groups of (N-1) AND elements with inverted inputs respectively, the first 5L and the second 5H boundary detection modules, a check is carried out for the presence of single groups containing ≥L and ≥H single bits, respectively, and upon detection of such single groups at the corresponding outputs of the AND element 13 and in the first groups of the (N-1)-th AND elements with inverted inputs single values are formed.

If there are single groups containing a bit greater than the specified limits in the input blocks G on the ID bus, respectively ≥L and ≥H, several desired adjacent single groups will be detected (single values will be set at the outputs of adjacent AND 13 elements and group ). Masking of adjacent single groups belonging to the same group in the input ID block is performed in the second group AND elements with an inverted input. In this case, the unit value is retained at the outputs of the elements corresponding to the initial (lower) digits of the identified unit groups.

Values from the outputs of element I 13 and the second group elements AND with an inverse input are the outputs of the Q modules for detecting the lower 5L and upper 5H boundaries and are connected to the corresponding bits of the internal N bit buses of the initial bits of the groups of the lower boundary BL and upper boundary BH, respectively.

Next in the third group of N AND gates with inverted input masking of the identified groups containing ≥N single bits is carried out. The values from the outputs of the third group of elements are the corresponding bits of the internal N-bit bus BLH of the initial bits of the groups of the given range, which are then fed to the group of inputs of the first unit counting block 11, in which the number of identified unit groups corresponding to the given range of boundaries ≥L and <H is counted in the current block of input data ID.

Next, the values from the output of the first unit counting block 11 are transmitted to the group of external outputs of the number of groups of the specified range QLH, and the values of the bits from the internal bus BLH of the initial bits of the groups of the specified range are the corresponding bits of the group of external outputs of the initial bits of the groups of the specified range QULH.

In addition, the values of the bits from the internal bus of the initial bits of the groups of the upper limit of the VN are the corresponding bits of the group of external outputs of the initial bits of the groups of the upper limit of the QUH, and are also sent to the group of inputs of the second unit counting block 12, in which the number of detected unit groups exceeding the upper limit of the range>H is counted, and the value from the output of the second unit counting block 12 is transmitted to the group of external outputs of the number of groups greater than the upper limit of the QH.

The proposed device operates as follows.

Fig. 2 shows the timing diagram for identifying single groups in the input N=8-bit ten data blocks. when setting the bit depth of the lower boundary IL=1, 2 and 4 and the upper boundary IH=4 and 5.

In cycles 1-3, detection of groups containing two or more single bits IL=2 and less than four bits 1H=4 in three input data blocks G1, G2, G3 is performed. For the specified range limits at the outputs of the first and the second in the groups of OR elements, the binary codes of the boundaries IL=2 and 1H=4 are transformed into the corresponding unitary L and H-bit single rows, starting from the first bit, which are transmitted to the corresponding internal buses of the lower boundary BUL=0000 0011 and the upper boundary BUH=0000 1111.

In cycle 1, the code Ш[8-1]=1101 1011 of the first block G1, containing three two-bit single groups, is set on the external N=8-bit input data bus. On OR elements with an inverse input detection blocks in the first 5L module of detection of the lower boundary, masking of six senior digits is carried out, and in the second 5H module of detection of the upper boundary, masking of four senior digits is carried out. Then, on the elements AND 13 and in the first groups of (N-1)-th AND elements with inverted inputs, respectively, the first 5L and the second 5H edge detection modules, check for the presence of single groups containing ≥L=2 and ≥H=4 single bits, respectively, and single values 5L (8[8-1], 13)=0100 1001, corresponding to the initial bits of the three detected two-digit single groups, and 5H (8[8-1], 13)=00000000, since there are no groups containing four or more single bits, are generated at the outputs. These values without masking through the corresponding second groups elements AND with an inverse input are transmitted to the Q output groups, respectively, of the first 5L and second 5H boundary detection modules, and then to the internal buses of the initial bits of the groups of the lower boundary BL=0100 1001 and the upper boundary BH=0000 0000. Then through the AND elements with an inverse input of the third group the value from the internal bus of the initial digits of the lower boundary groups BL without masking is transmitted to the internal bus BLH=0100 1001 of the initial digits of the groups of the specified range, which is then transmitted to the group of external outputs of the initial digits of the groups of the specified range QULH=0100 1001, since no groups containing four or more one bits have been detected. In this case, in the first block of counting units 11, the three detected two-digit one groups are counted, corresponding to the specified range of boundaries ≥L=2 and <Н=4 in the first block G1 of the input data for ID[8-1]=1101 1011, and the binary code is formed, transmitted to the group of external outputs of the number of one groups of the specified range QLH=3. At the same time, a zero value QH=0 is formed at the output of the second block of counting units 12 - the absence of detected groups greater than the upper boundary QH.

In cycle 2, the ID[8-1]=1101 code is set on the external 8-bit input data bus 1101 of the second G2 block, containing two-bit, three-bit and one-bit unit groups. Further, when masking the six senior bits in the first 5L module and the four senior bits in the second 5H module, at the outputs of AND elements 13 and in the first groups of AND elements with inverted inputs the values 5L (8[8-1], 13)=0100 1100 and 5H (8[8-1], 13)=0000 0000 are set. In this case, the single values set at the outputs of the adjacent third and fourth elements 5L (8[4-3])=11 correspond to one group (row) of three single bits in the input block ID. Therefore, in the second group elements AND with the inverse input of the first 5L lower boundary detection module, the single value from the output of the fourth element 8[4]=1 is masked and the code BL=0100 0100 is set on the internal bus of the initial digits of the lower boundary groups, corresponding to two single groups containing two or more single bits IL=2 (BUL=0000 OOP). Then, through the AND elements with the inverse input of the third the value from the internal bus of the initial digits of the lower boundary groups BL without masking is transmitted to the internal bus BLH=0100 0100 of the initial digits of the groups of the specified range, which is then transmitted to the group of external outputs of the initial digits of the groups of the specified range QULH=0100 0100, since no groups containing four or more one bits have been detected. In this case, at the output of the first block of counting units 11, the code of the number of one groups of the specified range QLH=2 is formed for the second block G2 of input data for ID[8-1]=1101 1101 and simultaneously at the output of the second block of counting units 12, the zero value QH=0 is formed - the absence of detected groups greater than the upper boundary QH.

In cycle 3, the ID[8-1]=1110 1111 code of the third G3 block, containing three-bit and four-bit single groups, is set on the external 8-bit input data bus. For this ID code, at the outputs of AND element 13 and in the first group of AND elements with inverted inputs the first 5L lower boundary detection module sets the values 5L (8[8-1], 13)=0110 0111, corresponding to the initial bits of the detected single groups containing ≥L=2 bits. In this case, the single values set at the outputs of adjacent elements correspond to one group (row) of three and the second group (row) of four single bits in the input block ID. Therefore, they are masked in the second group elements AND with inverse input and on the internal bus of the initial digits of the lower boundary groups, the code BL=0010 0001 is set. At the outputs of element AND 13 and in the first group of AND elements with inverse inputs the second 5H upper boundary detection module sets the values 5H (8[8-1], 13)=0000 0001, corresponding to the first digit of the detected four-digit unit group ≥H=4 bits, which is transmitted without masking to the internal bus of the initial digits of the upper boundary groups BH=0000 0001. Then, on the AND elements with the inverse input of the third group the first digit is masked and the code BLH=0010 0000 is set on the internal bus of the initial digits of the groups of the specified range, corresponding to one group from the specified range ≥L=2 and <Н=4, for which the code of the number of single groups of the specified range QLH=1 is formed at the output of the first unit counting block 11 for the third block G3 of input data for ID[8-1]=1110 1111 and simultaneously the value QH=1 is formed at the output of the second unit counting block 12, corresponding to one group containing one four-digit group ≥Н=4.

In cycles 4-6, detection of groups containing two or more single bits IL=2 and less than five bits Ш=5 in three input data blocks G4, G5, G6 is performed. For the specified range limits at the outputs of the first and the second

in the OR element groups, the binary codes of the boundaries IL=2 and IH=5 are converted into the corresponding unitary L and H-bit single rows, starting from the first bit, which are transmitted to the corresponding internal buses of the lower boundary BUL=0000 0011 and the upper boundary BUH=0001 1111.

In cycle 4, the ID[8-1]=0101 1101 code of the fourth G4 block, containing two one-bit and one three-bit single groups, is set on the external 8-bit input data bus. For this ID code, at the outputs of AND element 13 and in the first group of AND elements with inverted inputs the first 5L lower boundary detection module sets the values 5L (8[8-1], 13)=0000 1100, corresponding to one three-digit unit group. Therefore, the fourth digit is masked and the code BL=0000 0100 is set on the internal bus of the initial digits of the lower boundary groups. At the same time, the code BH=0000 0000 is set on the internal bus of the initial digits of the upper boundary groups. Therefore, through the AND elements with the inverse input of the third group the value from the internal bus of the initial digits of the lower boundary groups BL without masking is transmitted to the internal bus of the initial digits of the groups of the specified range BLH=0000 0100, which is then transmitted to the group of external outputs of the initial digits of the groups of the specified range QULH=0000 0100, and at the output of the first block of counting units 11, the code of the number of single groups of the specified range QLH=1 is formed for the fourth block G4.

In cycle 5, the code ID[8-1]=1111 0111 of the fifth block G5, containing three-bit and four-bit single groups, is set on the external 8-bit input data bus. For this ID code, at the outputs of AND element 13 and in the first group of AND elements with inverted inputs the first 5L lower boundary detection module sets the values 5L (8[8-1], 13)=0111 OOP, corresponding to the four-digit and three-digit single groups, for which single values are set in adjacent digits. Therefore, in the second group elements AND with the inverse input of the first 5L lower boundary detection module masks the single value in the senior digits for the detected groups and the code BL=0001 0001 is set on the internal bus of the initial digits of the lower boundary groups. At the same time, the code BH=0000 0000 is set on the internal bus of the initial digits of the upper boundary groups. Therefore, through the AND elements with the inverse input of the third group the value from the internal bus of the initial digits of the lower boundary groups BL without masking is transmitted to the internal bus of the initial digits of the groups of the specified range BLH=0001 0001, which is then transmitted to the group of external outputs of the initial digits of the groups of the specified range QULH=0001 0001, and at the output of the first block of counting units 11, the code of the number of unit groups of the specified range QLH=2 is formed for the fifth block G5.

In cycle 6, the code ID[8-1]=1111 1011 of the sixth block G6, containing two-bit and five-bit single groups, is set on the external 8-bit input data bus. For this code, the ID outputs of AND elements 13 and the first groups of AND elements with inverted inputs the values 5L (8[8-1], 13)=0111 1001 and 5H (8[8-1], 13)=0000 1000 are set. Then, in the first 5L lower boundary detection module, the single value is masked in the three most significant bits for the detected six-bit group and the code BL=0000 1001 is set on the internal bus of the initial bits of the lower boundary groups. Then, on the AND elements with an inverse input of the third group, the fourth digit is masked and the code BLH=0000 0001 is set on the internal bus of the initial digits of the groups of the specified range, corresponding to one group from the specified range ≥L=2 and <Н=5, for which the code of the number of single groups of the specified range QLH=T is formed at the output of the first unit counting block 11 for the input block G6 of the input data for ID[8-1]=1111 1011 and simultaneously the value QH=1 is formed at the output of the second unit counting block 12, corresponding to one group containing more than the upper limit ≥Н=5.

In cycles 7-8, detection of groups containing four or more single bits IL=4 and less than five bits Ш=5 in two input data blocks G7, G8 is performed. For the specified range limits, codes are set on the internal buses of the lower limit BUL=0000 1111 and the upper limit BUH=0001 1111.

In cycle 7, the ID[8-1]=1111 1011 code of the seventh block G7, containing six-bit and two-bit single groups, is set on the external 8-bit input data bus. For this ID code, the outputs of AND elements 13 and the first groups of AND elements with inverted inputs the values 5L (8[8-1], 13)=0001 1000 and 5H (8[8-1], 13)=0001 0000 are set. Then, in the first 5L lower boundary detection module, the single value in the two most significant digits for the detected six-digit group is masked and the code BL=0000 1000 is set on the internal bus of the initial digits of the lower boundary groups. Then, on the AND elements with the inverse input of the third group, the fourth digit is masked and a zero code BLH=0000 0000 is set on the internal bus of the initial digits of the groups of the given range, corresponding to the absence of groups from the given range ≥L=4 and<Н=5, therefore, at the output of the first unit counting block 11, a zero code of the number of unit groups of the given range QLH=0 is formed for the input block G6 of the input data for ID[8-1]=1111 1011 and, simultaneously, at the output of the second unit counting block 12, the value QH=1 is formed, corresponding to one group containing more than the upper limit ≥Н=5.

In cycle 8, the code ID[8-1]=1011 1100 of the eighth block G8, which contains one-bit and four-bit unit groups, is set on the external 8-bit input data bus. For this ID code, the values 5L (8[8-1], 13)=0000 0100 and 5H (8[8-1], 13)=0000 0000 are set, which are transferred without masking to the internal buses of the lower boundary BL=0000 0100 and the upper boundary BH=0000 0000. Then, the value of the lower boundary BL without masking is transferred to the internal bus BLH=0000 0100 of the initial digits of the groups of the specified range, and the codes of the number of groups QLH=1 and QH=0 are set at the outputs of the units counting blocks. Thus, when setting the value of the lower bound to L bits, and the value of the upper bound to be one more than H=(L+1), single groups with a bit depth equal to the lower bound L are detected.

In cycles 9-10, detection of groups containing one or more single bits IL=1 and less than five bits IH=5 in two input data blocks G9, G10 is performed. For the specified range limits, codes are set on the internal buses of the lower limit BUL=0000 0001 and the upper limit BUH=0001 1111.

In cycle 9, the code ID[8-1]=1001 0111 of the ninth block G9 is set on the external 8-bit input data bus, containing two one-bit and one three-bit unit groups. For this ID code, the values 5L (8[8-1], 13)=1001 0111 and 5H (8[8-1], 13)=0000 0000 are set. Then, in the first 5L lower boundary detection module, the unit value in the two most significant digits for the detected three-digit group is masked and the code BL=1001 0001 is set on the internal bus of the initial digits of the lower boundary groups. Then, the lower boundary value BL without masking is transmitted to the internal bus BLH=1001 0001 of the initial digits of the groups of the specified range, and the codes of the number of groups QLH=3 and QH=0 for the input block G9 are set at the outputs of the units counting blocks.

In cycle 10, the code ID[8-1]=1111 1101 of the tenth block G10, containing a one-bit and six-bit single groups, is set on the external 8-bit input data bus. For this ID code, the values 5L (8[8-1], 13)=1111 1101 and 5H (8[8-1], 13)=0000 0100 are set. Then, in the first 5L lower boundary detection module, the single value in the five most significant bits for the detected six-bit group is masked and the code BL=0000 0101 is set on the internal bus of the initial bits of the lower boundary groups. Then, on the AND elements with an inverted input of the third group, the second digit is masked and the code ВШ=0000 0001 is set on the internal bus of the initial digits of the groups of the specified range, corresponding to one group from the specified range ≥L=T and <Н=5, for which the code of the number of single groups of the specified range QLH=1 is formed at the output of the first unit counting block 11 for the input block G10 of the input data for ID[8-1]=1111 1101 and simultaneously the value QH=1 is formed at the output of the second unit counting block 12, corresponding to one group containing more than the upper limit ≥Н=5.

Thus, for N-bit input data blocks G, the identification of single groups (rows) containing a number of single bits within the specified range boundaries from L to H is carried out (the groups contain ≥L (L or more) and less than H single bits, where 1≤L<H, H≤N). A count of such groups and their arrangement in the input blocks is carried out

The proposed device can be used for hardware implementation of statistical tests developed by the National Institute of Standards and Technology (NIST, USA) Information Technology Laboratory, the purpose of which is to determine the randomness measure of binary sequences generated by random number generators. In particular, the proposed device calculates the number of single groups of a given dimension in N-bit input blocks.

When processing the results of physical experiments, the proposed device ensures the detection of events of a given dimension, determination of their number and placement in input blocks.

The above information allows us to conclude that the proposed device solves the task, has regularity of nodes and connections, and corresponds to the declared technical result - expansion of the arsenal of means for the same purpose in terms of ensuring the possibility of detecting groups of single bits in a given range of bit depth, determining the number of identified groups and their placement in data blocks.

Claims (9)

The device for detecting groups of single bits in data blocks within specified limits comprises an external N-bit input data bus ID of data blocks G, external M-bit input buses for setting the lower IL and upper IH limits, where M=]log ₂ N[ is a greater integer, groups of external outputs of the number of groups of a specified range QLH and greater than the upper limit QH, initial bits of groups of a specified range QULH and the upper limit QUH, first 1 and second 2 decoders, the first 3 ₁ , 3 ₂ , …, 3 _(N-1) and second 4 ₁ , 4 ₂ , … 4 _(N-1) groups of (N-1)-th OR elements, a third group of N AND elements with inverse input 10 ₁ , 10 ₂ , … 10 _N , first 11 and second 12 units counting units, the first lower limit detection module 5L and the second upper limit detection module 5H, each of which contains a group of N detection blocks 6 ₁ , 6 ₂ , …, 6 _N , N groups 7 ₁ , 7 ₂ , …, 7 ₁ of (N+1-I) OR elements with inverted input of the 1st detection blocks 6 ₁ , where 1=1, N, the first group of (N-1)-th AND elements with inverted inputs 8 ₂ , 8 ₃ , …, 8 _N , the second group of (N-1)-th AND elements with inverted input 9 ₂ , 9 ₃ , …, 9 _N and an AND element 13, and also internal buses of the lower BUL and upper BUH boundaries, initial digits of groups of a given range BLH, lower BL and upper HH boundaries were introduced, wherein the bits of the external input buses for setting the lower IL and upper IH boundaries are connected to the address inputs of the first 1 and second 2 decoders, respectively, whose outputs, from the first output to the (N-1)-th output, are connected to the first inputs of the corresponding like-named (N-1)-th OR elements of the first 3 ₁ , 3 ₂ , …, 3 _(N-1) and second 4 ₁ , 4 ₂ , …, 4 _(N-1) groups, respectively, the outputs of which are the corresponding like-named bits, from the first bit to the (N-1)-th bit, of the internal buses of the lower BUL and upper BUH boundaries, respectively, whose N-th bits are connected to the N-th outputs of the first 1 and second 2 decoders, respectively, as well as the outputs of the elements in the first 3 ₁ , 3 ₂ , …, 3 _(N-1) and second 4 ₁ , 4 ₂ , …, 4 _(N-1) groups, starting from the output of the (N-1)-th element to the second element, are connected to the second inputs of the corresponding previous OR elements in the first 3 ₁ , 3 ₂ , …, 3 _(N-1) and second 4 ₁ , 4 ₂ , …, 4 _(N-1) groups, starting from the (N-2)-th element to the first element, and the second inputs of the (N-1)-th elements of the groups are connected to the N-th outputs of the first 1 and second 2 decoders, respectively, wherein the bits of the external input data bus ID are connected to the first groups of inputs I1 of the first lower boundary detection module 5L and the second upper boundary detection module 5H, in which the second groups of inputs 12 are connected to the bits of the internal buses of the lower BUL and upper BUH boundaries, respectively, in addition, in the first lower boundary detection module 5L and the second upper boundary detection module 5H, the bits of the first groups of inputs I1 in groups of (N+1-I) bits, each of which begins with the I-th bit to the N-th bit (1=1, N), are connected in the corresponding I-th detection blocks 6 ₁ of the group 6 ₁ , 6 ₂ , …, 6 _N with the second direct inputs of the OR elements with an inverse input of the groups 7 ₁ , 7 ₂ , …, 7 _I , in which the first inverse inputs are connected to the bits of the second groups of inputs 12 in groups of (N+1-I) bits, each of which begins with the 1-st bit to the (N+1-I)-th bit, while the outputs of the OR elements with an inverse input of the groups 7 ₁ , 7 ₂ , …, 7 _I of the detection blocks 6 ₁ , starting from the second block 6 ₂ to the N-th block 6 _N , are connected to the direct inputs of the same-name AND elements with the inverse inputs of the first group 8 ₂ , 8 ₃ , …, 8 _N , the inverse inputs of which are connected to the digits of the second groups of inputs 12 groups of J digits, each of which starts from the N-th digit to the second digit, where (J=1, (N-1)), and the outputs of the OR elements with the inverse input of the group 7 ₁ , 7 ₂ , …, 7 _N of the first detection block 6 ₁ are connected to the inputs of the AND element 13, wherein the outputs of the AND elements with inverse inputs of the first group 8 ₂ , 8 ₃ , …, 8 _N are connected to the direct inputs of the same-name AND elements with inverse inputs of the second group 9 ₂ , 9 ₃ , …, 9 _N , in which the first inverse inputs (N-2) of the AND elements, starting from the third element 9 ₃ to the N-th element 9 _N , are connected to the direct inputs of the corresponding previous (N-2) AND elements from the second group 9 ₂ , 9 ₃ , …, 9 _N , starting from the second element 9 ₂ to the (N-1)-th element 9 _(N-1) , and the first inverse input of the second element 9 g is connected to the output of the AND element 13, in addition, the outputs of all (N-1) AND elements with an inverse input from the second group 9 ₂ , 9 ₃ , …, 9 _N are the corresponding identical (N-1) digits, starting from the second digit to the N-th digit, of the output groups Q of the corresponding modules for detecting the boundaries of the lower 5L and upper 5H, and the first digit of the outputs Q is connected to the output of the corresponding AND element 13, wherein the bits of the output groups Q of the detection modules of the lower 5L and upper 5H boundaries are the same-name bits of the internal buses of the initial bits of the groups of the lower BL and upper 5H boundaries, respectively, and all N bits of the bus of the lower boundary BL are connected to the direct inputs of the same-name AND elements with the inverse input of the third group 10 ₁ , 10 ₂ , ..., 10 _N , the outputs of which are the bits of the internal bus of the initial bits of the groups of the given range BLH, which is connected to the same-name bits of the external outputs of the initial bits of the groups of the given range QULH and is connected to the inputs of the first unit counting unit 11, the outputs of which are the corresponding bits of the group of external outputs of the number of groups of the given range QLH, wherein all N bits of the internal bus of the initial bits of the groups of the upper HH boundary are connected to the inverse inputs of the same-named AND elements with the inverse input of the third group 10 ₁ , 10 ₂ , …, 10 _N , and are also the same-named bits of the external outputs of the initial bits of the groups of the upper boundary QUH and are connected to the inputs of the second unit counting unit 12, the outputs of which are the corresponding bits of the group of external outputs of the number of groups greater than the upper boundary QH.

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