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KR970008172A - Leakage Current Sensing Circuit in Semiconductor Memory - Google Patents

Leakage Current Sensing Circuit in Semiconductor Memory Download PDF

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Publication number
KR970008172A
KR970008172A KR1019950022331A KR19950022331A KR970008172A KR 970008172 A KR970008172 A KR 970008172A KR 1019950022331 A KR1019950022331 A KR 1019950022331A KR 19950022331 A KR19950022331 A KR 19950022331A KR 970008172 A KR970008172 A KR 970008172A
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KR
South Korea
Prior art keywords
operating voltage
voltage
leakage current
fuse
power
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KR1019950022331A
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Korean (ko)
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KR0154750B1 (en
Inventor
김두응
곽충근
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김광호
삼성전자 주식회사
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Priority to KR1019950022331A priority Critical patent/KR0154750B1/en
Publication of KR970008172A publication Critical patent/KR970008172A/en
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Publication of KR0154750B1 publication Critical patent/KR0154750B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리의 누설전류 감지회로에 관한 것이다.The present invention relates to a leakage current sensing circuit of a semiconductor memory.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

누설전류 감지회로를 제공한다.Provide leakage current sensing circuit.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

다수의 메모리 셀들이 행 및 열라인들에 각기 교차 연결된 매트리스 형태의 구조로 배열되어 있는 셀 어레이를 가지는 반도체 메모리 장치는 상기 메모리 셀들에 동작전압을 각기 행단위로 인가하기 위한 전원라인들과, 대기전류 감지모드에서는 상기 동작전압으로서 테스트 전압을 제공하며 정상동작모드에서는 상기 동작전압으로서 전원전압을 제공하는 패드들 사이에 각기 연결되어 전원라인들에 상기 동작전압을 선택적으로 스위칭하는 수단을 복수개로 내장한 감지회로를 포한한다.A semiconductor memory device having a cell array in which a plurality of memory cells are arranged in a mattress-like structure that is cross-connected to row and column lines, respectively, includes a power line for applying an operating voltage to each of the memory cells in a row unit, and a standby current. In the sensing mode, a test voltage is provided as the operating voltage, and in a normal operating mode, a plurality of means for selectively switching the operating voltage on power lines are connected between pads providing a power supply voltage as the operating voltage. Include the sensing circuit.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리 특히, 스테이틱 램의 누설전류 감지를 위한 소자로서 적합하게 사용된다.It is suitably used as a device for detecting leakage current of a semiconductor memory, especially a static RAM.

Description

반도체 메모리의 누설전류 감지회로Leakage Current Sensing Circuit in Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 메모리 셀의 누설전류 감지회로도.3 is a leakage current sensing circuit diagram of a memory cell according to the present invention.

Claims (8)

메모리 셀들이 워드라인 방향으로 "M"개, 비트라인 방향으로 "N"개(여기서, M,N은 2 이상의 자연수)로 각각 배열되어 있는 셀 어레이를 가지는 스테이틱 램에 있어서; 상기 "M"개의 메모리 셀들에 동작전압을 인가하기 위한 전원라인과, 대기전류 감지모드에서는 상기 동작전압으로서 테스트 전압을 제공하며 정상동작모드에서는 상기 동작전압으로서 전원전압을 제공하는 패드사이에 연결되어 상기 전원라인에 상기 동작전압을 선택적으로 전달하는 전달수단을 가지는 스테이틱 램의 누설전류 감지회로.A static RAM having a cell array in which memory cells are arranged in " M " in the wordline direction and " N " in the bitline direction, where M and N are two or more natural numbers; A power supply line for applying an operating voltage to the "M" memory cells and a pad providing a test voltage as the operating voltage in a standby current sensing mode and a power supply voltage as the operating voltage in a normal operation mode. Leakage current detection circuit of a static RAM having a transmission means for selectively transmitting the operating voltage to the power line. 제1항에 있어서, 상기 전달수단은 피 모오스 트랜지스터 및 퓨즈로 구성되며, 상기 트랜지스터의 드레인단자는 상기 전원라인에 연결되고 소오스 단자는 상기 퓨즈의 일단에 연결되며 게이트 단자는 그라운드에 연결됨을 특징으로 하는 스테이틱 램의 누설전류 감지회로.The method of claim 1, wherein the transmission means comprises a PMOS transistor and a fuse, the drain terminal of the transistor is connected to the power line, the source terminal is connected to one end of the fuse and the gate terminal is connected to ground Leakage current detection circuit of static RAM. 제1항에 있어서, 상기 전달수단은 피 모오스 트랜지스터 및 퓨즈로 구성되며, 상기 트랜지스터의 드레인단자는 상기 전원라인에 연결되고 소오스 단자는 상기 퓨즈의 일단에 연결되며 게이트 단자는 상기 패드와는 다른 패드에 연결됨을 특징으로 하는 스테이틱 램의 누설전류 감지회로.The pad of claim 1, wherein the transfer unit comprises a PMOS transistor and a fuse, a drain terminal of the transistor is connected to the power line, a source terminal is connected to one end of the fuse, and a gate terminal is different from the pad. Leakage current sensing circuit of a static ram, characterized in that connected to. 제1항에 있어서, 상기 테스트 전압은 상기 메모리 셀의 페일 현상을 유발시킬 수 있는 정도의 전압레벨임을 특징으로 하는 스테이틱 램의 누설전류 감지회로.The leakage current detecting circuit of the static RAM of claim 1, wherein the test voltage is at a voltage level sufficient to cause a failure of the memory cell. 제1항에 있어서, 상기 패드는 메모리내의 다른 주변회로에 전압을 공급하지 않도록 하는 구조로 되어 있는것을 특징으로 하는 스테이틱 램의 누설전류 감지회로.The leakage current detecting circuit of the static RAM of claim 1, wherein the pad is configured to not supply voltage to other peripheral circuits in the memory. 다수의 메모리 셀들이 행 및 열라인들에 각기 교차 연결된 매트리스 형태의 구조로 배열되어 있는 셀 어레이를 가지는 반도체 메모리 장치에 있어서; 상기 메모리 셀들에 동작전압을 각기 행단위로 인가하기 위한 전원라인들과, 대기전류 감지모드에서는 상기 동작전압으로서 테스트 전압을 제공하며 정상동작모드에서는 상기 동작전압으로서 전원전압을 제공하는 패드들 사이에 각기 연결되어 상기 전원라인들에 상기 동작전압을 선택적으로 스위칭하는 수단을 복수개로 내장한 반도체 메모리 장치.Claims [1] A semiconductor memory device having a cell array in which a plurality of memory cells are arranged in a mattress-like structure each connected to row and column lines. Between the power lines for applying the operating voltage to each of the memory cells on a row basis, and between the pads providing the test voltage as the operating voltage in the standby current sensing mode and the power supply voltage as the operating voltage in the normal operation mode. And a plurality of means connected to the power lines to selectively switch the operating voltage. 제6항에 있어서, 상기 수단은 피 모오스 트랜지스터 및 퓨즈로 구성되며, 상기 트랜지스터의 드레인 단자는 상기 전원라인에 연결되고 소오스 단자는 상기 퓨즈의 일단에 연결되며 게이트 단자는 그라운드에 연결됨을 특징으로 하는 반도체 메모리 장치.The method of claim 6, wherein the means comprises a PMOS transistor and a fuse, the drain terminal of the transistor is connected to the power line, the source terminal is connected to one end of the fuse and the gate terminal is connected to ground Semiconductor memory device. 메모리 셀들이 워드라인 방향으로 "M"개, 비트라인 방향으로 "N"개(여기서, M, N 은 2 이상의 자연수)로 각각 배열되어 있는 메모리 셀 어레이를 가지는 반도체 메모리의 누설전류 감지방법에 있어서: 상기 "M"개의 메모리 셀들의 셀 파워단에 공통으로 연결된 전원라인과, 상기 전원라인에 동작전압을 제공하는 패드간에 차례로 연결될 모오스 트랜지스터 및 퓨즈소자를 제조시 칩내부에 준비하는 단계와; 대기전류 감지모드에서 상기 동작전압으로서의 테스트 전압을 상기 패드에 인가하고, 이 전압이 상기 모오스 트랜지스터를 통하여 상기 전원라인에 제공되게 하는 단계와; 상기 감지모드동안 상기 셀 파워단에서 그라운드 레벨로 흐르는 직류전류를 측정하는 단계와; 상기 직류전류가 허용값 이상인 경우에 상기 퓨즈를 커팅하여 상기 동작전압으로서의 전원전압이 상기 전원라인에 제공되지 않도록 하는 단계를 가짐을 특징으로 하는 방법.A method of detecting leakage current of a semiconductor memory having a memory cell array in which memory cells are arranged in "M" in a word line direction and "N" in a bit line direction, where M and N are two or more natural numbers. Preparing a MOS transistor and a fuse device to be connected in sequence between a power line commonly connected to cell power stages of the "M" memory cells and a pad providing an operating voltage to the power line; Applying a test voltage as the operating voltage to the pad in a standby current sensing mode, the voltage being provided to the power line through the MOS transistor; Measuring a DC current flowing from the cell power stage to the ground level during the sensing mode; And cutting the fuse so that the power supply voltage as the operating voltage is not provided to the power supply line when the DC current is larger than the allowable value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950022331A 1995-07-26 1995-07-26 Leakage current sensing circuit of semiconductor memory KR0154750B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311946B1 (en) * 1998-07-01 2001-12-28 김서곤 Mat for isolating frequence of water vein
KR100370956B1 (en) * 2000-07-22 2003-02-06 주식회사 하이닉스반도체 Test pattern for measuring leakage current
KR100790570B1 (en) * 2006-06-29 2008-01-02 주식회사 하이닉스반도체 Mat circuit for detecting a leakage current

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100463722B1 (en) * 1997-12-10 2005-04-06 삼성전자주식회사 Static random access memory device
KR102704694B1 (en) 2019-08-13 2024-09-10 삼성전자주식회사 Method of operating storage device for improving reliability and storage device performing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311946B1 (en) * 1998-07-01 2001-12-28 김서곤 Mat for isolating frequence of water vein
KR100370956B1 (en) * 2000-07-22 2003-02-06 주식회사 하이닉스반도체 Test pattern for measuring leakage current
KR100790570B1 (en) * 2006-06-29 2008-01-02 주식회사 하이닉스반도체 Mat circuit for detecting a leakage current

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