KR20230064102A - Method of fabricating semiconductor package - Google Patents

Abstract

Provided is a method for fabricating a semiconductor package capable of improving the reliability of the semiconductor package. The method for fabricating a semiconductor package includes: providing a base substrate which includes a first semiconductor substrate and constitutes a circuit pattern; dicing a plurality of semiconductor layers by using a multi-stage sawing blade including a first sawing blade and a second sawing blade which is different from the first sawing blade; stacking the plurality of diced semiconductor layers on the base substrate in a first direction; and applying pressure and curing the plurality of stacked semiconductor layers along the first direction, wherein each of the plurality of semiconductor layers includes: a semiconductor chip including the semiconductor substrate and a semiconductor element layer; a plurality of solder balls electrically connecting the plurality of semiconductor layers, respectively; and a non-conductive film injected between the plurality of solder balls so as to protect the solder balls from physical impact, and a length of the semiconductor chip in a second direction, which intersects the first direction, may be different from a length of the non-conductive film in the second direction, before applying pressure to the plurality of semiconductor layers.

Description

Semiconductor package manufacturing method {Method of fabricating semiconductor package}

The present invention relates to a method for manufacturing a semiconductor package. Specifically, it relates to a method for manufacturing a semiconductor package capable of controlling the volume of a non-conductive film (NCF) using a two-stage sawing blade.

BACKGROUND ART According to the rapid development of the electronic industry and user demands, electronic devices are becoming more compact, lightweight, and multi-functional. Semiconductor packages used in electrical devices are also required to be miniaturized, lightweight, and multifunctional, and accordingly, a semiconductor package including a plurality of semiconductor chips is required.

However, in the case of a semiconductor package including a plurality of semiconductor chips, there are problems in that defects due to cracks are frequent and product reliability is lowered.

In particular, in a semiconductor package, a crack surrounds a non-conductive film (NCF) for protecting a solder ball injected to electrically connect a plurality of semiconductor chips to each other, the semiconductor chip, and the package. may frequently occur in a portion where molding members come into contact with each other. Such cracks may occur due to variations in Coefficient of Thermal Expansion (CTE) between the non-conductive film, the semiconductor chip, and the molding member.

Therefore, in order to minimize the above cracks and increase the reliability of the semiconductor package, the need to control the volume of the non-conductive film has emerged.

Some technical problems to be solved by the present invention are non-conductive films (NCF) in the TC bonding (Thermal Compression bonding) process by using a two-stage sawing blade in the dicing process of a semiconductor chip. An object of the present invention is to provide a method of manufacturing a semiconductor package capable of improving reliability of the semiconductor package by minimizing cracks caused by a fillet layer formed by a film.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor package manufacturing method according to some embodiments for achieving the above technical problem includes providing a base substrate including a first semiconductor substrate and constituting a circuit pattern, a plurality of semiconductor layers with a first sawing blade, and a first sawing blade. Dicing is performed using a multi-stage sawing blade including a second sawing blade different from the sawing blade, the diced plurality of semiconductor layers are stacked on a base substrate in a first direction, and the stacked plurality of semiconductor layers are stacked in a first direction. Including applying pressure and curing in one direction, wherein each of the plurality of semiconductor layers includes a semiconductor chip including a semiconductor substrate and a semiconductor element layer, a plurality of solder balls electrically connecting each of the plurality of semiconductor layers, and a plurality of A non-conductive film injected between solder balls to protect the solder balls from physical impact, and before applying pressure to the plurality of semiconductor layers, a length in a second direction crossing the first direction of the semiconductor chip is a non-conductive film may be different from the length of in the second direction.

In some embodiments, a length of the non-conductive film in the second direction may be shorter than a length of the semiconductor chip in the second direction.

In some embodiments, the second sawing blade may be disposed one on each side of the first sawing blade.

In some embodiments, the first sawing blade and the second sawing blade may be coupled and rotated by the same axis of rotation.

In some embodiments, the first sawing blade may include dicing the semiconductor chip, and the second sawing blade may include removing a portion of the non-conductive film.

In some embodiments, the length of the radius of the second sawing blade may be shorter than the length of the radius of the first sawing blade.

In some embodiments, a difference between radii of the first sawing blade and the second sawing blade may be equal to or greater than a thickness of the semiconductor chip in the first direction.

In some embodiments, dicing of the semiconductor chip by the first sawing blade and removal of a portion of the non-conductive film by the second sawing blade may be simultaneously performed.

In some embodiments, a difference in length between the semiconductor chip and the non-conductive film in the second direction may be equal to a difference in length between the semiconductor chip and the non-conductive film in a third direction orthogonal to the second direction.

In some embodiments, the method of manufacturing the semiconductor package may further include covering the semiconductor package with a molding member after curing and applying pressure to the plurality of semiconductor layers in a first direction.

Details of other embodiments are included in the detailed description and drawings.

1 is a schematic diagram for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.
2 is a schematic diagram for explaining a semiconductor package manufactured by a semiconductor package manufacturing method according to some embodiments of the inventive concept.
3 is a schematic diagram for explaining a semiconductor package manufactured by a semiconductor package manufacturing method according to some embodiments of the inventive concept.
4 is a schematic diagram for explaining a method of manufacturing a semiconductor package using a two-stage sawing blade according to some embodiments of the inventive concept.
5 is a schematic diagram for explaining a semiconductor package manufacturing method using a two-stage sawing blade according to some embodiments of the inventive concept.
FIG. 6 is a diagram schematically illustrating a structure in which the semiconductor chips diced in FIGS. 4 and 5 and the non-conductive film are disposed, viewed from above.
7 is a flowchart illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms, only the present embodiments make the disclosure of the present invention complete, and the common knowledge in the art to which the present invention belongs It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numbers designate like elements throughout the specification.

When an element or layer is referred to as "on" or "on" another element or layer, it refers not only directly on the other element or layer, but also when another layer or other element is interposed therebetween. all inclusive On the other hand, when an element is referred to as “directly on” or “directly on”, it indicates that another element or layer is not intervened.

The spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between elements or components and other elements or components. Spatially relative terms should be understood as encompassing different orientations of elements in use or operation in addition to the orientations shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above. Elements may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

Although first, second, etc. are used to describe various elements, components and/or sections, it is needless to say that these elements, components and/or sections are not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Accordingly, it goes without saying that the first element, first element, or first section referred to below may also be a second element, second element, or second section within the spirit of the present invention.

Terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. As used herein, "comprises" and/or "comprising" means that a stated component, step, operation, and/or element is present in the presence of one or more other components, steps, operations, and/or elements. or do not rule out additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same or corresponding components regardless of reference numerals are given the same reference numerals, Description will be omitted.

1 is a schematic diagram for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.

Referring to FIG. 1 , a wafer W may include a plurality of memory chips MC. A semiconductor device such as a memory device or a logic device may be formed in each memory chip MC.

The semiconductor device may include various types of individual devices. For example, the individual devices may include MOSFETs such as CMOS transistors, system LSI (lagrge scale integration), image sensors such as CIS (CMOS image sensor), microelectromechanical systems (MEMS), and various other active and passive devices. can

The scribe lane SL may surround each memory chip MC. For example, the scribe lane SL may be in the form of a straight lane having a constant width. The plurality of memory chips MC may be separated from each other by a dicing or die sawing process performed along the scribe lane SL.

Each memory chip MC may be spaced apart from each other by a scribe lane SL. For example, as shown in FIG. 1 , a plurality of chips MC may be spaced apart from each other in a first direction X by a scribe lane SL extending in a second direction Y, and similarly Accordingly, the plurality of chips MC may be spaced apart from each other in the second direction (Y) by the scribe lane (SL) extending in the first direction (X).

2 and 3 are schematic diagrams for explaining a semiconductor package manufactured by a method for manufacturing a semiconductor package according to some embodiments of the inventive concept.

Referring to FIG. 2 , a semiconductor package 1 manufactured by a semiconductor package manufacturing method according to some embodiments includes a base substrate 10, first and second connection pads 21 and 22, and solder balls ( 23), a non-conductive film (NCF) 24, a first semiconductor chip 30, and a molding member 40.

The base substrate 10 may be, for example, a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the base substrate 10 may be a semiconductor chip including a semiconductor device. The base substrate 10 may function as a support substrate for a semiconductor package. For example, a first semiconductor chip 30 to be described later may be stacked on the base substrate 10 .

As shown in FIG. 2 , the base substrate 10 may include a first semiconductor substrate 12 and a first protective layer 11 .

The first semiconductor substrate 12 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the first semiconductor substrate 12 may be a silicon substrate, or other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, It may include gallium arsenide or gallium antimonide, but is not limited thereto.

The first protective layer 11 may cover the upper surface of the first semiconductor substrate 12 . In some embodiments, the first protective layer 11 may cover a backside of the first semiconductor substrate 12 . For example, a semiconductor device may be formed on a frontside of the first semiconductor substrate 12 , and a first protective layer 11 may be formed on a rear surface of the first semiconductor substrate 12 . The first protective layer 11 may be formed by, for example, a spin coating process or a spray process, but is not limited thereto.

In some embodiments, the base substrate 10 may further include a plurality of through vias 13 penetrating the first semiconductor substrate 12 . The through via 13 may have a column shape.

In some embodiments, the through via 13 may pass through the first semiconductor substrate 12 and the first protective layer 11 . For example, the bottom surface of the through via 13 may be exposed from the bottom surface of the first semiconductor substrate 12, and the top surface of the through via 13 may be exposed from the top surface of the first protective layer 11. there is.

In some embodiments, the through via 13 may include a barrier layer formed on a surface of a columnar shape and a conductive filling layer filling the inside of the barrier layer. The barrier layer may include at least one of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB, but is not limited thereto. The buried conductive layer may include at least one of a Cu alloy such as Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, W alloy, Ni, Ru, and Co, but is not limited thereto. no.

In some embodiments, an insulating layer may be interposed between the first semiconductor substrate 12 and the through via 13 . The insulating layer may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof, but is not limited thereto.

The semiconductor chip 30 may be stacked on the base substrate 10 . The semiconductor chip 30 may include a semiconductor device. For example, the semiconductor chip 30 may include a semiconductor substrate 31 and a semiconductor device layer 32 .

The semiconductor substrate 31 may be, for example, bulk silicon or SOI. Alternatively, the first semiconductor substrate 12 may be a silicon substrate, or other materials such as silicon germanium, SGOI, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. It may include, but is not limited thereto.

The semiconductor element layer 32 may be formed on the semiconductor substrate 31 . In some embodiments, the semiconductor element layer 32 may be formed on a surface of the semiconductor substrate 31 facing the first protective layer 11 . For example, the semiconductor element layer 32 may be interposed between the first protective layer 11 and the semiconductor substrate 31 .

The semiconductor device layer 32 may include a plurality of individual devices of various types and an interlayer insulating layer. The individual devices refer to various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale integration (LSI), and the like. ), flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, RRAM, an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active element, a passive element, and the like.

The individual elements of the semiconductor element layer 32 may be electrically connected to a conductive region formed in the first semiconductor substrate 12 . The semiconductor element layer 32 may include a conductive line or a conductive plug electrically connecting at least two of the plurality of individual elements, or a plurality of individual elements and a conductive region of the first semiconductor substrate 12 . . Also, the individual elements may be electrically separated from neighboring individual elements by insulating films.

The plurality of solder balls 23 may be interposed between the base substrate 10 and the semiconductor chip 30 . The plurality of solder balls 23 may electrically connect the base substrate 10 and the semiconductor chip 30 . For example, the plurality of solder balls 23 may be interposed between the first protective layer 11 and the semiconductor device layer 32 and connected to the through via 13 and the semiconductor device layer 32 .

In some embodiments, a plurality of first connection pads 21 may be formed on the first protective layer 11 . The first connection pad 21 may be formed on the top surface of the first protective layer 11 and connected to the top surface of the through via 13 . A plurality of solder balls 23 may be formed on the first connection pad 21 . Accordingly, the plurality of solder balls 23 may be electrically connected to the through vias 13 . In some embodiments, the width of the first connection pad 21 may be greater than that of the through via 13 .

In some embodiments, a plurality of second connection pads 22 may be formed on the semiconductor chip 30 . The second connection pad 22 may be formed on the bottom surface of the semiconductor chip 30 and connected to the plurality of solder balls 23 . Accordingly, the plurality of solder balls 23 may be electrically connected to the semiconductor chip 30 .

The non-conductive film 24 may be interposed between the base substrate 10 and the semiconductor chip 30 . In addition, the non-conductive film 24 may surround the first connection pad 21 , the second connection pad 22 , and the plurality of solder balls 23 . The non-conductive film 24 may be an underfill layer filling a space between the base substrate 10 and the semiconductor chip 30 . The non-conductive film 24 may be configured to protect the plurality of solder balls 23 from external physical impact.

Meanwhile, although the non-conductive film 24 is shown to exist independently in FIG. 2 , this is for convenience of explanation, and the non-conductive film 24 may be included in the first protective layer 11 .

The molding member 40 may be formed on the base substrate 10 . The molding member 40 may cover the non-conductive film 24 and the semiconductor chip 30 . The molding member 40 may include, for example, a polymer such as resin. For example, the molding member 40 may include EMC (Epoxy Molding Compound), but is not limited thereto.

Meanwhile, although one semiconductor chip 30 is illustrated as being stacked in FIG. 2 , the embodiment is not limited thereto and a plurality of semiconductor chips may be stacked on the base substrate 10 . For example, it includes four semiconductor chips on the base substrate 10, a plurality of solder balls for electrically connecting the plurality of semiconductor chips to each other, and a non-conductive film for protecting the plurality of solder balls from physical impact. A semiconductor layer may be further stacked. However, the embodiment is not limited thereto, and it is obvious that the number of semiconductor layers stacked on the base substrate 10 can be modified and implemented.

Subsequently, referring to FIG. 3 , thermal compression bonding (TC bonding) may be performed before the molding member 40 is formed. Specifically, in the TC bonding process, pressure is applied to the semiconductor package 1 along the third direction (Z), and a plurality of solder balls 23 may be jointed by a temperature change. In addition, the non-conductive film 24 is expanded along the first direction (X) by pressure, and as a result, the non-conductive film 24 is a fillet expanded along the first direction (X) compared to the existing shape. ) structure can be formed.

Meanwhile, the fillet structure of the non-conductive film as described above may adversely affect the reliability of the semiconductor package. Specifically, cracks may occur in a specific region due to variation in Coefficient of Thermal Expansion (CTE) of the non-conductive film 24, the semiconductor chip 30, and the molding member 40. Specifically, cracks may occur in areas A and B where the non-conductive film 24, the semiconductor chip 30, and the molding member 40 are in contact with each other. The crack generated as described above may gradually penetrate into the semiconductor package and cause various adverse effects such as shortening the lifespan of the semiconductor package.

Therefore, in the method of manufacturing a semiconductor package according to some embodiments of the present invention, before TC bonding is performed, a part of the non-conductive film is removed using a two-stage sawing blade in a dicing process of a semiconductor chip, so that in the TC bonding process, The volume of the fillet structure of the formed non-conductive film may be reduced, and thus reliability of the semiconductor package may be improved.

4 and 5 are schematic diagrams for explaining a method of manufacturing a semiconductor package using a two-stage sawing blade according to some embodiments of the inventive concept.

Referring to FIGS. 4 and 5 , in order to first stack a plurality of semiconductor layers included in the semiconductor package shown in FIGS. 2 to 3 , each of the plurality of semiconductor layers includes a dicing tape 60, a die It may include a semiconductor chip 30 disposed on an upper surface of the sing tape, and a non-conductive film disposed on an upper surface of the semiconductor chip 30 . Each of the plurality of semiconductor layers may be diced by the sawing blade 50 .

The sawing blade 50 may include a first sawing blade 51, a second sawing blade 52, and a rotation shaft 53.

The first sawing blade 51 may dicing the semiconductor chip 30 . Specifically, the first sawing blade 51 may dicing each of the plurality of memory chips MC on the wafer W along the scribing lane SL shown in FIG. 1 . That is, each memory chip MC shown in FIG. 1 may correspond to the semiconductor chip 30 shown in FIGS. 2 to 6 .

The second sawing blade 52 may be symmetrically arranged one by one on both sides of the first sawing blade 51 based on the first sawing blade 51 . Specifically, the second sawing blade 52 may be coupled and rotated by the same rotation shaft 53 as the first sawing blade 51 .

The second sawing blade 52 may remove a portion of the non-conductive film 24 while the first sawing blade 51 dices the semiconductor chip 30 .

Specifically, the radius of the first sawing blade 51 may have a length of R1, the radius of the second sawing blade 52 may have a length of R2 smaller than the length of R1. Accordingly, while the first sawing blade 51 having a larger radius cuts the semiconductor chip 30 located on the lower surface of the non-conductive film 24, the second sawing blade 52 cuts the non-conductive film 24 ) can be removed.

The rotating shaft 53 may couple the first sawing blade 51 and the second sawing blade 52 . The rotating shaft 53 may rotate the first sawing blade 51 and the second sawing blade 52 . That is, the rotating shaft 53 may include a spindle or a flange.

Meanwhile, the dicing tape 60 may be disposed on the lower surface of the semiconductor chip 30 . As described above, the dicing tape 60 may have a configuration provided to fix parts in the process of removing a part of the non-conductive film 24 and dicing the semiconductor chip 30 and then easily separating the tape 60 .

On the other hand, the second sawing blade 52 should remove only a part of the non-conductive film 24, but the first sawing blade 51 goes over the semiconductor chip 30 and dies disposed on the lower surface of the semiconductor chip 30. Sing tape 60 can be cut. Therefore, the difference between the radius R1 of the first sawing blade 51 and the radius R2 of the second sawing blade 52 is the thickness H of the semiconductor chip 30 in the third direction Z It can be equal to or greater than that.

FIG. 6 is a diagram schematically illustrating a structure in which the semiconductor chips diced in FIGS. 4 and 5 and the non-conductive film are disposed, viewed from above.

Referring to FIG. 6 , since the second sawing blade may remove part of the nonconductive film 24 while the first sawing blade dices the semiconductor chip 30 in FIGS. 4 and 5 , the nonconductive film ( 24) and the semiconductor chip 30 may not completely overlap as shown in FIG.

Specifically, referring to FIG. 1 , the first sawing blade 51 performs dicing along the scribing lane SL extending in the first direction X and the scribing lane SL extending in the second direction Y. At the same time as performing, since the second sawing blade 52 combined with the first sawing blade 51 removes a part of the non-conductive film 24 present on the outer portion of the semiconductor chip 30, the non-conductive film ( 24) and the semiconductor chip 30 may not completely overlap.

In addition, since the first sawing blade 51 equally performs dicing along the scribing lane SL extending in the first direction X and the scribing lane SL extending in the second direction Y, A length difference L1 between the semiconductor chip 30 and the non-conductive film 24 in the first direction X may be equal to a length difference L2 in the second direction Y.

7 is a flowchart illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.

Referring to FIG. 7 , when a dicing process for a semiconductor chip starts, a sawing blade used in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure may be used.

Specifically, the semiconductor chips may be diced by the first sawing blade described above to produce individual semiconductor chips (S110).

In addition, at the same time that the semiconductor chip is created, a portion of the non-conductive film disposed on the semiconductor layer existing on the outer portion of the semiconductor layer may be removed by the second sawing blade coupled to the first sawing blade and the rotational axis to operate. Yes (S120). That is, since the first sawing blade and the second sawing blade exist in a coupled form, the dicing of the semiconductor chip and the process of removing a portion of the non-conductive film may be simultaneously performed.

Thereafter, semiconductor chips are stacked, solder balls are jointed through TC bonding, and the solder balls and the non-conductive film may be cured (S130).

Meanwhile, the non-conductive film may form a fillet structure due to the pressure applied in this process, but the sawing blade used in the semiconductor package manufacturing method according to some embodiments of the present invention, specifically the second sawing blade, is used in the TC bonding process Since a part of the non-conductive film has been cut before, the volume of the fillet structure of the non-conductive film can be reduced.

Thereafter, a molding member for protecting the semiconductor package may be injected (S140).

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

1: Semiconductor package
23: solder ball
24: non-conductive film
30: semiconductor chip
50: sawing blade
51: first sawing blade
52: second sawing blade
53: axis of rotation

Claims (10)

Providing a base substrate constituting the circuit pattern;
Dicing the plurality of semiconductor layers using a multi-stage sawing blade including a first sawing blade and a second sawing blade different from the first sawing blade;
stacking the plurality of diced semiconductor layers on the base substrate in a first direction;
Including applying pressure and curing the plurality of semiconductor layers stacked along the first direction,
Each of the plurality of semiconductor layers,
A semiconductor chip including a semiconductor substrate and a semiconductor element layer;
A plurality of solder balls electrically connecting each of the plurality of semiconductor layers;
A non-conductive film injected between the plurality of solder balls to protect the solder balls from physical impact,
Before applying the pressure to the plurality of semiconductor layers, a length of the semiconductor chip in a second direction crossing the first direction is different from a length of the non-conductive film in the second direction. Method of manufacturing a semiconductor package . According to claim 1,
A method of manufacturing a semiconductor package in which a length of the non-conductive film in the second direction is shorter than a length of the semiconductor chip in the second direction. According to claim 1,
The second sawing blade is a method of manufacturing a semiconductor package is disposed one by one on both sides of the first sawing blade. According to claim 1,
The method of manufacturing a semiconductor package in which the first sawing blade and the second sawing blade are coupled and rotated by the same rotation axis. According to claim 1,
The first sawing blade includes dicing the semiconductor chip,
The second sawing blade method of manufacturing a semiconductor package comprising removing a portion of the non-conductive film. According to claim 1,
The method of manufacturing a semiconductor package in which the length of the radius of the second sawing blade is shorter than the length of the radius of the first sawing blade. According to claim 1,
The difference between the radii of the first sawing blade and the second sawing blade is greater than or equal to the thickness of the semiconductor chip in the first direction. According to claim 1,
The dicing of the semiconductor chip by the first sawing blade and the removal of a portion of the non-conductive film by the second sawing blade are simultaneously performed. According to claim 1,
Manufacturing of a semiconductor package in which a difference in length between the semiconductor chip and the non-conductive film in the second direction is equal to a difference in length between the semiconductor chip and the non-conductive film in a third direction orthogonal to the second direction method. According to claim 1,
The method of manufacturing a semiconductor package further comprising covering the semiconductor package with a molding member after applying pressure and curing the plurality of semiconductor layers along the first direction.

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