KR20230042569A - Semiconductor device - Google Patents

Abstract

The present invention relates to technology capable of improving heat dissipation performance or discharge performance of a protection device (protection circuit) for a surge of long pulse width. A semiconductor device includes a protection device configured by a MOSFET. The protection device has a multi-layer metal wiring structure. The multi-layer metal wiring structure includes a drain connection wire connected to a drain area of the MOSFET and a source connection wire connected to a source area of the MOSFET. For places in which the drain connection wire and the source connection wire co-exist in the same layer of the multi-layer metal wiring structure, any one of the drain connection wires or the source connection wire is formed in a granular layout shape.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present disclosure relates to a semiconductor device, and is a technique effective for application to a semiconductor device equipped with a protection element (protection circuit) against a surge pulse.

A semiconductor device is equipped with a protection element against a surge pulse. As a proposal of this type of semiconductor device, there is, for example, Japanese Unexamined Patent Publication No. 2020-161721.

Japanese Unexamined Patent Publication No. 2020-161721

In a semiconductor device mounted in an on-vehicle electronic control unit (ECU), a test is performed with a surge pulse width longer in time axis than an ESD (Electro-Static Discharge: Electrostatic Discharge/Surge) pulse. Also in consumer semiconductor devices, there is a demand for strengthening long pulse resistance.

An object of the present disclosure is to provide a technique capable of improving the discharge performance or heat dissipation performance of a protection element (protection circuit) against surges with a long pulse width.

Other problems and novel features will become clear from the description of the present specification and accompanying drawings.

A brief outline of representative ones of the present disclosure is as follows.

A semiconductor device according to one embodiment includes a protection element constituted by a MOSFET, and the protection element has a multilayer metal wiring structure. The multi-layer metal wiring structure includes a drain connection wiring connected to the drain region of the MOSFET and a source connection wiring connected to the source region of the MOSFET. In the same layer of the multi-layered metal wiring structure, at a location where the drain connection wiring and the source connection wiring coexist, one of the drain connection wiring and the source connection wiring has a granular layout shape.

According to the semiconductor device according to the above embodiment, it is possible to improve the discharge performance or heat dissipation performance of the protective circuit against long pulse width surges.

1 is a plan view illustrating the layout of a protection circuit according to a comparative example.
FIG. 2 is a cross-sectional view of the protection circuit taken along line A-A' in FIG. 1 .
3 is a plan view explaining the layout of the protection circuit according to the first embodiment.
FIG. 4 is a cross-sectional view of the protection circuit taken along the line A-A' of FIG. 3 .
FIG. 5 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 3 .
6 is a plan view explaining the layout of the protection circuit according to the second embodiment.
FIG. 7 is a cross-sectional view of the protection circuit taken along line A-A' of FIG. 6 .
FIG. 8 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 6 .
Fig. 9 is a plan view illustrating an arrangement example of the second wiring layer M2 in the layout of the protection circuit according to the third embodiment.
Fig. 10 is a plan view illustrating an arrangement example of the third wiring layer M3 in the layout of the protection circuit according to the third embodiment.
FIG. 11 is a cross-sectional view of the protection circuit taken along line A-A' of FIG. 9 .
FIG. 12 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 10 .
13 is a graph showing the results of measuring breakdown power in protection devices having different silicon areas when the surge pulse width is within the range of a surge test of a consumer semiconductor device.
14 is a graph showing the results of measuring breakdown power in protection elements having different silicon areas when the surge pulse width is within the range of a surge test of a vehicle-mounted semiconductor device.

Hereinafter, comparative examples, embodiments, and examples will be described using drawings. However, in the following description, the same reference numerals are given to the same constituent elements, and repetitive explanations are omitted in some cases. In addition, in order to make description clearer, although there may be cases where drawings are schematically displayed compared to actual embodiments, they are examples only and do not limit the interpretation of the present invention.

Before describing the embodiments, first, a configuration example of a layout of a protection circuit according to a comparative example will be described using FIGS. 1 and 2 . 1 is a plan view illustrating the layout of a protection circuit according to a comparative example. FIG. 2 is a cross-sectional view of the protection circuit taken along line A-A' in FIG. 1 . 1 shows a wiring M21 composed of the second wiring layer M2 and a wiring M31 composed of the third wiring layer M3 in the wiring layout of the protection circuit.

1 and 2, the MOS protection element 3r constituting the protection circuit 2r has a gate electrode G, a source region S, and a drain region D. The source region S and the drain region D are formed on a semiconductor substrate (SiSub) 1r made of silicon, and the gate electrode G is formed on the upper side of a gate oxide film (not shown) formed on the surface of the semiconductor substrate 1r.

The source region S is composed of the first via electrode V1, the first wiring M11 composed of the first wiring layer M1, the second via electrode V2, the second wiring M21 composed of the second wiring layer M2, the third via electrode V3, and the third wiring layer M3. It is electrically connected to the fourth wiring M41 composed of the fourth wiring layer M4 via the constructed third wiring M31 and the fourth via electrode V4. The fourth wiring M41 can be referred to as a bus wiring.

The drain region D is electrically connected to the third wiring M31 through the first via electrode V1, the first wiring M11, the second via electrode V2, the second wiring M21, and the third via electrode V3. The second wiring M21 and the third wiring M31 to which the drain region D is connected are connected to the pad electrode PAD. The first via electrode V1 can also be referred to as a contact electrode.

The first to fourth wirings M11 to M41 and the first to fourth via electrodes V1 to V4 are made of a metal such as copper (Cu) or aluminum (Al). The first to fourth wirings M11 to M41 and the first to fourth via electrodes V1 to V4 are covered with an insulating film (eg, silicon oxide film SiO ₂ ) 4r having a relatively low thermal conductivity.

As shown in Fig. 1, when a surge pulse is applied to the pad electrode PAD, a surge current Is indicated by a dotted line arrow flows. When the MOS protection element 3r is an N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the fourth wiring M41 is the ground potential (first reference potential) GND. On the other hand, when the MOS protection element 3r is a P-type MOSFET, the fourth wiring M41 is the power source potential (second reference potential) VDD (VDD>GND).

13 and 14 are graphs showing the results of measuring breakdown power in protection elements (N-type MOSFETs) having different silicon areas. Fig. 13 shows measurement results when the surge pulse width is within the surge test range of a consumer semiconductor device, and Fig. 14 shows measurement results when the surge pulse width is within the surge test range of a vehicle-mounted semiconductor device. 13 and 14, the vertical axis represents the breakdown power Pf (W) per unit Si area, and the horizontal axis represents the surge pulse pulse width (sec). Regarding the Si area, 5V-NA is small (×1), 5V-NB is medium (×2), and 5V-NC is large (×3). The number of metal wires on the drain (D) side is 28 for 5V-NA, 44 for 5V-NB, and 56 for 5V-NC. Here, in the surge test of the vehicle-mounted semiconductor device (also referred to as ECU surge test), test voltage: -150V, pulse width: 2ms, energy: 250mJ, or test voltage: +112V, pulse width: 50μs, energy: 20mJ There are tests such as In the surge test of consumer semiconductor devices, there are tests such as test voltage: +/-2 kV, pulse width: 150 ns, energy: 800 nJ.

As shown in FIG. 13, in the time domain TESD of surge pulses in ESD (Electro-Static Discharge: Electrostatic Discharge/Surge) tests of consumer semiconductor devices, the protection performance per unit Si area is 5V-NA, 5V For -NB, and 5V-NC, they are almost the same.

On the other hand, as shown in FIG. 14, in the time domain TECU of the surge pulse in the ECU surge test, when the pulse width of the surge pulse became 20 μs or more, a difference in protection performance due to the number of metal wires on the drain side appeared. . That is, when the pulse width is 20 μs or more, as the number of metal wires on the drain (D) side increases, the performance with respect to breakdown power Pf decreases, and the value of breakdown power Pf is 5V-NA > 5V-NB > 5V- It was understood that it was related to NC.

In summary, it can be said as follows. (1) With miniaturization of semiconductor devices formed in semiconductor devices and multilayering of metal wiring, performance degradation of protection elements due to heat generation effect of metal wiring becomes significant against surges with long pulse widths. (2) In the narrow-pitch metal wiring region, since the metal wiring layers M11 to M41 and V1 to V4 are covered with an interlayer insulating film 4r having low thermal conductivity, such as a silicon oxide film SiO ₂ , heat is accumulated between adjacent wirings. It is the main cause of the performance degradation of a protection element. In addition, the thermal conductivity of copper (Cu) is 403 (W/m·K), and the thermal conductivity of aluminum (Al) is 236 (W/m·K). On the other hand, the thermal conductivity of silicon (Si) is 160 (W/m·K), and the thermal conductivity of silicon oxide film SiO ₂ is 1.3 (W/m·K). (3) Increasing the wiring pitch (inter-wiring space) can reduce the effect of heat storage between the metal wirings (M11 to M41, etc.), but the Si area of the protection element increases, which increases the chip cost of the semiconductor device. there is

(Embodiment)

In order to solve the problems described above, the protection element 3 according to the embodiment of the present disclosure has the following configuration.

The protection element 3 formed on one surface of the semiconductor substrate SiSub is to improve surge resistance against a long surge pulse width (eg, several tens of μs or more) (here, the protection element 3) In the shape of the metal wirings M1d to M4d and M1s to M3s connected to the protection element 3, the multi-layer connection between the pad electrode PAD and the drain region D of the protection element 3 is described. A first connection wire (for example, also referred to as a drain connection wire) of the multi-layered first connection wire connected between the source region S of the protection element 3 and the bus wire M41 to which the ground potential GND or power supply potential VDD is supplied. In the copper layer in which two connection wires (for example, also referred to as source connection wires) are adjacent, of the connection wire to the pad electrode PAD (first connection wire) or the connection wire to the bus wire M41 (second connection wire) One or the other has a granular layout arrangement.

According to the layout arrangement described above, the density of the metal wiring can be reduced without increasing the Si area of the protection element 3 . Since the density of the metal wiring can be reduced, adverse effects due to heat storage in the interlayer insulating film accompanying heat generation in the metal wiring region can be avoided. Thereby, the discharge performance or heat dissipation performance of the protection element 3 against the surge of a long pulse width can be improved. For example, in a surge test with a pulse width of 50 μs, it becomes possible to improve the surge resistance per unit Si area by 1.5 to 2.0 times compared to the comparative example (see FIGS. 1 and 2).

When the protection element 3 is the protection element 3 constituted by a diode and a thyristor (SCR: Silicon Controlled Rectifier: Silicon Controlled Rectifier), the drain connection wiring and the source connection wiring are the anode connection wiring and the cathode connection. It can be said in terms of wiring. The anode connection wiring is connected to the anode regions of the diode and the thyristor, and the cathode connection wiring is connected to the cathode regions of the diode and the thyristor.

Hereinafter, each embodiment is described using drawings.

[Example 1]

Next, an example of the layout of the protection circuit 2 according to the first embodiment will be described with reference to FIGS. 3 to 5 . 3 is a plan view explaining the layout of the protection circuit according to the first embodiment. FIG. 4 is a cross-sectional view of the protection circuit taken along the line A-A' of FIG. 3 . FIG. 5 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 3 . 3 shows wirings M2s, M2d, and M2p constituted by the second wiring layer M2 in the wiring layout of the protection circuit.

In Example 1, in the metal wiring structure of the protection element 3 composed of MOSFETs, only the second source wiring M2s composed of the second wiring layer M2 is used as a granular phase. The second source wiring M2s is in a granular layout arrangement. In other words, the second source wiring M2s is laid out in a dot shape (dot shape) and is interspersed.

3, 4, and 5, the MOS protection element 3 constituting the protection circuit 2 has a gate electrode G, a source region S, and a drain region D. The source region S and the drain region D are formed on a semiconductor substrate (SiSub) 1 made of silicon, and the gate electrode G is on the upper side of a gate oxide film (not shown) formed on one main surface of the semiconductor substrate 1 (surface). is formed in

The drain region D includes the first drain via electrode V1d, the first drain wiring M1d composed of the first wiring layer M1, the second drain via electrode V2d, the second drain wiring M2d composed of the second wiring layer M2, and the third drain via electrode V3d. Through this, it is electrically connected to the third drain wiring M3d composed of the third wiring layer M3. The second drain wiring M2d and the third drain wiring M3d to which the drain region D is connected are connected to the pad electrode PAD. The pad electrode PAD is constituted by the second pad wiring M2p formed from the second wiring layer M2. The first drain via electrode V1 can also be referred to as a contact electrode. A multilayer first connection wiring (also referred to as a drain connection wiring) connected between the pad electrode PAD and the drain region D of the protection element 3 includes a first drain via electrode V1d, a first drain wiring M1d, and a second drain via electrode V2d, the second drain wire M2d, the third drain via electrode V3d, and the third drain wire M3d.

The source region S includes a first source via electrode V1s, a first source wiring M1s composed of the first wiring layer M1, a second source via electrode V2s, a second source wiring M2s composed of the second wiring layer M2, a third source via electrode V3s, It is electrically connected to the fourth wiring M41 composed of the fourth wiring layer M4 through the third source wiring M3s composed of the third wiring layer M3 and the fourth source via electrode V4s. The fourth wiring M41 can be referred to as a bus wiring. A multi-layered second connection wiring (also referred to as a source connection wiring) connected between the source region S of the protection element 3 and the bus wiring M41 to which the ground potential GND or power supply potential VDD is supplied is a first source via electrode V1s , the first source wiring M1s, the second source via electrode V2s, the second source wiring M2s, the third source via electrode V3s, the third source wiring M3s, and the fourth source via electrode V4s.

The first to fourth wirings M1s, M1d to M3s, M3d, and M41 and the first to fourth via electrodes V1s, V1d to V4s are made of a metal such as copper (Cu) or aluminum (Al). and covered by an insulating film 4 having a relatively low thermal conductivity composed of a silicon oxide film SiO ₂ or the like. The insulating film 4 is composed of a first insulating film 41 , a second insulating film 42 , a third insulating film 43 , a fourth insulating film 44 , and a fifth insulating film 45 .

The first insulating film 41 covers the source region S and the drain region D formed on the main surface of the semiconductor substrate 1 and the gate electrode G on the gate oxide film formed on the main surface of the semiconductor substrate 1. ) is formed on the principal surface of

The first via electrodes V1s and V1d are buried in through holes (also referred to as contact holes) provided in the first insulating film 41 and are electrically connected to the source region S and the drain region D. The first wirings M1s and M1d are formed on the first insulating film 41 so as to be electrically connected to the first via electrodes V1s and V1d. The second insulating film 42 is formed on the first insulating film 41 so as to cover the first wirings M1s and M1d.

The second via electrodes V2s and V2d are buried in through holes formed in the second insulating film 42 and are electrically connected to the first wirings M1s and M1d. The second wirings M2s and M2d are formed on the second insulating film 42 so as to be electrically connected to the second via electrodes V2s and V2d. The third insulating film 43 is formed on the second insulating film 42 so as to cover the second wirings M2s and M2d.

The third via electrodes V3s and V3d are buried in the through holes formed in the third insulating film 43 and are electrically connected to the second wirings M2s and M2d. The third wirings M3s and M3d are formed on the third insulating film 43 so as to be electrically connected to the third via electrodes V3s and V3d. The fourth insulating film 44 is formed on the third insulating film 43 so as to cover the third wirings M3s and M3d.

The fourth via electrode V4s is buried in the through hole formed in the fourth insulating film 44 and is electrically connected to the third wire M3s. The fourth wiring M41 is formed on the fourth insulating film 44 so as to be electrically connected to the fourth via electrode V4s. The fifth insulating film 45 is formed on the fourth insulating film 44 so as to cover the fourth wiring M41.

Here, as shown in Fig. 3, in the metal wiring of the protection element 3, only the second source wiring M2s constituted by the second wiring layer M2 is used as a granular phase. That is, the second source wiring M2s is arranged in a granular layout. Alternatively, the second source wiring M2s is laid out in a dot shape (dot shape) and is interspersed.

As a result, since only the second source wiring M2s constituted by the second wiring layer M2 is granular without increasing the Si area of the protection element 3, the density of the metal wiring of the protection element 3 can be reduced. . Since the density of the metal wiring can be reduced, adverse effects due to heat storage in the interlayer insulating film accompanying heat generation in the metal wiring region can be avoided. Thereby, the discharge performance or heat dissipation performance of the protection element 3 against the surge of a long pulse width can be improved.

[Example 2]

Next, an example of the layout of the protection circuit 2 according to the second embodiment will be described with reference to FIGS. 6 to 8 . 6 is a plan view explaining the layout of the protection circuit according to the second embodiment. FIG. 7 is a cross-sectional view of the protection circuit taken along line A-A' of FIG. 6 . FIG. 8 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 6 . 6 shows wirings M2s, M2d, and M2p constituted by the second wiring layer M2 in the wiring layout of the protection circuit. For simplicity of drawing, illustration of the insulating films 41, 42, 43, 44, and 45 is omitted.

In Embodiment 2, as shown in Fig. 6, in the metal wiring of the protection element 3 composed of MOSFETs, only the second drain wiring M2d composed of the second wiring layer M2 is used as a granular phase (second wiring layer M2). The drain wiring M2d is in a granular layout arrangement). Alternatively, the second drain wiring M2d is laid out in a dot shape (dot shape) and is interspersed. Other configurations of the second embodiment are the same as those of the first embodiment, and therefore, overlapping descriptions are omitted.

In this way, since only the second drain wiring M2d constituted by the second wiring layer M2 is made granular without increasing the Si area of the protection element 3, the density of the metal wiring of the protection element 3 can be reduced. . Since the density of the metal wiring can be reduced, adverse effects due to heat storage in the interlayer insulating film accompanying heat generation in the metal wiring region can be avoided. Thereby, the discharge performance or heat dissipation performance of the protection element 3 against the surge of a long pulse width can be improved.

[Example 3]

Embodiment 1 is a configuration example in which only the second source wiring M2s constituted by the second wiring layer M2 is arranged in a granular form, and Embodiment 2 is a configuration example in which only the second drain wiring M2d constituted by the second wiring layer M2 is arranged in a granular form. am. Embodiment 3 is a configuration example in which the second drain wiring M2d constituted by the second wiring layer M2 is arranged in a granular form, and further, the third source wiring M3s constituted by the third wiring layer M3 is arranged in a granular form.

An example of the layout of the protection circuit 2 according to the third embodiment will be described with reference to FIGS. 9 to 12 . Fig. 9 is a plan view illustrating an arrangement example of the second wiring layer M2 in the layout of the protection circuit according to the third embodiment. Fig. 10 is a plan view illustrating an arrangement example of the third wiring layer M3 in the layout of the protection circuit according to the third embodiment. FIG. 11 is a cross-sectional view of the protection circuit taken along the line A-A' of FIG. 9 . FIG. 12 is a cross-sectional view of the protection circuit taken along line BB′ of FIG. 10 . 9 shows wirings M2s, M2d, and M2p constituted by the second wiring layer M2 in the wiring layout of the protection circuit 2. As shown in FIG. 10 shows wirings M2s, M3d, and M3p constituted by the third wiring layer M3 in the wiring layout of the protection circuit 2. For simplicity of drawing, illustration of the insulating films 41, 42, 43, 44, 45, etc. is omitted.

Embodiment 3 differs from Embodiments 1 and 2 in that a fifth wiring layer M5 is added as a wiring layer, and a bus wiring to which ground potential GND to which source region S of protection element 3 is connected or power source potential VDD is supplied is supplied. The point is that it is a bus wiring M51 constituted by this fifth wiring layer M5. For this reason, as shown in Figs. 11 and 12, a source wiring M4s, a fifth via electrode V5s, a fourth via electrode V4d, and a drain wiring M4d are added.

A multilayer first connection wiring (also referred to as a drain connection wiring) connected between the pad electrode PAD and the drain region D of the protection element 3 includes a first drain via electrode V1d, a first drain wiring M1d, and a second drain via electrode V2d, second drain wiring M2d, third drain via electrode V3d, third drain wiring M3d, fourth drain via electrode V4d, and fourth drain wiring M4d.

A multi-layered second connection wiring (also referred to as a source connection wiring) connected between the source region S of the protection element 3 and the bus wiring M51 to which the ground potential GND or power source potential VDD is supplied is a first source via electrode V1s , the first source wire M1s, the second source via electrode V2s, the second source wire M2s, the third source via electrode V3s, the third source wire M3s, and the fourth source via electrode V4s, the fourth source wire M4s, the fifth It becomes the source via electrode V5s. Other configurations of Example 3 are the same as those of Embodiments 1 and 2, and therefore, overlapping descriptions are omitted.

In Example 3, as shown in Fig. 9, in the metal wiring of the protection element 3 constituted by MOSFET, the drain wiring M2d constituted by the second wiring layer M2 is disposed in a granular form, or, as shown in Fig. 10 As shown in , in the metal wiring of the protection element 3 composed of MOSFETs, the source wiring M3s composed of the third wiring layer M3 is arranged in a granular form. In addition, the drain connection wiring M2d in a granular layout and the source connection wiring M3s in a granular layout are alternately arranged diagonally on a plan view.

In this way, without increasing the Si area of the protection element 3, the drain wiring M2d constituted by the second wiring layer M2 is made granular and the source wiring M3s constituted by the third wiring layer M3 is made granular. The density of the metal wiring of element 3 can be reduced. Since the density of the metal wiring can be reduced, adverse effects due to heat storage in the interlayer insulating film accompanying heat generation in the metal wiring region can be avoided. Thereby, the discharge performance or heat dissipation performance of the protection element 3 against the surge of a long pulse width can be improved.

Also, for surges with short pulse widths (several microseconds or less), it is important to reduce the impedance of the entire discharge path. There is no deterioration of protective performance.

(modified example)

When the protection element 3 is a protection element composed of a diode and a thyristor (SCR: Silicon Controlled Rectifier: Silicon Controlled Rectifier), drain connection wiring and source connection wiring are replaced with anode connection wiring and cathode connection wiring. I can tell you.

The configuration of the protection element 3 of the present disclosure can be summarized as follows.

(1) The protection element 3 constituted by MOSFETs of a semiconductor device (or semiconductor integrated circuit) has a multi-layer metal wiring structure, and the same layer (for example, the second wiring layer M2 or the second wiring layer M2 or 3 In the location where the drain connection wires M2d and M3d and the source connection wires M2s and M3s coexist in the wiring layer M3, either the drain connection wires M2d or M3d or the source connection wires M2s or M3s One side has a granular layout shape.

(2) In the above (1), both the drain connection wire M2d and the source connection wire M3s are in a granular layout, and the drain connection wire M2d in the granular layout and the source connection wire in the granular layout (M3s) has a different layer (layer) in the multi-layer metal wiring structure (refer to Embodiment 3, Figs. 9 and 10).

(3) In the above (2), the drain connection wiring M2d in the granular layout and the source connection wiring M3s in the granular layout are alternately arranged diagonally in a plan view (see Figs. 9 and 10). .

(4) The protection element 3 constituted by diodes of a semiconductor device (or semiconductor integrated circuit) has a multi-layered metal wiring structure, and the same layer (for example, the second wiring layer M2 or the second wiring layer M2 or 3 In the location where the anode connection wires M2d and M3d and the cathode connection wires M2s and M3s coexist in the wiring layer M3, either the anode connection wires M2d or M3d or the cathode connection wires M2s or M3s One side has a granular layout shape.

(5) The protection element 3 constituted by the thyristors of the semiconductor device (or semiconductor integrated circuit) has a multi-layered metal wiring structure, and the copper layer (for example, the second wiring layer M2 or the second wiring layer M2 or 3 In the location where the anode connection wires M2d and M3d and the cathode connection wires M2s and M3s coexist in the wiring layer M3, either the anode connection wires M2d or M3d or the cathode connection wires M2s or M3s One side has a granular layout shape.

In the above, the invention made by the present inventors has been specifically described based on examples, but the present invention is not limited to the above embodiments and examples, and various changes are possible, of course.

1: semiconductor substrate
2: protection circuit
3: protection element
4: insulating film
M1 to M5: first to fifth wiring layers
M41, M51: Bus wiring
M1d, M2d, M3d, M4d: Drain wiring
V1d to V5d: drain via electrode
M1s, M2s, M3s, M4s: Source wiring
V1s to V5s: source via electrodes

Claims (5)

A protection element constituted by a MOSFET, the protection element having a multi-layer metal wiring structure, the multi-layer metal wiring structure comprising: a drain connection wire connected to a drain region of the MOSFET and a source region of the MOSFET source connection wiring, wherein either the drain connection wiring or the source connection wiring is located at a location where the drain connection wiring and the source connection wiring coexist in the same layer of the multilayer metal wiring structure. A semiconductor device in this granular layout shape. According to claim 1,
Both the drain connection wiring and the source connection wiring are in a granular layout shape, and the drain connection wiring in the granular layout shape and the source connection wiring in the granular layout shape have the multilayer metal wiring structure The semiconductor device according to , wherein the layers are different. According to claim 2,
The semiconductor device according to claim 1 , wherein the drain connection wiring in the granular layout shape and the source connection wiring in the granular layout shape are alternately arranged diagonally in a plan view. A protection element constituted by a diode, the protection element having a multi-layered metal wiring structure, the multi-layered metal wiring structure having an anode connection wiring connected to an anode region of the diode and a cathode connection to a cathode region of the diode and, in a co-layer of the multilayer metal wiring structure, at a location where the anode connection wiring and the cathode connection wiring coexist, either one of the anode connection wiring or the cathode connection wiring is used. A semiconductor device in this granular layout shape. A protection element constituted by a thyristor, the protection element having a multi-layer metal wiring structure, the multi-layer metal wiring structure having an anode connection wire connected to an anode region of the thyristor and a cathode region of the thyristor and, in a co-layer of the multilayer metal wiring structure, at a location where the anode connection wiring and the cathode connection wiring coexist, either one of the anode connection wiring or the cathode connection wiring is used. A semiconductor device in this granular layout shape.

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