KR20200112027A - Capacitive Micromachined Ultrasonic Transducer and method of fabricating the same - Google Patents

Abstract

The present invention relates to a capacitive micromachining ultrasonic transducer and a manufacturing method thereof. An object of the present invention is to provide the capacitive micromachining ultrasonic transducer (CMUT) capable of controlling parasitic capacitance while simplifying an insulation process to increase economic efficiency and the manufacturing method thereof. The manufacturing method of the capacitive micromachining ultrasonic transducer (CMUT) according to one aspect of the present invention may comprise the following steps of: forming a first region, in which impurity ions are implanted into a semiconductor substrate at a first average concentration, and a second region in which the impurity ions are not implanted or the impurity ions are implanted at a second average concentration lower than the first average concentration; oxidizing the semiconductor substrate to form an insulating layer including a first oxide layer, having a first thickness, in at least a portion of the first region and a second oxide layer, having a second thickness smaller than the first thickness, in at least a portion of the second region; and forming a membrane layer on the insulating layer and forming the membrane layer to define a gap between the second oxide layer and the membrane layer.

Description

Capacitive Micromachined Ultrasonic Transducer and method of fabricating the same}

The present invention relates to an ultrasonic device, and in particular, to a capacitive micromachined ultrasonic transducer (CMUT) and a method of manufacturing the same.

An ultrasonic transducer (or ultrasonic transducer) refers to a device that converts an electrical signal into an ultrasonic signal or converts an ultrasonic signal into an electrical signal. In the past, piezoelectric micromachined ultrasonic transducers (PMUTs) that process ultrasonic signals using piezoelectric materials have been widely used, but recently, the operating frequency range can be widened, the bandwidth of the transducer can be widened, and semiconductor processing can be improved. Research is being conducted on a Capacitive Micromachined Ultrasonic Transducer (CMUT) that can be integrated.

However, in the case of the conventional capacitive microfabricated ultrasonic transducer (CMUT), there were difficulties in the process, such as using at least two oxidation processes to form an insulating layer to insulate the upper electrode and the lower electrode while supporting the membrane. Due to this, there is a problem in that it is difficult to control the thickness of the entire wafer.

1. Unexamined Patent Publication 10-2017-0029497 (2017. 03. 15) 2. Unexamined Patent Publication 10-2018-0030777 (2018. 03. 26)

The present invention is to solve various problems, including the above problems, and provides a capacitive microfabricated ultrasonic transducer (CMUT) capable of controlling parasitic capacitance while simplifying the insulation process to increase economic efficiency and a manufacturing method thereof. It aims to do. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A method of manufacturing a capacitive microfabricated ultrasonic transducer (CMUT) according to an aspect of the present invention includes a first region in which impurity ions are implanted in a semiconductor substrate at a first average concentration, and the impurity ions are not implanted or the first region. Forming a second region into which the impurity ions are implanted at a second average concentration lower than the first average concentration, and oxidizing the semiconductor substrate to form a first oxide layer having a first thickness in at least a portion of the first region, and the Forming an insulating layer including a second oxide layer having a second thickness smaller than the first thickness in at least a portion of the second region, and forming a membrane layer on the insulating layer, wherein the second oxide layer and the membrane It may include forming the membrane layer to define a gap between the layers.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), the membrane layer may be supported by the first oxide layer.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), the forming of the first region and the second region includes exposing the first region on a semiconductor substrate and covering the second region. The method may include forming a first mask layer, and implanting the impurity ions at the first average concentration in the first region by using the first mask layer as an ion implantation protective layer.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), the semiconductor substrate may be doped with a first conductivity type, and the impurity ions may have a second conductivity type opposite to the first conductivity type. .

The method of manufacturing the capacitive microfabricated ultrasonic transducer (CMUT) further includes forming a third region in the semiconductor substrate into which the impurity ions are implanted at a third average concentration higher than the first average concentration. can do. Further, in the step of forming the insulating layer, the insulating layer is formed to further include a third oxide layer having a third thickness greater than the first thickness in at least a part of the third region, and in the step of forming the membrane layer , The gap may be further defined between the first oxide layer and the membrane layer, and the membrane layer may be supported by the third oxide layer.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), the forming of the first region, the second region, and the third region on the semiconductor substrate may include the first region and the third region. Exposing a region and forming a second mask layer covering the second region, and using the second mask layer as an ion implantation protective layer, the first region and the third region at the first average concentration Implanting the impurity ions, exposing the third region, forming a third mask layer covering the first region and the second region, and using the third mask layer as an ion implantation protective layer And implanting the impurity ions into the third region so that the ion implantation concentration in the third region becomes the third average concentration.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), in the semiconductor substrate, a structure in which the first region and the second region are sequentially disposed on both sides of the third region is repeated, In the insulating layer, a structure in which the first oxide layer and the second oxide layer are sequentially disposed on both sides of the third oxide layer may be repeated.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), in the semiconductor substrate, a structure in which the second region and the first region are respectively disposed on both sides of the third region is repeated, and the insulation In the layer, a structure in which the second oxide layer and the first oxide layer are disposed on both sides of the third oxide layer may be repeated.

According to the method of manufacturing the capacitive microfabricated ultrasonic transducer (CMUT), in the step of forming the second region, the second region is formed such that the concentration of the impurity ions gradually increases as the impurity ions go from the center to both ends. In the step of forming the insulating layer, the second oxide layer may be formed such that the thickness of the second oxide layer gradually increases from the center of the second region toward both ends.

According to the manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT), the forming of the second region may include exposing the first region and covering the second region, in the middle of the second region It may include forming a fourth mask layer that gradually decreases in thickness toward both ends, and implanting the impurity ions into the semiconductor substrate by using the fourth mask layer as an ion implantation protective layer.

According to the method of manufacturing the capacitive microfabricated ultrasonic transducer (CMUT), the forming of the membrane layer includes bonding a handle substrate including the membrane layer on the insulating layer of the semiconductor substrate, It may include the step of leaving the membrane layer on the insulating layer and separating the handle substrate.

The manufacturing method of the capacitive microfabricated ultrasonic transducer (CMUT) includes forming an upper wiring on the membrane layer, and forming a lower wiring connected to the semiconductor substrate through the membrane layer and the insulating layer. It may contain more.

In the capacitive microfabrication ultrasonic transducer according to another aspect of the present invention, a first region in which impurity ions are implanted at a first concentration and the impurity ions are not implanted or at a second concentration lower than the first concentration. A semiconductor substrate including a second region implanted with ions, a first oxide layer formed by oxidizing the semiconductor substrate and having a first thickness in at least a portion of the first region, and the second region in at least a portion of the second region. An insulating layer including a second oxide layer having a second thickness less than 1 thickness, and a membrane layer formed on the insulating layer, wherein the membrane layer is formed to define a gap between the second oxide layer and the membrane layer. do.

In the capacitive microfabricated ultrasonic transducer, the semiconductor substrate is doped with a first conductivity type, the impurity ions have a second conductivity type opposite to the first conductivity type, and the semiconductor substrate and the first A first voltage may be applied between regions, and a second voltage may be applied between the semiconductor substrate and the membrane layer.

In the capacitive microfabrication ultrasonic transducer, the semiconductor substrate further includes a third region in which the impurity ions are implanted at a third concentration higher than the first concentration, and the insulating layer is at least of the third region A third oxide layer having a third thickness greater than the first thickness is further included in a portion, wherein the gap is further defined between the first insulating layer and the membrane layer, and the membrane layer is supported by the third insulating layer. I can.

The capacitive micro-machining ultrasonic transducer (CMUT) according to the embodiments of the present invention made as described above can be economically manufactured because oxide layers having different thicknesses can be formed at once using impurity ion implantation. By controlling the concentration distribution of the impurity ion implantation, various insulating layer structures may be formed to implement various multilevel operations. Of course, the scope of the present invention is not limited by these effects.

1 to 6 are schematic cross-sectional views showing a capacitive microfabricated ultrasonic transducer (CMUT) and a method of manufacturing the same according to an embodiment of the present invention.
7 is a schematic diagram showing an application example of a capacitive microfabricated ultrasonic transducer (CMUT) according to an embodiment of the present invention.
8 to 11 are schematic cross-sectional views showing a capacitive microfabricated ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.
12 to 14 are schematic cross-sectional views showing a capacitive micromachining ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.
15 to 18 are schematic cross-sectional views showing a capacitive micromachining ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.

Hereinafter, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more completely describe the present invention to those of ordinary skill in the art, and the following examples may be modified in various other forms, and the scope of the present invention is as follows. It is not limited to the examples. Rather, these embodiments are provided to make the present disclosure more faithful and complete, and completely convey the spirit of the present invention to those skilled in the art. In addition, in the drawings, the thickness or size of each layer is exaggerated for convenience and clarity of description.

1 to 6 are schematic cross-sectional views showing a capacitive microfabricated ultrasonic transducer (CMUT) and a manufacturing method thereof according to an embodiment of the present invention.

Referring to FIG. 1, a first region 120 and a second region 125 having different concentrations of impurity ions 115 may be formed on a semiconductor substrate 105. For example, the first region 120 is implanted with the impurity ions 115 at a first average concentration, and the second region 125 is not implanted with the impurity ions 115 or is lower than the first average concentration. It may be injected at a second average concentration.

For example, the semiconductor substrate 105 may include a semiconductor material such as silicon, germanium, silicon-germanium, or the like. Such a semiconductor material may be doped with n-type or p-type to have conductivity. Furthermore, the semiconductor substrate 105 may be provided by processing a semiconductor wafer to a predetermined thickness.

More specifically, the forming of the first region 120 and the second region 125 includes a first region covering the second region 125 by exposing the first region 120 on the semiconductor substrate 105. Forming the mask layer 110, and implanting the impurity ions 115 at a first average concentration in the first region 120 using the first mask layer 110 as an ion implantation protective layer. can do.

For example, the first mask layer 110 may be formed by forming a photoresist layer (not shown) on the semiconductor substrate 105 and then patterning using a photolithography process. The first mask layer 110 prevents impurity ions 115 from being implanted into the second region 125 in the ion implantation step, or is relatively impurity in the second region 125 compared to the first region 120. Less ions 115 can be implanted. The impurity ions 115 may affect the oxidation rate of the semiconductor substrate 105 and may include As, P, BF2 ions, and the like.

Referring to FIG. 2, by oxidizing the semiconductor substrate 105, a first oxide layer 130 having a first thickness in at least a portion of the first region 120 and a first thickness in at least a portion of the second region 125 An insulating layer 140 including a second oxide layer 135 having a smaller second thickness may be formed. The first oxide layer 130 having a relatively thick thickness may serve as an insulating part having parasitic capacitance in a capacitive microfabricated ultrasonic transducer (CMUT). For example, the first oxide layer 130 may be formed to a predetermined depth from the surface in the first region 120 and the second oxide layer 135 may be formed to a predetermined depth from the surface in the second region 125.

The first region 120 and the second region 125 may have different oxidation rates according to different degrees of implantation of the impurity ions 115. For example, the first region 120 having a relatively high implantation concentration of the impurity ions 115 may have a higher degree of crystal defects, such as amorphization, than the second region 125, and thus the oxidation rate may be faster. Accordingly, by varying the concentration of ion implantation, the first oxide layer 130 and the second oxide layer 135 having different oxide thicknesses can be simultaneously formed in one oxidation.

This oxidation process is economical because the process can be simplified compared to the conventional two oxidation processes. Furthermore, by making the difference in concentration of the impurity ions 115 different, the thicknesses of the first oxide layer 130 and the second oxide layer 135 may be differently adjusted to a desired ratio.

3 and 4, a membrane layer 155 may be formed on the insulating layer 140. For example, the insulating layer 140 is supported by the first oxide layer 130 having a relatively thick thickness, and a gap 160 between the second oxide layer 135 having a relatively thin thickness and the membrane layer 155 This can be limited.

More specifically, as shown in FIG. 3, the handle substrate 150 including the membrane layer 155 may be bonded to the insulating layer 140 of the semiconductor substrate 105. A separation layer 152 may be formed on the handle substrate 150 under the membrane layer 155. Subsequently, the handle substrate 150 may be separated by leaving the membrane layer 155 on the insulating layer 140. For example, by separating the handle substrate 150 from the membrane layer 155 based on the separation layer 152, as shown in FIG. 4, the membrane layer 155 is adhered to the insulating layer 140 Structure can be formed.

Additionally, referring to FIGS. 5 and 6, the upper wiring 170 is formed on the membrane layer 155, and the lower portion connected to the semiconductor substrate 105 through the membrane layer 155 and the insulating layer 140. The wiring 175 may be formed. The upper wiring 170 and the lower wiring 175 may be formed of a conductive material such as metal or doped polysilicon as power or ground connection portions. Optionally, the upper wiring 170 may be referred to as an upper electrode, and the lower wiring 175 may be referred to as a lower electrode.

More specifically, as shown in FIG. 5, a via hole 165 penetrating the membrane layer 155 and the insulating layer 140 may be formed. For example, an upper portion of the via hole 165 is formed on the membrane layer 155 using a photolithography and etching process, and then the via hole 165 is formed on the first oxide layer 130 using a photolithography and etching process. The lower part can be formed.

Subsequently, as shown in FIG. 6, an upper wiring 170 and a lower wiring 175 may be formed by forming a wiring layer and patterning the wiring layer.

1 to 6, the capacitive micromachining ultrasonic transducer (CMUT) according to this embodiment includes a first region 120 in which impurity ions 115 are implanted at a first concentration, and impurity ions ( 115) is not implanted or is formed by oxidizing the semiconductor substrate 105 and the semiconductor substrate 105 including the second region 125 to which the impurity ions 115 are implanted at a second concentration lower than the first concentration. , A first oxide layer 130 having a first thickness in at least a portion of the first region 120 and a second oxide layer 135 having a second thickness smaller than the first thickness in at least a portion of the second region 125 The included insulating layer 140 and the membrane layer 155 formed on the insulating layer 140 may be included.

Furthermore, the capacitive microfabricated ultrasonic transducer (CMUT) is connected to the semiconductor substrate 105 through the upper wiring 170 formed on the membrane layer 155 and the membrane layer 155 and the insulating layer 140. A lower wiring 175 may be further included.

7 is a schematic diagram showing an application example of a capacitive microfabricated ultrasonic transducer (CMUT) according to an embodiment of the present invention.

Referring to FIG. 7, the semiconductor substrate 105 is doped with a first conductivity type, impurity ions 115 have a second conductivity type opposite to the first conductivity type, and the semiconductor substrate 105 and the first region ( A first voltage V1 may be applied between 120) and a second voltage V1 may be applied between the semiconductor substrate 105 and the membrane layer 155.

For example, when the semiconductor substrate 105 is doped with a p-type, the first region 120 may be doped with an n+ type. In the first region 120, at least an n+-type doped region may remain under the first oxide layer 130. In this case, the first power source V1 may be connected such that the first region 120 becomes a positive electrode, and the second power source V2 may be connected such that the membrane layer 155 becomes a positive electrode.

As another example, when the semiconductor substrate 105 is doped with an n-type, the first region 120 may be doped with a p+ type. In the first region 120, at least a p+-type doped region may remain under the first oxide layer 130. In this case, both the first power source V1 and the second power source V2 may be connected such that the semiconductor substrate 105 becomes a positive electrode.

According to this, a pn diode structure can be formed by ion implantation, and by using this pn diode connection structure, a substantial electric field applied to the first oxide layer 130 is lowered to reduce an electric field higher than the breakdown voltage of the oxide to the first oxide layer ( It can be applied between 130 and the semiconductor substrate 105. In this case, the thickness of the first oxide layer 130 can be reduced. Furthermore, since the parasitic capacitance applied to the first oxide layer 130 can be reduced through the pn junction capacitance, sensitivity can be increased by increasing the amount of capacitance change during operation of the CMUT.

8 to 11 are schematic cross-sectional views showing a capacitive microfabricated ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.

8 and 9, a first region 120a in a semiconductor substrate 105 having different concentrations of impurity ions 115. A second region 125a and a third region 127 may be formed. Impurity ions 115 are implanted in the first region 120a at a first average concentration, and impurity ions 115 are not implanted in the second region 125a or at a second average concentration lower than the first average concentration. The ions 115 may be implanted, and the impurity ions 115 may be implanted in the third region 127 at a third average concentration higher than the first average concentration.

For example, as shown in FIG. 8, the doped region 120-1 including the first region 120a and the third region 127 is exposed on the semiconductor substrate 105, and the second region 125a A second mask layer 110a1 covering) may be formed. Subsequently, impurity ions 115 at a first average concentration in the doped region 120-1 including the first region 120a and the third region 127 using the second mask layer 110a1 as an ion implantation protective layer. ) Can be injected. Subsequently, the second mask layer 110a1 may be removed.

Referring to FIG. 9, the third region 127 may be exposed, and a third mask layer 110a2 may be formed to cover the first region and the second region. Subsequently, impurity ions 115 may be implanted into the third region 127 so that the ion implantation concentration in the third region 127 becomes a third average concentration using the third mask layer 110a2 as an ion implantation protection layer. . Accordingly, the impurity ions 115 may be implanted once in the first region 120a and the impurity ions 115 may be implanted twice in the third region 127. Subsequently, the third mask layer 110a2 may be removed.

For example, in the semiconductor substrate 105, a structure in which the first region 120a and the second region 125a are sequentially disposed on both sides of the third region 127 may be repeated.

Referring to FIG. 10, an insulating layer 140a including a first oxide layer 130a, a second oxide layer 135a, and a third oxide layer 137 may be formed by oxidizing the semiconductor substrate 105. In the insulating layer 137, a structure in which the first oxide layer 130a and the second oxide layer 135a are sequentially disposed on both sides of the third oxide layer 137 may be repeated.

For example, the first oxide layer 130a is formed in at least a portion of the first region 120a to have a first thickness, and the second oxide layer 135a is formed in at least a portion of the second region 125a to have a first thickness. The third oxide layer 137 may be formed to have a second thickness, and the third oxide layer 137 may be formed in at least a portion of the third region 127 to a third thickness greater than the first thickness.

Referring to FIG. 11, a membrane layer 155 may be formed on the insulating layer 140a. For the formation of the membrane layer 155, the description of FIG. 3 may be referred to. Accordingly, the membrane layer 155 is supported by the third oxide layer 137 having the thickest thickness, and the gap 160a is formed between the first oxide layer 130a and the membrane layer 155, and the second oxide layer 135a. And it may be defined between the membrane layer 155.

Thereafter, with reference to the description of FIGS. 5 and 6, the upper wiring 170 and the lower wiring 175 may be further formed.

According to the present embodiment, by forming the insulating layer 140a having a multistage structure through multistage ion implantation, the capacitive micromachining ultrasonic transducer (CMUT) can be operated at multilevels.

12 to 14 are schematic cross-sectional views showing a capacitive micromachining ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.

Referring to FIG. 12, a fourth region that exposes the first region 120b of the semiconductor substrate 105 and covers the second region 125b, but gradually decreases in thickness from the center of the second region 125b toward both ends. A mask layer 110b may be formed. Subsequently, impurity ions 115 can be implanted into the semiconductor substrate 105 using the fourth mask layer 110b as an ion implantation protective layer.

Accordingly, the impurity ions 115 are implanted in the first region 120b at a first average concentration, and the impurity ions 115 are implanted in the second region 125b at a second average concentration lower than the first average concentration. It can be doped so that the impurity ions can go from the center to both ends and the concentration gradually increases.

Referring to FIG. 13, the semiconductor substrate 105 may be oxidized to form an insulating layer 140b including a first oxide layer 130b and a second oxide layer 135b. The first oxide layer 130b is formed to have a first thickness in at least a part of the first region 120b, and the second oxide layer 135b has a second thickness lower than the first thickness in at least a part of the second region 125b. However, the thickness of the second region 125b may be formed to increase gradually toward both ends of the second region 125b.

Referring to FIG. 14, a membrane layer 155 may be formed on the insulating layer 140b. For the formation of the membrane layer 155, the description of FIG. 3 may be referred to. Accordingly, the membrane layer 155 is supported by the first oxide layer 130b having a thick thickness, and the gap 160b may be defined between the second oxide layer 135b and the membrane layer 155.

Thereafter, with reference to the description of FIGS. 5 and 6, the upper wiring 170 and the lower wiring 175 may be further formed.

According to the present embodiment, the concentration of the impurity ions 115 in the second region 125b may be continuously changed, and accordingly, the thickness of the second oxide layer 135b may be continuously changed.

15 to 18 are schematic cross-sectional views showing a capacitive micromachining ultrasonic transducer (CMUT) and a method of manufacturing the same according to another embodiment of the present invention.

Referring to FIG. 15, a doped region 120-2 including a first region 120c and a third region 127c is exposed on the semiconductor substrate 105, and a second region covering the second region 125c. A mask layer 110c1 may be formed.

Subsequently, impurity ions 115 may be implanted into the doped region 120-2 including the first region 120c and the third region 127c using the second mask layer 110c1 as an ion implantation protection layer. .

Referring to FIG. 16, a third mask layer 110c2 may be further formed to expose the third region 127c and cover the first region 120c. Subsequently, impurity ions 115 may be implanted into the third region 127c using the second mask layer 110c1 and the third mask layer 110c2 as ion implantation protective layers. In the semiconductor substrate 105, a structure in which the second regions 125c and the first regions 120c are sequentially disposed on both sides of the third region 127c may be repeated.

As another example, in FIG. 15, the second mask layer 110c1 is removed, and in FIG. 17, the third mask layer 110c2 covers the first area 120c and the second area 125c, and the third area 127c It may be formed to expose.

Referring to FIG. 17, the semiconductor substrate 105 may be oxidized to form an insulating layer 140c including a first oxide layer 130c, a second oxide layer 135c, and a third oxide layer 137c. The first oxide layer 130c is formed to have a first thickness in at least a portion of the first region 120c, and the second oxide layer 135c has a second thickness less than the first thickness in at least a portion of the second region 125c And the third oxide layer 137c may be formed in at least a portion of the third region 127c to have a third thickness greater than the first thickness.

Accordingly, in the insulating layer 140c, a structure in which the second oxide layer 135c and the first oxide layer 130c are sequentially disposed on both sides of the third oxide layer 137c may be repeated.

Referring to FIG. 18, a membrane layer 155 may be formed on the insulating layer 140c. For the formation of the membrane layer 155, the description of FIG. 3 may be referred to. Accordingly, the membrane layer 155 is supported by the third oxide layer 137c having the thickest thickness, and the gap 160c is formed between the first oxide layer 130c and the membrane layer 155, and the second oxide layer 135c. ) And the membrane layer 155 may be defined.

Thereafter, with reference to the description of FIGS. 5 and 6, the upper wiring 170 and the lower wiring 175 may be further formed.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those of ordinary skill in the art will appreciate that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

105: semiconductor substrate
120, 120a, 120b, 120c: first area
125, 125a, 125b, 125c: second area
127, 127c: third area
130, 130a, 130b, 130c: first oxide layer
135, 135a, 135b, 135c: second oxide layer
137, 137c: third oxide layer
140, 140a, 140b, 140c: insulating layer
155: membrane layer
170: upper wiring
176: lower wiring

Claims (16)

Forming a first region in which impurity ions are implanted at a first average concentration in a semiconductor substrate and a second region in which the impurity ions are not implanted or to which the impurity ions are implanted at a second average concentration lower than the first average concentration ;
Insulation including a first oxide layer having a first thickness in at least a portion of the first region and a second oxide layer having a second thickness less than the first thickness in at least a portion of the second region by oxidizing the semiconductor substrate Forming a layer; And
Forming a membrane layer on the insulating layer, comprising forming the membrane layer to define a gap between the second oxide layer and the membrane layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
The membrane layer is supported by the first oxide layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
The step of forming the first region and the second region,
Forming a first mask layer covering the second region and exposing the first region on a semiconductor substrate; And
Using the first mask layer as an ion implantation protective layer, implanting the impurity ions in the first region at the first average concentration,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
The semiconductor substrate is doped with a first conductivity type,
The impurity ions have a second conductivity type opposite to the first conductivity type,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
The semiconductor substrate further comprises forming a third region in which the impurity ions are implanted at a third average concentration higher than the first average concentration,
In the step of forming the insulating layer, the insulating layer is formed to further include a third oxide layer having a third thickness greater than the first thickness in at least a portion of the third region,
In the step of forming the membrane layer, the gap is further defined between the first oxide layer and the membrane layer,
The membrane layer is supported by the third oxide layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 5,
Forming the first region, the second region, and the third region on the semiconductor substrate,
Exposing the first region and the third region, and forming a second mask layer covering the second region;
Implanting the impurity ions at the first average concentration into the first region and the third region by using the second mask layer as an ion implantation protective layer;
Exposing the third region and forming a third mask layer covering the first region and the second region; And
Including the step of implanting the impurity ions into the third region so that the ion implantation concentration in the third region becomes the third average concentration by using the third mask layer as an ion implantation protective layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 5,
In the semiconductor substrate, a structure in which the first region and the second region are sequentially disposed on both sides of the third region is repeated,
In the insulating layer, a structure in which the first oxide layer and the second oxide layer are sequentially disposed on both sides of the third oxide layer is repeated,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 5,
In the semiconductor substrate, a structure in which the second region and the first region are respectively disposed on both sides of the third region is repeated,
In the insulating layer, a structure in which the second oxide layer and the first oxide layer are respectively disposed on both sides of the third oxide layer is repeated,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
In the step of forming the second region, the second region is formed such that the concentration of the impurity ions gradually increases as the impurity ions go from the center to both ends,
In the step of forming the insulating layer, the second oxide layer is formed such that its thickness gradually increases toward both ends from the center of the second region,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 9,
Forming the second region,
Forming a fourth mask layer that exposes the first region and covers the second region, and gradually decreases in thickness from the center of the second region toward both ends; And
Including the step of implanting the impurity ions into the semiconductor substrate by using the fourth mask layer as an ion implantation protective layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
Forming the membrane layer,
Bonding a handle substrate including the membrane layer onto the insulating layer of the semiconductor substrate; And
Leaving the membrane layer on the insulating layer and separating the handle substrate,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. The method of claim 1,
Forming an upper wiring on the membrane layer, and forming a lower wiring connected to the semiconductor substrate through the membrane layer and the insulating layer,
Method of manufacturing a capacitive microfabricated ultrasonic transducer. A semiconductor substrate including a first region to which impurity ions are implanted at a first concentration and a second region to which the impurity ions are not implanted or to which the impurity ions are implanted at a second concentration lower than the first concentration;
A first oxide layer formed by oxidizing the semiconductor substrate and having a first thickness in at least a portion of the first region and a second oxide layer having a second thickness less than the first thickness in at least a portion of the second region An insulating layer;
Comprising a membrane layer formed on the insulating layer,
The membrane layer is formed to define a gap between the second oxide layer and the membrane layer,
Capacitive micromachined ultrasonic transducer. The method of claim 13,
The semiconductor substrate is doped with a first conductivity type,
The impurity ions have a second conductivity type opposite to the first conductivity type,
A first voltage is applied between the semiconductor substrate and the first region,
A second voltage is applied between the semiconductor substrate and the membrane layer,
Capacitive micromachined ultrasonic transducer. The method of claim 13,
The semiconductor substrate further includes a third region into which the impurity ions are implanted at a third concentration higher than the first concentration,
The insulating layer further includes a third oxide layer having a third thickness greater than the first thickness in at least a portion of the third region,
The gap is further defined between the first insulating layer and the membrane layer,
The membrane layer is supported by the third insulating layer,
Capacitive micromachined ultrasonic transducer. The method of claim 13,
The second region is formed such that the concentration of the impurity ions gradually increases as the impurity ions go from the center to both ends,
The second oxide layer is formed such that its thickness gradually increases from the center of the second region toward both ends,
Capacitive micromachined ultrasonic transducer.

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