KR20160109572A - Light emitting device and method for fabricating the same, and light emitting device package - Google Patents

Abstract

An embodiment of the present invention relates to a light emitting device. The light emitting device of the embodiment of the present invention, comprises a first conductive first semiconductor layer including a first dopant; a first conductive second semiconductor layer positioned on the first conductive first semiconductor layer; a first conductive third semiconductor layer positioned on the first conductive second semiconductor layer; an active layer positioned on the first conductive third semiconductor layer; and a second conductive semiconductor layer including a second dopant. The first conductive third semiconductor layer includes a plurality of pits with uniform size.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting device, a light emitting device,

Embodiments relate to a light emitting device, a method of manufacturing a light emitting device, and a light emitting device package.

A light emitting device is a p-n junction diode in which electric energy is converted into light energy. The light emitting device can be formed by combining elements of Group 3 and Group 5 on the periodic table. LEDs can be implemented in various colors by controlling the composition ratio of compound semiconductors.

When a forward voltage is applied to a light emitting device, the electrons in the n-layer and the holes in the p-layer are coupled to emit energy corresponding to the energy gap between the conduction band and the valance band. It emits mainly in the form of heat or light, and emits in the form of light.

For example, nitride semiconductors have received great interest in the development of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. Particularly, blue light emitting devices, green light emitting devices, ultraviolet (UV) light emitting devices, and the like using nitride semiconductors have been commercialized and widely used.

Meanwhile, the conventional light emitting device has a lattice constant difference between a growth substrate, for example, a sapphire substrate and a GaN layer, which is a nitride semiconductor, and a large difference in thermal expansion coefficient dislocations and the like, and many of these potentials generate leakage currents and deteriorate ESD (Electric Static Discharge) resistance.

On the other hand, in the prior art, a pit structure is introduced to improve ESD resistance. However, since the crystal quality of the active layer formed in the pit region is generally lowered, the light emitting region substantially contributing to light emission is reduced, there is a problem.

The embodiment provides a light emitting device having pits of uniform size.

The embodiment provides a light emitting device capable of improving the luminous efficiency of the active layer.

The light emitting device of the embodiment includes: a first conductive type first semiconductor layer including a first dopant; a first conductive type second semiconductor layer disposed on the first conductive type first semiconductor layer; A first conductive type third semiconductor layer disposed on the first conductive type second semiconductor layer; An active layer disposed on the first conductive type third semiconductor layer; And a second conductive type semiconductor layer including a second dopant, and the first conductive type third semiconductor layer may include a plurality of pits having a predetermined size.

Alternatively, the light emitting device package of the embodiment may include the light emitting element.

Alternatively, the method of manufacturing a light emitting device according to an embodiment of the present invention includes: forming a first conductive type first semiconductor layer including a first dopant; Forming a first conductive type second semiconductor layer on the first conductive type first semiconductor layer; Forming a first conductive type third semiconductor layer on the first conductive type second semiconductor layer; Forming an active layer on the first conductive type third semiconductor layer; And forming a second conductive type semiconductor layer on the active layer, wherein the first conductive type third semiconductor layer may include a plurality of pits having a predetermined size.

The embodiment can uniformly provide the size of the pits.

Embodiments can remove pits that degrade light efficiency.

The embodiment can provide a device resistant to ESD (elecrosatic discharge).

The embodiment has pits of uniform size, which can improve the reliability of the light emitting device and the light emitting device package.

1 is a cross-sectional view illustrating a light emitting device according to an embodiment.
Fig. 2 is an enlarged cross-sectional view of E1 in Fig. 1. Fig.
3 is a view showing pits of a general light emitting device.
4 is a view showing pits of a light emitting device according to an embodiment.
5 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment.
11 is a cross-sectional view illustrating a light emitting device according to another embodiment.
12 is a cross-sectional view illustrating a light emitting device package including the light emitting device of FIG.

In the description of the embodiments, each layer (film), region, pattern or structure is referred to as being "on" or "under" the substrate, each layer (film) Quot; on "and" under "are intended to include both" directly "or" indirectly " do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

1 is a cross-sectional view illustrating a light emitting device according to an embodiment, and FIG. 2 is an enlarged cross-sectional view of FIG.

Referring to FIGS. 1 and 2, the light emitting device 100 includes a substrate 105, a buffer layer 106, a light emitting structure 110, and first and second electrodes 151 and 152.

The light emitting structure 110 includes a first conductive semiconductor layer 121, a first conductive semiconductor layer 123, a first conductive semiconductor layer 125, an active layer 130, And a conductive semiconductor layer 140.

The substrate 105 may be a semiconductor single crystal, a material having excellent thermal conductivity, or may be a conductive substrate or an insulating substrate. At least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge and Ga ₂ O ₃ can be used as the substrate 105. A concavo-convex structure may be formed on the substrate 105, but the present invention is not limited thereto.

The buffer layer 106 may be formed on the substrate 105. The buffer layer 106 may reduce the lattice mismatch between the material of the light emitting structure 110 and the substrate 105. The buffer layer 106 has a group III-V compound semiconductor such as Al _x In _y Ga _(1-xy) N composition formula (0 x 1, 0 y 1, 0 x + y 1) A compound semiconductor, and may include at least one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN.

An undoped semiconductor layer may be further formed between the buffer layer 106 and the first conductive semiconductor layer 121 so that the undoped semiconductor layer is not doped with impurities. It can have lower conductivity.

The first conductive type first semiconductor layer 121 is formed on the buffer layer 106, and a first conductive type dopant may be added. The first conductive dopant may be an n-type dopant and includes, for example, Si, Ge, Sn, Se, and Te. The first conductive type first semiconductor layer 121 may be formed of any of Group III-V compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN.

The first semiconductor layer 125 of the first conductivity type includes a plurality of pits P. The plurality of pits P may have a concave shape from the upper surface of the first conductive type third semiconductor layer 125. The plurality of pits P may be of uniform size. For example, the plurality of pits P may have a certain depth. The complex pits P may extend to a lower surface of the first conductive type third semiconductor layer 125. Each of the plurality of pits P may be formed into a V-shaped side cross-section, and the planar shape may be a hexagonal shape. The plurality of pits P may be formed in the shape of a hexagonal prism, but the present invention is not limited thereto. One or a plurality of potentials (not shown) may be connected to the plurality of pits P. The size of the pit P may be controlled by the first conductive type second semiconductor layer 123 located under the first conductive type third semiconductor layer 125. [

The first conductive type second semiconductor layer 123 may be located on the first conductive type first semiconductor layer 121. The first conductive type second semiconductor layer 123 may be located between the first conductive type first semiconductor layer 121 and the first conductive type third semiconductor layer 125. That is, the first conductive type third semiconductor layer 125 may be located on the first conductive type second semiconductor layer 123. The pits P may be formed on the first conductive type second semiconductor layer 123.

The first conductive type second semiconductor layer 123 can control the size of the pits P formed in the first conductive type third semiconductor layer 125. The size of the pits P may be the depth of the pits P. [ The size of the pits P may be a horizontal width.

The first conductive type second semiconductor layer 123 can control the depth of the pit P according to the material, the thickness, the growth temperature, and the growth time. For example, the first conductive type second semiconductor layer 123 may be formed of any one of compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, and InAlGaN. The pits P may extend to the first conductive type second semiconductor layer 123. The depth of the pit P may be the same as the thickness of the first conductive type third semiconductor layer 125. The depth of the pits P may be the same as the thickness of the first conductive type second semiconductor layer 123 and the first conductive type third semiconductor layer 125.

The first conductive type second semiconductor layer 123 of the embodiment may be formed of an AlGaN-based semiconductor such as AlGaN or InAlGaN. When the first conductive type third semiconductor layer 125 is GaN, the first conductive type second semiconductor layer 123 may be AlGaN. It may be, for example, the first conductive type second semiconductor layer 123 is Al _{x 1 GaN1-x} or _{Al x GaN 1-x / In} x GaN1 1-x (0.1≤x≤0.3).

The first conductive type second semiconductor layer 123 may have a thickness of 150 nm or less. For example, the first conductive type second semiconductor layer 123 may have a thickness of 10 nm to 20 nm.

The first conductive type second semiconductor layer 123 may be grown at a temperature lower than that of the first conductive type first semiconductor layer 121. For example, the first conductive type second semiconductor layer 123 may be grown at a temperature of 200 ° C to 400 ° C.

The first conductive type second semiconductor layer 123 may grow at a slower rate than the first conductive type first semiconductor layer 121. For example, the growth rate of the first conductive type second semiconductor layer 123 may be 1/2 or less of the growth rate of the first conductive type first semiconductor layer 121.

The active layer 130 may be formed on the first conductive type third semiconductor layer 125. The embodiment is formed on the first conductive type third semiconductor layer 125 except for the region where the pits P are formed, but the embodiment is not limited thereto. For example, the active layer 130 may be formed on the pit P, and the thickness of the active layer 130 formed on the pit P may be greater than the thickness of the first conductive- May be different from the thickness of the active layer 130 formed on the active layer 125. That is, the thickness of the active layer 130 formed on the pits P may be thinner than the thickness of the active layer 130 formed on the first conductive type third semiconductor layer 125 except for the pits P have. The active layer 130 may include a quantum well (not shown) and a quantum wall (not shown). Although not shown in the figure, the active layer 130 may include a plurality of sub active layers. Here, each of the plurality of sub active layers may include a quantum well and a quantum wall. The quantum well / both barrier layers of the active layer 130 may be any one of a pair of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InGaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP) But the present invention is not limited thereto.

A supper lattice 160 may be formed between the active layer 130 and the first conductive type third semiconductor layer 125. The superlattice 160 may be formed of 10 pairs of InGaN / GaN or InGaN / InGaN, but is not limited thereto.

The first conductive type second semiconductor layer 123 of the embodiment is disposed between the first conductive type first semiconductor layer 121 including the n-type dopant and the superlattice 160 and is made of GaN and AlGaN type The plurality of pits P having a uniform thickness can be formed in accordance with the thickness, the growth temperature, and the growth time. That is, since the first conductive type second semiconductor layer 123 is formed to be formed from the start of the growth of the first conductive type third semiconductor layer 125, the first conductive type third semiconductor layer 125, It is possible to prevent the light output from being lowered due to the pit formed at the intermediate point of the light emitting element.

FIG. 3 is a view showing pits of a general light emitting device, and FIG. 4 is a view showing pits of the light emitting device of the embodiment.

Referring to FIG. 3, a typical light emitting device includes a first pit having a predetermined size and a second pit formed around the first pit. The second pit may have a smaller size than the first pit. That is, the second pit may have a smaller depth and a smaller horizontal width than the first pit.

Referring to FIG. 5, the light emitting device of the embodiment includes pits having a predetermined size. The pit of the size smaller than the pit is not included in the vicinity of the pit. Therefore, the embodiment includes upper and lower layers and a semiconductor layer having a large lattice mismatch to form a pit having a constant size, and the thickness, growth temperature, and growth time of the semiconductor layer are controlled, Lt; / RTI > can be removed.

In addition, the embodiment can provide a device which is resistant to electrostatic discharge (ESD) with a constant size of pits.

Further, the embodiment can provide uniformly sized pits, thereby improving the reliability of the light emitting device.

5 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment will be described with reference to FIGS. 5 to 10. FIG.

Referring to FIG. 5, a buffer layer 106 may be formed on a substrate 105. The substrate 105 may be a conductive substrate having excellent thermal conductivity or an insulating substrate. For example, the substrate 105 may use at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ . Although not shown in the drawing, the substrate 105 may have a concavo-convex structure on its upper surface, but the present invention is not limited thereto.

The buffer layer 106 includes a function of relieving the lattice mismatch between the material of the light emitting structure 110 and the substrate 105. The buffer layer 106 may be formed of at least one of Group III-V compound semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN.

The first conductive semiconductor layer 121 may be formed on the buffer layer 106.

The first conductive type first semiconductor layer 121 may be formed of a semiconductor compound. Group 3-Group 5, Group 2-Group 6, and the like, and the first conductive type dopant may be doped. When the first conductive type first semiconductor layer 112 is an n-type semiconductor layer, the first conductive type dopant includes n-type dopant such as Si, Ge, Sn, Se, and Te, but is not limited thereto .

The first conductive type first semiconductor layer 121 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, have.

6, a first conductive type second semiconductor layer 123 is formed on the first conductive type first semiconductor layer 121 and a first conductive type first conductive type semiconductor layer 123 is formed on the first conductive type second semiconductor layer 123, The third semiconductor layer 125 may be formed. The first conductive type third semiconductor layer 125 may have a plurality of pits P having a V-shaped cross section depending on the material and growth conditions.

Each of the plurality of pits P may be formed into a V-shaped side cross-section, and the planar shape may be a hexagonal shape. The plurality of pits P may be formed in the shape of a hexagonal prism, but the present invention is not limited thereto. One or a plurality of potentials (not shown) may be connected to the plurality of pits P. The size of the pit P may be controlled by the first conductive type second semiconductor layer 123 located under the first conductive type third semiconductor layer 125. [ The size of the pits P may be the depth of the pits P. [ The size of the pits P may be a horizontal width.

The first conductive type second semiconductor layer 123 may be located on the first conductive type first semiconductor layer 121. The first conductive type second semiconductor layer 123 may be located between the first conductive type first semiconductor layer 121 and the first conductive type third semiconductor layer 125.

The first conductive type second semiconductor layer 123 can control the depth of the pit P according to the material, the thickness, the growth temperature, and the growth time. For example, the first conductive type second semiconductor layer 123 may be formed of any one of compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, and InAlGaN. The pits P may extend to the first conductive type second semiconductor layer 123. The depth of the pit P may be the same as the thickness of the first conductive type third semiconductor layer 125. The depth of the pits P may be the same as the thickness of the first conductive type second semiconductor layer 123 and the first conductive type third semiconductor layer 125.

The first conductive type second semiconductor layer 123 of the embodiment may be formed of an AlGaN-based semiconductor such as AlGaN or InAlGaN. When the first conductive type third semiconductor layer 125 is GaN, the first conductive type second semiconductor layer 123 may be AlGaN. It may be, for example, the first conductive type second semiconductor layer 123 is Al _{x 1 GaN1-x} or _{Al x GaN 1-x / In} x GaN1 1-x (0.1≤x≤0.3).

The first conductive type second semiconductor layer 123 may have a thickness of 150 nm or less. For example, the first conductive type second semiconductor layer 123 may have a thickness of 10 nm to 20 nm.

The first conductive type second semiconductor layer 123 may be grown at a temperature lower than that of the first conductive type first semiconductor layer 121. For example, the first conductive type second semiconductor layer 123 may be grown at a temperature of 200 ° C to 400 ° C.

The first conductive type second semiconductor layer 123 may grow at a slower rate than the first conductive type first semiconductor layer 121. For example, the growth rate of the first conductive type second semiconductor layer 123 may be 1/2 or less of the growth rate of the first conductive type first semiconductor layer 121.

Referring to FIG. 7, a superlattice 160 and an active layer 130 may be formed on the first conductive type third semiconductor layer 125. The superlattice 160 may be formed of 10 pairs of InGaN / GaN or InGaN / InGaN, but is not limited thereto.

The active layer 130 may be formed of at least one of a single quantum well structure, a multi quantum well (MQW) structure, a quantum-wire structure, or a quantum dot structure. For example, the active layer 114 may be formed with a multiple quantum well structure by injecting trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) But is not limited thereto.

The quantum well / both barrier layers of the active layer 130 may be any one of a pair of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InGaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP) But the present invention is not limited thereto.

The superlattice 160 and the active layer 130 may be formed on the plurality of pits P.

Referring to FIG. 8, a second conductive semiconductor layer 140 may be formed on the active layer 130, and an ohmic layer 142 may be formed on the second conductive semiconductor layer 140.

When the second conductive semiconductor layer 140 is a p-type semiconductor layer, the second conductive dopant may include Mg, Zn, Ca, Sr, and Ba as p-type dopants.

Although the first conductive type first semiconductor layer 121 is an n-type semiconductor layer and the second conductive type semiconductor layer 140 is a p-type semiconductor layer, the present invention is not limited thereto.

The ohmic layer 142 may be formed by laminating a single metal, a metal alloy, a metal oxide, or the like so as to efficiently inject holes.

For example, the ohmic layer 142 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (ZnO), indium gallium tin oxide (AZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZON nitride, AGZO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Ni, IrOx / Au, and Ni / IrOx / , Au, and Hf, and is not limited to such a material.

Referring to FIG. 9, the ohmic layer 142, the second conductive semiconductor layer 140, the active layer 130, the superlattice 160, and the first conductive semiconductor layer 121 are formed to expose the first conductive semiconductor layer 121, Part of the first conductive type third semiconductor layer 125 and the first conductive type second semiconductor layer 123 can be removed.

10, a second electrode 152 may be formed on the ohmic layer 142 and a first electrode 151 may be formed on the exposed first conductive semiconductor layer 121 .

The light emitting device 100 according to the embodiment of FIGS. 1 to 10 includes pits P having a constant size. But does not include a pit having a size smaller than that of the pit P in the periphery of the pit P. Therefore, the embodiment includes a first conductive type second semiconductor layer 125 having upper and lower layers and a material having a large lattice mismatch to form pits P having a constant size, and the first conductive type The thickness of the second semiconductor layer 125, the growth temperature, and the growth time may be controlled to remove the pits that reduce the light efficiency of the light emitting device.

In addition, the embodiment can provide a device which is resistant to constant voltage discharge (ESD) by pits P having a constant size.

Further, the embodiment can provide uniformly sized pits, thereby improving the reliability of the light emitting device.

11 is a cross-sectional view illustrating a light emitting device according to another embodiment.

Referring to FIG. 11, FIG. 7 illustrates another electrode arrangement of the light emitting device of FIG. A detailed description of the components in Fig. 11 will be given with reference to the description of Fig.

Referring to FIG. 11, the light emitting device 200 includes a first electrode 251 on a first conductive type first semiconductor layer 221 and a second electrode 252 on a lower side.

The first electrode 151 may be formed after the substrate (not shown) is removed from the first conductive type first semiconductor layer 221. Here, the method of removing the substrate may be performed by a physical method (e.g., laser lift off) and / or a chemical method (wet etching), and the buffer layer formed on the substrate may be removed, The light emitting layer 221 may be exposed.

The first electrode 251 may have a variety of patterns, for example, an arm pattern or a bridge pattern, but the present invention is not limited thereto. A portion of the first electrode 251 may be used as a pad to which a wire (not shown) is bonded.

A first conductive type second semiconductor layer 123, a first conductive type third semiconductor layer 125, a superlattice 160, an active layer 130, and a second conductive type semiconductor layer 125 are formed under the first conductive type first semiconductor layer 121. 2 conductive semiconductor layer 140 is located. The first conductive type second semiconductor layer 123, the first conductive type third semiconductor layer 125, the superlattice 160, the active layer 130, and the second conductive type semiconductor layer 140 are illustrated in FIGS. 10, detailed description thereof will be omitted.

The second electrode 252 may include a plurality of conductive layers and may include a contact layer 256, a reflective layer 255, a bonding layer 254, and a conductive support member 253. The contact layer 256 may be a low conductive material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, or ATO or may be a metal of Ni or Ag. A reflective layer 255 is formed under the contact layer 256 and the reflective layer 255 is formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, And at least one layer made of a material selected from the group. A part of the reflective layer 255 may be in contact with the second conductive semiconductor layer 240, and may be in ohmic contact with a metal or ohmic contact with a conductive material such as ITO. However, the present invention is not limited thereto.

The bonding layer 254 may be formed below the reflective layer 255 and may be used as a barrier metal or a bonding metal. The material may be, for example, Ti, Au, Sn, Ni, Cr, Ga, Cu, Ag, and Ta and an optional alloy.

The conductive support member 253 is formed under the bonding layer 254 and may be a metal or a carrier substrate and may be formed of a material such as copper-copper, gold-gold, nickel-nickel, molybdenum Mo, Cu-W, or a carrier wafer such as Si, Ge, GaAs, ZnO, SiC, or the like. As another example, the conductive supporting member 173 may be embodied as a conductive sheet.

A light extracting structure such as a roughness may be formed on the upper surface of the first conductive type first semiconductor layer 221. An insulating layer (not shown) may be formed on the surface of the semiconductor layers, and the insulating layer may be formed on the light extracting structure.

The current blocking layer 280 may be located in a region between the second electrode 252 and the second conductive semiconductor layer 240 in a region overlapping the first electrode 251.

The passivation layer 270 may be disposed along an edge between the second electrode 252 and the second conductive semiconductor layer 240. The protective layer 270 and the current blocking layer 280 may be formed of an insulating material or a transparent conductive material, but the present invention is not limited thereto. The protective layer 270 and the current blocking layer 280 may be formed of the same material or different materials, but the present invention is not limited thereto.

12 is a view showing a light emitting device package having the light emitting device of FIG.

Referring to FIG. 12, the light emitting device package 300 includes a body 321, a first lead electrode 311, a second lead electrode 313, a light emitting device 100, and a molding portion 331.

The first and second lead electrodes 311 and 313 may be coupled to the body 321 and may be electrically connected to the light emitting device 100. The molding part 331 may be positioned on the light emitting device 100 exposed to the outside.

The body 321 may be formed of a silicon material, a synthetic resin material, or a metal material. The body 321 includes a cavity 325 therein when viewed from above. Here, the cavity 325 may include a sloped side surface with respect to the bottom surface of the cavity 325.

The first and second lead electrodes 311 and 313 may be electrically isolated from each other by a predetermined distance. Or may be formed on the surface of the body 321. That is, a part of the first and second lead electrodes 311 and 313 is located inside the cavity 325, and the other parts of the first and second lead electrodes 311 and 313 are located in the body 321, respectively.

The first and second lead electrodes 311 and 313 provide a path through which a driving signal for driving the light emitting device 100 is provided and transfer the heat from the light emitting device 100 to the outside do. The first and second lead electrodes 311 and 313 may be formed of a metal material and separated by a gap portion 323.

The light emitting device 100 may be mounted on the upper surface of one of the first and second lead electrodes 311 and 313. The light emitting device 100 may be overlapped with at least one of the first and second lead electrodes 311 and 313, but is not limited thereto.

A first electrode pad (not shown) of the light emitting device 100 may be connected to the first lead electrode 311 by a first wire 342 and may be connected to a second electrode pad May be connected to the second lead electrode 313 by a second wire 343, but is not limited thereto.

The molding member 331 covers the light emitting device 100 to protect the light emitting device 241. In addition, the molding member 331 may include a phosphor (not shown) that provides light of a specific wavelength band.

The light emitting device according to the embodiment may be applied to a backlight unit, a lighting unit, a display device, a pointing device, a lamp, a streetlight, a vehicle lighting device, a vehicle display device, a smart watch, but is not limited thereto.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

121, 221: a first conductive type first semiconductor layer
123, and 223: a first conductive type second semiconductor layer
125, 225: a first conductive type third semiconductor layer
P: PIT

Claims (16)

A first conductive type first semiconductor layer including a first dopant;
A first conductive type second semiconductor layer disposed on the first conductive type first semiconductor layer;
A first conductive type third semiconductor layer disposed on the first conductive type second semiconductor layer;
An active layer disposed on the first conductive type third semiconductor layer; And
And a second conductivity type semiconductor layer including a second dopant,
Wherein the first conductive type third semiconductor layer includes a plurality of pits having a predetermined size. The method according to claim 1,
Wherein the size of the pit is one of a depth and a horizontal width. The method according to claim 1,
And the pit extends to the first conductive type second semiconductor layer. The method according to claim 1,
And the depth of the pit is equal to the thickness of the first conductive type third semiconductor layer. The method according to claim 1,
Wherein a depth of the pit is equal to a thickness of the first conductive type second semiconductor layer and the first conductive type third semiconductor layer. The method according to claim 1,
Wherein when the first conductive type third semiconductor layer is GaN, the first conductive type second semiconductor layer is formed of an AlGaN-based semiconductor. The method according to claim 1,
The light emitting device of the first conductivity type second semiconductor layer is Al _{x 1 GaN1-x} or _{Al x GaN 1-x / In} x GaN1 1-x (0.1≤x≤0.3). The method according to claim 1,
And the first conductive type second semiconductor layer has a thickness of 150 nm or less. The method according to claim 1,
And the first conductive type second semiconductor layer has a thickness of 10 nm to 20 nm. The method according to claim 1,
Further comprising a superlattice formed of 10 pairs of InGaN / GaN or InGaN / InGaN between the first conductive type third semiconductor layer and the active layer. A light emitting device package comprising the light emitting element according to any one of claims 1 to 10. Forming a first conductive type first semiconductor layer including a first dopant;
Forming a first conductive type second semiconductor layer on the first conductive type first semiconductor layer;
Forming a first conductive type third semiconductor layer on the first conductive type second semiconductor layer;
Forming an active layer on the first conductive type third semiconductor layer; And
And forming a second conductive type semiconductor layer on the active layer,
Wherein the first conductive type third semiconductor layer includes a plurality of pits having a predetermined size. 13. The method of claim 12,
Wherein the first conductive type second semiconductor layer has a lower growth temperature than the first conductive type first semiconductor layer. 13. The method of claim 12,
Wherein the first conductive type second semiconductor layer is grown at a temperature of 200 ° C to 400 ° C. 13. The method of claim 12,
Wherein the first conductive type second semiconductor layer is grown at a slower rate than the first conductive type first semiconductor layer. 13. The method of claim 12,
Wherein a growth rate of the first conductive type second semiconductor layer is equal to or less than 1/2 of a growth rate of the first conductive type first semiconductor layer.

Images