KR20150078714A - Flat panel display and driving method the same - Google Patents

Abstract

The present invention relates to a flat panel display capable of preventing flickers and reducing power consumption, and a driving method thereof. It includes a display panel which drives pixels by using an oxide thin film transistor; a driving circuit which drives the gate lines and the data lines of the display panel; and a timing controller which supplies the driving circuit by arranging inputted image data, controls the driving circuit by outputting control signals, and operates with a normal mode or a low power mode according to the analysis result of the image data or the input signal of a user. The timing controller operates driving frames which outputs the image data and the control signals to frames, and hold frames which doesn′t output the image data and the control signals, respectively. All frames are set with the driving frame in the normal mode. The rate of the hold frame of the frames is higher than that of the driving frame in the lower power mode.

Description

Technical Field [0001] The present invention relates to a flat panel display,

The present invention relates to a flat panel display and a driving method thereof.

In recent years, flat panel display devices have been widely used as display devices. The flat panel display includes a liquid crystal display (OLED), an organic light emitting diode (OLED) display, and the like.

The flat panel display device is in a trend of becoming larger and higher in resolution, and therefore the power consumption of the flat panel display device is gradually increasing. Therefore, efforts to reduce the power consumption of the flat panel display device are continuously required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flat panel display capable of reducing power consumption and a driving method thereof.

According to an aspect of the present invention, there is provided a flat panel display comprising: a display panel for driving a plurality of pixels using an oxide thin film transistor; A driving circuit for driving gate lines and data lines of the display panel; And supplies the plurality of control signals to the driving circuit so as to operate in a normal mode or a low power mode according to a result of analysis of the input signal of the user or the image data A timing controller; Wherein the timing controller operates by dividing a plurality of frames into drive frames for outputting the image data and the plurality of control signals and hold frames for outputting the image data and the plurality of control signals, All frames are set as the driving frame, and in the low power mode, the ratio of the hold frame is set to be larger than the ratio of the driving frame in the plurality of frames.

The timing controller sets only the initial frames of the low-power mode as the driving frame and sets the remaining frames as the hold frame.

Wherein the timing controller operates in a first switching mode during a specific frame period between the normal mode and the low power mode when switching from the general mode to the low power mode, The number of the hold frames is gradually increased with respect to the number of the hold frames.

Wherein the timing controller operates in a second switching mode during a specific frame period between the low power mode and the normal mode when switching from the low power mode to the normal mode, And the number of the hold frames is gradually decreased with respect to the number of the hold frames.

The timing controller may determine whether the image data is a still image or a moving image, output a first selection signal indicating the normal mode if the image data is determined as a moving image, and if the image data is a still image, A mode selection unit for outputting a second selection signal indicating a low power mode; A frame rate control unit for outputting an output control signal or a blocking control signal in response to the first and second selection signals; An image alignment unit for aligning the image data, outputting aligned image data in response to the output control signal, and stopping driving in response to the interruption control signal; And a control signal generator for generating the plurality of control signals using the input sync signal and outputting the plurality of control signals in response to the output control signal and stopping the driving in response to the interruption control signal; Wherein the frame rate control unit outputs only the output control signal during every frame period in which the first selection signal is input and outputs the output control signal or the blocking control signal during each frame period in which the second selection signal is input, And outputs the cut-off control signal more than the output control signal.

According to another aspect of the present invention, there is provided a method of driving a flat panel display including a display panel driving a plurality of pixels using an oxide thin film transistor; And a driving circuit for driving the gate lines and the data lines of the display panel, wherein the timing controller supplies the image data inputted to the driving circuit to the driving circuit, and outputs a plurality of control signals And operating in a normal mode or a low power mode according to an analysis result of the input signal of the user or the image data; Wherein the timing controller operates by dividing a plurality of frames into drive frames for outputting the image data and the plurality of control signals and hold frames for outputting the image data and the plurality of control signals, All frames are set as the driving frame, and in the low power mode, the ratio of the hold frame is set to be larger than the ratio of the driving frame in the plurality of frames.

The timing controller sets only the initial frames of the low-power mode as the driving frame and sets the remaining frames as the hold frame.

Wherein the timing controller operates in a first switching mode during a specific frame period between the normal mode and the low power mode when switching from the general mode to the low power mode, The number of the hold frames is gradually increased with respect to the number of the hold frames.

Wherein the timing controller operates in a second switching mode during a specific frame period between the low power mode and the normal mode when switching from the low power mode to the normal mode, And the number of the hold frames is gradually decreased with respect to the number of the hold frames.

Wherein the step of operating the timing controller in the normal mode or the low power mode comprises the steps of determining whether the image data is a still image or a moving image and outputting a first selection signal indicating the normal mode when the image data is determined as a moving image, Outputting a second selection signal indicating the low power mode if the image data is determined to be a still image; And outputs the output control signal or the blocking control signal during every frame period in which the second selection signal is input, and outputs the blocking control signal during each frame period in which the first selection signal is input, Outputting more than the output control signal; Outputting an output control signal or a blocking control signal in response to the first and second selection signals; Arranging the image data, outputting the aligned image data in response to the output control signal, and stopping the output of the image data in response to the blocking control signal; Generating the plurality of control signals using the input sync signal and outputting the plurality of control signals in response to the output control signal and stopping the output of the plurality of control signals in response to the interruption control signal And a control unit.

The timing controller of the present invention operates in a normal mode or a low power mode according to a result of analysis of a user's input signal or image data. In the present invention, since the timing controller does not output image data and a plurality of control signals during the hold frame period in the low power mode, the power consumption of the timing controller can be reduced. In addition, since the driving circuits controlled according to a plurality of control signals are also stopped during the hold frame period, the power consumption of the driving circuit can be reduced. Since the switching element for driving the pixels of the display panel of the present invention is composed of an oxide TFT having excellent off current characteristics, the timing controller does not need to have a separate memory for storing image data during the hold frame period of the low power mode. In addition, the timing controller of the present invention can gradually increase or decrease the ratio of the hold frame period to the drive frame period at the time of switching between the normal mode and the low power mode, thereby preventing flickering due to abrupt change of the frame frequency.

1 is a configuration diagram of a flat panel display according to an embodiment of the present invention.
Fig. 2 is a configuration diagram of the timing controller 8 shown in Fig.
3 is a driving waveform diagram for explaining a normal mode.
4 is a driving waveform diagram for explaining the low power mode.
5 is a flowchart showing a driving method of the timing controller 8 according to another embodiment of the present invention.
6 is a driving waveform diagram for explaining the first switching mode.
7 is a driving waveform diagram for explaining the second switching mode.

Hereinafter, a flat panel display according to an embodiment of the present invention and a driving method thereof will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a flat panel display according to an embodiment of the present invention.

The flat panel display device shown in Fig. 1 includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8.

The display panel 2 includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersecting with each other. A plurality of pixels P are arranged in a crossing region of the gate line GL and the data line DL. Each pixel P displays an image according to a data voltage supplied from the data line DL in response to a scan pulse supplied from the gate line GL. To this end, each pixel P includes a thin film transistor (TFT) connected to the gate line GL and the data line DL. The display panel 2 may be a liquid crystal display panel of a liquid crystal display or an OLED display panel of an OLED display.

In particular, the present invention constitutes thin film transistors for driving a plurality of pixels P with an oxide TFT. For reference, an oxide TFT has excellent off current characteristics when compared with an amorphous silicon (a-Si) TFT widely used in a flat panel display of the prior art. Flicker is generally generated when pixels P of the display panel 2 are driven at a low frequency of 60 Hz or less. However, the present invention drives the pixels P using the oxide TFT, so flicker can be prevented even if the display panel 2 is driven at a low frequency of 60 Hz or less.

The gate driver 4 can be embedded in the non-display area of the display panel 2, as shown in Fig. Although not shown, the gate driver 4 may be integrated and connected to one side of the display panel 2. The gate driver 4 includes a gate shift register for supplying a scan pulse to the plurality of gate lines GL1 to GLn according to a plurality of gate control signals GCS provided from the timing controller 8. [

The data driver 6 converts digital image data RGB input from the timing controller 8 into data voltages using a reference gamma voltage in accordance with a plurality of data control signals DCS provided from the timing controller 8, And supplies the converted data voltage to the plurality of data lines DL. To this end, the data driver 6 includes a data shift register for outputting a sampling signal, a latch for latching image data, and a digital-analog converter.

The timing controller 8 arranges image data (RGB) input from the outside in accordance with the size and resolution of the display panel 2 and supplies the image data to the data driver 6. The timing controller 8 outputs a plurality of control signals GCS and DCS using synchronous signals SYNC input from the outside. The plurality of control signals GCS and DCS include a gate control signal GCS and a data control signal DCS. The gate control signal GCS is a signal for controlling the gate driver 4 and the data control signal DCS is a signal for controlling the data driver 6. [ The synchronization signals SYNC include a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and the like.

In particular, the timing controller 8 of the present invention operates in a normal mode or a low power mode according to a result of analysis of a user's input signal (not shown) or image data (RGB). To this end, the timing controller 8 includes a plurality of frames as driving frames for outputting image data RGB and a plurality of control signals GCS and DCS, image data RGB and a plurality of control signals GCS, DCS ) To hold frames. The timing controller 8 operates by setting all the frames as drive frames in the normal mode and operates by setting the ratio of the hold frame to the ratio of the drive frame among the plurality of frames in the low power mode. Therefore, since the timing controller 8 does not output the image data RGB and the plurality of control signals GCS and DCS during the hold frame period in the low power mode, the present invention can reduce the power consumption of the timing controller 8 have. Also, the driving circuits 4 and 6 controlled in accordance with the control signals GCS and DCS are also stopped during the hold frame period, so that the power consumption of the driving circuits 4 and 6 can be reduced.

Fig. 2 is a configuration diagram of the timing controller 8 shown in Fig. 3 is a driving waveform diagram for explaining a normal mode. 4 is a driving waveform diagram for explaining the low power mode. Hereinafter, the timing controller 8 of the present invention will be described more specifically with reference to Figs. 2 to 4. Fig.

2, the timing controller 8 includes a mode selection unit 10, a frame rate control unit 12, an image alignment unit 14, and a control signal generation unit 16.

The mode selection unit 10 analyzes image data RGB input from the outside and outputs a first selection signal SS1 or a second selection signal SS2 according to the analyzed result. The first selection signal SS1 is a signal indicating a normal mode and the second selection signal SS2 is a signal indicating a low power mode. The mode selection unit 10 outputs a first selection signal SS1 when the video data RGB is determined to be a moving picture and outputs a second selection signal SS2 when the video data RGB is determined to be a still picture.

The frame rate control unit 12 operates in a normal mode or a low power mode in response to the first and second selection signals SS1 and SS2 provided from the mode selection unit 10. [ The frame rate control unit 12 outputs an output control signal CS1 or a blocking control signal CS2 every frame in accordance with each mode.

The output control signal CS1 is a signal that instructs the timing controller 8 to output the image data RGB in alignment and generate and output a plurality of control signals DCS and GCS. The cutoff control signal CS2 is a signal for instructing the timing controller 8 to block the output of the image data RGB and the plurality of control signals DCS and GCS. If the timing controller 8 does not output the image data RGB and the plurality of control signals DCS and GCS, the operation of the driving circuits 4 and 6 for driving the display panel 2 is stopped, Accordingly, each pixel P of the display panel 2 maintains the data voltage charged in the previous frame period.

The frame rate control unit 12 can output the output control signal CS1 or the blocking control signal CS2 every frame based on the vertical synchronization signal Vsync among the synchronization signals SYNC.

Referring to FIG. 3, the frame rate controller 12 operates in the normal mode in response to the first selection signal SS1. In the normal mode, the frame rab control unit 12 outputs only the output control signal CS1 every frame. The timing controller 8 outputs the image data RGB and a plurality of control signals GCS and DCS for each frame and the driving circuits 4 and 6 output the image data RGB at a high frequency of 60 Hz or more, (P) of the pixels.

Referring to FIG. 4, the frame rate controller 12 operates in the low power mode in response to the second selection signal SS2. In the low power mode, the frame rate control unit 12 outputs the output control signal CS1 or the blocking control signal CS2, but outputs the blocking control signal CS2 more than the output control signal CS1. Then, in the timing controller 8, the period in which the hold frame operates as the drive frame becomes larger than the period in which the hold frame operates as the drive frame, and the drive circuits 4, Thereby driving the pixels P.

The frame rate control unit 12 can output only the initial specific control frames CS1 in the low power mode and output the blocking control signals CS2 in the remaining frames. In this case, the power consumption of the timing controller 8 and the driving circuits 4 and 6 can be reduced by the period during which the timing controller 8 and the driving circuits 4 and 6 operate as a hold frame. For example, as shown in FIG. 4, the frame rate control unit 12 may output the output control signal CS1 only in the first frame and output the blocking control signal CS2 in the remaining frames in the low power mode . The present invention prevents flickering of the display panel 2 even if a period of operating as a hold frame continues after the period in which the timing controller 8 and the driving circuits 4 and 6 operate as a driving frame. This is because, as described above, the display panel 2 drives the pixels P using an oxide TFT having an excellent off current characteristic.

As described above, the embodiment of the present invention cuts off the output of the timing controller 8 except for the initial specific frame period in the low power mode, and stops the operation of the driving circuits 4 and 6 to save power consumption. However, although the embodiment described above can reduce power consumption, flicker may be generated in the display panel 2 due to a sudden change in the frame frequency upon switching between the normal mode and the low power mode. Therefore, the present invention proposes a method for reducing flicker while reducing power consumption as follows.

5 is a flowchart showing a driving method of the timing controller 8 according to another embodiment of the present invention. 6 is a driving waveform diagram for explaining the first switching mode. 7 is a driving waveform diagram for explaining the second switching mode.

First, the timing controller 8 according to another embodiment of the present invention has the same configuration as that of the previous embodiment. 2, the timing controller 8 includes a mode selection unit 10, a frame rate control unit 12, an image alignment unit 14, and a control signal generation unit 16 .

However, when switching from the normal mode to the low power mode, the frame rate controller 12 of the timing controller 8 operates in the first switching mode (change mode 1) during the specific frame period between the normal mode and the low power mode, When the mode is switched from the normal mode to the normal mode, the operation mode is changed to the second mode (change mode 2) during a specific frame period between the low power mode and the normal mode. Hereinafter, the operation of the frame rate control unit 12 will be described in detail with reference to Figs. 5 to 7. Fig.

First, the frame rate control unit 12 checks whether the signal provided from the mode selection unit 10 is a first selection signal SS1 or a second selection signal SS2. (S1)

Then, the frame rate controller 12 determines whether the current state is a period during which the current state enters the low-power mode from the normal mode or a period during which the low-power mode advances to the normal mode, according to the checked signal.

The frame rate control unit 12 operates in the first switching mode when the current state is a period of entering the low power mode from the normal mode. In the first switching mode, the frame rate control unit 12 inserts frames outputting the blocking control signal CS2 between the frames outputting the output control signal CS1, as shown in Fig. The frame rate controller 12 gradually increases the number of output frames of the blocking control signal CS2 inserted between the frames outputting the output control signal CS1 from the beginning of the first switching mode to the latter half of the first switching mode. Then, in the consecutive frames driven by the timing controller 8, the number of the hold frames to the number of the drive frames gradually increases, and the frame frequency gradually decreases. Therefore, another embodiment of the present invention can prevent flicker on the display panel 2 by preventing a sudden change of the frame frequency when switching between the normal mode and the low-power mode (S5)

The frame rate control unit 12 operates in the low power mode when the ratio occupied by the hold frame during the first switching mode period increases and the driving frequency of the timing controller 8 falls below a preset value. The operation of the frame rate controller 12 in the low power mode is the same as in the previous embodiment. (S7)

On the other hand, the frame rate control unit 12 operates in the second switching mode when the current state is a period of entering the normal mode from the low power mode. In the second switching mode, the frame rate control unit 12 inserts frames outputting the blocking control signal CS2 between the frames outputting the output control signal CS1, as shown in Fig. The frame rate controller 12 gradually decreases the number of output frames of the blocking control signal CS2 inserted between the frames outputting the output control signal CS1 from the beginning of the second switching mode to the latter half of the second switching mode. Then, among the consecutive frames driven by the timing controller 8, the number of the hold frames to the number of the drive frames gradually decreases, and the frame frequency gradually increases. Therefore, another embodiment of the present invention can prevent flicker on the display panel 2 by preventing a sudden change of the frame frequency when switching between the low power mode and the general mode. (S9)

The frame rate control unit 12 operates in the normal mode when the ratio of the hold frame occupied during the second switching mode period decreases and the driving frequency of the timing controller 8 becomes higher than a predetermined value. The operation of the frame rate control unit 12 in the normal mode is the same as that of the previous embodiment (S11)

However, in another embodiment of the present invention, the second switching mode of the frame rate controller 12 may be deleted as the case may be. This is because the low power mode is a case of displaying a still image and the normal mode is a case of displaying a moving picture. Therefore, the process of switching from a still image to a moving picture is not limited to a case where the frame frequency is gradually increased The image quality may be better.

As described above, the timing controller of the present invention operates in a normal mode or a low power mode according to a result of analysis of a user's input signal or image data. In the present invention, since the timing controller does not output image data and a plurality of control signals during the hold frame period in the low power mode, the power consumption of the timing controller can be reduced. In addition, since the driving circuits controlled according to a plurality of control signals are also stopped during the hold frame period, the power consumption of the driving circuit can be reduced. Since the switching element for driving the pixels of the display panel of the present invention is composed of an oxide TFT having excellent off current characteristics, the timing controller does not need to have a separate memory for storing image data during the hold frame period of the low power mode. In addition, the timing controller of the present invention can gradually increase or decrease the ratio of the hold frame period to the drive frame period at the time of switching between the normal mode and the low power mode, thereby preventing flickering due to abrupt change of the frame frequency.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

8: timing controller 10: mode selector
12: frame rate control unit 14:
16: control signal generating unit SS1: first selection signal
SS2: second selection signal CS1: output control signal
CS2: Interrupt control signal

Claims (10)

A display panel for driving a plurality of pixels using an oxide thin film transistor;
A driving circuit for driving gate lines and data lines of the display panel;
And supplies the plurality of control signals to the driving circuit so as to operate in a normal mode or a low power mode according to a result of analysis of the input signal of the user or the image data A timing controller;
The timing controller
A plurality of frames are divided into driving frames for outputting the video data and the plurality of control signals, and hold frames for outputting the video data and the plurality of control signals,
Wherein the controller sets all the frames as the driving frame in the normal mode and sets the ratio of the hold frame to the ratio of the driving frame among the plurality of frames in the low power mode. The method according to claim 1,
The timing controller
Wherein the control unit sets only the specific frames of the initial period in the low power mode as the driving frame and sets the remaining frames as the holding frame. The method of claim 2,
The timing controller
Wherein when the normal mode is switched to the low power mode, the first switching mode is operated during a specific frame period between the normal mode and the low power mode,
Wherein the control unit gradually increases the number of the hold frames with respect to the number of the driving frames among the consecutive frames in the first switching mode. The method of claim 3,
The timing controller
And a second switching mode during a specific frame period between the low power mode and the general mode when switching from the low power mode to the normal mode,
Wherein the number of the hold frames is gradually decreased from the number of the drive frames in the continuous frames in the second switching mode. The method according to claim 1,
The timing controller
And outputs a first selection signal indicating the normal mode if the image data is determined as a moving image and outputs the first selection signal indicating the normal mode if the image data is determined as a moving image, A second selection signal for outputting a second selection signal;
A frame rate control unit for outputting an output control signal or a blocking control signal in response to the first and second selection signals;
An image alignment unit for aligning the image data, outputting aligned image data in response to the output control signal, and stopping driving in response to the interruption control signal;
And a control signal generator for generating the plurality of control signals using the input sync signal and outputting the plurality of control signals in response to the output control signal and stopping the driving in response to the interruption control signal;
The frame rate control unit
Only the output control signal is output for every frame period in which the first selection signal is input,
And outputs the output control signal or the cutoff control signal during every frame period in which the second selection signal is input, and outputs the cutoff control signal in a larger amount than the output control signal. A display panel for driving a plurality of pixels using an oxide thin film transistor; And a driving circuit for driving the gate lines and the data lines of the display panel,
The timing controller supplies the input image data to the driving circuit, outputs a plurality of control signals to control the driving circuit, and outputs the image data in a normal mode or a low power mode The method comprising the steps of:
The timing controller
A plurality of frames are divided into driving frames for outputting the video data and the plurality of control signals, and hold frames for outputting the video data and the plurality of control signals,
Wherein all the frames are set as the driving frame in the normal mode and the ratio of the hold frame in the plurality of frames in the low power mode is set to be larger than the ratio of the driving frame in the low power mode. The method of claim 6,
The timing controller
Wherein only the specific frames in the early stage of the low power mode are set as the driving frame and the remaining frames are set as the hold frame. The method of claim 7,
The timing controller
Wherein when the normal mode is switched to the low power mode, the first switching mode is operated during a specific frame period between the normal mode and the low power mode,
Wherein the number of the hold frames is gradually increased with respect to the number of the drive frames among the consecutive frames in the first switch mode. The method of claim 8,
The timing controller
And a second switching mode during a specific frame period between the low power mode and the general mode when switching from the low power mode to the normal mode,
Wherein the number of the hold frames is gradually decreased with respect to the number of the drive frames among the consecutive frames in the second switch mode. The method of claim 6,
Wherein the step of the timing controller operating in a normal mode or a low power mode
And outputs a first selection signal indicating the normal mode if the image data is determined as a moving image and outputs the first selection signal indicating the normal mode if the image data is determined as a moving image, And outputting a second selection signal for outputting a second selection signal;
And outputs the output control signal or the blocking control signal during every frame period in which the second selection signal is input, and outputs the blocking control signal during each frame period in which the first selection signal is input, Outputting more than the output control signal;
Outputting an output control signal or a blocking control signal in response to the first and second selection signals;
Arranging the image data, outputting the aligned image data in response to the output control signal, and stopping the output of the image data in response to the blocking control signal;
Generating the plurality of control signals using the input sync signal and outputting the plurality of control signals in response to the output control signal and stopping the output of the plurality of control signals in response to the interruption control signal And a driving method of the flat panel display device.

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