KR20110079605A - Thin film transistor array panel, display apparatus including the same, and manufacturing method for the display apparaus - Google Patents

Abstract

PURPOSE: A thin film transistor array panel of a display apparatus and a manufacturing method for the display apparatus are provided to easily being connected with a common electrode display panel using a light hardening member. CONSTITUTION: A thin film transistor array panel comprises a display area, a seal line area which surrounds the display area, a substrate in which a gate line(121), a data line(171), a pixel electrode(190), and a thin film transistor are formed, and a gate driving part. The gate driving part formed on the substrate comprises a wiring part which receives signal from outside and a circuit part which transmits a gate signal to the gate line in response to the wiring part.

Description

A thin film transistor array panel, a display device including the same, and a manufacturing method of the display device TECHNICAL FIELD {THIN FILM TRANSISTOR ARRAY PANEL DISPLAY APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHOD FOR THE DISPLAY APPARAUS}

The present invention relates to a thin film transistor array panel, a display device including the same, and a manufacturing method of the display device.

In general, a display device includes a display panel including a thin film transistor array panel including a gate line, a data line, a pixel electrode, and a thin film transistor, and a common electrode display panel, a gate driver for outputting a gate signal to the gate line, and a data signal to the data line. It consists of a data driver for outputting.

The gate driver and the data driver are formed in a chip form and mounted on the display panel. However, in recent years, in order to increase productivity while reducing the overall size of the display device, a structure in which the gate driver is incorporated in the display panel has been developed.

In the case of a liquid crystal display panel, which is a typical display panel, a thin film transistor array panel including a gate line, a data line, a pixel electrode, and a thin film transistor, a common electrode panel facing the thin film transistor array panel, and a gap between the thin film transistor array panel and the common electrode display panel And a sealant for bonding the liquid crystal layer and the thin film transistor array panel interposed therebetween to the common electrode display panel.

In the structure in which the gate driver is embedded in the thin film transistor array panel of the display panel, parasitic capacitance is generated between the gate driver and the common electrode formed on the common electrode display panel, and such parasitic capacitance causes a malfunction of the gate driver.

Therefore, recently, a structure for disposing a sealant between a gate driver and a common electrode has been proposed as a method for reducing parasitic capacitance.

Meanwhile, as the liquid crystal display panel becomes larger, not only a liquid crystal dropping method is generally used as a method of injecting a liquid crystal layer between the thin film transistor array panel and the common electrode display panel, but also to reduce misalignment between the thin film transistor array panel and the common electrode display panel. Mars sealants are commonly used. In this case, the photocurable sealant is cured by light to couple the thin film transistor array panel and the common electrode panel. In this case, since the light blocking layer is formed on the common electrode display panel corresponding to the region where the gate driver is formed, light is generally irradiated by a back exposure method incident from the rear surface of the thin film transistor array panel.

However, when the sealant provides light to the sealant in a structure provided between the gate driver and the common electrode to cure, the amount of light incident on the sealant by the gate driver decreases. In particular, when the line width is larger than 100 μm such as a power supply voltage line in which a high current flows, and the diffracted light is weak, the amount of light irradiated to the sealant of the portion decreases, so that curing of the sealant is not performed properly. The bonding force of the common electrode panel is reduced. In addition, since moisture is easily introduced from the outside through the sealant that is not properly bonded, corrosion of the gate driver is increased, thereby causing the gate driver to malfunction.

Accordingly, an object of the present invention is to provide a thin film transistor array panel that can be easily combined with a common electrode panel using a photocurable coupling member. In addition, to provide a display device including the thin film transistor array panel.

A thin film transistor substrate according to an aspect of the present invention includes a substrate and a gate driver. The substrate includes a gate line, a data line, a pixel electrode, and a thin film transistor. The gate driver includes a wiring unit formed on the substrate and receiving a signal from the outside, a circuit unit outputting the gate signal to the gate line in response to the external signal, and an opening formed in the wiring unit.

A display device according to an aspect of the present invention includes a display panel, a data driver, and a gate driver. The display panel may include a first substrate having a gate line, a data line, a pixel electrode, a thin film transistor, a second substrate facing the first substrate, and the first substrate and the second substrate interposed therebetween. And a coupling member for coupling the second substrate. The display panel displays an image in response to a gate signal and a data signal. The data driver outputs the data signal to the data line.

The gate driver includes a wiring unit for receiving a signal from the outside and a circuit unit for outputting the gate signal to the gate line in response to the signal, and is provided on the first substrate, and an opening is formed in the wiring unit. .

According to such a display device, in a structure in which a sealant including a photocurable material is interposed between the first substrate and the second substrate so as to cover a portion of the gate driver, a signal line of the gate driver may be formed to harden the sealant. Since the opening through which the incident light is transmitted through the rear surface of the first substrate is formed, the bonding force between the first and second substrates by the sealant can be improved, and as a result, the corrosion defect due to moisture introduced from the outside can be improved. Can be.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of the display device illustrated in FIG. 1 taken along the line II-II`.
FIG. 3 is an example of a block diagram of a shift register used as the gate driver shown in FIG.
4 is an example of a circuit diagram of one stage of the shift register shown in FIG.
5 is a schematic layout view of a gate driver according to an exemplary embodiment of the present invention.
FIG. 6 is an example of the layout of the wiring portion of the gate driver shown in FIG. 5.
FIG. 7 is a cross-sectional view of the wiring unit illustrated in FIG. 6 taken along the line VII-VII ′. FIG.
FIG. 8 is an example of a layout view of a part of a circuit portion of the gate driver shown in FIG. 5.
FIG. 9 is a cross-sectional view of the wiring unit illustrated in FIG. 8 taken along the line IX-IX '. FIG.
10 is a layout view of pixels of the display area DA.
FIG. 11 is a cross-sectional view of the pixel illustrated in FIG. 10 taken along the line XI-XI ′.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

1 is a plan view of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the display device shown in FIG. 1 taken along the line II-II '.

1 and 2, a display device 600 according to an exemplary embodiment of the present invention is provided in a display panel 300 and a display panel 300 that display an image in response to a data signal and a gate signal. The panel 300 includes a data driver 500 and a gate driver 400 for outputting data signals and gate signals, respectively.

The display panel 300 includes a thin film transistor array panel 100, a common electrode panel 200 facing the thin film transistor array panel 100, and a liquid crystal interposed between the thin film transistor array panel 100 and the common electrode panel 200. Layer 330 and sealant 350.

The display panel 300 includes a display area DA displaying an image, a seal line area SA surrounding the display area DA, and a first peripheral area positioned outside the seal line area SA. The second peripheral area PA2 is provided between the area PA1 and the display area DA and a part of the seal line area SA. The common electrode panel 200 is disposed in the seal line area SA and inside thereof, and the thin film transistor array panel 100 extends out of the seal line area SA to the first peripheral area PA1.

In an equivalent circuit, the display panel 300 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels connected thereto.

The gate lines GL1 to GLn and the data lines DL1 to DLm are formed on the substrate 110 of the thin film transistor array panel 100. The gate lines GL1 to GLn and the data lines DL1 to DLm cross each other insulated from each other in the display area DA, and extend to the second and first peripheral areas PA2 and PA1, respectively, so that the gate driver 400 and the data may extend. It is connected to the driver 500.

Each pixel includes a thin film transistor Tr positioned in the display area DA and connected to the gate lines GL1 to GLn and the data lines DL1 to DLm, and the liquid crystal capacitor Clc connected thereto.

The thin film transistor Tr is formed on the thin film transistor array panel 100 and has a control terminal connected to the gate lines GL1 to GLn, an input terminal connected to the data lines DL1 to DLm, and a liquid crystal capacitor Clc. It has an output terminal connected to. The thin film transistor Tr preferably includes amorphous silicon, but may also include polycrystalline silicon.

The liquid crystal capacitor Clc includes a pixel electrode (not shown) formed on the thin film transistor array panel 100, a common electrode 270 formed on the substrate 210 of the common electrode display panel 200, and a liquid crystal layer therebetween. 330. The pixel electrode is connected to the thin film transistor Tr, and the common electrode 270 is formed on the entire surface of the common electrode display panel 200 and receives a common voltage.

The data driver 500 having a chip shape is mounted on the thin film transistor array panel 100 of the first peripheral area PA1. The data driver 500 is electrically connected to the data lines DL1 to DLm to apply a data signal.

Meanwhile, a gate driver 400 is formed in the thin line transistor SA adjacent to the second peripheral area PA2 and the thin film transistor array panel 100 on the second peripheral area PA2. The gate driver 400 is electrically connected to the gate lines GL1 to GLn to apply a gate signal.

The sealant 350 is positioned in the seal line area SA and serves to couple the thin film transistor array panel 100 and the common electrode display panel 200 to confine the liquid crystal of the liquid crystal layer 330. The sealant 350 includes a photocurable material.

The sealant 350 overlaps a portion of the gate driver 400 positioned in the seal line area SA. Since the dielectric constant of the liquid crystal layer 330 is about 10 or more, and the dielectric constant of the sealant 350 is about 4.0 or less, in this way, the common electrode 270 of the common electrode display panel 200 and the gate driver 400 may be disposed. Can reduce parasitic doses produced in

As illustrated in FIG. 2, the light blocking layer 220 positioned in the seal line area SA and the second peripheral area PA2 is also formed in the common electrode display panel 200. A color filter layer (not shown) may be provided between the second substrate 210 and the common electrode 270 of the common electrode display panel 200, and the color filter layer may include three primary colors, for example, red, green, and blue. Display. However, the color filter layer may be provided in the thin film transistor array panel 100 and sometimes omitted.

In the liquid crystal display device, the liquid crystal layer 330 is sealed by the sealant 350 between the two display panels 100 and 200 through a dropping method. In the dropping method, the liquid crystal layer 330 may cover the two display panels 100 and 200. The liquid crystal droplets are dropped on the common electrode panel 200 or the thin film transistor array panel 100 before the sealant 350 is bonded, and then the two panels 100 and 200 are aligned, and the sealant 350 is exposed to light to cure. However, since the light blocking layer 220 blocks the light in the common electrode display panel 200, light is incident from the rear surface of the thin film transistor array panel 100 when the sealant 350 is cured.

FIG. 3 is an example of a block diagram showing the gate driver shown in FIG. 1, and FIG. 4 is an example of a circuit diagram of one stage of the gate driver shown in FIG.

Referring to FIGS. 3 and 4, the gate driver 400 is connected to each other and includes a plurality of stages ST ₁ to ST _{n +1} that sequentially output gate signals, and include a gate off voltage Voff, First and second clock signals CKV and CKVB and an initialization signal INT are input. All stages ST ₁ to ST _{n + 1} except for the last stage ST _{n +1 are} connected to the gate lines GL1 to GLn one-to-one.

Each stage ST ₁ to ST _{n +1} includes a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power supply voltage terminal GV, and a frame rear. It has a set terminal FR, and a gate output terminal OUT1 and a carry output terminal OUT2.

Each stage, for example, the j-th stage (ST _j) the set terminal (S), the carry output of the front end stage (ST _j-1), i.e. shear carry output [Cout (j-1)] is a reset terminal ( The gate output of the rear stage ST _{j +1} , that is, the rear gate output Gout (j + 1), is input to R, and the clock signals CKV, CKVB are provided to the first and second clock terminals CK1, CK2. ) Is input, the gate off voltage V _off is input to the gate voltage terminal GV, and the initialization signal INT is input to the frame reset terminal FR. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j). The carry output Cout (n + 1) of the last stage ST _{n +1} is provided to each stage ST1 to ST _n as an initialization signal INT.

However, the scan start signal STV is input to the first stage ST ₁ of the shift register 400 instead of the front carry output, and the scan start signal STV is output to the last stage ST _{n +1} instead of the rear gate output. Is entered. In addition, when the first clock signal CKV is input to the first clock terminal CK1 of the j th stage ST _j and the second clock signal CKVB is input to the second clock terminal CK2, The second clock signal CKVB is provided at the first clock terminal CK1 of the j-1) th and (j + 1) th stages ST _{j -1} and ST _{j +1} , and is provided at the second clock terminal CK2. The first clock signal CKV is input.

The first and second clock signals CKV and CKVB are equal to the gate-on voltage V _on when the voltage level is high so as to drive the transistor Tr of the pixel, and gate-off voltage V _{off when the} voltage is low. Is preferred. The first and second clock signals CKV and CKVB may have a duty ratio of 50% and a phase difference of 180 °.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j th stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output unit ( 450). These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the second clock terminal CK2, and gates of the transistor T5 are connected to the first clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T11 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the first clock terminal CK1 and the contact J3, and a first transistor T12. And a transistor T7 connected between the one clock terminal CK1 and the contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the first clock terminal CK1. Connected and the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and is connected to the first clock terminal CK1 through the capacitor C1, the drain is connected to the first clock terminal CK1, and the source is the contact J4. The capacitor C2 is connected between the contact J3 and the contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs the transistors T9, T13, T8, T3, T2, and T6 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T9 is connected to the reset terminal R, the drain is connected to the contact J1, the gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drain is respectively a contact. It is connected to (J3, J4). The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2. The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, and the source is connected to the gate off voltage terminal GV.

The output unit 450 includes a pair of transistors T1 and T15 having a drain and a source connected between the first clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of the transistor T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of description, a voltage corresponding to a high level of the first and second clock signals CKV and CKVB is called a high voltage, and a magnitude of a voltage corresponding to a low level of the first and second clock signals CKV and CKVB. Is equal to the gate off voltage (V _off ) and is referred to as low voltage.

First, when the second clock signal CKVB and the front carry output Cout (j-1) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T15 are turned on so that the first clock signal CKV is output to the output terminals OUT1 and OUT2. At this time, the voltage of the contact J2 and the first clock signal CKV are low voltage. , The output voltages Gout (j) and Cout (j) become low voltages. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the first clock signal CKV and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, and T8 connected to the gate are connected. , T2) are all off.

Subsequently, when the second clock signal CKVB becomes low, the transistors T11 and T5 are turned off. At the same time, when the first clock signal CKV becomes high, the output voltage of the transistor T1 and the contact point J2 of the transistor T1 are turned off. The voltage becomes a high voltage. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the first clock signal CKV and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be substantially the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, and thus the transistor T3 turns off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Accordingly, the output terminals OUT1 and OUT2 are connected only to the first clock signal CKV and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the second clock signal CKVB go high and the first clock signal CKV goes low, the transistors T9 and T2 are turned on so that the contact J1, It transmits low voltage to J2). At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Accordingly, the two transistors T1 and T15 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, whereby the output terminals OUT1 and OUT2 become the first clock signal CKV. It is connected to and emits low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T15 is turned off and the output terminal OUT2 is cut off from the first clock signal CKV. Therefore, the carry output Cout (j )] Floats to maintain a low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the first clock signal CKV and the voltage of the contact J2 is low.

Next, when the first clock signal CKV becomes high, the transistors T12 and T7 are turned on, the voltage of the contact J4 is increased, the transistor T3 is turned on, and a low voltage is transmitted to the contact J2. OUT1 continues to emit a low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the first clock signal CKV and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the first clock terminal CK1 is connected to the drains of the two transistors T1 and T15 so that the first clock signal CKV is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the first clock signal CKV becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain regions, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 is the first clock signal CKV and the second voltage is high. When the clock signal CKVB is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

Meanwhile, the transistor T6 receives the initialization signal INT, which is the carry output Cout (n + 1) of the last dummy stage ST _{n +1} , and transfers the gate off voltage V _off to the contact J1. To set the voltage at the contact J1 again to a lower voltage.

In this manner, the stage ST _j is based on the front carry signal Cout (j-1) and the rear gate signal Gout (j + 1) and synchronized with the first and second clock signals CKV and CKVB. To generate a carry signal Cout (j) and a gate signal Gout (j).

Next, an arrangement on the thin film transistor array panel 100 of the gate driver 400 illustrated in FIG. 4 will be described in detail with reference to FIGS. 5, 6, and 8.

5 is a schematic layout view of a gate driver according to an exemplary embodiment of the present invention, FIG. 6 is a layout view of a wiring part of the gate driver shown in FIG. 5, and FIG. 8 is a layout view of a part of a circuit part of the gate driver shown in FIG. 5. to be.

FIG gate driver 400 according to this embodiment Referring to 5, the various input to the circuit (CS), and these stages (ST ₁ ST ~ _{n +1)} consisting of above-described stages (ST ₁ ST ~ _{n +1)} And a wiring part LS for transmitting the signals Voff, CKV, CKVB, and INT.

The wiring part LS may include the gate-off voltage line SL1 for transmitting the gate-off voltage Voff, and the first and second clock signal lines SL2 and SL3 for transmitting the first and second clock signals CKV and CKVB, respectively. And an initialization signal line SL4 for transmitting the initialization signal INT. Each signal line SL1 to SL4 extends mainly in the vertical direction, and is arranged in order from the left in the order of the gate-off voltage line SL1, the clock signal lines SL2 and SL3, and the initialization signal line SL4 to the shift register 400. Getting closer. In addition, these signal lines SL1 to SL4 have connecting lines extending horizontally toward the stages ST ₁ to ST _{n +1} , and the gate-off voltage line SL1 and the initialization signal line SL4 are connected to one stage ST ₁ to ST. _{Although n + 1 is} connected one by one, the first and second clock signal lines SL2 and SL3 are positioned near the boundary of the stages ST ₁ to ST _{n +1} and alternately are connected one by one.

In the circuit section CS, the arrangement of the transistors T1 to T13 and T15 in each of the stages ST ₁ to ST _{n +1} , for example, the (j-1) th stage, shows the front carry signal at the upper left side close to the front stage. A transistor T4 to which [Cout (j-1)] is input is disposed, and a transistor T1 that receives the first clock signal CKV along a connection line of the first clock signal line SL2 extending in the horizontal direction. And T15 are disposed, and transistors T7, T10, and T12 that receive the first clock signal CKV are also disposed below the transistor T15. In addition, the transistors T11 and T5 connected to the connection line of the second clock signal line SL3 rising from the bottom to receive the second clock signal CKVB are disposed on the lower left side, and the initialization signal line SL4 coming from the left side. The transistor T6 connected to the connection line of the signal receiving the initialization signal INT is disposed on the leftmost side. In addition, the transistors T2, T3, T8, T9, and T13 that receive the gate-off voltage Voff are disposed below the connection line of the gate-off voltage line SL1 extending in the horizontal direction.

In the j-th stage ST _j adjacent thereto, the first clock signal line SL2 and the first clock signal CKV are converted into the second clock signal line SL3 and the second clock signal CKVB, and vice versa. Except that the signal line SL3 and the second clock signal CKVB are replaced with the first clock signal line SL2 and the first clock signal CKV, the arrangement of each transistor is the (J-1) th stage (ST _{j). -1} )

In this case, the wiring part SL is located in the seal line area SA, a part of the circuit part CS is also located in the seal line area SA, and another part of the circuit part CS is a process margin area of the seal line area SA. It is located at (SA '). The width of the process margin area SA ′ is about 0.3 mm, which means the maximum error range that may occur when the sealant 350 is applied to the seal line area SA.

As described above, when the sealant 350 is cured, the light is irradiated from the rear surface of the thin film transistor array panel 100 so that the signal lines and the transistors positioned in the seal line area SA and the seal line process margin area SA ′ may emit light. It has a flat structure that can pass through well.

Referring to FIG. 6, the wide signal lines SL1 to SL3 have a ladder or a net shape and have a plurality of openings through which light can pass. Accordingly, each of the signal lines SL1 to SL3 includes a pair of one or more vertical portions extending in length and a plurality of horizontal portions connecting them, and have openings surrounded by them. The width and spacing of the longitudinal sections are determined to the extent that light can be diffracted and transmitted and preferably about 20 to 30 μm, preferably about 25 μm. The total line width of each signal line 122a to 122c is appropriately determined in consideration of the increase in resistance caused by the opening. It is preferable to have such a structure in the case where the light is not diffracted because the line width when no opening is formed is about 100 µm or more.

Referring to FIG. 8, a large thin film transistor positioned in the seal line area SA and the seal line process margin area SA ′, for example, the transistors T4 and T15 in FIG. It is divided into (T41 ~ T45) and there is a sufficient gap between them to allow light to pass between the small transistors (T41 ~ T45). The width and spacing of the small thin film transistors T41 to T45 are also determined to allow light to diffract and transmit, and are preferably about 100 μm or less.

Next, the structure of the thin film transistor array panel including the gate driver 400 will be described in detail with reference to FIGS. 7 and 9 through 11 and FIGS. 6 and 8.

FIG. 7 is a cross-sectional view of the wiring unit illustrated in FIG. 6 taken along the line VII-VII ′, and FIG. 9 is a cross-sectional view of the wiring unit illustrated in FIG. 8 taken along the line IX-IX ′, and FIG. It is a layout view of the pixel of area | region DA, and FIG. 11 is sectional drawing which cut | disconnected and showed the pixel shown in FIG. 10 along line XI-XI '.

A plurality of gate lines 121 and a plurality of driving signal lines 122, 122a through 122d are formed on the insulating substrate 110.

Referring to FIG. 10, the gate line 121 transmits a gate signal, mainly extends in a horizontal direction, and extends to be connected to the gate driver 400. A portion of each gate line 121 forms a plurality of gate electrodes 124, and the other portion protrudes downward to form a plurality of projections 127.

Referring to FIG. 6, the driving signal lines 122a to 122d transmit gate-off voltages Voff, first and second clock signals CKV and CKVB, and an initialization signal INT, respectively, and extend in the vertical direction. Except for the narrowest initialization signal line 122c, the remaining driving signal lines 122a to 122c have a ladder shape, and include a pair of one or more vertical portions extending in length and a plurality of horizontal portions connecting them, and the openings surrounded by them. Has The width and spacing of the longitudinal sections are determined to the extent that light can be diffracted and transmitted and preferably about 20 to 30 μm, preferably about 25 μm. The total line width of each signal line 122a to 122c is appropriately determined in consideration of the increase in resistance caused by the opening. It is preferable to have such a structure in the case where the light is not diffracted because the line width when no opening is formed is about 100 µm or more. On the other hand, the initialization signal line 122d has a plurality of branches extending in the horizontal direction toward each stage.

Referring to FIG. 8, the driving signal line 122 transmits a signal in the gate driver and is expanded to serve as a control electrode of the thin film transistor of the gate driver.

The gate line 121 and the driving signal lines 122 and 122a to 122d may be formed of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper (Cu), copper alloys, and the like. It consists of copper-based metals, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), tantalum (Ta) and titanium (Ti). However, the gate line 121 may include two layers having different physical properties, that is, a lower layer (not shown) and an upper layer (not shown) thereon. The upper layer has a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum (Ag) or silver alloy to reduce signal delay or voltage drop of the gate line 121. It may be made of a copper-based metal such as a metal of the series, copper (Cu) or a copper alloy. In contrast, the underlayer is a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti) Or the like. The chromium lower film, the aluminum-neodymium (Nd) alloy upper film, the molybdenum upper film and the aluminum-neodymium (Nd) alloy lower film are good examples.

Side surfaces of the gate line 121 and the driving signal lines 122, 122a through 122d are inclined with respect to the surface of the substrate 110, and the inclination angle is in the range of about 30 to 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate line 121 and the driving signal lines 122 and 122a to 122d.

A plurality of linear semiconductors 151 and island semiconductors 152 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of protrusions 154 extend toward the gate electrode 124, and the width of the linear semiconductor 151 is increased near the point where the linear semiconductor 151 meets the gate line 121. The large area of 121 is covered. The island type semiconductor 152 is positioned on the control electrode of the gate driver as shown in FIG. 8, or is positioned on a part of the driving signal lines 122, 122a to 122d as shown in FIGS. 6 and 8, and the driving signal line 122. , 122a through 122d).

On top of the semiconductors 151, 152 a plurality of linear and island ohmic contacts 161, 162, 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities. ) Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151. The island resistive contact member 162 is positioned over the island semiconductor 152.

Side surfaces of the semiconductors 151 and 152 and the ohmic contacts 161, 162 and 165 are also inclined and have an inclination angle of 30 to 80 degrees.

A plurality of data lines 171, a plurality of output electrodes 175, and a plurality of storage capacitor conductors are formed on the ohmic contacts 161, 162, and 165 and the gate insulating layer 140. 177 and a plurality of connection signal lines 172, 172a to 172c.

Referring to FIG. 10, the data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the output electrode 175 form the input electrode 173. The pair of input electrode 173 and the output electrode 175 are separated from each other and positioned opposite to the control electrode 124.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

Referring to FIG. 6, the connection signal line 172a is positioned between the gate-off voltage line 122a and the first clock signal line 122b and is plurally oriented in a horizontal direction toward each stage from a stem and a stem extending in a vertical direction. Has branches. Each of the connection signal lines 172b and 172c is positioned between the first clock signal line 122b and the second clock signal line 122c, and is connected to a vertical portion extending at the longitudinal direction and at its end, and is disposed in the horizontal direction toward each stage. Includes a plurality of horizontal sections.

Referring to FIG. 8, the connection signal line 172 transmits a signal in the gate driver, and portions disposed on the island semiconductor 152 and the island resistive contact member 162 serve as input and output electrodes of the thin film transistor. Portions on the thin film transistor have a pod shape to increase the driving current of the transistor.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are made of a refractory metal such as molybdenum-based metal, chromium, tantalum, or titanium. It may have a multilayer film structure including a lower film having good contact characteristics. The end portion 179 of each data line 171 is extended in width for connection with another layer or an external device.

The side of the data line 171, the output electrode 175, the connection signal lines 172, 172a to 172c, and the conductor 177 for the storage capacitor are also inclined with respect to the surface of the substrate 110, and the inclination angle thereof is about 30 degrees. -80 ° range.

The ohmic contacts 161, 162, and 165 exist only between the semiconductors 151 and 152 below and the data line 171, the connection signal line 172, and the output electrode 175 thereon, and lower the contact resistance. Play a role. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion where the gate line 121 meets, thereby preventing disconnection of the data line 171. The island type semiconductor 152 is also positioned at a portion that intersects the driving signal lines 122, 122a through 122d and the connection signal lines 172, 172a through 172c to prevent disconnection of the connection signal lines 172, 172a through 172c.

The planarization characteristics are excellent and photosensitivity is formed on the data line 171, the output electrode 175, the connection signal lines 172, 172a to 172c, and the conductive capacitor 177 for the storage capacitor and the exposed semiconductor 151. Organic material having a low dielectric constant insulating material having a dielectric constant of 4.0 or less, such as a-Si: C: O, a-Si: O: F, which is formed by plasma enhanced chemical vapor deposition (PECVD), or an inorganic material. A passivation layer 180 made of silicon nitride is formed. Alternatively, the passivation layer 180 may be formed of a double layer of organic material and silicon nitride.

The passivation layer 180 has a plurality of contacts exposing the end portion 179 of the data line 171, the output electrode 175, the conductor 177 for the storage capacitor, and the end portions of the connection signal lines 172, 172a ˜ 172c, respectively. Contact holes 182, 185, 187, and 188 are formed, and a plurality of contact holes 189 are formed to expose the driving signal lines 122, 122a through 122d together with the gate insulating layer 140.

A plurality of pixel electrodes 190, a plurality of contact assistants 82, and a connection assistant 88 formed of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the output electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the output electrode 175 and to receive the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied, thereby creating a liquid crystal layer 3 between the two electrodes 190 and 270. Rearrange the liquid crystal molecules.

In addition, as described above, the pixel electrode 190 and the common electrode 270 form a liquid crystal capacitor to maintain an applied voltage even after the thin film transistor is turned off, and another capacitor connected in parallel with the liquid crystal capacitor to enhance the voltage holding capability. This is called the "storage electrode". The storage capacitor is formed by the superposition of the pixel electrode 190 and the neighboring gate line 121 (which is called a “previous gate line”), and the like. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer. Alternatively, the storage capacitor can be made by overlapping the storage electrode and the pixel electrode 190 provided separately.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary member 82 is connected to the end portion 179 of the data line through the contact hole 182. The contact assisting member 82 is not essential to serve to protect adhesiveness between the end portion 179 of the data line 171 and an external device and to protect them, and application thereof is optional.

The connection auxiliary member 88 is connected to the driving signal lines 122a to 122c and the connection signal lines 172a to 172c through the contact holes 188 and 189 to receive various signals from the driving signal lines 122a to 122c to receive the connection signal lines ( 172a through 172c). The connection auxiliary member 88 has a large area and is connected to one signal line through several contact holes. The reason why the connecting auxiliary member 88 is left large without dividing is because the connecting auxiliary member 88 is transparent and allows light to pass. This is because, if a plurality of contact holes are made and connected, the possibility of disconnection of the connection auxiliary member 88 is reduced by that much.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistant 82 may be made of a material different from the pixel electrode 190, in particular, ITO or IZO.

Unlike the above-described example, the driving signal lines 122 and 122a to 122d may be the same layer as the data line 171, and the connection signal lines 172 and 172a to 172c may be the same layer as the gate line 121. You can make them in several ways.

As described above, the openings are provided in the driving signal lines SL1 to SL3, so that the light provided from the rear surface of the thin film transistor array panel 100 penetrates the openings and easily reaches the photocurable sealant 350 so that the sealant 350 is closed. Allow to cure stably. As a result, the bonding force between the thin film transistor array panel 100 and the common electrode display panel 200 is increased, the corrosion caused by moisture introduced from the outside is prevented, and the driving failure due to the malfunction of the gate driver 400 is reduced.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

100: thin film transistor array panel 110: first substrate
500: data driver 400: gate driver
200: common electrode display panel 210: second substrate
270: common electrode 300: display panel
330: liquid crystal layer 350: sealant
600: display device

Claims (24)

A substrate including a display region, a seal line region surrounding the display region, and a peripheral region positioned between the display region and the seal line region, on which a gate line, a data line, a pixel electrode, and a thin film transistor are formed, and
A gate driver formed on the substrate, the wiring driver receiving a signal from the outside and a circuit driver configured to output a gate signal to the gate line in response to a signal from the wiring unit;
The wiring portion includes a signal line having an opening portion, is adjacent to the circuit portion, and is disposed only within the seal line region.
Thin film transistor array panel. In claim 1,
A line width of a portion of the signal line defining the opening is 100 μm or less. In claim 1,
The signal line includes a first conductive layer including aluminum, an aluminum alloy, or silver or a silver alloy, and a second conductive layer including chromium, molybdenum, titanium, or tantalum. In claim 1,
And the signal line is formed of the same layer as the gate line or the data line. In claim 1,
The circuit portion includes a shift register consisting of a plurality of stages cascaded and in turn generating an output signal,
The wiring unit includes first to third signal lines which transmit first and second clock signals having a phase different from a power supply voltage to the shift register. In claim 5,
The first to third signal lines all have openings. In claim 5 or 6,
And a fourth signal line configured to transfer an initialization signal to the shift register. In claim 7,
And the first to fourth signal lines are arranged in sequence from a position far to a position close to the shift register. 9. The method of claim 8,
The wiring unit may further include a plurality of connection lines connecting at least one of the first to fourth signal lines and the shift register. In claim 9,
The connection line is a thin film transistor array panel consisting of a layer different from the signal line. 11. The method of claim 10,
And the connection line and the signal line are connected through a connection auxiliary member. In claim 11,
The connection auxiliary member is transparent and is connected to the connection line and the signal line through a plurality of contact holes. In claim 1,
The circuit portion includes a plurality of transistors, wherein at least one of the plurality of transistors located in or adjacent to the seal line region is formed of a plurality of sub-transistors. In claim 13,
The thin film transistor array panel of which a gap between the sub transistors is 100 μm or less. In claim 1,
And the wiring portion overlapping the seal line region. In claim 1,
The wiring portion includes a plurality of signal lines located outside the circuit portion,
And a signal line positioned furthest from the circuit portion among the plurality of signal lines includes an opening, and a signal line positioned nearest to the circuit portion does not include an opening. A substrate including a display region, a seal line region surrounding the display region, and a peripheral region positioned between the display region and the seal line region, on which a gate line, a data line, a pixel electrode, and a thin film transistor are formed, and
A gate driver formed on the substrate, the wiring driver receiving a signal from the outside and a circuit driver configured to output a gate signal to the gate line in response to a signal from the wiring unit;
The wiring portion includes a ladder-shaped signal line,
The gate driver may be disposed in the seal line region and the peripheral region, and the circuit unit may include a plurality of transistors, and at least one of the plurality of transistors positioned in the seal line region may include a plurality of sub transistors spaced apart from each other.
Thin film transistor array panel. The method of claim 17,
The ladder-shaped signal line may include a plurality of first portions extending in a first direction and a plurality of second portions connecting the first portions. The method of claim 18,
And a width and a spacing between the first portions of the signal lines are about 20 to 30 μm. A substrate including a display region, a seal line region surrounding the display region, and a peripheral region positioned between the display region and the seal line region, on which a gate line, a data line, a pixel electrode, and a thin film transistor are formed, and
A gate driver formed on the substrate, the wiring driver receiving a signal from the outside and a circuit driver configured to output a gate signal to the gate line in response to a signal from the wiring unit;
The gate driver is located in the seal line region and the peripheral region,
The circuit part includes a plurality of transistors, and at least one of the plurality of transistors positioned in the seal line region includes a plurality of sub transistors spaced apart from each other.
Thin film transistor array panel. 20. The method of claim 20,
The thin film transistor array panel of which a gap between the sub transistors is 100 μm or less. A first substrate including a display region, a seal line region surrounding the display region, and a peripheral region positioned between the display region and the seal line region, the first substrate having a plurality of gate lines and a plurality of data lines, and the first substrate A second substrate facing the first substrate and a coupling member interposed between the first substrate and the second substrate to couple the first and second substrates to display an image in response to a data signal and a gate signal. Display panel,
A data driver for outputting the data signals to the plurality of data lines, and
A gate driver provided on the first substrate, the wiring unit configured to receive a plurality of signals from the outside and a circuit unit configured to output the gate signals to the plurality of gate lines in response to the external signals;
The wiring portion includes a signal line overlapping the coupling member and having an opening portion;
The gate driver is located in the seal line region and the peripheral region,
The circuit portion includes a plurality of transistors, and at least one of the plurality of transistors positioned in the seal line region includes a plurality of sub transistors spaced apart from each other.
Display device. The method of claim 22,
The coupling member includes a photocurable material. Forming a gate driving circuit including a wiring part including at least one signal line having an opening on the first substrate and a circuit part generating a gate signal according to a signal from the wiring part;
Forming a light shielding film on the second substrate,
Applying a sealant on the first or second substrate,
Dropping liquid crystal onto the first or second substrate,
Aligning the first substrate with the second substrate, and
Irradiating light to the sealant through a gap between the opening of the first substrate and the sub transistor;
The first substrate may include a display area, a seal line area surrounding the display area, and a peripheral area positioned between the display area and the seal line area.
The gate driving circuit is positioned in the seal line region and the peripheral region,
And the circuit unit includes a plurality of transistors, and at least one of the plurality of transistors positioned in the seal line region comprises a plurality of sub-transistors spaced apart from each other.

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