KR20100104112A - Circuit board used for semiconductor package, method thereof and semiconductor package using the same - Google Patents

Abstract

PURPOSE: A circuit board for a semiconductor package, a manufacturing method thereof, and the semiconductor package using the same are provided to simplify a manufacturing process by forming a preset pattern on an insulation thin film. CONSTITUTION: A circuit board(110) for a semiconductor package(101) includes an insulation thin film(111) and a plurality of via lines. The via lines pass through the insulation thin film and are made of conductive materials. The insulation thin film is made of photosensitive materials.

Description

 Circuit board for semiconductor package, manufacturing method thereof and semiconductor package using same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuit boards used in the manufacture of semiconductor packages, and more particularly to circuit boards for semiconductor packages used in place of leadframes.

In order to manufacture a semiconductor package, a lead frame is widely used as an intermediate device for mounting a semiconductor chip and electrically connecting the semiconductor chip to an external device. Semiconductor chips process a wide variety of electrical signals. In order to process such a plurality of electrical signals, the leadframe must have a large number of leads or lands.

For example, leadframes for quad flat non-lead (QFN) packages have multi-rows for the transmission of multiple electrical signals. Multirow refers to implementing second row lands in a row immediately after the first row lands around an existing pad. However, this method of forming a tie-bar, which processes the lands of each row when there are more than three rows, forces the sawing in the semiconductor package manufacturing process to connect the lands connected to each other. You need a breaking process. For example, in the current dual-row QFN package, in order to saw one unit, a sawing process of the unit and the unit, and a sawing process of the first row and the second row in one unit Additionally needed.

As described above, in order to use the lead frame in the semiconductor package, a number of processes are required.

It is an object of the present invention to provide a circuit board for a semiconductor package and a method of manufacturing the same, which form a circuit by plating on a preformed pattern to simplify the manufacturing process.

Another object of the present invention is to provide a method of manufacturing a semiconductor package using the circuit board.

The present invention to achieve the above object,

Insulating thin film; And a plurality of via lines formed vertically through the insulating thin film and formed of a conductive material.

In order to achieve the above object, the present invention also provides

(a) disposing an insulating thin film on the conductive substrate;

(b) forming a plurality of via holes vertically penetrating the insulating thin film;

(c) filling the plurality of via holes with the conductive material from the conductive substrate by an electroplating method to form a plurality of via lines; And

(d) providing a method of manufacturing a circuit board for a semiconductor package comprising separating the conductive substrate from the insulating thin film.

In order to achieve the above another object, the present invention,

(a) disposing an insulating thin film on the conductive substrate; (b) forming a plurality of via holes vertically penetrating the insulating thin film; (c) filling the plurality of via holes with the conductive material from the conductive substrate by an electroplating method to form a plurality of via lines; (d) disposing the semiconductor chip on the insulating thin film and electrically connecting the semiconductor chip to the plurality of via holes; (e) a molding step of sealing a plurality of via lines formed on an upper surface of the semiconductor chip and the insulating thin film; And (g) separating the conductive substrate from the insulating thin film.

According to the present invention, since a predetermined pattern is formed on an insulating thin film and a circuit is formed by plating without using a lead frame as a circuit board for a semiconductor package, a circuit board for a semiconductor package having a plurality of electrical input / output pads of various forms; The manufacturing process of the semiconductor package using this becomes very simple.

As a result, the production cost of the semiconductor package is reduced, the productivity is improved, and the quality is good.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a cross-sectional view of a semiconductor package according to the present invention. Referring to FIG. 1, the semiconductor package 101 includes a semiconductor chip 141 bonded onto the circuit board 110. The semiconductor package 101 is preferably applied to a package without a lead, such as a quad flat non-lead (QFN) package.

The circuit board 110 serves as a substrate that supports and supports the semiconductor package 101. The circuit board 110 may include an insulating thin film 111, and the insulating thin film 111 may be formed of a material having adhesiveness, insulating property, and thickness. The insulating thin film 111 is preferably composed of a photosensitive material having all of the above properties, such as a dry film resist. As such, as the thickness of the circuit boards 110 and 111 becomes thinner, the overall thickness of the semiconductor package 101 becomes thinner.

The photosensitive thin film 111 is formed with a plurality of via lines 121 penetrating vertically between the top and bottom surfaces. The plurality of via lines 121 is made of a conductive material, for example, copper. Therefore, the electrical signal applied from the semiconductor chip 141 to the upper portions of the via lines 121 is transmitted to the external device (not shown) contacting the lower portions of the via lines 121 through the via lines 121. The electrical signals applied to the lower portions of the via lines 121 from the external device are transmitted to the semiconductor chip 141 through the via lines 121.

The semiconductor package 101 may be flip-chip bonded to an external substrate (not shown) through the plurality of via lines 121 exposed on the bottom surface of the insulating thin film 111.

The semiconductor package 101 can secure a large number of via lines 121 serving as an input / output terminal by using the circuit board 110 as a substrate. Therefore, no matter how many electric signals are inputted and outputted to the semiconductor chip 141, the semiconductor package 101 can accommodate all of these signals.

Both ends of the plurality of via lines 121, that is, upper and lower ends of the via lines 121 are plated with a specific metal material 131. As an example of the plating treatment, PPF (Pre Plated Frame) plating may be applied. PPF plating generally refers to forming a sequential plating layer of Ni / Pd and plating additional functional plating layers Au, Ag, Pd, and their alloys before molding a semiconductor package. By applying the PPF plating, the diffusion preventing effect of the via lines 121 is increased to improve the reliability of the semiconductor package 101.

The semiconductor chip 141 is bonded to the circuit board 110 by the adhesive material 145 or disposed on the circuit board 110. The semiconductor chip 141 includes a plurality of electrode pads (not shown). The plurality of electrode pads and the plurality of via lines 121 are connected to each other by connecting portions 151, for example, wires. Therefore, an electrical signal output from the semiconductor chip 141 is transmitted to the upper ends of the via lines 121 through the connecting portions 151, and an electrical signal applied to the lower ends of the via lines 121 from the outside is connected to the connecting portions. The semiconductor chip 141 is transferred to the semiconductor chip 141 through 151.

The plurality of via lines 121 formed on the upper surface of the semiconductor chip 141, the connecting portions 151, and the insulating thin film 111 are sealed by the molding resin 161 to be protected from the external environment.

In another embodiment, a groove (not shown) may be formed in a portion of the insulating thin film 111 on which the semiconductor chip 141 is disposed, and the semiconductor chip 141 may be mounted in the groove. As such, by forming a groove in the insulating thin film 111 and attaching the semiconductor chip 141 to the groove, the height of the semiconductor chip 141 protruding from the insulating thin film 111 is lowered. Therefore, the step between the semiconductor chip 141 and the via lines 121 is lowered to facilitate bonding of the connection parts 151. In addition, the overall thickness of the semiconductor package 101 also becomes thin.

In another embodiment, a via hole (not shown) is formed in a portion of the insulating thin film 111 on which the semiconductor chip 141 is disposed, and a thin layer is formed below the via hole by using a conductive material such as copper. Form a plate (not shown). The semiconductor chip 141 is adhered to the thin plate. As such, by forming a hole in the insulating thin film 111 and adhering the semiconductor chip 141 on the conductive plate formed under the hole, the conductive plate serves as a heat sink and a ground plate. Therefore, the heat generated from the semiconductor chip 141 is quickly dissipated to the outside through the conductive plate, thereby preventing the semiconductor chip 141 from malfunctioning due to heat. In addition, since the step between the semiconductor chip 141 and the via lines 121 is lowered, not only the connection of the connecting portions 151 is easy, but the overall thickness of the semiconductor package 101 is also thinned.

FIG. 2 shows an embodiment of the via line shown in FIG. 1. Referring to FIG. 2, the via line 121 is formed of a plating layer of two or more metals. The via line 121 is formed of, for example, tin (Sn) 121a, copper (Cu) 121b, nickel (Ni) 121c, lead (Pd) 121d, and gold (Au) 121e from the bottom surface thereof. It may be composed of a plating layer sequentially stacked. The thickness of the tin (121a), copper (121b), nickel (121c), lead (121d), and gold (121e), the type of plating layer, and the order of lamination depend on the characteristics of the product using the circuit board 110 and the reliability conditions. Subject to change.

In this way, by forming the via line 121 as a multilayer plating layer, the connecting force to which the via line 121 is connected to an external device, for example, an external circuit board, which is in contact with the lower portion of the semiconductor package 101 is improved.

The via line 121 is made of copper in addition to the multilayer plating layer illustrated in FIG. 2, and the via line 121 is plated on at least one surface of one or more functional plating layers with respect to a surface exposed to the outside of the via line 121. ) And the connection between the external device can also be improved.

In this embodiment, it is preferable to first form a functional plating on the electrical connection between the semiconductor package and the external substrate as a portion exposed after the conductive substrate is first removed after the via hole is formed. It is preferable to form the soldering property which is generally applied to the surface mounting of a semiconductor package like an alloy. In addition, the plating layer may be sequentially formed, and the uppermost surface of the plating layer may serve as a pad for electrical connection with the semiconductor chip, for example, one of gold (Au), silver (Ag), and palladium (Pd). It is preferable to form one of the alloys in the uppermost layer. The alloy typically includes a gold-silver alloy, a gold-palladium alloy, and the like, and thus, in the finished semiconductor package, the inner and outer sides of the via line form a functional plating layer most suitable for each part, thereby assembling and mounting the semiconductor package. Excellent effect.

In the case where the via line is formed by the sequential functional plating, the conductive substrate (105 in FIG. 4) may be removed after the molding process is completed in the semiconductor package manufacturing process. In this case, the circuit board for the semiconductor device ( The thickness of 110 is so thin that it is possible to maintain a predetermined thickness that is easy to move between processes .

3 to 8 are cross-sectional views sequentially illustrating a method of manufacturing a circuit board of a semiconductor package according to an embodiment of the present invention, and FIGS. 9 and 10 show a method of manufacturing a semiconductor package using the circuit board.

Referring to FIG. 3, a conductive substrate 105 is prepared. As the conductive substrate 105, it is preferable to prepare a substrate made of copper. This is because a substrate made of copper has an advantage of good conductivity and low cost.

Referring to FIG. 4, an insulating thin film 111, which is adhesive, insulating, and thin, is adhered onto the conductive substrate 105, for example, a photosensitive material such as a dry film resist.

Referring to FIG. 5, a masking process, an exposure process, and a developing process are performed on the insulating thin film 111. Specifically, a mask (not shown) in which a specific pattern is formed is manufactured (masking process). After aligning the mask on the insulating thin film 111, ultraviolet rays are irradiated from above the mask (exposure step). Then, ultraviolet rays reach the insulating thin film 111 through the mask. At this time, the portion of the insulating thin film 111 irradiated with ultraviolet rays is cured, and the portion not irradiated with ultraviolet rays is maintained in its original state. Subsequently, the insulating thin film 111 is immersed in a developer or the developer is sprayed on the insulating thin film 111. Then, all the unhardened part of the insulating thin film 111 is removed (development process).

Accordingly, as shown in FIG. 5, a plurality of via holes 171 having a specific pattern and penetrating the insulating thin film 111 are formed.

A laser beam 217 may be used as described with reference to FIG. 12 instead of the masking, exposing and developing processes to form the plurality of via holes.

Referring to FIG. 6, a plurality of via holes 171 of FIG. 5 are filled with a conductive material to form a plurality of via lines 121 formed in the insulating thin film 111. In order to form the plurality of via lines 121, a material constituting the conductive substrate 105 by applying electricity to the conductive substrate 105 fills the plurality of via holes (171 of FIG. 5) to form a plurality of via lines. The electroplating method of forming the field 121 can be used.

Referring to FIG. 7, the conductive substrate (105 in FIG. 6) is separated from the insulating thin film 111. Various methods may be applied to separate the conductive substrate (105 in FIG. 6) from the insulating thin film 111. For example, when heat is applied to the conductive substrate (105 in FIG. 6), the adhesive force between the conductive substrate (105 in FIG. 6) and the insulating thin film 111 is weakened, so that the conductive substrate (105 in FIG. 6) is removed from the insulating thin film 111. Can be easily separated.

Referring to FIG. 8, upper and lower ends of the via lines 121, that is, both ends, are plated with a specific metal material 131. Thus, the circuit board 110 is completed. By plating both ends of the via lines 121, the both ends of the via lines 121 may be prevented from being corroded or spreading. As an example of the plating treatment, PPF plating may be applied. In other words, both ends of the via lines may be formed of, for example, Ni / Pd / Au or some alloy thereof.

Referring to FIG. 9, a die attach film, which is a kind of adhesive material 145, is attached on the insulating thin film 111, and the semiconductor chip 141 is mounted on the die attach film 145. The adhesive material 145 may be made of an insulating material or may be made of an electrically conductive material. The semiconductor chip 141 is firmly adhered to the insulating thin film 111 by the adhesive material 145.

Referring to FIG. 10, the plurality of electrode pads and the plurality of via lines 121 formed on the upper surface of the semiconductor chip 141 are bonded to the connection parts 151, for example, the wires 151. Thus, the semiconductor chip 141 is electrically connected to the plurality of via lines 121. In this case, when bumps for connection are formed in place of the electrode pads in the semiconductor chip 141, the bumps of the semiconductor chip 141 are directly adhered to the plurality of via lines 121, thereby the semiconductor chip 141. And the plurality of via lines 121 may be electrically connected to each other.

In this state, the plurality of via lines 121 exposed on the semiconductor chip 141, the plurality of connecting portions 151, and the upper surface of the insulating thin film 111 are sealed with a molding resin (161 of FIG. 1). Accordingly, the semiconductor chip 141, the plurality of connection parts 151, and the plurality of via lines 121 exposed on the upper surface of the insulating thin film 111 are safely protected from the external environment. After the sealing process is completed, the semiconductor package 101 as shown in FIG. 1 is completed.

11 to 17 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention, and FIGS. 18 to 21 show a method of manufacturing a semiconductor package using the circuit board. This embodiment corresponds to an embodiment in which the material of the insulating thin film 211 in which the via line is formed uses an insulating thin film material which can easily form the via hole without using a photosensitive material.

Referring to FIG. 11, an insulating thin film 211 is prepared. The thin film 211 may be a thermoplastic or thermosetting material having an adhesive force on one surface thereof, and may have an insulating property and a thin thickness. The thin film 211 is preferably composed of a photosensitive material such as a dry film resist having all these characteristics.

Referring to FIG. 12, a laser device 215 is disposed on the thin film 211. The laser device 215 irradiates the laser beam 217. Since a plurality of holes 225 of FIG. 13 should be formed on the thin film 211, when there is only one laser device 215, the laser beam 217 is irradiated while moving the laser device 215 horizontally. At this time, the laser device 215 irradiates the laser beam 217 according to a specific pattern, and accordingly, a plurality of via holes 225 of FIG. 13 are formed in the thin film 211.

 Referring to FIG. 13, a plurality of via holes 225 are formed in the thin film 211 by the laser device shown in FIG. 12. In order to form the plurality of via holes 225 in the thin film 211, a physical method, that is, a punching operation, may be performed in addition to the laser device (215 of FIG. 12) according to the shape of the semiconductor package or the type or number of input / output pads. have.

Referring to FIG. 14, the conductive substrate 205 is attached to the lower portion of the photosensitive thin film 211. As the conductive substrate 205, it is preferable to prepare a metal substrate having good conductivity such as copper or aluminum.

Referring to FIG. 15, the plurality of via holes 225 of FIG. 14 are filled with a conductive material to form a plurality of via lines 221. In order to form the plurality of via lines 221, a material forming the conductive substrate 205 by applying electricity to the conductive substrate 205 may fill the plurality of via holes (225 of FIG. 14) to form the plurality of via lines. The electroplating method which forms 221 can be used.

Referring to FIG. 16, the conductive substrate 205 of FIG. 15 is separated from the thin film 211. Various methods may be applied to separate the thin film 211 and the conductive substrate 205 of FIG. 15. For example, when heat is applied to the conductive substrate 205 of FIG. 15, the adhesive force between the conductive substrate 205 of FIG. 15 and the thin film 211 is weakened, and thus the conductive substrate 205 of FIG. 15 and the thin film 211. Can be easily separated.

Referring to FIG. 17, both ends of the via lines 221 are plated with a specific metal material 231. Thus, the circuit board 210 is completed. By plating both ends of the via lines 221, it is possible to prevent both ends of the via lines 221 from being corroded or spreading. As an example of the plating treatment, PPF plating may be applied. That is, the plating layer 231 may be formed at both ends of the via lines 221 using a Ni / Pd / Au three-layer alloy or some alloy thereof.

Referring to FIG. 18, the adhesive material 245 is adhered on the insulating thin film 211. It is preferable that the adhesive material 245 be equipped with a die attach film. The adhesive material 245 may be made of an insulating material or may be made of an electrically conductive material.

Referring to FIG. 19, a semiconductor chip 241 is mounted on an adhesive 245. The semiconductor chip 241 is firmly adhered to the insulating thin film 211 by the adhesive material 245.

Referring to FIG. 20, the plurality of electrode pads and the plurality of via lines 221 formed on the upper surface of the semiconductor chip 241 are bonded to the connection portions 251, for example, wires. Thus, the semiconductor chip 241 is electrically connected to the plurality of via lines 221. In this case, when the bumps for the connection are formed in the semiconductor chip 241 instead of the electrode pads, the bumps of the semiconductor chip 241 are directly adhered to the plurality of via lines 221 so that the semiconductor chip 241 and the plurality of bumps are connected. The via lines 251 may be electrically connected to each other.

Referring to FIG. 21, a plurality of via lines 221 exposed on the upper surface of the semiconductor chip 241, the plurality of connection parts 251, and the insulating thin film 211 may be sealed with a molding resin 261 to seal the semiconductor package ( 201) is completed. As such, the plurality of via lines 221 exposed on the semiconductor chip 241, the plurality of connection parts 251, the adhesive material 245, and the upper surface of the insulating thin film 211 may be sealed in the molding resin 261 to be external. Safe from the environment

Referring to FIG. 22, a plurality of semiconductor packages 101 and 201 may be simultaneously manufactured in one frame 301. In this case, by sawing along scribe lines 311 between the plurality of semiconductor packages 101 and 201, the plurality of semiconductor packages 101 and 201 are separately separated.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a cross-sectional view of a semiconductor package according to the present invention.

FIG. 2 shows an embodiment of the via line shown in FIG. 1.

3 to 10 are cross-sectional views sequentially illustrating a circuit board for a semiconductor package and a method of manufacturing the semiconductor package according to an embodiment of the present invention.

11 to 21 are cross-sectional views sequentially illustrating a circuit board for a semiconductor package and a method of manufacturing the semiconductor package according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

101/201; Semiconductor package, 105/205; Conductive substrate

110/210; Circuit board

111/211; Insulating thin films, 121/221; Multiple via lines

131/231; Plating layer 141/241; Semiconductor chip

145/245; Adhesive, 151/251; A plurality of bonding wires

161/261; Molding resin, 171/271; Multiple Beer Holes

Claims (16)

Insulating thin film; And And a plurality of via lines formed through the insulating thin film and formed of a conductive material. The circuit board of claim 1, wherein the insulating thin film is a photosensitive material. The semiconductor package circuit board of claim 1, wherein the plurality of via lines are filled by plating. The method of claim 3, wherein the plating is tin (Sn), copper (Cu), nickel (Ni), palladium (Pd) and gold (Au) or an alloy thereof, characterized in that the plating layer sequentially laminated from the lower surface Circuit board for semiconductor package. The semiconductor package circuit board of claim 1, wherein a semiconductor chip is disposed on the insulating thin film, and a portion of the plurality of via lines is formed at a portion where the semiconductor chip is disposed. 4. The circuit board of claim 3, wherein the plating is filled with copper (Cu) and at least one plating layer is formed on an outer side of the copper plating layer. The method of claim 1, A semiconductor chip disposed on the insulating thin film; A plurality of connections electrically connecting the semiconductor chip and the plurality of via lines; And And a molding resin sealing the plurality of via lines formed on the semiconductor chip, the plurality of connection parts, and the insulating thin film. (a) disposing an insulating thin film on the conductive substrate; (b) forming a plurality of via holes vertically penetrating the insulating thin film; (c) filling the plurality of via holes with the conductive material from the conductive substrate by an electroplating method to form a plurality of via lines; And and (d) separating the conductive substrate from the insulating thin film. The method of claim 8, wherein the insulating thin film is made of a photosensitive material. The method of claim 8, wherein the plurality of via holes are formed through a laser beam. The method of claim 8, further comprising forming one or more plating layers on some of the ends of each of the plurality of via lines after the step (d). The method of claim 8, wherein after step (d) (e) disposing a semiconductor chip on the insulating thin film, and electrically connecting the semiconductor chip with the plurality of via holes. (a) disposing an insulating thin film on the conductive substrate; (b) forming a plurality of via holes penetrating the insulating thin film; (c) filling the plurality of via holes with the conductive material from the conductive substrate by an electroplating method to form a plurality of via lines; (d) disposing a semiconductor chip on the insulating thin film, and electrically connecting the semiconductor chip with the plurality of via holes; (e) a molding step of sealing a plurality of via lines formed on an upper surface of the semiconductor chip and the insulating thin film; And (g) separating the conductive substrate from the insulating thin film. The method of manufacturing a semiconductor package according to claim 13, wherein the insulating thin film is made of a photosensitive material. The method of claim 13, wherein the plurality of via holes are formed through a laser beam. The method of claim 13, wherein the step (C) comprises tin (Sn), copper (Cu), nickel (Ni), palladium (Pd), and gold (Au) or an alloy thereof in the plurality of via holes. A method of manufacturing a semiconductor package, characterized in that the step of sequentially forming a plating layer.

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