KR20090130759A - Method of manufacturing transistor comprising omega type gate - Google Patents

Abstract

PURPOSE: A method of manufacturing transistor comprising a omega type gate is provided to reduce a gate length between a drain and a source by preventing a step height between a channel and the source and the drain. CONSTITUTION: In a device, an active layer(42) is formed on a substrate(40). The active layer is covered with insulating layers(44,46,50). An opening(52) exceeding the limit of the lithography is formed the insulating layer. A part of the substrate and the active layer are exposed by opening. An undercut is formed under the exposed active layer. The gate insulating layer is formed on the active layer which is exposed through the undercut and the opening. The gate electrode is formed on the gate insulating layer. The opening is formed as a multi-stage.

Description

Method of manufacturing transistor comprising omega type gate

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an omega gate transistor.

One way to increase the integration of semiconductor devices, such as semiconductor memory devices, is to reduce the size of transistors. However, in order to reduce the size of the transistor, it is inevitable to reduce the distance between the source and the drain. When the distance between the source and the drain is reduced, a gate field is applied to the channel. Short channel effect appears. This short channel effect makes it difficult to control the channel through the gate, in particular electrical degradation such as punch-through, drain-induced barrier lowering (DIBL), and threshold voltage roll-off. Appears.

This short channel effect is increased as the gate length between the source and drain becomes less than 65 nm, and as a result, switching operation, which is a basic function of the transistor, may be impossible.

In order to solve the short channel effect in the process of reducing the transistor size, various methods such as channel doping, ultra-shallow junction, and gate dielectric thinning have been introduced. However, as the gate length between the source and the drain becomes less than 65 nm, additional problems such as random doping problem or gate leakage occur.

Along with this problem, a transistor having a three-dimensional gate structure, that is, a three-dimensional transistor, is introduced to increase channel controllability per unit area as a method for solving a short channel effect.

Three-dimensional transistors include an omega gate transistor, a fin field effect transistor (FinFET), a double gate transistor, a tri-gate transistor, and a gate-all-around transistor. transistors).

Such three-dimensional transistors adjust the channel using a plurality of gates, thereby improving channel control capability.

Among the three-dimensional transistors, the omega gate transistor has a structure in which the under cut is further provided under the gate body in the tree gate transistor, and the gate is extended in the under cut to expand the entire gate region. Accordingly, it is known that an omega gate transistor has a shorter channel effect and a higher drive current than a tree gate transistor. However, to ensure uniformity and reproducibility, it is necessary to set the manufacturing process more accurately.

In the omega gate transistor, the substrate is mainly a silicon on insulator (SOI) substrate. Currently known major manufacturing processes for omega gate transistors include body patterning, buried oxide over-etch and undercutting processes, and gate stack deposition, which define active regions. Process, gate patterning process, source / drain process, and the like.

In the case of an omega gate transistor fabricated by such a manufacturing process, a gate conductor used as a gate electrode, which is deposited in the gate stack deposition process in the gate patterning process, is patterned, and the problem is undercut formed under the gate body. The gate conductive layer deposited on is not patterned in the gate patterning process. Therefore, even after the gate patterning process, the gate conductive layer is present in the undercut outside the gate region. This often results in a short between the source and the drain.

In order to solve this problem, a two-step dry etching process using anisotropic dry etching and isotropic dry etching may be performed.

However, even when performing the two-step dry etching process, it is difficult to secure process reproducibility, and gate leakage may occur due to damage of the gate stack by dry etching. In addition, the dry etching results in a step in which the channel becomes higher than the source / drain, resulting in a large resistance, and thus the on-state current I _on of the omega gate transistor may be drastically reduced, and, above all, process uniformity. It can be difficult to secure.

The present invention can ensure uniformity or reproducibility, prevent damage of the gate while preventing the gate conductive layer from remaining in the undercut outside the gate area, and prevent the formation of a step between the channel and the source / drain. The present invention provides a method for manufacturing an omega gate transistor that can reduce the gate length between a drain and a drain.

The present invention provides a method for manufacturing an omega gate transistor, the method comprising: forming an active layer on a substrate, covering the active layer with an insulating layer, and forming an opening in the insulating layer, the active layer and a portion of the substrate exposed beyond a lithography limit. Forming an under cut under the exposed active layer, forming a gate insulating film in the opening and the active layer exposed through the under cut, and forming a gate electrode on the gate insulating film. A method of manufacturing a gate transistor is provided.

In this manufacturing method, the opening can be formed in a multi-step.

According to an embodiment of the present disclosure, the forming of the opening may include forming an upper insulating layer on the insulating layer, exposing a portion of the insulating layer to the upper insulating layer, and forming a limit width in the lithography. The method may further include forming a first opening having a diameter, narrowing the diameter of the first opening, and etching the insulating layer exposed through the narrowed first opening.

In addition, after forming the opening, a spacer may be formed on the sidewall of the opening and the side surface of the active layer exposed through the opening before the undercut is formed. In this case, the spacer may be removed before the gate insulating layer is formed.

The forming of the gate electrode may further include forming a gate conductive layer filling the opening in which the gate insulating layer is formed, and patterning the gate conductive layer on the insulating layer.

According to another embodiment of the present invention, the gate insulating film is formed on the insulating layer to cover the sidewall of the opening and the portion exposed through the opening,

After forming a gate conductive layer on the gate insulating film,

The gate electrode may be formed by planarizing the gate conductive layer until the insulating layer is exposed.

According to another embodiment of the present invention, after the gate conductive layer is formed, and before the planarization,

Forming a second opening in the stack including the insulating layer, the gate conductive layer, and the gate insulating layer, the second opening exposing the active layer through the second opening on the stack; Forming an insulating film and forming a second gate conductive layer filling the second opening on the second gate insulating film,

The planarization may be performed from the second gate conductive layer until the insulating layer is exposed.

Narrowing the diameter of the first opening,

Depositing a spacer forming material layer on the upper insulating layer covering a sidewall of the first opening and covering a portion exposed through the first opening, and exposing the upper insulating layer and the insulating layer of the first opening. Anisotropically etching the spacer forming material layer may be further included.

Hereinafter, a method of manufacturing an omega gate transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

1 to 19 are cross-sectional views sequentially illustrating a method of manufacturing an omega gate transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the conductive layer 42, the first insulating layer 44, and the second insulating layer 46 are sequentially stacked on the substrate 40. The substrate 40 may be an insulating layer. In subsequent processes, the source, drain and channel regions are set in the conductive layer 42. The conductive layer 42 may be a doped silicon layer. The substrate 40 and the conductive layer 42 may constitute an SOI substrate. The lower conductive layer may be provided under the substrate 40. The first insulating layer 44 may be formed of a silicon oxide layer. In this case, the first insulating layer 44 may be formed to a thickness of 1000 kPa. The first insulating layer 44 may be formed of an insulating material other than silicon oxide. The second insulating layer 46 may be formed of an insulating material having a different etching selectivity from the first insulating layer 44. For example, the second insulating layer 46 may be formed of a silicon nitride layer. In this case, the second insulating layer 46 may be formed to a thickness of about 1000 GPa. The second insulating layer 46 may be formed of an insulating material other than silicon nitride, provided that the etching selectivity is different from that of the first insulating layer 44.

The mask M1 is formed on the second insulating layer 46. The mask M1 may be a photoresist film or a hard mask. The mask M1 is for defining an active region in the conductive layer 42 and includes first to third regions A1, A2, and A3. The first and second regions A1 and A2 have a width and an area larger than those of the third region A3. The third area A3 connects the first and second areas A1 and A2. One of the first and second regions A1 and A2 defines a source region of the omega gate transistor, and the other region defines a drain region. The third region A3 may define a channel region of the omega gate transistor.

After the mask M1 is formed, the second insulating layer 46, the first insulating layer 44, and the conductive layer 42 around the mask M1 are sequentially etched. Such etching may be performed until the substrate 40 is exposed. After etching, the mask M1 is removed. By etching, the pattern of the mask M1 is transferred to the second insulating layer 46, the first insulating layer 44, and the conductive layer 42 as it is, and after etching, the mask M1 is shown in FIG. 2. The conductive layer 42 and the first and second insulating layers 44 and 46 having the same pattern as () are formed.

Referring to FIG. 3, an interlayer insulating layer covering the conductive layer 42 having the same pattern as the mask M1 and the first and second insulating layers 44 and 46 on the substrate 40 exposed by the etching. Form 48. The top surface of the interlayer insulating layer 48 is planarized until the second insulating layer 46 is exposed. Such planarization can be carried out using, for example, chemical mechanical polishing (Chemicla Mechanical Polishing). The interlayer insulating layer 48 may be formed of a silicon oxide layer, for example, an SiO 2 layer. In this case, the interlayer insulating layer 48 may be formed by a high density plasma deposition method.

4 is a plan view of FIG. 3. 5A is a cross-sectional view of FIG. 4 taken in the direction of 5a-5a '. In addition, FIG. 5B shows a cross-sectional view of FIG. 4 in the 5b-5b 'direction.

5A and 5B show cross sections orthogonal to each other. Hereinafter, in each drawing, FIG. A shows a cross section cut in the same direction as FIG. 5A, and b shows a cross section cut in the same direction as FIG. 5B.

6A and 6B, a third insulating layer 50 is formed on the second insulating layer 46. The third insulating layer 50 may be formed of the same material layer as the second insulating layer 46. In this case, the third insulating layer 50 can be formed to a thickness of about 1200 kPa.

7A and 7B, a region 52 in which a portion of the second insulating layer 46 is exposed is formed in the third insulating layer 50. A portion of the second insulating layer 46 exposed through the region 52 of the third insulating layer 50 is spaced apart from the first and second regions A1 and A2 of the mask M1 of FIG. 1. It corresponds to a partial area of the three areas A2. Since the gate electrode is formed in the region 52 of the third insulating layer 50 in the subsequent process, when the source and the drain are connected by a conductive layer formed in the undercut under the channel in the process of forming the gate electrode, It does not occur. In other words, the short between the source and the drain can be blocked at source. The region 52 exposing a part of the second insulating layer 46 of the third insulating layer 50 may be a line-shaped hole.

8A and 8B, spacers 54 are formed on sidewalls of the region 52 of the third insulating layer 50. The spacer 54 may be formed by forming a spacer forming material layer on the surface of the third insulating layer 50 and then anisotropically etching the spacer forming material layer. In this case, the anisotropic etching may be performed until the interlayer insulating layer 48 is exposed. The anisotropic etching is performed under an etching condition having a high etching selectivity of the spacer forming material layer relative to the interlayer insulating layer 48. The anisotropic etching may be further performed by a given time even after the interlayer insulating layer 48 is exposed to complete formation of the spacer 54. In other words, there may be excessive etching in the anisotropic etching. The spacer forming material layer may be the same as the second insulating layer 46. By forming the spacer 54, the width of the region 52 of the third insulating layer 50 is narrowed. This also narrows the gate width to be formed in subsequent processes. Therefore, the length of the channel under the gate is also shortened. Since the thickness of the bottom of the spacer 54 is changed according to the deposition thickness of the spacer forming material layer, the width of the gate and the length of the channel may be adjusted by adjusting the deposition thickness of the spacer forming material layer. In addition, the spacer 54 forming process is a self alignment process. Therefore, when the width of the region 52 of the third insulating layer 50 is the limit that can be formed by photolithography, for example, the width of the region 52 of the third insulating layer 50 is the KrF light source. When the minimum width (e.g., 180 nm) that can be formed by a photolithography process using an exposure apparatus using a light emitting device is formed, the third insulating layer is formed by forming the spacers 54 in the region 52 of the third insulating layer 50. The width of the area 52 of the layer 50 will be narrower than the minimum width. In other words, by forming the spacer 54, the region 52 of the third insulating layer 50 may have a width beyond the limit of the photolithography process. This means that a gate having a width beyond the limits of the photolithography process may be formed, and a channel having a length that cannot be realized by the photolithography process may be formed.

Next, after the spacer 54 is formed, a portion of the interlayer insulating layer 48 is etched, as shown in FIGS. 8B and 9B. This etching is performed until the height of the top surface of the interlayer insulating layer 48 is the same level as the conductive layer 42. Such etching is performed on the second insulating layer 46, the third insulating layer 50, and the spacer 54 under etching conditions with high etching rate of the interlayer insulating layer 48.

Next, the second insulating layer 46 exposed through the open portion 52 in which the spacers 54 of the third insulating layer 50 are formed is etched. The second insulating layer 46, the third insulating layer 50, and the spacer 54 are made of the same material. Therefore, while the exposed portion of the second insulating layer 46 is etched, the third insulating layer 50 and the spacer 54 are also etched together. When the thickness of the third insulating layer 50 is thicker than the second insulating layer 46, a part of the third insulating layer 50 may remain even after the etching. The etching may be performed until the first insulating layer 44 is exposed. As a result of this etching, a region 56 in which the first insulating layer 44 is exposed is formed in the second insulating layer 46 as illustrated in FIG. 10A. The region 56 may be an open portion in the form of a line. Such etching may be anisotropic etching. Therefore, the shape of the region 52 in which the spacers 54 of the third insulating layer 50 are formed is transferred as it is to the region 56 formed in the second insulating layer 46. 10A and 10B show the results of the etching.

Next, referring to FIGS. 10A and 10B, the interlayer insulating layer 48 and the second insulating layer 46 of the circumference are formed using the second insulating layer 46 and the third insulating layer 50 remaining thereon as an etch mask. The first insulating layer 44 exposed through the region 56 formed in the etch is etched. The interlayer insulating layer 48 and the first insulating layer 44 may be the same material. Therefore, the etching may be performed on the second and third insulating layers 46 and 50 under etching conditions in which the etch rates of the interlayer insulating layer 48 and the first insulating layer 44 are high. Etching may be performed until the conductive layer 42 and the substrate 40 are exposed. The thickness of the interlayer insulating layer 48 remaining around the conductive layer 42 is similar to the thickness of the first insulating layer 44 by the etching performed previously. Therefore, the conductive layer 42 and the substrate 40 may be exposed at the same time in the etching. Accordingly, the upper surface of the conductive layer 42 may be prevented from being excessively etched in the etching, and as a result, a step in which the channel becomes high between the channel and the source / drain may be prevented.

11A and 11B, an open portion 58 in which the conductive layer 42 is exposed is formed on the first insulating layer 44, and the substrate (not shown) exists in the region 58. The interlayer insulating layer 48 formed on the 40 is removed. Therefore, a portion of the conductive layer 42 and a portion of the substrate 40 are exposed through the region 58 of the first insulating layer 44. The exposed portion of the conductive layer 42 is a part of the third region AA3 of the conductive layer 42 corresponding to the third region A3 of the mask M1 of FIG. 1. The first and second regions AA1 and AA2 of the conductive layer 42 correspond to the first and second regions A1 and A2 of the mask M1 of FIG. 1, respectively. The exposed portion of the conductive layer 42 is spaced apart from the first and second regions AA1 and AA2 to be used as source or drain regions. Therefore, even if the gate electrode material is deposited in the exposed region of the conductive layer 42 in a subsequent process, the gate electrode material cannot be connected to the source and drain regions. Therefore, the short between the source and drain regions can be prevented.

Next, referring to FIGS. 12A and 12B, spacers 60 are formed on sidewalls of a region 58 where the conductive layer 42 of the first insulating layer 44 is exposed. The spacer 60 is formed to completely cover the entire sidewall of the region 58. By forming the spacer 60 in this manner, it is possible to prevent the first insulating layer 44 from being exposed and etched in the wet etching process for subsequent undercut formation. Accordingly, the length of the channel may be prevented from changing in the wet etching process. The spacer 60 is also formed on the side surface of the conductive layer 42 exposed through the region 58. The spacer 60 can be formed in the same manner as when forming the spacer 54 shown in Fig. 8A. The spacer 60 may be formed of the same material as the second insulating layer 46.

Next, referring to FIGS. 13A and 13B, an undercut 64 is formed under the conductive layer 42 after the spacer 60 is formed. The portion close to the side of the underside of the conductive layer 42 is exposed through the undercut 64. The under cut 64 may be formed by wet etching the exposed substrate 40 through the region 58 formed in the first insulating layer 44. By adjusting the wet etch rate, the undercut 64 may be adjusted to a desired size. When the substrate 40 is silicon oxide, the wet etching may be performed by using diluted hydrofluoric acid as an etchant.

Next, after the wet etching, the third insulating layer 50, the second insulating layer 46, and the spacer 60 are wet-etched. When the third insulating layer 50, the second insulating layer 46, and the spacer 60 are silicon nitride, the wet etching may be performed using phosphoric acid as an etchant. 14A and 14B show the result after this wet etching.

15A and 15B, the gate insulating film may be formed on the entire surface of the conductive layer 42 exposed through the region 58 of the first insulating layer 44 and exposed through the undercut 64. 66). The gate insulating film 66 may be formed of a silicon oxide film. The gate insulating film 66 may also form a dielectric film having a high dielectric constant such as an HfO 2 film, an Al 2 O 3 film, a La 2 O 3 film, a ZrO 2 film, an HfSiO film, an HfSiON film, an HfLaO film, a LaAlO film, an SrTiO film, or the like. The gate insulating layer 66 may be formed by atomic layer deposition.

16A and 16B, a gate conductive layer 68 filling the region 58 is formed on the first insulating layer 44 and the interlayer insulating layer 48. The gate conductive layer 68 is used as a gate electrode after patterning. The gate conductive layer 68 may be a doped polysilicon layer. The gate conductive layer 68 may also be formed of a W layer, a TaN layer, an HfN layer, or a TiN layer. The gate conductive layer 68 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering.

After the gate conductive layer 68 is formed in this manner, the gate conductive layer 68 is patterned to form the gate electrode 68A as shown in FIGS. 17A and 17B. The gate electrode 68A is in the form of a line located between the source and drain regions.

17A and 17B, after forming the gate electrode 68A, the first insulating layer 44 formed on the conductive layer 42 is removed. The first insulating layer 44 may be removed by wet etching. Since the interlayer insulating layer 48 is the same material as the first insulating layer 44, the interlayer insulating layer 48 remaining on the substrate 40 may also be removed while the first insulating layer 44 is removed.

In this way, as shown in FIGS. 18A and 18B, the first and second regions AA1 and AA2 of the conductive layer 42 are exposed. 19 is a plan view of a result to which the first and second regions AA1 and AA2 are exposed. 18A is a cross-sectional view of FIG. 19 taken along the direction of 18A-18A '.

After the first and second regions AA1 and AA2 of the conductive layer 42 are exposed, a process of implanting ions into the first and second regions AA1 and AA2, a silicide forming process, and a contact process may be performed. Can be.

Meanwhile, according to another embodiment of the present invention, the gate insulating film and the gate electrode may be formed by applying a damascene process.

20A and 20B, the same steps as described above may be performed until the region 58 in which the conductive layer 42 is exposed and the undercut 64 are formed in the first insulating layer 44. have.

After forming the region 58 in the first insulating layer 44, the sidewalls of the region 58 are covered on the first insulating layer 44, and the upper portion of the conductive layer 42 exposed through the region 58 is exposed. A gate insulating layer 70 is formed to cover the surface and side surfaces and the exposed portion of the substrate 40 and to cover the bottom surface of the conductive layer 42 exposed through the undercut 64. The gate insulating layer 70 may be the same as the gate insulating layer 66 described above. A gate conductive layer 72 is formed on the gate insulating layer 70 to fill the region 58 of the first insulating layer 44. The gate conductive layer 72 may be the same as the gate conductive layer 68 described above. The gate conductive layer 72 is planarized. Planarization may be performed until the first insulating layer 44 is exposed. The planarization can be carried out using CMP.

21A and 21B, by the planarization, the gate insulating layer 70 and the gate conductive layer 72 are removed from the first insulating layer 44, and the gate conductive layer 72 is formed of the first insulating layer ( It exists only in the area 58 of 44. The gate conductive layer 72 existing only in the region 58 of the first insulating layer 44 is used as the gate electrode. The first insulating layer 44 is removed by the above-described wet etching method to expose the first and second regions AA1 and AA2 of the conductive layer 42. The subsequent process is as described above.

When using such a damascene process, since the gate electrode is formed self-aligned through the planarization process, a separate alignment process for gate patterning is not necessary. Thus, misalignment that may occur during gate patterning may be prevented.

The damascene process applied to form the gate electrode 72 may be applied to form a CMOS transistor, and FIGS. 23 to 26 show an example thereof.

23 to 26 show step by step a method of manufacturing a CMOS transistor to which the damascene process is applied. For convenience, only the cross section in which the conductive layer 42 is cut in the direction parallel to the conductive layer 42 is shown in FIGS. 23 to 26. Like reference numerals denote like elements.

Referring to FIG. 23, forming a region 58 in which the conductive layer 42 is exposed on the first insulating layer 44 and forming an undercut under the conductive layer 42 exposed through the region 58. Up to the step may be the same as described above.

A gate insulating layer 70 is formed on the first insulating layer 44 to cover the sidewall of the region 58 and to cover the conductive layer 42 exposed through the region 58. A gate conductive layer 72 filling the region 58 is formed on the gate insulating layer 70. Hereinafter, the gate insulating film 70 and the gate conductive layer 72 are referred to as a first gate insulating film and a first gate conductive layer, respectively. The first gate insulating film 70 may be formed of the above-described dielectric film having a high dielectric constant. The first gate conductive layer 72 is used as the gate electrode for the n-MOS transistor. The first gate conductive layer 72 may be formed of a W 2 N layer, a TaSiN layer, a (RE) TaN layer, or a WC layer.

Referring to FIG. 24, a region 74 in which the conductive layer 42 is exposed is formed in a laminate including the first insulating layer 44, the first gate insulating layer 70, and the first gate conductive layer 72. . The region 74 may be formed in the same manner as the region 58 formed in the first insulating layer 44. The stack including the first insulating layer 44, the first gate insulating layer 70, and the first gate conductive layer 72 in which the region 74 is formed includes the first insulating layer 44 in which the region 58 is formed. Corresponds to). Hereinafter, for convenience, the region 58 formed in the first insulating layer 44 is referred to as a first region, and the region 74 formed in the laminate is referred to as a second region. A second gate insulating layer 76 is formed on the second gate conductive layer 72 to cover sidewalls of the second region 74 and to cover the conductive layer 74 exposed through the second region 74. The second gate insulating layer 76 may be the same as the first gate insulating layer 70. A second gate conductive layer 78 filling the second region 74 is formed on the second gate insulating layer 76. The second gate conductive layer 78 is used as the gate electrode of the p-MOS transistor. The second gate conductive layer 78 may be formed of a TiAlN layer, a MoN layer, or a TaCN layer.

Next, the second gate conductive layer 78 is planarized. Planarization is performed until the first insulating layer 44 is exposed. Such planarization can be carried out using CMP. As a result of this planarization, as illustrated in FIG. 25, the first gate insulating layer 70, the first gate conductive layer 72, the second gate insulating layer 76, and the first gate insulating layer formed on the upper surface of the first insulating layer 44 are formed. The two gate conductive layer 78 is removed. After the planarization, the first gate conductive layer 72 exists only in the first region 58, and the second gate conductive layer 78 exists only in the second region 74. The first gate conductive layer 72 filling the first region 58 is a gate electrode of the n-MOS transistor. The second gate conductive layer 78 filling the second region 74 is a gate electrode of the p-MOS transistor.

Next, the first insulating layer 44 is removed by wet etching. 26 shows the result after removing the first insulating layer 44. After removing the first insulating layer 44, an ion implantation process may be performed to form a source and a drain for each of the transistor types in the conductive layer 42. Subsequently, a silicide process for lowering contact resistance and a contact formation process for source / drain contacts may be performed in a subsequent process.

In FIG. 26, reference numeral T1 denotes an n-MOS transistor region and T2 denotes a p-MOS transistor region.

As shown in FIGS. 23 to 25, the damascene process for forming the gate electrodes 72 and 78 has the following advantages as compared with the case of forming the gate electrode using dry etching.

In other words, when the gate conductive layer is patterned by dry etching to form the gate electrode, it is troublesome to tune the dry etching process every time according to the material used as the gate conductive layer. In the case of forming, since the gate conductive layer and the gate insulating film are planarized, it is not necessary to tune the process every time. In addition, when the damascene process is used, the gate electrode may be formed in a self-aligned method, thereby preventing alignment errors.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may use materials other than those described above for the components of the transistors introduced in the process of manufacturing the omega gate transistor.

In addition, there may be another method of forming an undercut in the above-described method of manufacturing an omega gate transistor.

For example, instead of forming the conductive layer 42 directly on the substrate 40 as shown in FIG. 27, the width between the conductive layer 42 and the substrate 40 is smaller than that of the conductive layer 42. The insulating layer 80 is formed. The insulating layer 80 may be made of the same material as the substrate 40 or may be made of a material having an etching rate similar to that of the substrate 40 with respect to the wet etching. The circumference of the insulating layer 80 is filled with a material having a higher etch rate than the substrate 40 and the insulating layer 80 with respect to the wet etching. Thereafter, the conductive layer 42 is formed on the insulating layer 80 and proceeds to the step before forming the undercut as described above. Subsequently, when the material 82 filled around the insulating layer 80 is removed by wet etching, an undercut 84 is formed under the conductive layer 42 as shown in FIG. 28. The process after the undercut 84 is formed may proceed in the same manner as after the undercut 64 of FIG. 13B is formed.

There may be another way to form the under cut.

Specifically, as shown in FIG. 29, a portion of the substrate 40 to be removed by wet etching at the time of the undercut formation is removed before the conductive layer 42 is formed. In this way, the board | substrate 40 becomes a structure which has the processus | protrusion 40P in which the conductive layer 42 is formed. The width of the projection 40P is narrower than the width of the conductive layer 42 to be formed. Subsequently, as shown in FIG. 30, the material 90 having a higher etch rate with respect to wet etching than the substrate 40 is filled in the portion where the substrate 40 is removed. Thereafter, the conductive layer 42 covering the protrusion 40P is formed, and then the process proceeds to the step before the undercut formation as described above. Thereafter, as shown in FIGS. 31 and 32, the material 90 filled in the place where a portion of the substrate 40 is removed is wet etched. As a result, as shown in FIG. 32, an undercut 94 is formed under the conductive layer 42.

 Since the present invention can be variously modified, the scope of the present invention should be determined by the technical spirit described in the claims rather than by the described embodiments.

1 to 19 are cross-sectional views sequentially illustrating a method of manufacturing an omega gate transistor according to an exemplary embodiment of the present invention.

20A and 20B to 22A and 22B are cross-sectional views illustrating a method of forming a gate electrode to which a damascene process is applied.

23 to 26 are cross-sectional views illustrating a method of fabricating a CMOS for forming a p-type gate electrode and an n-type gate electrode by applying a damascene process.

27 and 28 are cross-sectional views illustrating a modified example of forming an undercut in the method of manufacturing an omega gate transistor according to an embodiment of the present invention.

29 to 32 are cross-sectional views illustrating another modified example of forming an undercut in the method of manufacturing an omega gate transistor according to an embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40: substrate 42: conductive layer (active layer)

44, 46, 50: first to third insulating layers 48: interlayer insulating layers

52, 56, 58: Open portion 54, 60: Spacer

64, 84, 94: undercut 66, 70, 76: gate insulating film

68, 72, 78: gate conductive layer 68A: gate electrode

80: insulating layer 82: material filled around the insulating layer (80)

40P: protrusion (projection part)

90: a material filling a place where a portion of the substrate 40 is removed

A1, AA1: first region A2, AA2: second region

A3, AA3: third region

Claims (9)

In the method of manufacturing an omega gate transistor, Forming an active layer on the substrate; Covering the active layer with an insulating layer; Forming openings in the insulating layer, wherein the active layer and portions of the substrate are exposed beyond the lithography limit; Forming an under cut under the exposed active layer; Forming a gate insulating film in the active layer exposed through the opening and the undercut; And Forming a gate electrode on the gate insulating film. The method of claim 1, wherein the opening is formed in a multi-step. The method of claim 1, wherein the forming of the opening comprises: Forming an upper insulating layer on the insulating layer; Exposing a portion of the insulating layer to the upper insulating layer and forming a first opening having a limit width that can be formed by the lithography; Narrowing the diameter of the first opening; And Etching the insulating layer exposed through the first opening, the diameter of which is narrowed. The method of claim 1, wherein after forming the opening, a spacer is formed on sidewalls of the opening and on side surfaces of the active layer exposed through the opening before forming the undercut. The method of claim 4, wherein the spacer is removed before the gate insulating layer is formed. The method of claim 1, wherein the forming of the gate electrode comprises: Forming a gate conductive layer on the insulating layer, the gate conductive layer filling the opening formed with the gate insulating film; And And patterning the gate conductive layer. The gate insulating layer of claim 1, wherein the gate insulating layer is formed on the insulating layer to cover a sidewall of the opening and a portion exposed through the opening. After forming a gate conductive layer on the gate insulating film, And planarizing the gate conductive layer to form the gate electrode until the insulating layer is exposed. The method of claim 7, wherein after the gate conductive layer is formed, before the planarization is performed, Forming a second opening in the stack including the insulating layer, the gate conductive layer, and the gate insulating layer to expose the active layer; Forming a second gate insulating layer on the stack to cover a portion exposed through the second opening; And Forming a second gate conductive layer filling the second opening on the second gate insulating layer; And the planarization is performed from the second gate conductive layer until the insulating layer is exposed. The method of claim 3, wherein narrowing the diameter of the first opening portion, Depositing a spacer forming material layer on the upper insulating layer covering a sidewall of the first opening and covering a portion exposed through the first opening; And Anisotropically etching the spacer forming material layer until the upper insulating layer and the insulating layer of the first opening are exposed.

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