KR20090053036A - Method of manufacturing a flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, comprising: forming a stacked layer of a tunnel insulating film, a first conductive film, and a device isolation mask in an active region, and providing a semiconductor substrate having a trench formed in the device isolation region; Forming a liner insulating film having a first and second insulating film stacked structures along the surfaces of the lamination film and the trench to fill a portion of the trench; Performing a first annealing process to densify the second insulating film; Forming a third insulating film on the second insulating film densified so as to fill the trench, the third insulating film having an etching selectivity higher than that of the dense second insulating film; Etching and planarizing the first insulating film, the densified second insulating film, and the third insulating film until the device isolation mask is exposed; Performing the third insulating film etching process such that the third insulating film is lower than an upper surface of the semiconductor substrate; And forming a fourth insulating film on the third insulating film remaining to fill the trench.

Floating gate, double liner insulating film, etch selectivity, PSZ film, coupling ratio

Description

Method of manufacturing a flash memory device

The present invention relates to a method for manufacturing a flash memory device, which can improve the coupling ratio of a cell by increasing the area of the floating gate by increasing the thickness of the conductive film for the floating gate and improving the loss using an etching ratio difference. A method of manufacturing a flash memory device.

As the semiconductor devices are highly integrated, the process of forming a device isolation layer is becoming more difficult. Accordingly, an isolation layer is formed by using a shallow trench isolation (STI) method in which a trench is formed in a semiconductor substrate and then embedded. On the other hand, there are a number of methods for the STI method, among which a tunnel insulating film, a polysilicon film and a hard mask film stacked on a semiconductor substrate are sequentially etched to form a trench, and an oxide film is formed on the entire structure to fill the trench. This is applied to, for example, a NAND flash memory device. However, in the case of highly integrated devices, since the trench depth is deeper than the inlet width of the trench, the trench has no void due to the high density plasma (HDP) oxide used in the past due to the large aspect ratio. It is becoming more difficult to form a device isolation layer by fully gap-filling. In order to solve this problem, studies are being actively conducted on materials used to gap fill trenches without voids.

Among the methods for solving the above problem, there is a method of completely gap filling the trench by using polysilazane (PSZ), which is one of spin on dielectric (SOD) materials. The PSZ material has a low viscosity and flows like water, so the trench can be completely gap filled. However, the PSZ material contains a lot of impurities and moisture therein so that the tunnel insulation film is deteriorated when the PSZ material is formed adjacent to the tunnel insulation film. Accordingly, an HDP oxide film is formed on the trench surface in the form of a liner to prevent the tunnel insulating film from being contaminated by impurities contained in the PSZ material.

Recently, as the program speed needs to be improved, the thickness of the floating gate is increased to increase the cell coupling ratio. However, PSZ increases the aspect ratio when the thickness of the floating gate is increased, thereby increasing the target thickness to be etched during the PSZ wet etchback process, which aims to secure the gap fill margin and the etching selectivity. All of the HDP oxide film under the film is lost, thereby exposing the conductive film for the floating gate to be attacked. The loss of the conductive film for the floating gate is exposed and deepened again during the subsequent HDP deposition process and the wet etch back process for controlling the effective field oxide height (EFH), which causes an attack on the tunnel insulation layer during the subsequent gate etching process. By deteriorating the device, the reliability of the device is reduced. In addition, the area of the floating gate is reduced, thereby reducing the coupling ratio between the floating gate and the control gate, which results in lowering program speed.

The present invention forms a double-layer liner insulating layer of a material having a lower etching selectivity than a trench gap fill material, thereby minimizing the loss of the floating gate conductive layer by remaining the liner insulating layer on the sidewall of the conductive layer for the floating gate during the subsequent wet etching process. In addition, the present invention provides a method of manufacturing a flash memory device capable of improving a coupling ratio of a cell by increasing an area of a floating gate by improving a loss by using a thickness difference between a floating gate conductive layer and an etching ratio difference.

In the method of manufacturing a flash memory device according to an embodiment of the present invention, a stacked layer of a tunnel insulating film, a first conductive film and a device isolation mask is formed in an active region, and a semiconductor substrate having a trench formed in the device isolation region is provided. Forming a liner insulating film of the first and second insulating film stacking structures along the laminated film and the surface of the trench so that a portion of the trench is filled; densifying the second insulating film by performing a first annealing process, and densifying the trench to fill the trench Forming a third insulating film having an etching selectivity higher than that of the densified second insulating film on the second insulating film, and etching and planarizing the first insulating film, the densified second insulating film, and the third insulating film until the device isolation mask is exposed. step; Performing a third insulating film etching process such that the third insulating film is lower than the upper surface of the semiconductor substrate, and forming a fourth insulating film on the third insulating film remaining to fill the trench.

In the above, the etching selectivity is different between the first insulating film and the second insulating film. The third insulating film has a higher etching selectivity than the first insulating film. The first insulating film is formed of an HDP (High Density Plasma) oxide film. The HDP oxide film uses Ar and He gases when heated before deposition.

The second insulating film is formed of any one of a high aspect ratio process (HARP) insulating film, a high temperature oxide (HTO) insulating film, and a spin on dielectric (SOD) insulating film. The HARP insulating film is formed of an O ₃ -TEOS (Tetra Ethyl Ortho Silicate) film. The SOD insulating film is formed of a polysilazane (PSZ) film, wherein the PSZ film is formed by applying a PSZ chemical by spin coating and then performing a curing process.

The first annealing process is performed at a loading temperature and treatment temperature of 150 to 450 ° C. in an O ₂ or N ₂ gas atmosphere. The etching ratio of the second insulating film densified compared to the second insulating film is reduced by 40 to 60% by the first annealing process.

The third insulating film is formed of a PSZ film, wherein the PSZ film is formed by applying a PSZ chemical by spin coating and then performing a curing process.

The third insulating layer is lower than the upper surface of the semiconductor substrate by etching using a wet etchback process. The wet etchback process is performed using HF (H ₂ 0: HF = 50: 1 to 100: 1) solution and SC-1 (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 4: 20) solution. Is carried out. The wet etch back process is performed such that the third insulating film is lowered by a thickness of 200 to 400 GPa from the upper surface of the semiconductor substrate. In the performing of the third insulating film etching process such that the third insulating film is lower than the upper surface of the semiconductor substrate, the first insulating film and the densified second insulating film protect the sidewalls of the first conductive film.

The method may further include densifying the remaining third insulating layer by performing a second annealing process before forming the fourth insulating layer. The second annealing process is carried out at a temperature of 850-1000 ° C. The fourth insulating film is formed of an HDP oxide film.

After forming the fourth insulating film, etching and planarizing the fourth insulating film until the device isolation nitride film of the device isolation mask is exposed, removing the remaining device isolation mask, and etching the fourth insulating film to adjust the effective oxide film height. And forming a dielectric film and a second conductive film on the fourth insulating film and the first conductive film. The remaining device isolation mask is removed by an etching process using phosphoric acid (H ₃ PO ₄ ) solution and BOE (Buffered Oxide Etchant) sequentially. A solution containing HF is used to adjust the effective field oxide height (EFH).

The present invention has the following effects.

First, when the thickness of the floating gate is increased, the etching selectivity is lower than that of the trench gap fill material, and a double liner insulating film is formed on the sidewall of the conductive film for the floating gate, thereby wet etching to secure a gap fill margin and an etching selectivity. By minimizing the loss of the conductive film for the floating gate by leaving the liner insulating film on the sidewall of the conductive film for the floating gate during the process, the thickness of the floating gate conductive film is improved and the loss is improved by using the difference in etching ratio. Program / erase speed can be improved by improving the coupling ratio.

Second, it is possible to improve voids caused by the profile deformation of the conductive film for the floating gate, improve the deterioration characteristics by preventing the attack of the tunnel insulating film, and improve the reliability of the device.

Third, it is possible to secure a process that can increase the thickness of the floating gate by minimizing the loss of the conductive film for the floating gate through a simple process change.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1I are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, the tunnel insulating layer 102, the first conductive layer 104, and the device isolation mask 106 are sequentially formed on the semiconductor substrate 100. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. The first conductive layer 104 is used as a floating gate of a flash memory device, and is undoped polysilicon to control the concentration of phosphorus (P) at the interface of the tunnel insulating layer 102. It can be formed in a laminated structure of a film and a doped polysilicon film.

In this case, the first conductive layer 104 is formed by increasing the thickness of the dope polysilicon layer so that the thickness is higher than the thickness of the existing target floating gate, and the thickness ratio of the undoped polysilicon layer to the doped polysilicon layer To 1: 3 to 1: 5 to improve electrical characteristics such as APC (Abnormal Programming Cell) or cycling (cycling). For example, the undoped polysilicon film may be formed to a thickness of 50 to 250 GPa, and the undoped polysilicon film may be formed to a thickness of 500 to 800 GPa.

The device isolation mask 106 is used as an etching mask in the subsequent trench formation, and is used to prevent loss of the first conductive layer 104. The device isolation mask 106 may include a buffer oxide layer (not shown), a nitride layer and a hard mask. It can be formed in a laminated structure of a film.

Next, the trench 108 is formed by etching the device isolation mask 106, the first conductive film 104, the tunnel insulating film 102, and the semiconductor substrate 100 in the device isolation region. More specifically described as follows. A photoresist (not shown) is applied on the device isolation mask 106 and an exposure and development process is performed to form a photoresist pattern (not shown) that exposes the device isolation mask 106 in the device isolation region. Subsequently, the device isolation region of the device isolation mask 106 is etched by an etching process using a photoresist pattern. Thereafter, the photoresist pattern is removed. Subsequently, the first conductive film 104 and the tunnel insulating film 102 are etched by an etching process using the device isolation mask 106. As a result, the semiconductor substrate 100 in the device isolation region is exposed. In the process of etching the device isolation mask 106, the first conductive film 104, and the tunnel insulating film 102, the hard mask film of the device isolation mask 106 is also etched by a predetermined thickness. Subsequently, the semiconductor substrate 100 of the exposed device isolation region is etched to a predetermined depth. As a result, the trench 108 is formed in the device isolation region. As such, the trench 108 may be formed by performing an ASA-STI (Advanced Self Align-Shallow Trench Isolation) process on the semiconductor substrate 100.

Subsequently, an insulating material is deposited on the device isolation mask 106 including the trench 108 to fill a portion of the trench 108 to form the first insulating layer 110. The sidewalls of the first conductive layer 104 may not be exposed to the first insulating layer 110 during the wet etch process for the purpose of securing a subsequent gap-fill margin and securing an etching selectivity. It is formed in the form of a liner using a material having an etch selectivity lower than the trench gap fill material in order to use the difference in the etch rate between the materials. In addition, the first insulating layer 110 should be formed using a material whose reliability has been verified in order to prevent the tunnel insulating layer 102 from deteriorating due to impurities contained in the PSZ material.

According to an embodiment of the present invention, since the gap fill is performed using a PSZ film having excellent trench gap fill characteristics, the first insulating film 110 has an etching selectivity of about 6 to 10 times lower than that of the PSZ film. It is preferable to form an HDP oxide film using a High Density Plasma (HDP) method.

At this time, in the deposition process of the first insulating layer 110, in order to prevent the area of the first conductive layer 104 is reduced by oxidizing the first conductive layer 104 during deposition, O ₂ during heating before deposition. Unlike conventional Ar and He gas, Ar and He gas are used.

Referring to FIG. 1B, an insulating material is deposited on the first insulating layer 110 to fill a portion of the trench 108 to form the second insulating layer 112. The second insulating layer 112 is to minimize sidewall loss of the first insulating layer 110 during a wet etching process for the purpose of securing a subsequent gap fill margin and securing an etching selectivity. The excellent HARP (High Aspect Ratio Process) insulating film, High Temperature Oxide (HTO), or SOD (Spin On Dielectric) insulating film may be used to form a liner.

In this case, the HARP (High Aspect Ratio Process) insulating film is preferably formed of a HARP insulating film made of O ₃ -TEOS (Tetra Ethyl Ortho Silicate). The HARP insulating film is formed using a HARP process, and in this case, the HARP process may be performed using 1000 to 3000 mg of TEOS and 5000 to 20000 sccm of O ₃ as a reaction source at a temperature of 500 to 600 ° C. and a pressure of 500 to 700 Torr. Can be.

In addition, the SOD insulating film may be formed of a polysilazane (PSZ) film. In this case, the PSZ film is formed by applying a PSZ chemical by spin coating and then performing a curing process. Curing process is carried out at a temperature of 350 to 500 ℃ in O ₂ and H ₂ O gas atmosphere to remove the coating PSZ film contains a lot of impurities and moisture. After completion of curing, N is desorbed from the PSZ material consisting of Si, H and N, and H is substituted to form a solidified PSZ film made of SiO x film. Such a PSZ film has a very vulnerable property to an etchant.

Subsequently, an annealing process is performed to lower the etching selectivity during the wet etching process in which the film quality of the second insulating film 112 is densified to secure the gap fill margin and the etching selectivity. At this time, the annealing process is a loading temperature (treatment temperature) and the treatment temperature (treatment temperature) to a temperature of 150 to 450 ℃ in order to avoid the phenomenon of smiling (smiling) and bending of the active region in the O ₂ or N ₂ gas atmosphere Do it. The second insulating film 112 densified by the annealing process has an etching ratio of 40 to 60% less than that before the annealing process.

Meanwhile, a baking process may be further included to prevent cracking due to dehydration and condensation of the PSZ film before curing the PSZ film. The baking process may be performed sequentially the first, second and third baking process, in this case O ₂ , N ₂ And it is carried out for 1 to 10 minutes at a temperature of 100 to 200 ℃ in the air atmosphere.

As a result, a liner insulating film 114 having a double structure including a laminated film of the first insulating film 110 and the second insulating film 112 is formed on the sidewall of the first conductive film 104, and the second insulating film 112 is formed. It is formed into a dense thin film.

As such, the liner insulating film 114 including the first insulating film 110 made of the HDP oxide film and the second insulating film 112 densified by the annealing process may be used to secure a subsequent gap fill margin and an etching selectivity. During the wet etching process, the liner insulating layer 114 is left on the sidewall of the first conductive layer 104 due to the difference in etching between the liner insulating layer 114 and the trench 108 gap fill material. 104 loss can be minimized.

Referring to FIG. 1C, a third insulating film 116 is formed on the dense second insulating film 112 so that the trench 108 is filled. The third insulating film 116 is formed of an SOD insulating film having excellent trench gap fill characteristics, and may be preferably formed of a PSZ film.

At this time, the PSZ film is formed by applying a PSZ chemical by spin coating and then performing a curing process. The curing process is performed at a temperature of 350 to 500 ° C. in an O ₂ and H ₂ O gas atmosphere to remove impurities and moisture in the applied PSZ film. After completion of curing, N is desorbed from the PSZ material consisting of Si, H and N, and H is substituted to form a solidified PSZ film made of SiOx film.

As such, when the PSZ film, which is a fluid material, is used, the bottom surface of the trench 108 may be easily filled, so that the third insulating layer 116 may be formed without voids to gap fill the trench 108. However, since the PSZ film has a very weak property to the etching solution, the etching selectivity is higher than that of the first insulating film 110 and the densified second insulating film 112.

Referring to FIG. 1D, an etching process is performed until the upper portion of the device isolation mask 106 is exposed. Here, the etching process may be performed by a planarization etching process, for example, chemical mechanical polishing (CMP) process. As a result, the first, second, and third insulating layers 110, 112, and 116 remain only in the trench 108 in the device isolation region.

Referring to FIG. 1E, an etching process of the third insulating layer 116 is performed in order to secure a gap fill margin and an etching selectivity of the trench 108. This is because the PSZ film has excellent trench 108 gap fill characteristics but reliability has not been verified so that only a portion of the PSZ film remains on the bottom of the trench 108 to secure a subsequent trench 108 gap fill margin.

To this end, the etching process may be carried out by a wet etching process, preferably a wet etchback process, the HF (H ₂ 0: HF = 50: 1 to 100: 1) solution and SC-1 (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 4: 20) solution. In this case, the etching process is performed such that the third insulating film 116 is lowered by 200 to 400 kV from the upper surface of the semiconductor substrate 100.

In general, when the etching ratio for the HF solution and the SC-1 solution is 1, the HDP oxide film is 2, the HARP insulating film is 3-4, and the PSZ film is 8-9. Therefore, during the etching process, the third insulating layer 116 formed of the PSZ layer is etched faster than the densified second insulating layer 112 or the first insulating layer 110 and remains lower from the upper surface of the semiconductor substrate 100. On the other hand, a portion of the side walls of the first and second insulating layers 110 and 112 are etched together during the etching process, but part of the side walls remain on the sidewall of the first conductive layer 104 due to the etching difference. In particular, the first insulating layer 110 having a lower etching ratio and shorter exposure time to the etchant is left on the sidewall of the first conductive layer 104 thicker than the second insulating layer 112. As a result, the sidewall of the first conductive layer 104 is prevented from being exposed during the etching process of the third insulating layer 116, so that the first conductive layer 104 is lost due to the attack by the etchant. It can be minimized. As such, when the loss of the first conductive film 104 is improved, the area of the first conductive film 104 may be increased by increasing the thickness of the first conductive film 104, thereby increasing the contact area between the floating gate and the control gate to be formed later. Coupling ratios can be improved.

In addition, when the loss of the first conductive layer 104 is prevented, attack of the tunnel insulating layer 102 may be prevented during the subsequent gate etching process to improve deterioration characteristics, thereby improving reliability of the device.

Subsequently, an annealing process is further performed to lower the etching selectivity of the remaining third insulating layer 116 during the wet etching process for controlling the effective field oxide height (EFH). In this case, the annealing process can be carried out at a temperature of 850 to 1000 ℃. The film quality of the third insulating film 116 is densified by the annealing process to lower the etching selectivity. Thus, the etching solution penetrates into the third insulating film 116 during the wet etching process for controlling the EFH. You can prevent it from sitting down. In addition, even if a void occurs in the upper layer, it may be prevented from being transferred to the third insulating layer 116.

Referring to FIG. 1F, a fourth insulating layer 118 is formed on the third insulating layer 116 remaining to fill the trench 108. The fourth insulating layer 118 may be formed of an HDP film. As the aspect ratio is reduced due to the third insulating film 116 remaining under the trench 108 when the fourth insulating film 118 is deposited, a gap fill margin is secured to form the fourth insulating film 118 having excellent reliability without voids. have.

Referring to FIG. 1G, an etching process is performed until the device isolation nitride film of the device isolation mask 106 is exposed. Here, the etching process may be performed by a planarization etching process, for example, a CMP process. As a result, the first to fourth insulating layers 110, 112, 116, and 118 remain only in the trench 108 of the device isolation region, and include the first to fourth insulating layers 110, 112, 116, and 118. 120 is formed.

Referring to FIG. 1H, the remaining device isolation mask 106 is removed. Removal of the remaining device isolation mask 106 is performed by an etching process using a phosphoric acid (H ₃ PO ₄ ) solution and a buffered oxide etch (BOE) sequentially, thereby removing the remaining device isolation mask 106 The nitride film and the buffer oxide film are sequentially removed to expose the surface of the first conductive film 104 and the upper sidewall of the device isolation film 120.

Subsequently, an etching process for adjusting the effective field oxide height (EFH) is performed. In this case, in the etching process, the upper portion of the device isolation layer 120 is etched by a predetermined thickness using a solution including HF. As a result, the upper sidewall of the first conductive film 104 is exposed. However, after etching the third insulating layer 116, as shown in FIG. 1E, as the first and second insulating layers 110 and 112 remain on the sidewalls of the first conductive layer 104, the etching liquid in the process of adjusting the effective oxide layer height. The loss of the first conductive film 104 can be improved by shortening the time for which the first conductive film 104 is exposed. In this case, it is preferable that the device isolation layer 120 remain higher than the upper surface of the semiconductor substrate 100 in the active region in consideration of cycling characteristics.

Meanwhile, after the effective oxide film height is adjusted, the remaining device isolation mask 106 may be removed.

Referring to FIG. 1I, a dielectric film 122 and a second conductive film (not shown) are sequentially formed on the first conductive film 104 and the device isolation film 120. The dielectric film 122 may be formed of a stacked structure of an oxide film, a nitride film, and an oxide film (Oxide-Nitride-Oxide (ONO)) or a high dielectric material having a dielectric constant of 3.9 or more. The second conductive film is intended to be used as a control gate of a flash memory device, and may be formed of a polysilicon film, a metal layer, and a laminated film thereof.

Subsequently, the second conductive film, the dielectric film 122, and the first conductive film 104 are patterned by a conventional etching process, and include a floating gate 104a and a second conductive film formed of the first conductive film 104. The control gate 124 is formed. At this time, a gate pattern having a stacked structure of the tunnel insulating film 102, the floating gate 104a, the dielectric film 122, and the control gate 124 is formed.

As described above, according to an embodiment of the present invention, even if the thickness of the floating gate 104a is increased, a double liner having an etch selectivity lower than that of the third insulating layer 116 on the sidewall of the first conductive layer 104. By forming the insulating layer 114, the loss of the first conductive layer 104 can be minimized by remaining the liner insulating layer 116 on the sidewall of the first conductive layer 104 due to the etching difference in the subsequent wet etching process. have. Accordingly, the area of the floating gate 104a may be increased by increasing the thickness of the floating gate 104a and improving the loss of the first conductive layer 104, and thus, between the floating gate 104a and the control gate 124. By increasing the area facing each other, the coupling ratio of the cell can be improved to increase the program / erase speed. In addition, the reliability of the device may be improved by minimizing the loss of the first conductive layer 104 for the floating gate to prevent attack of the tunnel insulating layer 102 when the gate is etched, thereby improving deterioration characteristics.

Furthermore, the process of increasing the thickness of the floating gate 104a may be secured by minimizing the loss of the first conductive layer 104 for the floating gate through a simple process change using the double liner insulating layer.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1I are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: first conductive film 104a: floating gate

106: device isolation mask 108: trench

110: first insulating film 112: second insulating film

114: liner insulating film 116: third insulating film

118: fourth insulating film 120: device isolation film

122: dielectric film 124: control gate

Claims (24)

Providing a semiconductor film including a tunnel insulating film, a first conductive film, and a device isolation mask in an active region, and a semiconductor substrate having a trench formed in the device isolation region; Forming a liner insulating film having a first and second insulating film stacked structures along the surfaces of the lamination film and the trench to fill a portion of the trench; Performing a first annealing process to densify the second insulating film; Forming a third insulating film on the second insulating film densified so as to fill the trench, the third insulating film having an etching selectivity higher than that of the dense second insulating film; Etching and planarizing the first insulating film, the densified second insulating film, and the third insulating film until the device isolation mask is exposed; Performing the third insulating film etching process such that the third insulating film is lower than an upper surface of the semiconductor substrate; And Forming a fourth insulating film on the third insulating film remaining to fill the trench. The method of claim 1, The method of claim 1, wherein the first insulating layer and the second insulating layer have different etching selectivity. The method of claim 1, The third insulating film has a higher etching selectivity than the first insulating film manufacturing method of the flash memory device. The method of claim 2 or 3, And the first insulating film is formed of a high density plasma (HDP) oxide film. The method of claim 4, wherein The HDP oxide film is a method of manufacturing a flash memory device using Ar and He gas when heated before deposition. The method of claim 2, The second insulating layer is formed of any one of a high aspect ratio process (HARP) insulating film, a high temperature oxide (HTO) insulating film, and a spin on dielectric (SOD) insulating film. The method of claim 6, The HARP insulating film is a method of manufacturing a flash memory device formed of O ₃ -TEOS film. The method of claim 6, The SOD insulating film is a method of manufacturing a flash memory device formed of a polysilazane (PSZ) film. The method of claim 8, The PSZ film is formed by applying a PSZ chemical by spin coating, followed by a curing process. The method of claim 1, And the first annealing process is performed in an O ₂ or N ₂ gas atmosphere. The method of claim 10, And the first annealing process is performed at a loading temperature and a treatment temperature at a temperature of 150 to 450 ° C. The method of claim 1, And a etch ratio of the densified second insulating film is reduced by 40 to 60% compared to the second insulating film by the first annealing process. The method of claim 1, And the third insulating film is formed of a PSZ film. The method of claim 13, The PSZ film is formed by applying a PSZ chemical by a spin coating method followed by a curing process. The method of claim 1, And the third insulating layer is lower than an upper surface of the semiconductor substrate by etching using a wet etchback process. The method of claim 15, The wet etchback process uses HF (H ₂ 0: HF = 50: 1 to 100: 1) solution and SC-1 (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 4: 20) solution Method for manufacturing a flash memory device carried out by the. The method of claim 15, And the wet etch back process is performed such that the third insulating film is lowered by a thickness of 200 to 400 microseconds from an upper surface of the semiconductor substrate. The method of claim 1, wherein the third insulating film etching process is performed such that the third insulating film is lower than an upper surface of the semiconductor substrate. And the first insulating film and the densified second insulating film protect sidewalls of the first conductive film. The method of claim 1, And performing a second annealing process to densify the remaining third insulating film before forming the fourth insulating film. The method of claim 19, The second annealing process is a manufacturing method of a flash memory device performed at a temperature of 850 to 1000 ℃. The method of claim 1, And the fourth insulating film is formed of an HDP oxide film. The method of claim 1, wherein after forming the fourth insulating film, Etching and planarizing the fourth insulating film until the device isolation nitride film of the device isolation mask is exposed; Removing the remaining device isolation mask; Etching the fourth insulating film to adjust an effective oxide film height; And The method of claim 1, further comprising forming a dielectric film and a second conductive film on the fourth insulating film and the first conductive film. The method of claim 22, The remaining device isolation mask is removed by an etching process using a phosphoric acid (H ₃ PO ₄ ) solution and BOE (Buffered Oxide Etchant) sequentially. The method of claim 22, A method of manufacturing a flash memory device using a solution containing HF when adjusting the effective field oxide height (EFH).

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