KR20080038954A - Power on reset circuit - Google Patents

Abstract

A power-on reset circuit is provided to reduce power consumption and offer a power-on reset signal stably by enabling the power-on reset signal to block a current flowing in a standby state. A generator(320) generates a power-on reset signal by power voltage. A current breaker(310) receives the power-on reset signal from the generator and cuts off a current of the generator according to an output level of the power-on reset. The generator includes a first transistor(340) operated by ground voltage between the power voltage and a first node, a register connected between the first node and a second node, a plurality of invertors(330) buffering electric potential of the first node, a second transistor(350) connected between the second node and the grounding voltage, and operated by an output signal of the current breaker, and a stabilizer stabilizing the voltage level of the first node and an output terminal of the inverter connected to the first terminal.

Description

Power on reset circuit

1 is a circuit diagram of a conventional power on reset circuit.

FIG. 2 is a diagram illustrating a time when the standby current of FIG. 1 flows.

3 is a circuit diagram of a power-on reset circuit according to an embodiment of the present invention.

4 is an operation timing diagram of FIG. 3.

5A and 5B are operation timing diagrams according to the delay adjustment of FIG. 3.

* Brief description of the main parts of the drawings *

310: current blocking unit 320: generation unit

330: inverter unit 340: first stabilizing unit

350: second stabilizer

The present invention relates to the removal of standby by current of a power-on reset circuit, and more particularly, to a power-on reset circuit capable of removing a standby current of a power on reset (POR) block that exists after power-on. will be.

Chips that contain many functions, such as memory devices, have many circuits whose initial conditions must be determined for proper operation. In this case, initialization must be done even before the chip is operating, typically with a power on reset circuit. The power-on reset circuit generates a pulse (hereinafter referred to as a 'power-on reset signal') by detecting a constant potential before the chip is turned on to raise all internal voltages.

This power-on reset signal allows the internally latched, flip-flop, register, and other circuit blocks that need to be initialized before the chip can operate.

An ideal power-on reset circuit requires that the potential of the power-on reset signal be stable with respect to the ramping time and noise of the power supply, and is less susceptible to physical variables such as process changes and temperature. by current).

1 is a circuit diagram of a conventional power on reset circuit.

Referring to FIG. 1, the power on reset circuit may include a generator 110 generating a power on reset (POR) signal according to a potential of a power supply voltage, and a power on reset signal of the generator 110. And an inverter unit 120 for inverting the POR, and first and second stabilization units 130 and 140 for stabilizing the power reset signal POR of the generator 110. The apparatus further includes first and second inverters IN1 and IN2 for buffering the power-on reset signal POR output through the inverter unit 120.

The generation unit 110 includes a first PMOS transistor P1 and a resistor R. The inverter unit 120 includes a second PMOS transistor P2 and a first NMOS transistor N1.

The first stabilization unit 130 includes third and fourth PMOS transistors P3 and P4, and the second stabilization unit 140 includes second and third NMOS transistors N2 and N3.

The generation unit 110 outputs a division voltage due to the first PMOS transistor P1 and the resistor R, and the inverter unit 120 outputs a high or low level by the voltage level of the division voltage.

Meanwhile, when the input terminal of the inverter unit 120 is at a low level and the output terminal of the first inverter IN1 is at a high level, the first stabilization unit 130 reliably moves the input terminal of the second inverter IN2 to a high level. Keep it.

When the input terminal of the inverter unit 120 is at a high level and the output terminal of the first inverter IN1 is at a low level, the second stabilization unit 140 maintains the input terminal of the second inverter IN2 at a low level. .

FIG. 2 is a diagram illustrating a time when the standby current of FIG. 1 flows.

Referring to FIG. 2, the voltage level of the node 1 of FIG. 1 gradually increases as the power supply voltage is supplied. When the voltage level exceeds a predetermined level, the power-on reset signal POR maintains a low level output. Even in the state, current i continues to flow through node 1.

As described above, the current i flowing in the standby state consumes a certain portion of the entire current of the chip, thus causing unnecessary power consumption.

Accordingly, an aspect of the present invention is to provide a power on reset circuit for removing a current that may flow in the standby mode.

Power on reset circuit according to an aspect of the present invention for achieving the above technical problem,

A circuit for outputting a power on reset signal, comprising: a generator for generating a power on reset signal by a power supply voltage; And a current blocking unit configured to receive a power-on reset signal output from the generator and to block a current of the generator from a power level of the power-on reset call.

The generation unit includes: a first transistor connected between a power supply voltage and a first node and operated by a ground voltage; A resistor connected between the first node and a second node; A plurality of inverters for buffering the potential of the first node; And a second transistor connected between the second node and a ground voltage and operated according to an output signal of the current blocking unit.

The current blocking unit may include: a third transistor connected between a power supply voltage and a third node and operating according to an output voltage level of the first node of the generation unit; A delay outputting a delayed output voltage level of the first node of the generation unit for a set time; A fourth transistor connected between the third node and a ground voltage and operating according to an output of the delay; And a latch circuit connected between the third node and the fourth node, wherein the second transistor operates according to the state of the fourth node.

The generation unit may further include a stabilization unit that stabilizes the potential of the output terminal of the inverter connected to the first end of the first node and the plurality of inverters.

The stabilization unit may be operated according to an inverted signal of the potential of the first node and the power on reset signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a circuit diagram of a power-on reset circuit according to an embodiment of the present invention.

Referring to FIG. 3, a power-on reset circuit according to an exemplary embodiment of the present invention includes a current shut-off unit 310, a generation unit 320, an inverter unit 330, a first stabilization unit 340, and a second unit. The stabilizer 350 and the fifth and sixth inverters IN5 and IN6 are included.

The current blocking unit 310 cuts off the standby current flowing through the generation unit 320. The current blocking unit 310 may include the first to fourth inverters INV1 to INV4, the first PMOS transistor MP1, and the first NMOS transistor MN1. ) And the delay 311.

The generation unit 320 generates a power on reset signal POR and includes a second PMOS transistor MP2, a resistor R, and a second NMOS transistor MN3.

The inverter unit 330 performs an inverting operation according to the output voltage output from the node d of the generation unit 320, and includes a third PMOS transistor MP3 and a third NMOS transistor MN3. .

When the output of the inverter unit 330 is high, the first stabilization unit 340 holds the output of the fifth inverter unit INV5 at a high level, and the fourth and fifth PMOS transistors MP4 and MP5. It includes.

The second stabilization unit 350 holds the output of the fifth inverter INV5 at a low level when the output of the inverter unit 330 is low, and holds the fourth and fifth NMOS transistors MN4 and MN5. Include.

The fifth and sixth inverters INV5 and IN6 buffer the POR signals output through the inverter unit 330 and output the buffered POR signals to the output node POR.

Referring to the connection relationship and operation of each part of the power-on reset circuit according to an embodiment of the present invention as described above are as follows.

First, the first inverter INV1 of the current blocking unit 310 outputs a signal inverted using the signal of the output terminal POR as an input signal and inputs it to the gate of the first PMOS transistor MP1.

The first PMOS transistor MP1 is connected between a power supply voltage and a node a, and is operated by an output signal of the first inverter INV1. The input signal to the first inverter INV1 is powered on and reset. Since the signal POR, the first PMOS transistor MP1 is driven by the inverted signal of the power-on reset circuit.

That is, the first PMOS transistor MP1 is turned on while the power on reset signal POR is at the high level, and the first PMOS transistor MP1 is turned on while the power on reset signal POR is at the low level. It is off.

Meanwhile, the output signal of the first inverter INV1 is input to the delay 311 and input to the first NMOS transistor MN1 after a set time.

The delay time of the delay 311 can be freely set by the user.

The first NMOS transistor MN1 is connected between the node a and the ground voltage and driven by the signal of the delay 311. The operation of the first NMOS transistor MN1 is turned off after a predetermined time delay when the power on reset signal POR is at a high level, and after a predetermined time delay when the power on reset signal POR is at a low level. It is turned on.

Therefore, in the standby mode in which the power-on reset signal POR continues to be at the high level, the first PMOS transistor MP1 is turned on and the first NMOS transistor MN1 is turned off, so that the node (a) has a high level. The node b is at a low level.

The second NMOS transistor MN2 is turned on while the node b is at the low level. However, at this time, since the power supply voltage for applying the power-on reset signal POR is not input to the generation unit 320, there is no current flowing to the generation unit, so even if the second NMOS transistor MN2 is turned on. No current is consumed.

When a power supply voltage is applied to apply the power-on reset signal POR for the operation of the chip, the node d initially receives a low division voltage due to a gradually precharged power supply voltage, thereby inverting the inverter unit 320. It outputs a high level, which causes the power-on reset signal POR to maintain a high level to some extent.

However, when the precharging of the power supply voltage proceeds, the node d is applied with a division voltage above a predetermined level, and the inverter unit 320 outputs a low level by the voltage level of the node d.

The power-on reset signal POR is applied to the low level by the low level of the inverter unit 320, and maintains the low level while the chip is operating.

When the power on reset signal POR is changed from the high level to the low level, the first inverter INV1 changes the node h to the high level.

Due to the high level of the node h, the first PMOS transistor MP1 is turned off. However, while the delay 311 is delayed, the first NMOS transistor MN1 is still turned off so that the state of the node a remains at its first high state, and the second NMOS transistor MN2 is turned on. Is maintained.

After the time delay of the delay 311, the first NMOS transistor is turned on due to the high level of the node h, and the node a is changed to the low level.

When node a goes low, node b goes high and node c goes low. When the node c becomes low level, the second NMOS transistor MN2 is turned off.

When the second NMOS transistor MN2 is turned off, the current flowing in the generation unit 320 cannot flow to the ground voltage, thereby obtaining a current blocking effect in the standby state.

4 is an operation timing diagram of FIG. 3.

Referring to FIG. 4, while the power supply voltage is gradually precharged, the node d is also gradually precharged due to the distribution voltage due to the second PMOS transistor MP2 and the resistor R.

동안 로우 레벨로 유지된다. 이러한 상태에서 딜레이(311)의 지연값을 조절함으로써 제 2 NMOS 트랜지스터(NM2)를 턴오프 시킴으로써 커런트를 없앤다.In the operation description of FIG. 3, the POR signal is generated according to the precharge of the node d.

Is held at a low level. In this state, the current is eliminated by turning off the second NMOS transistor NM2 by adjusting the delay value of the delay 311.

5A and 5B are operation timing diagrams according to the delay adjustment of FIG. 3.

시간 동안 제 1 PMOS 트랜지스터(MP1)를 턴 온 시켜 노드(a)를 하이로 동작 시킨다. 따라서 노드(d)가 하이 레벨이 되고, 제 2 NMOS 트랜지스터(MN2)가 턴 온 되어, 노드(d)는 기존과 동일하게 프리차지된다.5A and 5B, by adjusting the delay time of the delay 311,

The node a is driven high by turning on the first PMOS transistor MP1 for a period of time. Accordingly, the node d becomes high level, the second NMOS transistor MN2 is turned on, and the node d is precharged as before.

시간 이후에 파워 온 리셋 신호(POR)가 로우 레벨로 되면, 제 1 PMOS 트랜지스터(MP1)를 턴오프 된다. 이때도 딜레이(311)의 지연값에 의해 제 1 NMOS 트랜지스터(MN1)는 턴오프 상태이므로 여전히 노드(a)는 하이 레벨로 래치되어 있어 여전히 제 2 NMOS 트랜지스터(MN2)는 턴 온 상태를 유지한다.And

When the power-on reset signal POR becomes low after a time, the first PMOS transistor MP1 is turned off. In this case, since the first NMOS transistor MN1 is turned off due to the delay value of the delay 311, the node a is still latched at a high level, and the second NMOS transistor MN2 remains turned on. .

이 지나면, 제 1 NMOS 트랜지스터(MN1)가 턴 온 되고, 노드(a)는 로우 레벨로 변경되고, 제 2 NMOS 트랜지스터(MN2)가 턴 오프 된다. 제 2 NMOS 트랜지스터(MN2)가 턴오프 되면, 생성부(320)에 흐르는 커런트의 흐름을 차단한다.Delay time of delay 311 later

After this, the first NMOS transistor MN1 is turned on, the node a is changed to a low level, and the second NMOS transistor MN2 is turned off. When the second NMOS transistor MN2 is turned off, the flow of current flowing to the generation unit 320 is blocked.

In addition, since the path d to the ground voltage is eliminated because the second NMOS transistor MN2 is turned off, the node d is precharged to the power supply voltage, thereby eliminating a voltage drop, thereby becoming more resistant to noise.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the power-on reset circuit according to the present invention cuts off the current flowing in the standby state to reduce power consumption and provide a stable power-on reset signal.

Claims (5)

In a circuit for outputting a power-on reset signal, A generator configured to generate a power-on reset signal by a power supply voltage; And A current blocking unit for receiving a power-on reset signal output from the generator and blocking current of the generator from a power level of the power-on reset call Power on reset circuit comprising a. The method of claim 1, The generation unit, A first transistor connected between a power supply voltage and a first node and operated by a ground voltage; A resistor connected between the first node and a second node; A plurality of inverters for buffering the potential of the first node; And A second transistor coupled between the second node and a ground voltage and operated according to an output signal of the current interrupter Power on reset circuit comprising a. The method of claim 2, The current blocking unit, A third transistor connected between a power supply voltage and a third node and operating according to an output voltage level of the first node of the generator; A delay outputting a delayed output voltage level of the first node of the generation unit for a set time; A fourth transistor connected between the third node and a ground voltage and operating according to an output of the delay; And A latch circuit coupled between the third node and a fourth node, And the second transistor operates according to the state of the fourth node. The method of claim 1, The generation unit, And a stabilizing unit for stabilizing a potential of an output terminal of the inverter connected to the first end of the first node and the plurality of inverters. The method of claim 4, wherein And the stabilizing unit operates according to the potential of the first node and the inverted signal of the power on reset signal.

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