KR20080019133A - Liquid crystal display device and driving method of the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to control a power supply part and to increase brightness of a light source part at each frame gradually by a light source control part for lowering brightness of the light of a backlight unit at an upper part of a screen and increasing brightness at a lower part gradually, thereby reducing non-uniformity of the brightness of the screen. An LCD device comprises an LCD panel(300), a signal control part, and a backlight unit. The backlight unit includes light source parts(910), a power supplying part, and a light source control part. The light source control part adjusts the power supplying part to increase the brightness of the light source parts at each frame gradually. The light source parts include multiple sub light sources(911) parallel to gate lines. The light source control part controls the power supply part to drive the sub light sources sequentially. Thereby, non-uniformity of the brightness of the screen is reduced.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention;

2 is a layout view of a liquid crystal display panel according to a first embodiment of the present invention;

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is a view for explaining a light source unit according to a first embodiment of the present invention;

5 is a view showing transmittance according to pixel voltage in the liquid crystal display according to the first embodiment of the present invention.

6A and 6B are diagrams for describing a difference in pixel voltage according to a gate signal delay.

7 is a view for explaining driving of a liquid crystal display panel according to a first embodiment of the present invention;

8 is a view for explaining the driving of the light source unit according to the first embodiment of the present invention;

9 is a view for explaining the driving of the light source unit according to the second embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

100: thin film transistor substrate 170: pixel

200: color filter substrate 300: liquid crystal display panel

400: gate driver 500: data driver

600: signal controller 700: driving voltage generator

800: gray voltage generator 900: backlight unit

910: light source 911: sub light source

920: power supply unit 930: light source control unit

The present invention relates to a liquid crystal display and a driving method thereof.

The liquid crystal display device includes a first substrate on which a thin film transistor is formed, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed therebetween.

The gate line and the data line provided on the thin film transistor substrate cross each other to form pixels, and each pixel is connected to the thin film transistor. When the gate signal (gate on voltage Von) is applied to the gate line and the thin film transistor is turned on, the data voltage Vd applied through the data line is charged in the pixel. The arrangement state of the liquid crystal layer is determined according to the electric field formed between the pixel voltage Vp charged in the pixel and the common voltage Vcom formed on the common electrode of the color filter substrate. The data voltage Vd is applied with different polarities for each frame.

The data voltage Vd applied to the pixel is dropped by the parasitic capacitance Cgs between the gate electrode and the source electrode to form the pixel voltage Vp. The voltage difference between the data voltage Vd and the pixel voltage Vp is called a kickback voltage Vkb.

The gate line receives a gate signal through a gate pad connected to an end of the gate line. The low delay gate signal is applied to the thin film transistor adjacent to the gate pad, and the high delay signal is applied to the pixel electrode far from the gate pad.

However, the magnitude of the kickback voltage varies according to the delay level of the gate signal, thereby causing a problem in that the brightness of the screen is uneven due to the change in charging rate.

Accordingly, an object of the present invention is to provide a liquid crystal display device with uniform luminance.

Another object of the present invention is to provide a method of driving a liquid crystal display device having a uniform brightness.

The object of the present invention is to provide a liquid crystal display panel including a gate line and a data line, a signal control unit for sequentially and repeatedly driving pixels of the liquid crystal display panel along a driving direction parallel to the data line, and positioned on a rear surface of the liquid crystal display panel. A liquid crystal display device comprising a backlight unit, the backlight unit comprising: a light source unit; A power supply unit supplying power to the light source unit; In each frame, it is achieved by including a light source control unit for controlling the power supply unit so that the brightness of the light source unit increases with time.

The light source unit may include a plurality of sub light sources parallel to the gate line, and the light source control unit may control the power supply unit to repeatedly drive the plurality of sub light sources sequentially.

Preferably, the signal controller inputs a horizontal synchronization start signal (STH) to the liquid crystal display panel, and the light source controller controls the power supply unit in synchronization with the horizontal synchronization start signal.

The light source unit preferably includes a lamp or a light emitting diode.

The liquid crystal display panel preferably includes a liquid crystal layer of VA mode.

Another object of the present invention is to provide a liquid crystal display panel including a gate line and a data line, a signal control unit for sequentially and repeatedly driving pixels of the liquid crystal display panel along a driving direction parallel to the data line, A method of driving a liquid crystal display device including a backlight unit positioned on a rear surface, wherein the backlight unit includes a light source unit, and in each frame, controlling the backlight unit such that the brightness of the light source unit increases with time. Is achieved.

The light source unit may include a plurality of sub light sources parallel to the gate line, and the plurality of sub light sources may be repeatedly driven sequentially.

The signal controller inputs a horizontal synchronization start signal (STH) to the liquid crystal display panel, and the light source unit is driven in synchronization with the horizontal synchronization start signal.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Prior to the detailed description, like reference numerals refer to like elements throughout the various embodiments. The same components are representatively described in the first embodiment and may not be described in other embodiments.

1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

The liquid crystal display device 1 according to an exemplary embodiment of the present invention includes a liquid crystal display panel 300, a gate driver 400, a data driver 500, and a driving voltage generator 700 and a data driver 500 connected to the gate driver 400. ) Includes a gray voltage generator 800 and a signal controller 600 for controlling the gray voltage generator 800. In addition, the liquid crystal display device 1 further includes a backlight unit 900 for supplying light to the liquid crystal display panel 300.

The liquid crystal display panel 300 will be described with reference to FIGS. 2 and 3 as follows.

The liquid crystal display panel 300 includes a thin film transistor substrate 100 and a color filter substrate 200 facing each other, and a liquid crystal layer 260 positioned between both substrates 100 and 200.

First, in the thin film transistor substrate 100, gate wirings 121, 122, and 123 are formed on the first insulating substrate 111. The gate wirings 121, 122, and 123 may be a metal single layer or multiple layers. The gate wirings 121, 122, and 123 overlap the gate electrode 121 and the pixel electrode layer 151 of the thin film transistor T connected to the gate line 121 and the gate line 121 extending in the horizontal direction. It includes a common electrode line 123 to form a storage capacity.

On the first insulating substrate 111, a gate insulating layer 131 made of silicon nitride (SiNx) or the like covers the gate lines 121, 122, and 123.

A semiconductor layer 132 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 131 of the gate electrode 122, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 132. An ohmic contact layer 133 made of a material such as hydrogenated amorphous silicon is formed. The ohmic contact layer 133 is divided into two parts around the gate electrode 122.

Data lines 141, 142, and 143 are formed on the ohmic contact layer 133 and the gate insulating layer 131. The data lines 141, 142, and 143 may also be a single layer or multiple layers of a metal layer. The data wires 141, 142, and 143 are formed in a vertical direction and branch to the data line 141 and the data line 141 that cross the gate line 121 to form a pixel, and to the upper portion of the ohmic contact layer 133. The source electrode 143 which is separated from the extended drain electrode 142 and the drain electrode 142 and is formed on the ohmic contact layer 133 opposite to the drain electrode 142 with respect to the gate electrode 122. Include.

 The a-Si: C: O film or a-Si: O: F film and the acrylic organic insulating film deposited by silicon nitride and PECVD on the data wirings 141, 142, and 143 and the semiconductor layer 132 which are not covered by the semiconductor wires. A protective film 134 made of or the like is formed. In the passivation layer 134, a contact hole 161 exposing the source electrode 143 is formed.

The pixel electrode layer 151 is formed on the passivation layer 134. The pixel electrode layer 151 is generally made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The pixel electrode cut pattern 152 is formed on the pixel electrode layer 151. The pixel electrode cutting pattern 152 is formed to divide the liquid crystal layer 260 into a plurality of domains together with the common electrode cutting pattern 252 described later.

In the color filter substrate 200, a black matrix 221 is formed on the second insulating substrate 211. The black matrix 221 generally distinguishes between red, green, and blue filters, and serves to block direct light irradiation to the thin film transistor T positioned on the thin film transistor substrate 100. The black matrix 221 is usually made of a photosensitive organic material to which black pigment is added. As the black pigment, carbon black or titanium oxide is used.

The color filter layer 231 is formed by repeating the red, green, and blue filters on the black matrix 221. The color filter layer 231 serves to impart color to light emitted from the light source unit 400 and passed through the liquid crystal layer 260. The color filter layer 231 is usually made of a photosensitive organic material.

An overcoat layer 241 is formed on the black matrix 221 which is not covered by the color filter layer 231 and the color filter layer 231. The overcoat layer 241 serves to protect the color filter layer 231 while planarizing the color filter layer 231, and typically an acrylic epoxy material is used.

The common electrode layer 251 is formed on the overcoat layer 241. The common electrode layer 251 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode layer 251 directly applies a voltage to the liquid crystal layer 260 together with the pixel electrode layer 151 of the thin film transistor substrate. The common electrode cutout pattern 252 is formed on the common electrode layer 251. The common electrode cut pattern 252 divides the liquid crystal layer 260 into a plurality of domains together with the pixel electrode cut pattern 152 of the pixel electrode layer 151.

The pixel electrode cut pattern 152 and the common electrode cut pattern 252 may be formed in various shapes. For example, both the pixel electrode cutting pattern 152 and the common electrode cutting pattern 252 may be formed diagonally and orthogonally to each other.

The liquid crystal layer 260 is positioned between the thin film transistor substrate 100 and the color filter substrate 200. The liquid crystal layer 260 is a VA (vertically aligned) mode, and the liquid crystal molecules are vertical in the length direction when no voltage is applied. When voltage is applied, the liquid crystal molecules lie perpendicular to the electric field because the dielectric anisotropy is negative. However, when the pixel electrode incision pattern 152 and the common electrode incision pattern 252 are not formed, the liquid crystal molecules are arranged randomly in various directions because the azimuth angle of the lying down is not determined, and the foreground lines at the boundary planes having different orientation directions. ) The pixel electrode cut pattern 152 and the common electrode cut pattern 252 form a fringe field when a voltage is applied to the liquid crystal layer 260 to determine the azimuth angle of the liquid crystal alignment. In addition, the liquid crystal layer 260 is divided into multiple regions according to the arrangement of the pixel electrode cutting pattern 152 and the common electrode cutting pattern 252.

The driving voltage generator 700 generates a gate on voltage Von for turning on the thin film transistor T, a gate off voltage Voff for turning off the thin film transistor T, and a common voltage Vcom applied to the common electrode layer 251. do.

The gray voltage generator 800 generates a plurality of gray scale voltages related to the luminance of the liquid crystal display 1.

The gate driver 400 may also be referred to as a scan driver. The gate driver 400 may be connected to the gate line 121 and formed of a combination of a gate on voltage Von and a gate off voltage Voff from the driving voltage generator 700. Is applied to the gate line 121. The gate driver 400 may be connected to the liquid crystal panel 300 in a chip form or may be directly mounted on the liquid crystal panel 300. When directly mounted, the gate driver 400 is called a shift register.

The data driver 500 is also referred to as a source driver. The data driver 500 receives a gray voltage from the gray voltage generator 800 and selects a gray voltage according to the control of the signal controller 600 to select a data voltage on the data line 141. (Vd) is applied.

The signal controller 600 generates control signals for controlling operations of the gate driver 400, the data driver 500, the driving voltage generator 700, the gray voltage generator 800, and the like. ), The data driver 500, and the driving voltage generator 8000.

Hereinafter, the operation of the liquid crystal display device 1 will be described in detail.

The signal controller 600 controls an RGB gray level signal R, G, B and its display from an external graphic controller, for example, a vertical synchronizing signal. , Vsync), a horizontal synchronizing signal (Hsync), a main clock (CLK), and a data enable signal (DE). The signal controller 600 generates a gate control signal, a data control signal, and a voltage selection control signal (VSC) based on the control input signal, and outputs grayscale signals R, G, and B from the outside. After appropriately converting the display panel 300 according to the operating conditions, the gate control signal is sent to the gate driver 400 and the driving voltage generator 700, and the data control signal and the processed gray level signals R ', G', and B are processed. ') Is sent to the data driver 500, and the voltage selection control signal VSC is sent to the gray voltage generator 800.

The gate control signal includes a vertical synchronization start signal (STV) for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal for controlling the output timing of the gate-on pulse, and And a gate on enable signal (OE) that limits the width of the gate on pulse. Among them, the gate-on enable signal OE and the gate clock signal CPV are supplied to the driving voltage generator 700. The data control signal includes a horizontal synchronization start signal (STH) indicating the start of input of the gray scale signal and a load signal (load signal, LOAD or TP) for applying a corresponding data voltage Vd to the data line 141. And an inversion control signal RVS and a data clock signal HCLK for inverting the polarity of the data voltage.

First, the gray voltage generator 800 supplies a gray voltage having a voltage value determined according to the voltage selection control signal VSC to the data driver 500.

The gate driver 400 sequentially applies the gate-on voltage Von to the gate line 121 in the driving direction according to the gate control signal from the signal controller 600 to connect the thin film transistor T to the gate line 121. Turn on. At the same time, the data driver 500 controls the gray level signals R ', G', and B 'of the pixel 170 connected to the turned-on thin film transistor T according to the data control signal from the signal controller 600. The analog data voltage Vd from the gray voltage generator 800 corresponding to the data signal is supplied to the data line 141 as a data signal.

The data signal supplied to the data line 141 is applied to the pixel 170 through the turned-on thin film transistor T. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines 121 during one frame to apply the data signals to all the pixels 170. When one frame is finished and the inversion control signal RVS is supplied to the driving voltage generator 700 and the data driver 500, the polarities of all data signals of the next frame are changed.

The backlight unit 900 includes a light source unit 910, a power supply unit 920 for supplying power to the light source unit 910, and a light source control unit 930 for controlling the power supply unit 920.

The light source unit 910 includes k sub light sources 911 as shown in FIG. 4. The light source unit 910 corresponds to the liquid crystal panel 300 and is provided in a direct type. The sub light sources 911 extend in parallel with the gate line 121, that is, in the driving direction and the vertical direction, and are disposed in parallel with each other. In the first embodiment, the sub light source 911 includes a lamp and may be a cold cathode fluorescent lamp or an external electrode fluorescent lamp.

The power supply unit 920 may supply power for each sub light source 911, and may adjust the size of the supplied power. The light source controller 930 receives the horizontal synchronization start signal STH from the signal controller 600, and controls the power supply unit 920 such that the sub light source 911 is sequentially and repeatedly driven.

The liquid crystal display device 1 described above is a normally black mode, and the transmittance according to the pixel voltage is shown in FIG. 5. The change in transmittance at low gradations shown in part A of FIG. 5 is about three times more rapid than that of TN (twisted nematic) liquid crystal.

The gate line 121 receives a gate signal through the gate driver 400 connected to the end. A gate signal having a low delay is applied to a pixel adjacent to the gate driver 400, and a gate signal having a high delay is applied to a pixel far from the gate driver 400.

The larger the delay of the gate signal, the smaller the kickback voltage, and the greater the kickback voltage when the negative pixel voltage is applied than when the positive pixel voltage is applied. On the other hand, if the gate signal delay is large, the difference in kickback voltage between the positive pixel voltage and the negative pixel voltage is reduced.

Referring to FIGS. 6A and 6B, a kickback voltage is described for a first pixel having a small gate signal delay adjacent to the gate driver 400 and a second pixel having a large delay of the gate signal far from the gate driver 400. do.

In the case of the first pixel illustrated in FIG. 6A, for example, the kickback voltage is 1V when the positive pixel voltage is applied, and the kickback voltage is 1.2V when the negative pixel voltage is applied. In the case of the second pixel, the kickback voltage is 0.8V both when the positive pixel voltage is applied and when the negative pixel voltage is applied.

As a result, the root mean square voltage at which the first pixel finally remains in the pixel becomes larger. As shown in FIG. 5, in the low gray level, since the luminance difference is large according to the difference in pixel voltage, the left portion corresponding to the first pixel is recognized as whiter. Therefore, the brightness of the screen becomes uneven.

In the first embodiment of the present invention, the problem caused by the gate delay difference is reduced by driving the backlight unit 900. This will be described with reference to FIGS. 7 and 8.

Referring to FIG. 7, in one frame, the gate line 121 is sequentially turned from top to bottom in the driving direction according to the horizontal synchronization start signal STH. Accordingly, the pixels connected to the gate lines 121 also display the screen sequentially from the top to the bottom.

Referring to FIG. 8, each sub light source 911 is sequentially turned on in synchronization with a horizontal synchronization start signal. 8 illustrates only the sub light source 911 that is turned on. At this time, the brightness of each sub light source 911 increases according to the driving direction. That is, the luminance of the k-th sub-light source 911 that is turned on in synchronization with the n-th horizontal simultaneous start signal is higher than the luminance of the first sub-light source 911 that turns on in synchronization with the first horizontal synchronization start signal.

As such, the luminance of the light supplied by the backlight unit 900 in one frame is lower in the upper portion of the screen, and the luminance increases toward the lower portion of the screen. This reduces the nonuniformity of the screen brightness.

In the first embodiment, the single sub light source 911 may correspond to the plurality of adjacent gate lines 121. In this case, the light source controller 930 may be synchronized with all horizontal synchronization start signals, or may be synchronized with some horizontal synchronization start signals at regular intervals. When synchronized with all the horizontal synchronization start signals, the single sub light source 911 may provide different luminance according to the gate line 121.

A second embodiment of the present invention will be described with reference to FIG.

The light source unit 910 of the backlight unit 900 according to the second embodiment is not driven for each sub light source 911, and all the sub light sources 911 are always lit.

The light source controller 930 controls the power supply unit 920 so that the luminance of the light source unit 910 increases with time in synchronization with the STH signal within one frame.

In the above embodiment, the light source unit 910 includes a lamp, but in another embodiment, the light source unit 910 may include a light emitting diode.

The light emitting diode may have brightness controlled for each area parallel to the data line 141. The light source unit 910 may provide a low luminance on the left side of the screen adjacent to the gate driver 400, and may supply a high luminance as it moves away from the gate driver 400, thereby reducing non-uniformity of the screen luminance. As shown in the second embodiment, the light source unit 910 may be turned on regardless of driving of the liquid crystal panel 300.

Although embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that the present embodiments may be modified without departing from the spirit or principles of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

As described above, according to the present invention, a liquid crystal display device with uniform luminance is provided.

In addition, a method of driving a liquid crystal display device having a uniform brightness is provided.

Claims (8)

A liquid crystal display panel including a gate line and a data line, a signal controller for sequentially and repeatedly driving pixels of the liquid crystal display panel along a driving direction parallel to the data line, and a backlight unit positioned on a rear surface of the liquid crystal display panel. In the liquid crystal display device comprising: The backlight unit, A light source unit; A power supply unit supplying power to the light source unit; And a light source control unit for controlling the power supply unit so that the luminance of the light source unit increases with time in each frame. The method of claim 1, The light source unit includes a plurality of sub light sources parallel to the gate line, And the light source control unit controls the power supply unit to repeatedly drive the plurality of sub light sources. The method of claim 2, The signal controller inputs a horizontal synchronization start signal (STH) to the liquid crystal display panel. And the light source controller controls the power supply in synchronization with the horizontal synchronization start signal. The method according to any one of claims 1 to 3, The light source unit includes a lamp or a light emitting diode. The method according to any one of claims 1 to 3, The liquid crystal display panel comprises a liquid crystal layer of VA mode. A liquid crystal display panel including a gate line and a data line, a signal controller for sequentially and repeatedly driving pixels of the liquid crystal display panel along a driving direction parallel to the data line, and a backlight unit positioned on a rear surface of the liquid crystal display panel. In the method of driving a liquid crystal display device comprising: The backlight unit includes a light source unit, And controlling each of the backlight units so that the luminance of the light source unit increases with time in each frame. The method of claim 6, The light source unit includes a plurality of sub light sources parallel to the gate line, And the plurality of sub light sources are sequentially and repeatedly driven. The method of claim 7, wherein The signal controller inputs a horizontal synchronization start signal (STH) to the liquid crystal display panel. And the light source unit is driven in synchronization with the horizontal synchronization start signal.

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