KR20040033851A - A method for manufacturing a thin film transistor array panel - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and a method for manufacturing the same are provided to secure width of data lines by using an upper film as an etching barrier film for a lower film, thereby preventing an aperture ratio of a pixel from reducing. CONSTITUTION: A conductive film is accumulated on an insulation substrate, and then is patterned to form gate wiring including gate lines(121) and gate electrodes. A gate insulating film(140) and a semiconductor layer(150) are formed, a lower film(701) for data wiring and an upper film(702) for data wiring are accumulated. The upper film for data wiring is patterned by a photo etching process to form data lines(171). A photo sensitive film is applied and photo sensitive film patterns(212) are formed. A part of the photo sensitive film patterns is formed inside the upper film. The lower film for data wiring and the semiconductor layer are patterned by using the photo sensitive film patterns as etching masks and using and the upper film as barrier film to form data wiring including data line, source electrodes and drain electrodes(175). Pixel electrodes to be connected with the drain electrodes are formed.

Description

A thin film transistor array substrate and a method for manufacturing the same

The present invention relates to a method for manufacturing a thin film transistor array substrate, and more particularly, to a method for manufacturing a thin film transistor array substrate used as a substrate of a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In the liquid crystal display, in order to prevent signal delay, a gate wire or a data wire that transmits an image signal generally uses a low resistance material such as aluminum (Al) or an aluminum alloy (Al alloy) having a low resistance. Since it contacts with a silicon layer, chromium etc. which are excellent in fire resistance are added and used. In addition, the pixel electrode is formed using indium tin oxide (ITO) or the like, which is a transparent conductive material.

In the method of manufacturing the liquid crystal display, a substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. In this case, it is preferable to reduce the number of masks in order to reduce the production cost. To this end, a technique of completing a thin film transistor array substrate by forming two layers having different patterns by a photolithography process using one mask has been developed. .

However, in the manufacturing process of the thin film transistor array substrate, when one film is patterned, another film, which is a wiring, is also etched, thereby causing a problem in that the width of the wiring is reduced. In order to solve this problem, when the wiring width is designed to be wide, the aperture ratio of the pixel is reduced.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array substrate and a method of manufacturing the same, which can prevent the opening ratio from being reduced and ensure the width of wiring.

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array substrate shown in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor array substrate in a first step of manufacturing in accordance with an embodiment of the invention,

4B and 4C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

5A is a layout view of a thin film transistor array substrate showing the next step of FIG. 4A fabricated in accordance with an embodiment of the present invention;

5B and 5C are cross-sectional views taken along the lines Vb-Vb 'and Vc-Vc' in FIG. 5A, respectively.

6A and 6B are cross-sectional views taken along the lines Vb-Vb 'and Vc-Vc' of FIG. 5A, respectively, and are cross-sectional views of the next steps of FIGS. 5B and 5C;

FIG. 7A is a layout view of a thin film transistor array substrate in a subsequent step of FIGS. 5A to 5C;

7B and 7C are cross-sectional views taken along the lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively.

8A, 9A, 10A and 8B, 9B, 10B are cross-sectional views taken along the lines VIIb-VIIb 'and VIIc-VIIc' in Fig. 7A, respectively, illustrating the following steps in the order of the process; ,

11A is a layout view of a thin film transistor array substrate in the next step of FIGS. 10A and 10B;

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

In the thin film transistor array substrate and the manufacturing method thereof according to the present invention, the data line is formed as a double layer, but the upper layer is patterned first, and the upper layer is used as an etch stop layer so that the lower layer is not etched together with the photoresist pattern for patterning the lower layer.

More specifically, in the method for manufacturing a thin film transistor array substrate according to the present invention, a gate wiring including a gate line and a gate electrode is first formed on an insulating substrate, and a gate insulating film covering the gate wiring is laminated thereon. Next, a semiconductor layer is formed on the gate insulating layer, and the upper layer and the lower layer are patterned through different photolithography processes to form a data line including a data line, a source electrode, and a drain electrode. Next, a pixel electrode connected to the drain electrode is formed.

In this case, the photoresist pattern for patterning the lower layer may be formed on the upper layer after the upper layer is patterned, and the photoresist pattern positioned on the upper layer may be formed to be located inside the upper layer.

The lower film is preferably formed of chromium or molybdenum or molybdenum alloy, and the upper film is formed of aluminum or aluminum alloy.

In the thin film transistor array substrate completed through the manufacturing process according to the present invention, a gate wiring including a gate line and a gate electrode connected to the gate line is formed on the insulating substrate, and a semiconductor layer is formed on the gate insulating film covering the gate wiring. Is formed. The upper layer includes a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode around the gate electrode. The upper layer is patterned differently from the lower layer and the lower layer. The data wiring is formed, and the pixel electrode connected to the drain electrode is formed.

In this case, the lower layer may include molybdenum or molybdenum alloy or chromium, the upper layer may include aluminum or an aluminum alloy, and the data line may include both the upper layer and the lower layer, and the drain electrode may include only the lower layer.

The semiconductor device may further include a passivation layer formed between the data line and the pixel electrode. The semiconductor layer except for the channel portion between the source electrode and the drain electrode may have the same pattern as the lower layer of the data line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are along the II-II 'and III-III' lines of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

First, a gate wiring made of a conductive material having a low resistance such as aluminum or an aluminum alloy is formed on the insulating substrate 110 in a tapered structure. The gate line is connected to the gate line 121 and the gate line 121 which extend in the horizontal direction, so that the gate pad 125 and the gate line 121 receive a gate signal from the outside and transfer the gate signal to the gate line 121. ), The gate electrode 123 of the thin film transistor is connected. In addition, the upper part of the substrate 110 is connected to the sustain electrode line 131 and the sustain electrode line 131 which are parallel to the gate line 121 and receive a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The holding wiring including the electrode 133 is formed. The storage electrode 133 overlaps the drain electrode 175 connected to the pixel electrode 190, which will be described later, to form a storage capacitor that improves the charge retention capability of the pixel. The storage electrode 133 and the gate line 121 of the front end of the pixel electrode 190 will be described later. It may not be formed if the holding capacity generated by the overlap of is sufficient.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate wirings 121, 125, and 123 and the storage wirings 131 and 133 to form the gate wirings 121, 125, and 123 and the storage wirings 131 and 131, respectively. 133).

A semiconductor pattern 152 made of polycrystalline silicon or amorphous silicon is formed on the gate insulating layer 140, and amorphous silicon doped with a high concentration of n-type or p-type impurities such as phosphorus (P) on the semiconductor pattern 152. An ohmic contact layer pattern or intermediate layer patterns 163 and 165 are formed.

On the resistive contact layer patterns 163 and 165, a data line including a conductive film made of chromium, molybdenum or molybdenum alloy having good contact properties with other materials is formed in a tapered structure. The data line is a thin film transistor which is a branch of the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the data line 171. And a data line portion of the source electrode 173 of the source electrode 173, and separated from the data line portions 171, 179, and 173 of the source electrode 173 with respect to the gate electrode 123 or the channel portion C of the thin film transistor. The drain electrode 175 of the thin film transistor is disposed on the opposite side and extends to the upper portion of the sustain electrode 133. When the storage wirings 131 and 133 are not formed, the drain electrode 175 may not extend to the center portion of the pixel region. Here, although the drain electrode 175 extends to the upper portion of the storage electrode 133, a conductive pattern for a storage capacitor may be formed separately from the drain electrode 175 and connected to the pixel electrode.

In this case, the data wires 171, 173, 175, and 179 include a lower layer 701 made of molybdenum or molybdenum alloy or chromium and an upper layer 702 made of aluminum or aluminum alloy, and the upper layer 702 includes data. The line 171 is constituted. In FIG. 1, the upper film 702 is shown in a wide width, but as shown in FIG. 2, the upper film 702 and the lower film 701 disposed below the substantially same width.

The contact layer patterns 163 and 165 lower contact resistances of the semiconductor pattern 152 below and the data lines 171, 173, 175 and 179 thereon, and the data lines 171, 173 and 175. , 179). That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179, and 173, and the drain electrode intermediate layer pattern 165 is the same as the drain electrode 175.

The semiconductor pattern 152 has the same shape as the data lines 171, 173, 175 and 179 and the ohmic contact layer patterns 163 and 165 except for the channel portion C of the thin film transistor. Specifically, the semiconductor pattern 152 for thin film transistors is slightly different from the rest of the data wiring and contact layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern for the drain electrode. Although 165 is also separated, the semiconductor pattern 152 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

Low dielectric constant including an organic material having excellent planarization characteristics and a photosensitive property, or a-Si: C: O: H, on the data lines 171, 173, 175, and 179 and the semiconductor layer 152 not covered by the data lines. A protective film 180 of an insulating material is formed. Here, the passivation layer 180 may further include an insulating layer made of silicon nitride. In this case, the insulating layer may be disposed under the organic insulating layer to directly cover the channel portion of the semiconductor pattern 152. In addition, it is preferable to completely remove the organic insulating material from the pad portion in which the gate pad 125 and the data pad 179 are located. This structure is formed on the pad portion of the gate pad 125 and the data pad 179. The present invention is particularly advantageous when applied to a COG (chip on glass) type liquid crystal display device in which a gate driving integrated circuit and a data driving integrated circuit are directly mounted on the thin film transistor substrate so as to transfer scan signals and image signals, respectively.

The passivation layer 180 has contact holes 189 and 185 exposing the data pad 179 and the drain electrode 175 made of only a lower layer 701 made of a conductive material having excellent contact properties with other materials. Along with 140 is a contact hole 182 exposing the gate pad 125.

A pixel electrode 190 is formed on the passivation layer 180 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as indium zinc oxide (IZO) or indium tin oxide (ITO), and is connected to the drain electrode 175 through the contact hole 185 to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional.

Next, a method of manufacturing a thin film transistor array substrate for a liquid crystal display device having the structure of FIGS. 1 to 3 will be described in detail with reference to FIGS. 1 to 3 and FIGS. 4A to 11C.

First, as illustrated in FIGS. 4A to 4C, a conductive film made of aluminum or an aluminum alloy or a conductive film made of chromium or molybdenum or molybdenum alloy is further laminated and patterned by a photolithography process using a mask to form a gate line 121 and a gate. The gate wiring including the pad 125 and the gate electrode 123 and the storage wiring including the storage electrode line 131 and the storage electrode 133 are formed in a tapered structure. In this case, the photolithography process is patterned by wet etching, and the taper angle is preferably in the range of 30 to 80 °.

Next, as shown in FIGS. 5A to 5C, the chemical vapor deposition method is performed on the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 of undoped amorphous silicon, and the intermediate layer 160 of doped amorphous silicon. To 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, and 1400 kPa to 600 kPa, respectively. Subsequently, a data wiring lower layer 702 made of molybdenum or molybdenum alloy or chromium and a data wiring upper layer 702 of aluminum or aluminum alloy are sequentially stacked by sputtering or the like, and then used for data wiring by a photolithography process using a mask. Only the upper layer 702 is patterned to form the data line 171.

6A and 6B, the photoresist film 210 is applied on the upper portion of the data wiring lower layer 701 to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 210 is irradiated with light through a mask and then developed to form photoresist patterns 212 and 214 as shown in FIGS. 7B and 7C. At this time, the channel portion C of the photosensitive film patterns 212 and 214, that is, the first portion 214 positioned between the source electrode 173 and the drain electrode 175, is the data wiring portion A, that is, the data. The thickness of the wirings 171, 173, 175, and 179 is smaller than that of the second portion 212 positioned at the portion where the wirings 171, 173, 175, and 179 are to be formed. In this case, the second portion 212, which is the data wiring portion A, which is already patterned and formed on the upper layer 702 that forms part of the data line 171, is formed to have a narrower width than that of the upper layer 702. In an embodiment, the edge portion of the upper layer 701 may be exposed out of the second portion 212. The data line 171 uses the upper layer 702 as an etch stop layer when the lower layer 701 is patterned using the photoresist patterns 212 and 214 etched back in the subsequent process. This is to prevent the width of) from decreasing. This will be described in more detail later. In addition, the ratio of the thickness of the photoresist film 214 remaining in the channel part C and the thickness of the photoresist film 212 remaining in the data wiring part A should be different depending on the process conditions in an etching process which will be described later. It is preferable to make the thickness of the 1st part 214 into 1/2 or less of the thickness of the 2nd part 212, for example, it is good to be 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 214 and the underlying layers, that is, the lower layer 701 for data wiring, the intermediate layer 160, and the semiconductor layer 150. In this case, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the upper three layers 701, 160, 150 is removed to expose the gate insulating layer 140.

First, as shown in FIGS. 8A and 8B, the exposed lower layer 701 for data wiring of the other portion B is removed to expose the lower intermediate layer 160. In this process, a wet etching method or a dry etching method may be used. In this case, the data layer lower layer 701 may be etched and the photoresist patterns 212 and 214 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the data line lower layer 701 is etched and the photoresist patterns 212 and 214 are not etched, so that the photoresist patterns 212 and 214 may be etched together. In this case, the thickness of the first portion 214 is made thicker than that of the wet etching so that the first portion 214 is removed in this process so that the lower data wiring lower layer 701 is not exposed. At this time, as described above, the upper layer 702 for data wiring is also used as an etching mask to remove the lower layer 701 for data wiring that is not covered by the upper layer 702 for data wiring.

In this way, as shown in FIGS. 8A and 8B, only the data wiring lower layer 701 of the channel portion C and the data wiring portion A, that is, the source / drain lower layer 178 remains, and the other portion B is left. The lower layer 701 for data wiring is removed to reveal the intermediate layer 160 below. In this case, the remaining lower layer 178 is the same as that of the data lines 171, 173, 175, and 179 except that the source and drain electrodes 173 and 175 are connected without being separated, and dry etching is performed. In this case, the photoresist patterns 212 and 214 are also etched to some extent.

9A and 9B, the exposed intermediate layer 160 of the other portion B and the semiconductor layer 150 thereunder are simultaneously removed together with the first portion 214 of the photoresist film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 212 and 214 and the intermediate layer 160 and the semiconductor layer 150 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, it is preferable to etch under conditions in which the etching ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are the same, the thickness of the first portion 214 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 150 and the intermediate layer 160.

9A and 9B, the first portion 214 of the channel portion C is removed to reveal the source / drain conductor pattern 178, and the intermediate layer 160 of the other portion B is exposed. The semiconductor layer 150 is removed to expose the gate insulating layer 140 under the semiconductor layer 150. On the other hand, since the second portion 212 of the data line portion A is also etched, the thickness becomes thin. In this step, the semiconductor pattern 152 is completed. Reference numeral 168 denotes an intermediate layer pattern under the source / drain conductor patterns 178, respectively.

Subsequently, the photoresist residue left on the surface of the source / drain conductor pattern 178 of the channel part C is removed through an etch back process. In this case, the photoresist pattern 212 is partially removed. When the photo wiring pattern 212 having a reduced thickness and width is used as an etch mask to remove the lower layer 701 for data wiring, the width of the data line is reduced. In order to prevent this, as in the present invention, the data wiring conductive film is formed as a double film, and the data wiring upper film 702 is first patterned, and the data wiring lower film 701 constituting the data line 171 is patterned. By using the etching mask, it is possible to prevent the width of the data line 171 from being reduced.

Next, as illustrated in FIGS. 10A and 10B, the source / drain conductor pattern 178 of the channel portion C and the source / drain interlayer pattern 168 under the channel portion C are etched and removed. In this case, the etching may be performed only by dry etching for both the source / drain conductor pattern 178 and the intermediate layer pattern 168. For the source / drain conductor pattern 178, the etching solution may be used as described above. By wet etching, the intermediate layer pattern 168 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 178 and the interlayer pattern 168 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 152 remaining in the. Examples of the etching gas used to etch the intermediate layer pattern 168 and the semiconductor pattern 152 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} may leave the semiconductor pattern 152 with a uniform thickness. At this time, as shown in FIG. 10B, a portion of the semiconductor pattern 152 may be removed to reduce the thickness, and the second portion 212 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the photoresist pattern is formed so that the second portion 212 is etched so that the data lines 171, 173, 175, and 179 beneath it are not exposed. Of course, thick is preferable.

In this case, as shown in FIGS. 7A, 10A, and 10B, the source electrode 173 and the drain electrode 175 are separated from each other, and the data line 171, 173, 175, and 179 and the contact layer pattern 163 beneath it. 165) is completed.

Finally, the photosensitive film second portion 212 remaining in the data wiring portion A is removed. However, the removal of the second portion 212 may be performed after removing the conductor pattern 178 for the channel portion C source / drain and before removing the intermediate layer pattern 168 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data lines 171, 173, 175, and 179 in this manner, as illustrated in FIGS. 11A through 11C, silicon nitride is stacked or an organic material having excellent planarization characteristics and photosensitive properties is formed on the substrate 110. A protective film 180 is formed by depositing a low dielectric constant CVD film such as an a-Si: C: O film or an a-Si: O: F film by coating or coating a plasma enhanced chemical vapor deposition (PECVD) method. Subsequently, the passivation layer 180 is etched together with the gate insulating layer 140 by a photolithography process using a mask to expose the drain electrodes 175, the gate pads 125, and the data pads 179, respectively. 185 is formed into a tapered structure. At this time, the taper angle is preferably in the range of 30-80 °.

1 to 3, the pixel electrode 190 and the gate pad 125 which are connected to the drain electrode 175 by depositing IZO having a thickness of 500 to 1,000 Å and wet etching using a mask. ) And an auxiliary data pad 97 connected to the auxiliary gate pad 92 and a data pad 179.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, the data line is formed as a double layer, but the upper layer is patterned first, and the width of the data line can be secured by using the etch stop layer so that the lower layer is not etched thereafter, thereby preventing the aperture ratio of the pixel from being reduced. Can be.

Claims (9)

Insulation board, A gate line formed on the insulating substrate and including a gate line and a gate electrode connected to the gate line; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode around the gate electrode, the lower layer and the lower layer formed on the semiconductor layer. Data wiring having a top film patterned in a different shape from the film, A pixel electrode connected to the drain electrode Thin film transistor array substrate comprising a. In claim 1, The lower layer may include molybdenum or molybdenum alloy or chromium, and the upper layer may include aluminum or an aluminum alloy. In claim 1, The data line includes both the upper layer and the lower layer, and the drain electrode includes only the lower layer. In claim 1, And a passivation layer formed between the data line and the pixel electrode. In claim 1, The semiconductor layer except for the channel portion between the source electrode and the drain electrode has the same pattern as the lower layer of the data line. Forming a gate wiring including a gate line and a gate electrode on the substrate, Stacking a gate insulating film on the substrate; Forming a semiconductor layer on the gate insulating layer; Patterning an upper layer and a lower layer formed through different photolithography processes to form a data line including a data line, a source electrode, and a drain electrode; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array substrate comprising a. In claim 6, The lower layer is formed of chromium or molybdenum or molybdenum alloy, and the upper layer is formed of aluminum or aluminum alloy. In claim 6, And a photoresist pattern for patterning the lower layer is formed on the upper layer after patterning the upper layer. In claim 8, The photoresist pattern positioned on the upper layer is a method of manufacturing a thin film transistor substrate to form the upper layer inward.