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KR20030002624A - a method for manufacuring of semiconductor device - Google Patents

a method for manufacuring of semiconductor device Download PDF

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Publication number
KR20030002624A
KR20030002624A KR1020010038303A KR20010038303A KR20030002624A KR 20030002624 A KR20030002624 A KR 20030002624A KR 1020010038303 A KR1020010038303 A KR 1020010038303A KR 20010038303 A KR20010038303 A KR 20010038303A KR 20030002624 A KR20030002624 A KR 20030002624A
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South Korea
Prior art keywords
insulating film
semiconductor device
insulating layer
manufacturing
heat treatment
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KR1020010038303A
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Korean (ko)
Inventor
이동호
김연수
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주식회사 하이닉스반도체
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Priority to KR1020010038303A priority Critical patent/KR20030002624A/en
Publication of KR20030002624A publication Critical patent/KR20030002624A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A fabrication method of semiconductor devices is provided to improve RC-delay time of metal lines by using an inter-metal dielectric having a low permittivity. CONSTITUTION: Metal lines(102) are formed on a semiconductor substrate(101). After forming the first insulating layer(103) on the metal lines(102), the second insulating layer(104) is deposited on the first insulating layer. At this time, the second insulating layer(104) is made of an organic polymer containing carbon, such as polymide, polyether, and aromatic hydrocarbon. The second insulating layer(104) is then annealed at low temperature. After depositing the third insulating layer on the second insulating layer(104), the third insulating pattern(105a) having an air-gap(A) is formed by annealing at O2 atmosphere.

Description

반도체 소자의 제조방법{a method for manufacuring of semiconductor device}Method of manufacturing a semiconductor device {a method for manufacuring of semiconductor device}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 금속배선간 절연막의 유전율을 낮추어 금속배선의 RC-딜레이 타임(RC-Delay time)을 개선시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving the RC-delay time of metal wiring by lowering the dielectric constant of an insulating film between metal wirings.

현재 반도체 소자의 금속배선 절연막에 적용되고 있는 것은 CVD(Chemical Vapor Deposition:화학기상 증착법)방식의 실리콘 산화막(SiO)이 주류이다. 상기 실리콘 산화막을 이용한 금속배선간 절연막은 금속배선간 매립 및 유전체막 측면에서 문제가 있어 0.13㎛ 이하의 반도체 소자의 제조공정에 적용할 경우, 반도체 소자의 제품 특성에 악영항을 미친다.Currently, a silicon oxide film (SiO) of CVD (Chemical Vapor Deposition) method is mainly applied to the metallization insulating film of a semiconductor device. The inter-wire insulating film using the silicon oxide film has problems in the inter-wire interconnection and the dielectric film side, and when applied to the manufacturing process of the semiconductor device of 0.13㎛ or less, adversely affects the product characteristics of the semiconductor device.

이로 인해 유전율을 낮추는 절연막 및 금속배선간의 매립특성이 우수한 절연막의 증착방법 및 새로운 절연막 구조의 형성방법 등이 연구되고 있다.For this reason, a method of depositing an insulating film and a method of forming a new insulating film having excellent embedding properties between the insulating film and the metal wiring to lower the dielectric constant has been studied.

그러나 유전율을 4.0∼4.5로 낮춘 절연막 후보로는 아직 명확하게 결정된 것이 없으며 이러한 물질로 2.0∼3.5 정도의 유전율을 갖는 것이 주류여서 금속배선으로 쓰이는 물질과 상관관계를 고려해야하는 등 많은 문제점이 있다.However, as an insulating film candidate having a dielectric constant lowered to 4.0 to 4.5, it has not been clearly determined yet, and a dielectric constant of about 2.0 to 3.5 with such a material is mainstream. Therefore, there are many problems such as correlation with a material used for metal wiring.

상기와 같은 문제점을 해결하기 위하여 금속배선간 절연막을 유기물계 절연막으로 사용한 후, 산소열처리하여 RC-딜레이 타임을 개선시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the RC-delay time by using an oxygen insulating process between the metal wiring insulating film as an organic insulating film.

도 1a 내지 도 1b는 본 발명의 일실시예에 따른 반도체 소자의 제조방법을 나타낸 공정 단면도1A through 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 102 : 금속배선101: semiconductor substrate 102: metal wiring

103 : 제 1 절연막 104 : 유기물 계열의 제 2 절연막103: first insulating film 104: second organic insulating film

105 : 제 3 절연막 105a : 에어-갭을 갖는 제 3 절연막105: third insulating film 105a: third insulating film having air-gap

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판에 금속배선을 형성하는 단계와, 상기 금속배선상에 유기물계열의 제 1 절연막을 증착한 후, 저온 열처리하는 단계와, 상기 유기물계열의 제 1 절연막상에 제 2 절연막을 증착한 후, 산소열처리하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a metal wiring on a semiconductor substrate, depositing a first insulating film of an organic series on the metal wiring, and then performing a low temperature heat treatment; And depositing a second insulating film on the first insulating film of the organic material series, followed by oxygen heat treatment.

또한, 상기 유기물계열의 제 1 절연막은 탄소를 함유하는 폴리마이드(polymide), 폴리에테르(polyether), 아로매틱 하이드로우카본(aromatic hydrocarbon)과 같은 유기성 폴리머를 사용하는 것을 특징으로 한다.In addition, the first insulating film of the organic material series is characterized by using an organic polymer such as polymide (polymide), polyether (polyether), aromatic hydrocarbon (aromatic hydrocarbon) containing carbon.

또한, 상기 유기물계열의 제 1 절연막에 저온 열처리시 온도는 100∼250℃인것을 특징으로 한다.In addition, the low temperature heat treatment to the first insulating film of the organic series is characterized in that the temperature is 100 ~ 250 ℃.

또한, 상기 제 2 절연막에 산소열처리시 상기 제 1 절연막내의 탄소을 CO2의 형태로 외부로 확산시켜 에어-갭을 갖는 제 2 절연막을 형성하는 것을 특징으로 한다.In addition, during the oxygen heat treatment, the second insulating film having an air gap is formed by diffusing carbon in the first insulating film to the outside in the form of CO 2 .

또한, 상기 제 2 절연막은 350∼450℃ 온도에서 PECVD 계열의 실리콘 산화막을 증착하는 것을 특징으로 한다.In addition, the second insulating film is characterized in that the deposition of PECVD-based silicon oxide film at a temperature of 350 ~ 450 ℃.

또한, 상기 산소열처리시 온도는 400∼500℃인 것을 특징으로 한다.In addition, the temperature during the oxygen heat treatment is characterized in that 400 to 500 ℃.

상기 제 2 절연막은 500∼1000Å인 것을 특징으로 한다.The second insulating film is characterized by being 500 to 1000 kV.

이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 제조방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1b는 본 발명의 일실시예에 따른 반도체 소자의 제조방법을 나타낸 공정 단면도이다.1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 1a에 도시한 바와 같이 반도체 기판(101)에 일정간격을 갖는 금속배선(102)을 형성하고, 상기 금속배선(102)상에 제 1 절연막(103)을 형성한 후, 상기 제 1 절연막(103)상에 유기물계열의 제 2 절연막(104)을 증착한다. 이때, 상기 제 1 절연막(103)은 캡 산화막이고, 상기 유기물계열의 제 2 절연막(104)은 탄소를 함유하는 폴리마이드(polymide), 폴리에테르(polyether), 아로매틱 하이드로우카본(aromatic hydrocarbon)과 같은 유기성 폴리머를 사용한다.As shown in FIG. 1A, a metal wiring 102 having a predetermined interval is formed on the semiconductor substrate 101, a first insulating film 103 is formed on the metal wiring 102, and then the first insulating film ( The second insulating film 104 of the organic material series is deposited on the 103. In this case, the first insulating film 103 is a cap oxide film, the second insulating film 104 of the organic series is a polyamide (polymide), polyether (polyether), aromatic hydrocarbon (aromatic hydrocarbon) containing carbon Use organic polymers such as

이어, 상기 유기물계열의 제 2 절연막(104)에 100∼250℃의 온도로 저온 열처리한다. 이때, 저온 열처리 공정은 상기 유기물계열의 제 2 절연막(104)에 함유된 수분를 제거하기 위한 것이다.Subsequently, the organic insulating series second insulating film 104 is subjected to low temperature heat treatment at a temperature of 100 to 250 ° C. In this case, the low temperature heat treatment process is for removing moisture contained in the second insulating film 104 of the organic material series.

한편, 상기 제 2 절연막(104)에 저온 열처리 공정을 한 후, 에치백 공정을 이용하여 평탄화한다.On the other hand, the second insulating film 104 is subjected to a low temperature heat treatment process, and then planarized using an etch back process.

도 1b에 도시한 바와 같이 상기 제 2 절연막(104)상에 제 3 절연막(105)을 증착한 후, 산소분위기에서 400∼500℃로 열처리하여 상기 제 2 절연막(104)내에 함유되어 있는 탄소을 CO2형태로 외부로 확산(out-diffusion)시켜 에어-갭(air-gap) 즉, 얇은 보이드(A)을 갖는 제 3 절연막(105a)을 형성한다. 이때, 상기 제 3 절연막(105)은 500∼1000Å 두께의 PECVD 계열의 실리콘 산화막을 350∼450℃ 온도로 증착한다.As shown in FIG. 1B, the third insulating film 105 is deposited on the second insulating film 104, and then heat-treated at 400 to 500 ° C. in an oxygen atmosphere to deposit carbon contained in the second insulating film 104. The second insulating film 105a having an air-gap, ie, a thin void A, is formed by out-diffusion to the outside in two forms. At this time, the third insulating film 105 is deposited at a temperature of 350 ~ 450 ℃ PECVD series silicon oxide film of 500 ~ 1000Å thickness.

또한, 도면에는 도시하지 않았지만 절연막이 증착된 반도체 기판상에 유기물계열의 절연막을 증착하고, 캡 절연막 및 CMP 베리어층으로 실리콘 질화막을 증착한다. 그리고 상기 절연막상에 다마신 구조를 형성하고, 금속배선을 형성한 후, 산소열처리하여 절연막 내부에 에이-캡을 형성한다.Although not shown in the drawings, an organic material-based insulating film is deposited on a semiconductor substrate on which an insulating film is deposited, and a silicon nitride film is deposited using a cap insulating film and a CMP barrier layer. A damascene structure is formed on the insulating film, a metal wiring is formed, and oxygen heat treatment is performed to form an A-cap inside the insulating film.

이상에서 설명한 바와 같이 본 발명의 반도체 소자의 제조방법에 의하면, 추가 장비의 투자없이 향후 개발 예정인 고집적 반도체 소자의 절연막 제조공정에 적용이 가능하다.As described above, according to the method for manufacturing a semiconductor device of the present invention, it can be applied to an insulating film manufacturing process of a highly integrated semiconductor device, which will be developed in the future without investing additional equipment.

그리고 우수한 동작특성을 갖는 금속배선 구조의 형성이 가능하므로 우수한제품 특성 및 신뢰성을 갖는 제품개발이 가능하다.And since it is possible to form a metal wiring structure having excellent operating characteristics it is possible to develop a product having excellent product characteristics and reliability.

또한, 다마신 구조의 금속배선 형성에 적용할 경우 금속배선의 특성이 우수하여 신뢰성 및 수율을 향상시킬 수 있다.In addition, when applied to the metal wiring formation of the damascene structure, it is excellent in the characteristics of the metal wiring can improve the reliability and yield.

Claims (7)

반도체 기판에 금속배선을 형성하는 단계와;Forming a metal wiring on the semiconductor substrate; 상기 금속배선상에 유기물계열의 제 1 절연막을 증착한 후, 저온 열처리하는 단계와;Depositing a first insulating film of an organic series on the metal wiring, and then performing a low temperature heat treatment; 상기 유기물계열의 제 1 절연막상에 제 2 절연막을 증착한 후, 산소열처리하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And depositing a second insulating film on the first insulating film of the organic material series, followed by oxygen heat treatment. 제 1 항에 있어서,The method of claim 1, 상기 유기물계열의 제 1 절연막은 탄소를 함유하는 폴리마이드(polymide), 폴리에테르(polyether), 아로매틱 하이드로우카본(aromatic hydrocarbon)과 같은 유기성 폴리머를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The first insulating film of the organic material series is a method of manufacturing a semiconductor device, characterized in that it uses an organic polymer such as polymide (polymide), polyether (polyether), aromatic hydrocarbon (aromatic hydrocarbon) containing carbon. 제 1 항에 있어서,The method of claim 1, 상기 유기물계열의 제 1 절연막에 저온 열처리시 온도는 100∼250℃인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that the temperature during the low temperature heat treatment to the first insulating film of the organic material series is 100 ~ 250 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막에 산소열처리시 상기 제 1 절연막내의 탄소을 CO2의 형태로 외부로 확산시켜 에어-갭을 갖는 제 2 절연막을 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And forming a second insulating film having an air-gap by diffusing carbon in the first insulating film to the outside in the form of CO 2 when the oxygen heat treatment is performed on the second insulating film. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막은 350∼450℃ 온도에서 PECVD 계열의 실리콘 산화막을 증착하는 것을 특징으로 하는 반도체 소자의 제조방법.The second insulating film is a semiconductor device manufacturing method, characterized in that for depositing a PECVD-based silicon oxide film at a temperature of 350 ~ 450 ℃. 제 1 항에 있어서,The method of claim 1, 상기 산소열처리시 온도는 400∼500℃인 것을 특징으로 하는 반도체 소자의 제조방법.The temperature of the oxygen heat treatment is a manufacturing method of a semiconductor device, characterized in that 400 ~ 500 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막은 500∼1000Å인 것을 특징으로 하는 반도체 소자의 제조방법.The second insulating film is a manufacturing method of a semiconductor device, characterized in that 500 to 1000 Å.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100688758B1 (en) * 2002-12-30 2007-02-28 동부일렉트로닉스 주식회사 Method for forming gap fill of metal line for semiconductor
KR100778867B1 (en) * 2006-07-24 2007-11-22 동부일렉트로닉스 주식회사 Manufacturing method of a semiconductor device with a low-k dielectric layer
KR100927777B1 (en) * 2007-10-05 2009-11-20 주식회사 하이닉스반도체 Manufacturing Method of Memory Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100688758B1 (en) * 2002-12-30 2007-02-28 동부일렉트로닉스 주식회사 Method for forming gap fill of metal line for semiconductor
KR100778867B1 (en) * 2006-07-24 2007-11-22 동부일렉트로닉스 주식회사 Manufacturing method of a semiconductor device with a low-k dielectric layer
KR100927777B1 (en) * 2007-10-05 2009-11-20 주식회사 하이닉스반도체 Manufacturing Method of Memory Device

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