KR20010065036A - a method of fabricating the array substrate for TFT type liquid crystal display device - Google Patents

Abstract

PURPOSE: A method for fabricating an array substrate for a thin film transistor liquid crystal display(TFT LCD) is provided to prevent a disconnection of a data line generated in a cross part crossing with a gate line. CONSTITUTION: A thin film transistor including a gate electrode(110) and an active channel layer(116) and a source electrode(117) and a drain electrode(118) is formed on a point where a data line(119) overlapped with an active line(128) crosses with a gate line(113). The disconnection of the data line is prevented by extending it along one direction from the active channel layer and by reducing a step between both sides(B,C) of the gate line by forming the width of the active line of a part(D) crossing with the gate line wider than the width of the data line. The array substrate includes a substrate, and a plurality of gate lines on the substrate, and the first insulation layer on an upper part of the gate line, and the active channel layer, and the drain electrode.

Description

A method of fabricating the array substrate for TFT type liquid crystal display device}

The present invention relates to a thin film transistor type liquid crystal display (TFT-LCD), and more particularly, to a method for manufacturing an array substrate for a liquid crystal display device including a data line and a gate line. .

In general, a liquid crystal display may be largely divided into a display part and a pad part.

The display unit is a liquid crystal panel (LC panel) and consists of two transparent substrates interposed between liquid crystals. A common electrode is formed on one substrate of the liquid crystal panel, and the other substrate is an array substrate. A plurality of thin film transistors that drive each pixel is formed corresponding to the pixel Pixel.

The pad part includes a gate pad for applying a signal voltage to the gate wiring and a source pad for applying a data voltage to the source wiring. In general, the gate pads are configured to be in contact with both sides of the display unit, and the source pads are configured to be in contact with one side not facing the gate pad.

In order to form the above-described array substrate, each element is formed while repeating deposition, photolithography, and etching for each process.

1 is a plan view showing a part of a conventional array substrate for a liquid crystal display device.

As shown in the drawing, the array substrate for a liquid crystal display device transmits a data signal to the pixel P, the gate wiring 13 which transmits a scanning signal to the pixel, and the pixel electrode 35 positioned on the pixel region P. And a switching element A formed at the intersection of the gate wiring 13 and the data wiring 19. The switching device is a device composed of a composite material by depositing and patterning a plurality of materials, generally using a thin film transistor as the switching device.

A gate pad 11 having a predetermined area is formed at one end of the gate wiring 13. In addition, data pads 15a and 15b having a predetermined area are formed at one end of the data line 13.

The thin film transistor is planarly spaced apart from the source electrode 17 and the source electrode 17 which protrude and extend from a portion of the gate electrode 10 connected to the gate line 13 and the data line 19. The drain electrode 18 is formed.

In addition, an active channel layer 16 overlapping the source electrode 17, the drain electrode 18, and the gate electrode 10 to serve as a channel is formed, and the active channel layer 16 includes the data wiring ( It extends below 19 and overlaps the data line 19 with a width smaller than that of the data line, which is referred to as an active line 28.

In this case, the data wiring of the portion F where the active line is not patterned among the portions F intersecting with the gate wiring is patterned in the photolithography process due to the height of the etched active line 28 and the side step difference of the gate wiring. Lifting phenomenon occurs in the F portion of the photoresist portion, and eventually, an etchant penetrates into the lower portion of the photoresist to overetch the lower portion of the data wiring metal layer 19, which causes a pattern defect of the data wiring 19. do.

A manufacturing process of the array substrate having such a configuration will be described below with reference to FIGS. 2A to 2E.

2A to 2E are cross-sectional views illustrating the process steps of cutting along the lines II-II and III-III of FIG. 1, respectively.

First, a first conductive metal layer is formed on the glass substrate 11 by depositing aluminum (Al) or an aluminum alloy and a conductive metal such as molybdenum (Mo), tantalum (Ta), tungsten (W), or antimony (Sb). .

Next, as shown in FIG. 2A, the first conductive metal layer is patterned by a first mask process to form a gate electrode 13 and a gate electrode protruding from the gate wiring 13 in a predetermined area in one direction. 10) form.

Next, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiO _x ) is deposited on the entire surface of the substrate 11 on which the gate electrode 10 and the gate wiring 13 are formed, or in some cases BCB (BenzoCycloButene) ) Or an organic insulating material such as an acrylic resin is applied to form the first insulating layer 12.

Next, a semiconductor material such as pure amorphous silicon (n + a-Si) and amorphous silicon to which impurities are added are sequentially deposited on the first insulating layer 12 to form a semiconductor layer and an impurity semiconductor layer.

Next, as shown in FIG. 2B, the impurity semiconductor layer and the active layer are patterned by a second mask process to extend in one direction from the channel layer and the channel layer formed on the gate electrode and the gate wiring. An active line 28 is formed to intersect vertically.

The active line 28 is a buffer layer to mitigate an unstable interface state between the first insulating layer 12 and a data line to be formed later, and between the first insulating layer and a data line 19 to be formed later. It is formed interposed.

The impurity semiconductor layer and the underlying semiconductor layer are patterned to form an ohmic contact layer 16a planarly overlapping the active layer channel layer 16 and the active line 28.

Next, a second conductive metal layer is formed by depositing a metal such as chromium (Cr) or chromium alloy on the entire surface of the substrate on which the active channel layer 16 is formed.

Next, as shown in FIG. 2C, the second conductive metal layer is patterned by a third mask process, and the source electrode 17 and the drain electrode 18 spaced apart from each other by a predetermined distance on the active channel layer 16. The data line 19 extends from the source electrode and overlaps the active line 28 formed in the one direction, and crosses the gate line 13 to form a data line 19 defining the pixel region P.

Next, an inorganic insulating film such as silicon nitride film (SiNx) or silicon oxide film (SiO ₂ ), or the like, is deposited on the entire surface of the substrate on which the data line and the source electrode are formed. An organic insulating material such as resin is applied to form a protective layer 31 which is a second insulating layer.

Next, as shown in FIG. 2D, the protective layer 31 is patterned by a fourth mask process to form a drain contact hole 33 on the drain electrode 18.

Next, as shown in FIG. 2E, indium-tin-oxide (ITO) and indium-zinc-oxide are formed on the entire surface of the substrate on which the drain contact hole 33 is formed. : Deposit a transparent conductive metal such as IZO and pattern it in a fifth mask process to form a pixel electrode 35 in contact with the drain electrode 18 through the drain contact hole 33 and positioned on the pixel region. do.

At this time, the line width of the active line 28 is formed to be narrower than the line width of the data line 19. Accordingly, the data line passing through the intersection portion F with the gate line is affected by the step difference between the height of the active line 28 including the ohmic contact layer and the height of the gate line 13.

That is, as described with reference to FIG. 1, the data line 19 of the intersection portion F is patterned in the photolithography process under the influence of the height of the etched active line 28 and the side step difference of the gate line 13. Lifting phenomenon occurs at the intersection portion F of the photoresist portion, and the etching solution penetrates into the lower portion of the photoresist, and the pattern of the data wiring 19 due to the excessive etching of the data wiring metal layer 19 thereunder. Problems can occur that are defective.

Accordingly, an object of the present invention is to propose a method of manufacturing an array substrate for a liquid crystal display device for preventing disconnection of data lines occurring at intersections intersecting the gate lines.

1 is a plan view showing a part of a conventional liquid crystal display array substrate;

2A to 2E are process cross-sectional views cut along the lines II-II and III-III of FIG. 1,

3 is a plan view showing a portion of a liquid crystal display array substrate according to the first embodiment of the present invention;

4A to 4B are enlarged cross-sectional views each illustrating A of FIG. 3.

<Brief description of the main parts of the drawing>

110: gate electrode 113: data wiring

116 active channel layer 117 source electrode

118: drain electrode 119: gate wiring

128: active line

According to an aspect of the present invention, a method for manufacturing an array substrate for a liquid crystal display device includes: a substrate; A plurality of gate wirings on the substrate; A first insulating layer on the gate wiring; An active layer which extends in one direction on the first insulating layer and extends in one direction and has a large area of the portion intersecting the gate wiring, and an active channel layer protruding from the active layer on the gate electrode; ; And a data line overlapping the active layer planarly on the active layer, a source electrode protruding from the data line above the active channel, and a drain electrode spaced apart from the predetermined distance.

Preferably, the active layer is formed by increasing the area of the active layer on one side of the gate line and the other side of the active layer crossing the gate line.

Preferably, the active layer is formed by branching from one side of the gate line and the other side of the gate line at a portion crossing the gate line.

Preferably, the active layer is characterized in that the semiconductor material.

The present invention is to solve the above-mentioned problems by increasing the area of the active line below the data line at the intersection of the data line and the gate line.

Since the manufacturing process of the present invention is the same as the above-described process sequence of Figures 2a to 2e will be omitted and will be described a preferred embodiment according to the present invention with reference to the plan view.

3 is a plan view illustrating an intersection of a gate wiring and a data wiring formed on the array substrate for a liquid crystal display according to the present invention.

As shown, the gate electrode 110, the active channel layer 116, the source electrode 117, and the drain at the intersection of the data line 119 and the gate line 113 overlapping the active line 128 planarly. The thin film transistor including the electrode 118 is configured.

In this case, the width of the active line 128 of the portion D extending in one direction from the active channel layer 116 and intersecting the gate line 113 is greater than the width of the data line 119. In addition, the gate wiring 113 serves to prevent disconnection of the data line by reducing the step difference between both sides B and C as much as possible.

The shape of the active line crossing the gate line may be variously modified.

The various modifications will be described below with reference to FIGS. 4A and 4B.

4A and 4B are enlarged views illustrating D of FIG. 3.

As shown in FIG. 4A, an area of the active line 128 passing through the stepped portions of both sides B and C of the gate wiring 113 among the portions where the gate wiring 113 and the data wiring 119 cross each other. Only can form wide.

Alternatively, as shown in FIG. 4B, the active line 128 at the portion where the gate line 113 and the data line 119 cross each other is branched from the portion passing through the step of the gate line 113. Can be formed.

By using these various modifications, the conventional data wiring disconnection problem can be solved.

Therefore, as described above, in the liquid crystal display array substrate according to the present invention, the area of the active line where the gate line and the data line intersect is formed to be larger than the area of the data line formed to overlap the active line in plan view. By preventing the disconnection of the data line at the intersection with the gate line, there is an effect of reducing the process defect and improving the yield of the product.

Claims (4)

A substrate; A plurality of gate wirings on the substrate; A first insulating layer on the gate wiring; An active layer which extends in one direction on the first insulating layer and extends in one direction and has a large area of the portion intersecting the gate wiring, and an active channel layer protruding from the active layer on the gate electrode; ; A data line overlapping the active layer planarly on the active layer, a source electrode protruding from the data line above the active channel, and a drain electrode spaced apart from the predetermined distance Array substrate for a liquid crystal display device comprising a. The method of claim 1, And an active substrate having a larger area of the active layer on one side of the gate line and the other side of the active layer crossing the gate line. The method of claim 1, And the active layer is formed by branching from one side of the gate line and the other side of the gate line at a portion crossing the gate line. The method of claim 1, And the active layer is a semiconductor material.