KR20010010027A - Method for forming trench isolation - Google Patents

Abstract

PURPOSE: A method for forming a trench isolation layer is provided to prevent a dent, generating between a trench isolation layer and an upper substrate. CONSTITUTION: A pad oxide layer(212) is formed on a semiconductor substrate(210). The first HTO(High temperature Oxide layer)(214), a silicon nitride layer, and an ARC(Anti-reflective Coating layer) are deposited by sequence on the pad oxide layer(212). By etching the ARC, the silicon nitride layer, and the first HTO(214), an opening is made. Using the ARC as a mask, the pad oxide layer(212) and the substrate(210) are etched, and a trench is built. An oxide layer(222) is vaporized inside of the substrate of the trench through a heat oxidization method. A liner(224) covers the whole substrate(210) including the trench. A trench isolation layer(226) is doped on the substrate(210) for filling up the trench. To expose the silicon nitride layer, the trench isolation layer(226), the liner(224), and the ARC are flattened by a CMP(Chemical Mechanical Polishing) method or a dry etch back step and the ARC is removed. Through a strip process, the silicon nitride layer and the liner are removed. When removing the liner, the liner is overetched and recessed, and a dent(D) is formed between the first HTO(214) and the trench isolation layer(226). The second HTO is vaporized on the whole substrate(210), and reclaims the dent(D). The second and the first HTO is erased with the dent(D) using a wet etch step.

Description

How to Form Trench Isolation {METHOD FOR FORMING TRENCH ISOLATION}

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of forming trench isolation.

As semiconductor integration increases, design rules are becoming smaller than sub-quarter microns (0.25 μm). With high integration, problems such as maintaining and increasing capacitor capacity and isolation between devices are on the rise. In particular, isolation between devices already shows limitations of the conventional LOCOS (LOCal Oxidation of Silicon) method, but most of them use the shallow trench isolation (STI) method. Shallow trench isolation is a method of digging a substrate in an isolation region and filling it with an insulating film.

1A and 1B are cross-sectional views illustrating a trench forming method and a problem in a conventional semiconductor memory device.

Referring to FIG. 1A, a pad oxide film 112, a silicon nitride film 114, and an anti-reflective coating (ARC) film (not shown) are sequentially formed on the semiconductor substrate 110. The ARC film and the silicon nitride film 114 are etched through the photolithography process to form a trench etching mask. Since the pad oxide layer 112 and the substrate 110 are etched using the trench etch mask, trenches are formed in the substrate 110.

An oxide film 116 is formed on the inner wall of the trench. The liner 118 is deposited on the entire surface of the substrate 110 including the trench. A trench isolation layer 120 is deposited on the entire surface of the substrate 110 to fill the trench. The trench isolation layer 120, the liner 118, and the ARC layer are planarized and etched to expose the silicon nitride layer 114.

Referring to FIG. 1B, the silicon nitride film 114 is removed. At this time, since the liner 118 is made of the same material as the silicon nitride film 114, the liner 118 is simultaneously etched. Since overetching is performed to completely remove the silicon nitride film 114, the liner 118 is also etched and recessed. In other words, a groove is formed between the substrate 110 and the trench isolation layer 120 by etching below the upper surface of the substrate 110. This groove is called the dent (D).

The dent (D) generates a hump (hum) in the transistor to reduce the activity of the DRAM (Dynamic Random Access Memory), a problem of gate poly bridge (gate poly bridge) of the gate formed in the trench isolation layer and Problems with the threshold voltage down of the transistor may occur.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a trench isolation formation method capable of preventing dents generated between the trench isolation layer and the upper portion of the substrate.

1A and 1B are cross-sectional views illustrating problems and methods of forming a conventional trench isolation;

2A through 2F are cross-sectional views sequentially illustrating a manufacturing process of a trench isolation forming method according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

110. 210: semiconductor substrate 112, 212: pad oxide film

214: first HTO film 114, 216 silicon nitride film

218: ARC film 220: opening

116, 222: oxide film 118, 224: liner

120, 226: trench isolation 228: second HTO film

First, second, third and fourth insulating films are sequentially formed on the semiconductor substrate. The fourth, third and second insulating layers are etched through the photolithography process to form a trench etch mask. The trench is etched using the trench etch mask to form a trench in the substrate. An oxide film is formed on the inner wall of the trench. The liner is deposited on the entire surface of the substrate including the trench. A fifth insulating film is deposited on the entire surface of the substrate to fill the trench. The fifth and fourth insulating layers are planarized and etched to expose the upper surface of the third insulating layer. The third insulating layer is removed through a wet etching process. A sixth insulating film is deposited on the second insulating film. The sixth and second insulating layers are removed to expose the first insulating layer. The first insulating film is removed.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2F.

In the novel trench isolation formation method of the present invention, a first HTO film having an etch selectivity is deposited before silicon nitride film deposition. When the silicon nitride film is removed, the reeler is etched but not below the first HTO film. A second HTO film is deposited on the entire surface of the substrate. Next, the second and first HTO film is removed. This results in trench isolation without dents.

2A through 2F are cross-sectional views sequentially illustrating a method of forming trench isolation according to an embodiment of the present invention.

Referring to FIG. 2A, a pad oxide film 212 is formed on the semiconductor substrate 210. The pad oxide film 212 is formed in a thickness range of 70-240 kPa through a thermal oxidation process. A first HTO film (High Temperature Oxide layer) is deposited on the pad oxide film 212 to a thickness of about 300 kPa at a temperature of about 900 ° C. An oxide layer having an etching selectivity with a subsequent silicon nitride layer 214 may be used instead of the first HTO layer 214. A silicon nitride film 216 is deposited on the first HTO film 214. An ARC film (Anti-Reflective Coating layer) 218 is formed on the silicon nitride film 214. The ARC film 218 is formed by a TiN, SiON, SiC, and a carbon-based polymer (200-1000 Å thickness range). The ARC film 218 is an antireflection film for preventing patterning tolerance that may occur due to diffuse reflection of light at the time of exposure, thereby improving the patterning accuracy of the photoresist film during the subsequent photographing process.

Referring to FIG. 2B, the ARC film 218, the silicon nitride film 216, and the first HTO film 214 are etched through a photographic process to form an opening 220.

Referring to FIG. 2C, the ARC layer 218 is used as a mask to etch the pad oxide layer 212 and the substrate 210 to form a trench. Through the thermal oxidation process, the substrate 210 of the inner wall of the trench is oxidized to form an oxide film 222. The oxide film is formed to a thickness of about 100 GPa and serves to prevent damage to the substrate 210, for example, dislocation, which may occur during a subsequent process. A liner 224 is deposited on the entire surface of the substrate 210 including the trench. The liner 224 is formed with a silicon nitride film (Si ₃ N ₄ ) or a silicon rich nitride film (Si ₄ N ₄ ) to a thickness of about 100 kPa by a low pressure chemical vapor deposition (LPCVD) method. The liner 224 prevents the semiconductor substrate 210 of the inner wall of the trench from being oxidized and reduces stress applied to the substrate 210. A trench isolation layer 226 is deposited on the entire surface of the substrate 210 to fill the trench. The trench isolation layer 226 may be formed of a material having good filling characteristics, such as a USG film by LPCVD, a boron phosphorus silicate glass (BPSG) film, or a phosphorus silicate glass (PSG) film by a reflow method. And an HDP oxide film by HDP (High Density Plasma) method.

As shown in FIG. 2D, the trench isolation layer 226, the liner 224, and the ARC layer 218 are planarized and etched to expose the silicon nitride layer 216. The planarization etching is performed through a chemical mechanical polishing (CMP) method or a dry etch back method. The ARC film 218 is removed by the planarization process.

Referring to FIG. 2E, the silicon nitride film 216 is etched and removed through a strip process. Phosphoric acid (H ₃ PO ₄ ) is used as the strip solution. At this time, since the liner 224 is made of the same material as the silicon nitride film 216, the liner 224 is simultaneously etched. In this process, the liner 224 is overetched and recessed. That is, a dent D is formed between the first HTO layer 214 and the trench isolation layer 226 by etching down further than the silicon nitride layer 216. A second HTO film 228 is deposited on the entire surface of the substrate 210. At this time, the second HTO film 228 is filled in the dent (D).

Referring to FIG. 2F, the second and first HTO layers 228 and 214 are removed through a wet etch process. The wet etching solution is HF and D.I. Deionized water mixed solution is used. In the process, the dent (D) is also removed. At this time, the trench isolation layer 226 and the liner 224 may be slightly etched. However, the liner 224 is not recessed below the top surface of the substrate 210. Next, since the pad oxide layer 212 is removed, trench isolation without dents is formed.

According to the present invention, since the HTO film is deposited before the silicon nitride film is deposited, the HTO film is removed after the silicon nitride film is removed, and the HTO films are removed, there is an effect of preventing dents generated between the trench isolation layer and the substrate.

Claims (3)

A method for forming trench isolation in semiconductor devices; Forming a first insulating film 214 having a predetermined thickness or more on the entire surface of the semiconductor substrate 210; Forming a second insulating film (216) on the first insulating film (214); Sequentially removing portions of the first and second insulating films (214, 216) and forming trenches in the exposed semiconductor substrate (210); Forming a third insulating film 224 having a predetermined thickness on a surface of the trench; Filling the trench with an insulating material (226) having an etching selectivity different from that of the third insulating film (224); Removing the second insulating film (216) completely such that the third insulating film (224) is at a higher position than the surface of the semiconductor substrate (210). The method of claim 1, And depositing a fourth insulating film on the entire surface of the substrate (210) and then removing the fourth insulating film together with the first insulating film. The method of claim 2, And the first and fourth insulating layers (212, 228) are HTO films having an etching selectivity with the second and third insulating layers (216, 224) and having a thickness of 100 GPa or more.