KR20000000580A - Nonvolatile semiconductor memory device and operating method thereof - Google Patents

Abstract

PURPOSE: A NAND-type flash EEPROM(Electrically Erasable Programmable Read Only Memory) is provided to prevent a leakage current through a field transistor by applying a negative voltage to a word line. CONSTITUTION: The NAND-type EEPROM comprises memory cell arrays(MC1-MC16) arranged a matrix structure, a plurality of bit lines common connected to a drain of the memory cells, and a plurality of word lines connected to a control gate of the memory cells. The operating method of the EEPROM comprises the steps of: applying a negative voltage to a selective word line; applying a voltage more than 0V to a selective bit line; applying 0V to a non-selective bit line, a source line, a bulk selective line and a ground selective line; and applying a voltage more than 0V to a string selective line and a non-selective word line.

Description

Nonvolatile semiconductor memory device and operation method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of operating the same, and more particularly, to a NAND flash EPIROM device and a method of operating the same.

In general, a semiconductor memory device may be classified into a volatile memory device in which data is largely lost over time and a nonvolatile memory device in which data stored once is retained even if time passes. In this non-volatile memory device, the EPyrom (Electrically Programmable Read Only Memory) can electrically program data, but in order to erase the programmed data, it is cumbersome to separate the chip from the board and scan ultraviolet light. . Accordingly, the flash Y pyrom which can compensate for the disadvantage of the above pyramid and electrically program and erase the data was introduced in IEDM P.464 in 1984. The flash Y pyrom cell is a device that can be electrically erased at high speed even without being separated from the circuit board. The structure of the flash Y pyrom cell is simple, and the manufacturing cost per unit memory is low, and the refresh operation for long-term data retention is unnecessary. In this field, the demand is gradually increasing.

The flash Y pyrom can be divided into NAND type and NOA type according to the cell connected to the bit line. In the NOA type flash Y pyrom, each cell is paralleled between the bit line and the ground line, and one contact is formed per two cells. As it is disadvantageous for high integration, the cell current is high, which has the advantage of high speed.NAND-type flash Y pyrom has a little disadvantage in terms of high-speed operation compared to the Noah type, but multiple cells are connected in series and share one contact. It is very advantageous in terms of high integration.

The NAND flash Y pyrom device includes a bit line, a word line, and a source line having unit cells each having a stacked gate having a structure in which a floating gate and a control gate are stacked. Are connected to form a cell array. In particular, the NAND flash Y pyrom cell array structure with multiple word lines between the bit line and the source line is described in 1990 symposium on VLSI circuits pp105-106, entitled "A 4-Mbit nand eeprom with tight programmed vt distribution." The vertical cross-sectional structural diagram and equivalent circuit diagram thereof are shown in FIGS. 1 and 2.

1 and 2, a typical NAND type flash EEPROM cell array includes a string select transistor (SST) for selecting a unit string and a ground select transistor (GST) for selecting ground. ), A plurality of memory cell transistors MC1, ..., MC16 having a structure in which a floating gate 18 and a control gate 22 are stacked between each other are configured in series to form a string. . The string is connected to a plurality of bit lines (B / L1, B / L2, ...) in parallel to form a block, and the blocks are symmetrically arranged around the bit line contacts. . The transistors are arranged in a matrix of rows and columns, and the gates of the string select transistor SST and the ground select transistor GST arranged in the same columns are respectively a string select line SSL and a ground select line ground. select line (GSL). In addition, the gates of the memory cell transistors MC1, ..., MC16 arranged in the same columns are connected to corresponding word lines W / L1, ..., W / L16. A bit line B / L is connected to a drain of the string select transistor SST, and a common source line CSL is connected to a source of the ground select transistor GST.

The memory cell transistors MC1,..., MC16 have a floating 18 formed on the semiconductor substrate 10 on which the N well 12 and the pocket pewell 14 regions are formed through a tunnel oxide film 16, and an upper portion of the floating gate 18. The control gates 22 formed through the interlayer dielectric film 20 are stacked. The floating gate 18 is formed over the active region and a portion of the edge of the field region on both sides of the active region to be isolated from the floating gate 18 of the neighboring cell transistor. The control gate 22 includes a floating gate 18 independently formed with a field region therebetween to be connected to the control gate 22 of a neighboring cell transistor to form a word line.

Since the select transistors SST and GST do not require a floating gate for storing data, the metal line may be connected to the floating gate 18 and the control gate 22 through a butting contact 23 above the field region in the cell array. Connect with Thus, the selection transistors are electrically operated as MOS transistors having a single gate.

The bias conditions applied to operate the NAND type flash EEPROM device having the above-described structure are shown in Table 1 below.

erase program read B / L1 Floating 0 V 0.7V B / L2 Floating Vpi 0 V SSL Vers Vpass Vcc W / Ln 0 V Vpass Vcc W / L3 0 V Vpgm 0 V GSL Vers 0 V Vcc CSL Floating 0 V 0 V BULK Vers 0 V 0 V

First, referring to Table 1, a program operation of an EPROM cell will be described. A voltage of 0 V is applied to a bit line connected to the selected cell transistor A and a program voltage Vpgm is applied to a word line connected to the selected cell transistor A. Thus, electrons in the channel region are injected into the floating gate by Fowler-Nordheim (FN) tunneling due to a high voltage difference between the channel region of the cell transistor and the control gate. At this time, a pass voltage (Vpgm) for transferring data (0V) applied to the selected bit line to the selected cell transistor A in a word line connected to an unselected cell transistor among a plurality of memory cells located between the bit line and the ground node. Is applied. At this time, the threshold voltage of the selected cell transistor A is changed to a positive voltage.

The erase operation removes electrons stored in the floating gate. When an erase voltage of about 20 V is applied to the bulk and OV is applied to a word line connected to the selected cell transistor A, the erase operation is performed in the opposite direction to the program operation. The electrons stored in the floating gate are erased by the electric field by the erase voltage Verase, and holes are injected. By the erase operation, the initial state of the cell transistor has a threshold voltage of about -3V.

The read operation is a word selected using a threshold voltage Vth of + 1V when electrons are stored in the cell transistor and a threshold voltage of -3V when holes are stored in the cell transistor. 0V is applied to the line to read data of "0" or "1" depending on whether or not a current path is formed through the selected cell transistor.

In the above operation, it can be seen that the cell array is configured in the pocket pewell 14 region to separate the voltage of about 20V applied to the bulk during the erasing from the bulk operation region of the peripheral circuit. However, in the cell operation, a Vpi voltage of about 7V is applied to the bit line while the cell connected to the select word line of the unselected bit line B / L2 is applied to the bit line, while 0V is applied to the selected bit line and 18V applied to the word line. When the device isolation region between cells is insufficient due to the high Vpgm voltage inside and outside, a field transistor is formed in which the unselected bit line voltage generates a leakage current to the selected bit line. As a result, the bit line voltage of the unselected cells is lowered, which may cause disturbances in which the unselected cells are programmed.

As a method for solving the above problem, there is a method of lowering the word line voltage Vpgm of the field transistor or increasing the thickness of the field oxide film, or increasing the concentration of the bulk region under the field oxide film. However, since the word line voltage of the field transistor is determined by the tunneling field, it is very difficult to control the voltage. The method of increasing the thickness of the field oxide film is increased by the bird's beak in the LOCOS process or the PBL process, which is an improved LOCOS process. Since the field oxide film is greatly increased, it is impossible to solve the problem without increasing the cell area. In addition, the method of increasing the bulk concentration under the field oxide film has a problem in that the breakdown voltage of the PN junction must be lowered since the depletion region decreases according to the voltage applied between the n + diffusion region and the silicon substrate to which the bit line voltage is applied. There is an urgent need for a better solution that can prevent disturbance of selected cells.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of preventing leakage current through a field transistor due to a voltage applied to a word line during a program operation.

It is still another object of the present invention to provide an improved program operation method capable of preventing leakage current through a field transistor due to a voltage applied to a word line during a program operation.

In order to achieve the above objects, the present invention provides a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with a drain of the memory cells, and a control gate of the memory cells. CLAIMS What is claimed is: 1. A method of programming a nonvolatile memory device having a plurality of word lines coupled with a method, comprising: applying a negative voltage to a selected word line; Applying a voltage of at least 0V to the select bit line; Applying 0V to the unselected bit lines, source lines, bulk and ground select lines; And applying a voltage of 0V or more to the string select line and the unselected word line.

In order to achieve the above object, the present invention provides a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with the drains of the memory cells, and control of the memory cells. 10. A nonvolatile memory device having a plurality of word lines connected to a gate thereof; The drain region of the memory cell has an N + structure, the source region has a low doping drain structure consisting of N− and N +, and the source and drain regions of the string select line and the ground select line have an N + structure. A nonvolatile memory device is provided.

In order to achieve the above object, the present invention provides a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with the drains of the memory cells, and control of the memory cells. 10. A nonvolatile memory device having a plurality of word lines connected to a gate thereof; The drain region of the memory cell has an N + structure, and the source and drain regions of the source region, the string selection line, and the ground selection line of the cell have a low doping drain structure consisting of N− and N +. Provided is a volatile memory device.

In order to achieve the above object, the present invention provides a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with the drains of the memory cells, and control of the memory cells. 10. A nonvolatile memory device having a plurality of word lines connected to a gate thereof; The drain region and the source region of the memory cell have an N + structure, and the source and drain regions of the string select line and the ground select line have a low doping drain structure consisting of N − and N +. To provide.

1 is a cross-sectional view showing the vertical structure of the cell array of the NAND flash Y pyrom device manufactured according to the conventional method

2 is an equivalent circuit diagram according to FIG.

3A to 3D are cross-sectional views in a bit line direction for explaining a manufacturing process of a cell according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a cell transistor fabrication process of a NAND flash easy pyrom device according to an embodiment of the present invention.

First, FIG. 3A illustrates a step of ion implantation of n + impurity 118 into the drain region of the semiconductor substrate 100 where the enwell 102 and pocket pewell 104 regions are formed. The tunnel oxide layer 106, the floating gate 108, the interlayer dielectric layer 110, and the control gate 112 are sequentially stacked to form the stacked gate 114 to form the memory cell transistors MC1, ..., MC16, and then there is no need for a floating gate for storing data. A string select transistor and a ground select transistor connect the floating gate 108 and the control gate 112 with a metal line through a butting contact 113 above the field region in the cell array. After the stacked gate 114 is formed, an ion implantation process of implanting n + impurity 118 into only the drain region of the memory cell is performed. In this case, in order to implant the n + impurity 118 only into the drain region of the memory cell, the first photosensitive film 116 may be selectively formed, and then an ion implantation process may be performed.

3B illustrates ion implantation of n- impurity 120 on the entire surface of the semiconductor substrate 100. After removing the photoresist 116, an ion implanted with n- impurity 120 is implanted into the entire upper surface of the semiconductor substrate 100. As a result of the implantation of the n− impurity 120, the n + region formed in the n + impurity 118 ion implantation step remains as it is, and the n− region is formed only in the region not exposed by the photosensitive film 116.

3C illustrates a step of forming spacers 122 on both sidewalls of the stacked gate 114 and then ion implanting n + impurity 126 into the source region. In the present invention, spacers 122 are formed on both sidewalls of the stacked gate 114 to form a lightly doped drain (LDD) structure. Then, the second photosensitive film 124 is partially formed only in the drain region, and then n + impurity 126 is implanted. As a result of the ion implantation, since the n + impurity 126 is not implanted in the region covered with the spacer 122, an LDD structure is formed in which the n− impurity region exists only under the spacer 122.

3D illustrates forming an insulating film 128 and a metal film 130 to complete a cell according to an embodiment of the present invention. The second photosensitive layer 124 which functions as an ion implantation mask for implanting n + impurity 126 into the spacer 122 and the source region formed to form the LDD structure is removed.

The NAND flash Y pyrom device completed by the above process is the same as the equivalent circuit diagram of the NAND flash Y pyrom device according to the conventional method shown in FIG. 2 according to the present invention with reference to FIG. The operation of the cell will be described. In the cell operating method according to the present invention, the read operation is performed in the same manner as in the conventional art, but during the program operation, the electrons in the floating gate are discharged in bulk to lower the Vth of the cell to -3 V. It is characterized by increasing the Vth of the cell to + 1V by injecting. In more detail, the erase operation applies a program voltage of about 18V to all selected word lines and 0V to all bit lines, sources, and bulk regions. As a result, electrons are injected into the floating gate in the bulk region by an electric field formed between the floating gate and the bulk substrate, thereby increasing the Vth of the cell. At this time, since all the cell of the word line to which the program voltage Vpgm is applied are erased at the same time, it can be seen that no inter-cell field transistor is formed. Such a word-line erase method is standardized and used in a specific erase unit as in the conventional art. Thereafter, the operation of selectively programming a cell may apply a voltage of about -10V to -15V to a select word line, a voltage of about 3V to 7V to a select bit line, and apply 0V to an unselected bit line, a source, and a bulk region. The electrons in the floating gate are discharged to the n + drain diffusion region through the tunnel oxide layer by the electric field between the floating gate and the n + drain diffusion region by the word line voltage and the bit line voltage of the selected cell, thereby reducing the cell Vth to around -3V. do. In this case, a pass voltage Vpass of about 5 V to 10 V is applied to the string select line and the word line between the select word line and the string select line so that the bit line voltage is applied to the drain diffusion region of the select cell. Such a program operation may eliminate a leakage current generated in the field transistor by the program voltage Vpgm applied to the word line. That is, in the related art, a high voltage of about + 18V is induced on a word line, thereby inverting the p-type bulk substrate region under the field oxide to n-type, thereby turning on the channel of the field transistor. Since the p-type bulk substrate region under the field oxide film is applied to the p-type, the channel of the field transistor is always in the off state, thereby solving the problem of the field transistor. In addition, the thickness of the conventional field oxide film can be further lowered, thereby facilitating the reduction of the cell area for high density memory fabrication.

As described above, according to the present invention, since the p-type bulk substrate region under the field oxide film is accumulated in the p-type by applying a negative voltage to the word line, the channel of the field transistor is always kept off, thereby preventing leakage current through the field transistor. There is an effect that is solved.

Claims (7)

A nonvolatile memory having a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with drains of the memory cells, and a plurality of word lines connected with control gates of the memory cells In the programming operation of the memory device: Applying a negative voltage to the selected word line; Applying a voltage of at least 0V to the select bit line; Applying 0V to the unselected bit lines, source lines, bulk and ground select lines; And applying a voltage of at least 0V to the string select line and the unselected word line. 2. The method of claim 1 wherein the voltage applied to the select word line is between about -10 and -15 volts. 3. The method of claim 2 wherein the voltage applied to the select bit line is between about 3V and 7V. 4. The method of claim 3, wherein the voltage applied to the string select line and the unselected word line is between about 5V and about 10V. A nonvolatile memory having a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with drains of the memory cells, and a plurality of word lines connected with control gates of the memory cells In the memory device: The drain region of the memory cell has an N + structure, the source region has a low doping drain structure consisting of N− and N +, and the source and drain regions of the string select line and the ground select line have an N + structure. Nonvolatile memory device. A nonvolatile memory having a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with drains of the memory cells, and a plurality of word lines connected with control gates of the memory cells In the memory device: The drain region of the memory cell has an N + structure, and the source and drain regions of the source region, the string selection line, and the ground selection line of the cell have a low doping drain structure consisting of N− and N +. Volatile memory device. A nonvolatile memory having a memory cell array in which a plurality of memory cells are formed in a matrix form, a plurality of bit lines connected in common with drains of the memory cells, and a plurality of word lines connected with control gates of the memory cells In the memory device: The drain region and the source region of the memory cell have an N + structure, and the source and drain regions of the string select line and the ground select line have a low doping drain structure consisting of N − and N +. .