KR19990005811A - FET gate oxide film formation method - Google Patents
FET gate oxide film formation method Download PDFInfo
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- KR19990005811A KR19990005811A KR1019970030029A KR19970030029A KR19990005811A KR 19990005811 A KR19990005811 A KR 19990005811A KR 1019970030029 A KR1019970030029 A KR 1019970030029A KR 19970030029 A KR19970030029 A KR 19970030029A KR 19990005811 A KR19990005811 A KR 19990005811A
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 title 1
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 239000000460 chlorine Substances 0.000 claims description 7
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- -1 chlorine ions Chemical class 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 13
- 230000003647 oxidation Effects 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
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- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 FET의 게이트 산화막 형성방법에 관한 것으로서, 본 발명의 목적은 FET에서 다른 두께를 갖는 게이트 산화막을 형성할 때 게이트 산화막 형성부분에 이온을 주입하여 이온에 따른 산화속도를 달리함으로서 두께가 다른 산화막을 형성하는 FET의 게이트 산화막 형성방법을 제공함에 있다. 상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판위에 게이트가 형성될 영역에만 이온이 주입되도록 하기 위한 마스크를 형성하는 단계와, 형성된 마스크의 노출부분으로 이온을 주입하는 단계와, 상기 결과물을 산화시켜 산화막을 형성하는 단계로 이루어져 한번의 산화공정으로 두께가 다른 게이트 산화막을 형성함으로서 다수번의 산화에 의한 산화막의 열화를 방지할 수 있어 트랜지스터의 특성을 향상시킬 수 있다는 이점이 있다.The present invention relates to a method for forming a gate oxide film of a FET, and an object of the present invention is to inject ions into the gate oxide film forming portion when the gate oxide film having a different thickness is formed in the FET, thereby varying the oxidation rate according to the ions. A method of forming a gate oxide film of a FET for forming an oxide film is provided. According to an aspect of the present invention, there is provided a mask for implanting ions only into a region where a gate is to be formed on a silicon substrate, implanting ions into an exposed portion of the formed mask, and oxidizing the resultant. By forming a gate oxide film having a different thickness in one oxidation process, the oxide film can be prevented from deterioration of the oxide film due to a plurality of oxidations, thereby improving the characteristics of the transistor.
Description
본 발명은 FET의 게이트 산화막 형성방법에 관한 것으로서, 보다 상세하게는 FET에서 다른 두께를 갖는 게이트 산화막을 형성할 때 게이트 산화막 형성부분에 이온을 주입하여 이온에 따른 산화속도를 달리함으로서 두께가 다른 산화막을 형성하는 FET의 게이트 산화막 형성방법에 관한 것이다.The present invention relates to a method of forming a gate oxide film of a FET, and more particularly, to form a gate oxide film having a different thickness in the FET, by implanting ions into the gate oxide film forming portion to vary the oxidation rate according to the ions, and thus having different thicknesses A method of forming a gate oxide film of a FET for forming a FET.
FET(Field-Effect Transistor; 전계효과 트랜지스터)라 함은 다수 캐리어가 반도체 표면을 따라서 드리프트 하는 것을 게이트 전계에 의해 제어하는 방식의 트랜지스터를 말하는 것으로서 소수캐리어의 주입이 없으므로 축적효과에 의한 응답 속도의 저하가 없고, 잡음이 적은 장점이 있다. 전계효과 트랜지스터에는 게이트의 구조에 의해 접합형 전계효과 트랜지스터(Junction Field-Effect Transistor ; JFET)와 쇼트키 장벽 게이트형 및 절연 게이트형 전계효과 트랜지스터(Insulator Gate Field Effect Transistor ; IGFET)가 있다.FET (Field-Effect Transistor) refers to a transistor in which a majority of carriers drift along the semiconductor surface by a gate electric field, and there is no injection of a small number of carriers, thereby reducing the response speed due to the accumulation effect. There is no noise and low noise. Field effect transistors include junction field-effect transistors (JFETs) and Schottky barrier gate type and insulator gate field effect transistors (IGFETs) by gate structures.
상기 절연 게이트형 전계효과 트랜지스터는 절연막을 삽입하고 게이트 전극을 설치한 구조의 전계효과 트랜지스터로 절연물 층에는 SiO2, Al2O3, Si3N4가 사용된다. 특히 절연막으로 SiO2막을 쓴 것을 MOSFET(Metal Oxide Semiconductor FET)라 부른다. 이러한 형태의 FET는 접합형에 비해 게이트 입력임피던스가 훨씬 더 크고, 확산공정이 1회로 간단하고, 소자간의 분리가 필요없다는 등의 장점을 갖고 있기 때문에 고밀도 집적화에 적합한 특징을 갖고 있다.The insulated gate field effect transistor is a field effect transistor having a structure in which an insulating film is inserted and a gate electrode is used, and SiO 2 , Al 2 O 3 , and Si 3 N 4 are used as the insulator layer. In particular, the SiO 2 film used as the insulating film is called a MOSFET (Metal Oxide Semiconductor FET). This type of FET is suitable for high-density integration because it has advantages such as a much larger gate input impedance, a simple diffusion process, and no separation between devices than a junction type.
도1은 종래의 게이트 산화막 형성방법에 따라 MOSFET의 형성공정중 게이트(40)가 형성되는 단계까지를 나타낸 단면도이다.1 is a cross-sectional view showing a step of forming a gate 40 in a MOSFET forming process according to a conventional gate oxide film forming method.
도1의 (a)는 실리콘 기판(10)위에 절연막으로 SiO2의 산화막(20)을 형성한 상태를 나타낸 단면도이다.FIG. 1A is a cross-sectional view illustrating a state in which an oxide film 20 of SiO 2 is formed as an insulating film on a silicon substrate 10.
도1의 (b)는 도1의 (a)에서 형성된 산화막(20)위에 게이트(40)가 형성될 부분 즉, 산화막(20)의 두께를 두껍게 형성시킬 부분을 제외한 나머지 부분을 식각하기 위해 감광막을 형성한 상태를 나타낸 단면도이다.FIG. 1B is a photosensitive film for etching the remaining portion except for a portion where the gate 40 is to be formed on the oxide film 20 formed in FIG. 1A, that is, a portion in which the thickness of the oxide film 20 is to be formed thick. It is sectional drawing which showed the state formed.
도1의 (c)는 도1의 (b)의 감광막 마스크(30)를 이용하여 선택적으로 식각하여 게이트(40)가 형성될 부분만 남겨놓은 상태를 나타낸 단면도이다.FIG. 1C is a cross-sectional view illustrating a state in which only a portion where the gate 40 is to be formed is left by selectively etching using the photoresist mask 30 of FIG. 1B.
도1의 (d)는 도1의 (c)의 결과물을 다시 산화시켜 두께가 다른 게이트(40) 산화막(20)을 형성한 상태를 나타낸 단면도이다.FIG. 1D is a cross-sectional view showing a state in which the oxide film 20 having a different thickness is formed by oxidizing the resultant product of FIG. 1C again.
도1의 (e)는 도1의 (d)에서 형성된 게이트(40) 산화막(20)위에 게이트(40)를 형성한 상태를 나타낸 단면도이다.FIG. 1E is a cross-sectional view illustrating a state in which the gate 40 is formed on the gate 40 oxide film 20 formed in FIG. 1D.
이와 같은 방법으로 형성된 FET의 게이트(40) 산화막(20)을 사용할 때 얇은 쪽의 게이트(40) 산화막(20)은 한번 산화되어 아무런 문제가 발생하지 않으나 게이트(40)가 형성된 두꺼운 쪽의 산화막(20)은 산화가 두번 이루어져 산화막(20)이 열화되기 쉽기 때문에 열화되어 특성저하가 발생될 수 있다는 문제점이 있다.When the gate 40 oxide film 20 of the FET formed in this manner is used, the thin gate 40 oxide film 20 is oxidized once so that no problem occurs, but the thick oxide film having the gate 40 formed thereon ( 20) there is a problem in that the oxidation is performed twice, so that the oxide film 20 is easily deteriorated, thereby deteriorating and deteriorating characteristics.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 FET의 게이트가 형성될 부분에 이온을 주입하여 이온에 따른 산화속도를 달리함으로서 두께가 다른 게이트 산화막을 형성하는 FET의 게이트 산화막 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to inject ions into a portion where a gate of the FET is to be formed, thereby varying the oxidation rate according to the ions, thereby forming a gate oxide film having a different thickness. A method of forming a gate oxide film is provided.
도1은 종래의 게이트 산화막 형성방법에 따른 공정을 단계적으로 나타낸 단면도이다.1 is a cross-sectional view illustrating a process according to a conventional method of forming a gate oxide film in stages.
도2는 본 발명에 의한 게이트 산화막 형성방법에 따른 공정을 단계적으로 나타낸 단면도이다.2 is a cross-sectional view showing a step in a process according to the method for forming a gate oxide film according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10 : 기판 20 : 산화막10 substrate 20 oxide film
30 : 마스크 40 : 게이트30 mask 40 gate
상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판위에 게이트가 형성될 영역에만 이온이 주입되도록 하기 위한 마스크를 형성하는 단계와, 형성된 마스크의 노출부분으로 이온을 주입하는 단계와, 상기 결과물을 산화시켜 산화막을 형성하는 단계로 이루어진다.According to an aspect of the present invention, there is provided a mask for implanting ions only into a region where a gate is to be formed on a silicon substrate, implanting ions into an exposed portion of the formed mask, and oxidizing the resultant. To form an oxide film.
상기와 같은 방법으로 게이트 산화막을 형성하면 한번의 산화로 두께가 다른 게이트 산화막이 형성된다. 즉, 이온이 주입된 부분은 산화속도가 이온이 주입되지 않은 부분보다 빠르기 때문에 같은 시간 만큼 산화를 시켰을 때 이온이 주입된 부분은 산화막이 두껍게 형성되고 이온이 주입되지 않은 부분은 산화막이 얇게 형성된다.When the gate oxide film is formed in the same manner as described above, a gate oxide film having a different thickness is formed by one oxidation. That is, since the portion of the ion implanted is faster than the portion without the ion implantation, when the oxidation is performed for the same time, the portion where the ion is implanted is formed with a thick oxide film, and the portion where the ion is not implanted is formed with a thin oxide film. .
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2는 본 발명에 의한 게이트(40) 산화막(20) 형성방법으로 FET를 형성하는 공정중 게이트(40)가 형성되는 공정까지를 나타낸 단면도이다.2 is a cross-sectional view showing a process of forming a gate 40 and forming a gate FET in the method of forming a gate 40 oxide film 20 according to the present invention.
도2의 (a)는 실리콘 기판(10)위에 이온을 주입할 부분만이 오픈된 마스크(30)를 형성한 상태를 나타낸 단면도이다.FIG. 2A is a cross-sectional view illustrating a state in which a mask 30 in which only a portion to inject ions is opened is formed on the silicon substrate 10.
도2의 (b)는 도2의 (a)에서 형성된 마스크(30)의 오픈된 부분에 염소(Cl) 이온을 주입하여 실리콘 기판(10)의 농도를 변화시킨다.In FIG. 2B, chlorine (Cl) ions are implanted into the open portion of the mask 30 formed in FIG. 2A to change the concentration of the silicon substrate 10.
본 실시예에서 특히 사용한 염소이온은 산화막(20) 내에 존재하여 산화막(20)의 특성을 저하시키는 Na+, K+ 등과 반응하여 안정한 NaCl이나 KCl으로 변환되어 산화막(20)의 특성을 향상시키게 된다.The chlorine ions particularly used in the present embodiment react with Na + and K +, which are present in the oxide film 20 to reduce the properties of the oxide film 20, and are converted into stable NaCl or KCl to improve the properties of the oxide film 20.
도2의 (c)는 도2의 (b)에서 염소 이온이 주입된 실리콘 기판(10)을 산화시켜 농도가 변화되어 산화속도가 빨라져 이온이 주입된 부분은 산화막(20)이 두껍게 형성된 상태를 나타낸 단면도이다.FIG. 2 (c) shows a state in which the oxide film 20 is thickly formed in the portion in which ions are implanted by oxidizing the silicon substrate 10 into which chlorine ions are implanted in FIG. It is sectional drawing shown.
산화막(20)을 형성시킬 때 성장시키는 온도와 산화시키기 전의 온도를 어느정도 올려 어닐링(Annealing)시킴으로서 이온주입에 의한 산화막(20)의 형성 두께 증가를 조절할 수 있다.When the oxide film 20 is formed, the growth temperature and the temperature before oxidation are raised to some extent to anneal, thereby controlling the increase in the thickness of the oxide film 20 formed by ion implantation.
예를 들면, 동일한 양의 염소(Cl) 이온이 주입된 웨이퍼를 산화시킬 때 더 낮은 온도에서 산화시킬수록 이온주입에 의한 두께증가 효과가 크게 된다. 또한 산화시키기전에 설정온도를 일정온도 올려 어닐링시키면 어닐링 온도가 높을수록 두께증가 효과가 적게된다.For example, when oxidizing a wafer into which the same amount of chlorine (Cl) ions are implanted, the oxidization at a lower temperature increases the effect of increasing the thickness by ion implantation. In addition, if the annealing is raised by a predetermined temperature before oxidation, the higher the annealing temperature, the smaller the effect of increasing the thickness.
이와 같은 방법을 이용하면 게이트(40)가 형성될 부분의 두께와 다른 부분의 산화막(20) 두께를 조절할 수 있다.Using this method, the thickness of the portion where the gate 40 is to be formed and the thickness of the oxide film 20 in the other portion can be adjusted.
도2의 (d)는 도2의 (c)에서 형성된 게이트(40) 산화막(20)에 게이트(40)를 형성한 상태를 나타낸 단면도이다.FIG. 2D is a cross-sectional view illustrating a state in which the gate 40 is formed on the gate 40 oxide film 20 formed in FIG. 2C.
그런다음 소오스와 드레인을 형성할 영역의 산화막(20)을 부분식각하여 소오스와 드레인을 형성하여 FET를 형성하게 된다.Then, the oxide film 20 in the region where the source and the drain are to be formed is partially etched to form the source and the drain to form the FET.
상기한 바와 같이 본 발명은 FET의 게이트 산화막의 형성시 게이트가 형성될 부분의 실리콘 기판에 이온을 주입하여 산화속도를 다르게 하여 산화막을 형성함으로서 한번의 산화공정으로 두께가 다른 게이트 산화막을 형성할 수 있게 되어 다수번에 의한 산화막의 열화에 의한 특성저하을 방지할 수 있다는 이점이 있다.As described above, in the present invention, when the gate oxide film of the FET is formed, the oxide film is formed by implanting ions into the silicon substrate of the portion where the gate is to be formed to vary the oxidation rate, thereby forming a gate oxide film having a different thickness in one oxidation process. There is an advantage that it is possible to prevent the deterioration of characteristics due to the deterioration of the oxide film by a number of times.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970030029A KR19990005811A (en) | 1997-06-30 | 1997-06-30 | FET gate oxide film formation method |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970030029A KR19990005811A (en) | 1997-06-30 | 1997-06-30 | FET gate oxide film formation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200298275A1 (en) * | 2019-03-20 | 2020-09-24 | Korea Institute Of Science And Technology | Capacitive micromachined ultrasonic transducer and method of fabricating the same |
| KR20210126423A (en) | 2020-04-10 | 2021-10-20 | 주식회사 오성전자 | Remote controller with waterproof structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0340431A (en) * | 1989-07-07 | 1991-02-21 | Fuji Electric Co Ltd | Formation of oxide film of silicon semiconductor device |
| JPH05198808A (en) * | 1991-11-22 | 1993-08-06 | Toshiba Corp | Thin film transistor and manufacturing method thereof |
| JPH08236640A (en) * | 1994-11-30 | 1996-09-13 | At & T Corp | Process of forming gate oxides with different thickness on semiconductor substrate |
-
1997
- 1997-06-30 KR KR1019970030029A patent/KR19990005811A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0340431A (en) * | 1989-07-07 | 1991-02-21 | Fuji Electric Co Ltd | Formation of oxide film of silicon semiconductor device |
| JPH05198808A (en) * | 1991-11-22 | 1993-08-06 | Toshiba Corp | Thin film transistor and manufacturing method thereof |
| JPH08236640A (en) * | 1994-11-30 | 1996-09-13 | At & T Corp | Process of forming gate oxides with different thickness on semiconductor substrate |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200298275A1 (en) * | 2019-03-20 | 2020-09-24 | Korea Institute Of Science And Technology | Capacitive micromachined ultrasonic transducer and method of fabricating the same |
| KR20200112027A (en) * | 2019-03-20 | 2020-10-05 | 한국과학기술연구원 | Capacitive Micromachined Ultrasonic Transducer and method of fabricating the same |
| US11944998B2 (en) | 2019-03-20 | 2024-04-02 | Korea Institute Of Science And Technology | Capacitive micromachined ultrasonic transducer and method of fabricating the same |
| KR20210126423A (en) | 2020-04-10 | 2021-10-20 | 주식회사 오성전자 | Remote controller with waterproof structure |
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