KR102680914B1 - Method for predicting occurrence of defects in epitaxial silicon wafers and method for manufacturing epitaxial silicon wafers - Google Patents

Abstract

A method for predicting the occurrence of defects (SF: stacking faults) in epitaxial silicon wafers for arbitrary phosphorus concentrations and thermal histories of crystals is provided. The method for predicting the occurrence of defects includes the steps of calculating the cooling curve of a silicon single crystal, calculating the concentration of at least interstitial phosphorus in each temperature process from the concentration of doped phosphorus, and calculating the concentration of interstitial phosphorus during cooling from the degree of supersaturation of interstitial phosphorus during cooling. Calculating the size and density of the phosphorus and silicon precipitates upon completion, and estimating the density of defects (SF: stacking faults) in the silicon wafer after epitaxial growth from the size and density of the phosphorus and silicon precipitates. Includes a defect estimation step.

Description

Method for predicting occurrence of defects in epitaxial silicon wafers and method for manufacturing epitaxial silicon wafers

The present invention relates to a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer.

Epitaxial silicon wafers for power MOS transistors are required to have a low resistivity of the substrate. For this reason, a silicon wafer doped with phosphorus (P) at a high concentration is used as a substrate for epitaxial growth.

On the other hand, when the resistivity of the substrate is lower than 0.9 mΩcm, it is known that many stacking faults (hereinafter referred to as SF) occur in the epitaxial film. These SFs (stacking faults) can be detected by etching, can be confirmed with the naked eye or under an optical microscope, and can generate densities. This SF (stacking fault) causes problems when creating power MOS transistors. Therefore, various methods are being attempted to suppress the occurrence of the defect.

For example, in Patent Document 1, the cause of SF (stacking fault) occurring in the epitaxial film is a cluster formed by combining phosphorus and oxygen during the crystal growth process of the substrate crystal, and they are formed at the interface with the epitaxial film. It is assumed that this is the starting point for the occurrence of SF (stacking fault). And, by examining the relationship with the thermal history during cooling of the crystal, the density of SF is correlated with the residence time during which the crystal passes through a temperature range of 570°C ± 70°C (500°C to 640°C), and the stay It is said that when the time is 200 minutes or more, SF (stacking faults) in the epitaxial wafer increases. However, in Patent Document 1, the existence of a cluster generated by combining phosphorus and oxygen has not been confirmed. In addition, the reason why the cluster formed by combining phosphorus and oxygen was assumed to be the cause of SF in Patent Document 1 is that phosphorus atoms cannot diffuse in the temperature range of 570°C ± 70°C, so oxygen atoms that have the possibility of diffusion are phosphorus. This is because it was assumed that they gather around atoms.

Additionally, in Patent Document 2, when annealing was performed for 30 minutes in an argon atmosphere at 1200°C before epitaxial growth, the density and phosphorus concentration of SF (stacking fault) occurring after epitaxial growth, and 570°C ± 70°C of the crystal. An empirical formula for the relationship between residence time in the temperature range, input temperature in argon annealing, and epitaxial growth temperature is proposed.

Additionally, in Non-Patent Document 3, 1.0 mΩcm crystals of phosphorus dope were additionally heat treated for 500 hours at each step while raising the temperature from 400°C to 800°C in 25°C steps to investigate changes in phosphorus precipitation. . As a result, it was shown that SiP precipitates between 500°C and 700°C, but when heated to 775°C, SiP generated at the low temperature stage dissolves and disappears, and only SF and dislocation are observed. Some of the present inventors believe that when epitaxial growth treatment at 1130°C is applied to a crystal containing high-density SiP precipitates, SiP in the bulk portion of the wafer disappears, resulting in SF having the same density as the density of SiP present in As grown. (Stacking fault) is observed to exist.

Patent Document 1: Japanese Patent No. 5890587 Patent Document 2: Japanese Patent Publication No. 2019-142733

Non-patent Document 1: Senda Takeshi, Ishikawa Takashi, Fujimori Hiroyuki, Matsumura Hisashi, Narimatsu Shingo, Abe Yoshiaki, Horikawa Tomoyuki: Lecture preview of the 78th Annual Meeting of the Applied Physics Society Fall Academic Lecture (2017 Fukuoka International Conference Center), 7p-PB6-5 Non-patent Document 2: Vladimir Voronkov, Robert Falster, Maria Porrini, and Januscia Duchini, Physica status solidi a, Volume 209, No. 10, (2012) page 1898 Non-patent Document 3: P. Ostoja, D. Nobili, A. Armigliato, and R. Angelucci, Journal of Electrochemical Society, Volume 123 (1976) page 124 Non-patent Document 4: V.V. Voronkov, R. Falster, Journal of Crystal Growth Volume 194 (1998) page 76

As mentioned above, methods for suppressing the occurrence of SF (stacking fault) in the epitaxial film have been proposed, but as will be explained below, they are still not sufficient. Additionally, the following analysis was made by the present inventors.

For example, in Patent Document 1, the cause of SF (stacking fault) occurring in the epitaxial film is said to be a cluster formed by combining phosphorus and oxygen formed during the crystal growth process of the substrate crystal. However, in Non-Patent Document 1, some of the present inventors observed through TEM that high-density SiP precipitates were present in the as-grown state in the crystal of high-concentration phosphorus dope (resistivity 0.87 mΩcm). It is reported by . Here, SiP is a compound of silicon and phosphorus, and, contrary to speculation in Patent Document 1, does not contain oxygen.

In addition, in Patent Document 1, in an epitaxial film using a substrate with a resistivity of 0.7 mΩcm or more and 0.9 mΩcm or less in phosphorus doping, in order to reduce SF (stacking fault) to 0.1/cm ² or less, the crystal growth process of the substrate crystal is required. It is said that it is necessary to keep the residence time between the temperature range of 500°C and 640°C to 200 minutes or less. However, in the case of phosphorus dope, when the resistivity is 0.7 mΩcm or more and 0.9 mΩcm or less, it is disclosed that the temperature range during crystal growth that must be controlled is 500°C to 640°C, but the temperature range that must be controlled when the resistivity is outside the above range is unclear. The temperature range that needs to be managed is thought to correspond to the temperature range where SiP precipitates are generated and grow, and is thought to change depending on the resistivity (phosphorus concentration). Therefore, in order to apply the method of Patent Document 1, it is necessary to manage each resistivity. It is necessary to obtain the temperature range to be performed through experimentation, which requires a very large number of experiments.

Additionally, since the method described in Patent Document 2 is also an empirical formula, it can be applied only within the range of sample conditions from which the empirical formula was derived. In addition, the resistivity of the sample for which the empirical formula was derived in Patent Document 2 is 0.6725, 0.68375, and 0.7225 mΩcm, and the application range is very narrow. In addition, it can only be applied when annealing in an argon atmosphere at 1200°C for 30 minutes is performed before epitaxial growth.

Additionally, in Patent Document 2, as one of the mechanisms for reducing SF (stacking fault) by lowering the temperature inside the furnace when the wafer is introduced in the pre-anneal process, the amount of interstitial silicon introduced into the wafer is Holding something that is shrinking. However, as disclosed in Non-Patent Document 2, in a phosphorus-doped crystal, most of the phosphorus atoms exist in positions that replace the lattice positions where silicon atoms exist, but some phosphorus atoms exist between the lattice positions of silicon. And, generally, the diffusion coefficient of interstitial atoms is several orders of magnitude larger than that of atoms at substitution sites. On the other hand, the method described in Patent Document 2 does not take into account the influence of interstitial phosphorus.

In this way, a method for suppressing the occurrence of SF (stacking fault) in the epitaxial film has been proposed, but it cannot be applied to any resistivity (i.e., phosphorus concentration). Additionally, the scope of application regarding the thermal history of crystals is limited.

The present invention was made in view of the above problems, and provides a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer, targeting a certain phosphorus concentration and thermal history of the crystal. The purpose is to

The method for predicting the occurrence of defects in an epitaxial silicon wafer according to the present invention made to achieve the above object is an epitaxial silicon wafer manufactured by growing an epitaxial film using a phosphorus-doped silicon single crystal as a substrate. As a method for predicting the occurrence of defects,

A thermal history calculation step of calculating a cooling curve of the silicon single crystal from temperature characteristics and a pulling speed including a pulling device for manufacturing the silicon single crystal;

A concentration calculation step of calculating at least an interstitial phosphorus concentration in each temperature process of the cooling curve from the concentration of phosphorus doped in the silicon single crystal;

A precipitate calculation step of calculating the size and density of phosphorus and silicon precipitates upon completion of cooling from the degree of supersaturation of interstitial phosphorus during cooling of the silicon single crystal;

and a defect estimation step of estimating the density of defects (SF: stacking faults) in the silicon wafer after epitaxial growth from the size and density of the phosphorus silicon precipitates.

The method for predicting the occurrence of defects in an epitaxial silicon wafer of the above configuration is that the phosphorus and silicon precipitates that cause stacking faults (SF: stacking faults) in the epitaxial silicon wafer are higher than the phosphorus present at the substitution position. Since it is thought that interstitial phosphorus is the cause, the method for predicting the occurrence of defects can be improved by calculating the concentration of interstitial phosphorus as the center.

In addition, in the concentration calculation step, it is desirable to calculate not only the concentration of interstitial phosphorus but also the concentration of vacancies, interstitial silicon, and reactants of phosphorus and vacancies.

This is because, in the cooling process of the crystal, various reactions occur with interstitial phosphorus, vacancies, interstitial silicon, and reactants of phosphorus and vacancies.

In the defect estimation step, it is preferable to estimate the density of defects in the epitaxially grown silicon wafer using a threshold value of the size of phosphorus and silicon precipitates to be detected determined in a prior experiment.

This is because the size of SF (stacking fault) that is annealed out varies depending on the prebake conditions performed in the previous stage of epitaxial growth.

For example, if the critical value of the size of the phosphorus and silicon precipitates is 12 nm, prebake is performed for 60 seconds in a hydrogen atmosphere at 1130°C, and then a 3 μm epitaxial film is grown at 1130°C. Suitable for cases.

In addition, in the method for producing an epitaxial silicon wafer according to the present invention, the occurrence of the defect is predicted, and when the predicted defect density does not meet the specified level, the pulling speed is adjusted to predict the defect. It is preferable to manufacture a phosphorus-doped silicon single crystal under the condition that the density of defects satisfies a specified level, and to grow an epitaxial film using the silicon single crystal as a substrate. Yield is improved by predicting the density of defects before actual manufacturing. In addition, it is also conceivable to adjust the conditions of the prebake performed in all stages of epitaxial growth.

According to the present invention, it is possible to provide a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer for any phosphorus concentration and thermal history of the crystal.

1 is a schematic diagram of an example of a single crystal pulling device by the CZ method.
Figure 2 is a graph showing the resistivity at each position of the crystal (A) and crystal (B) in a straight line.
Figure 3 is a graph showing the cooling curve at each position of the crystal (A) in the linear motion.
Figure 4 is a graph showing the cooling curve at each position of the crystal (B) in the linear motion.
Figure 5 is a graph showing the density of SF (stacking faults) after epitaxial growth when crystals at each linear position in crystal (A) and crystal (B) are used as a substrate.
Figure 6 is a graph showing the density of SiP calculated for crystal (A).
Figure 7 is a graph showing the density of SiP calculated for crystal (B).
Figure 8 is a graph comparing experimental results and calculation results of the relationship between the density of SF (stacking fault) of the epitaxial film in crystal (A) and the linear position.
Figure 9 is a graph comparing experimental results and calculation results of the relationship between the density of SF (stacking faults) of the epitaxial film in crystal (B) and the linear position.
Fig. 10 is a flow chart schematically showing the procedures of the defect occurrence prediction method.

Hereinafter, a method for predicting the occurrence of defects in an epitaxial silicon wafer according to an embodiment of the present invention will be described based on the drawings. However, the method for predicting the occurrence of defects in an epitaxial silicon wafer according to the embodiment of the present invention is not limited to the embodiment described below. The attached drawings are schematic, and the dimensions and proportions of each element may differ from the actual ones.

First, considering the results of Non-Patent Document 1 and Non-Patent Document 3, and the results of Patent Document 1 together, the SF (stacking fault) in the epitaxial film when using a substrate wafer of 0.9 mΩcm or less in phosphorus dope is It is assumed that occurrence is produced by the following process.

(1) For crystals of 0.9 mΩcm or less in phosphorus dope, SiP is generated and grows in the temperature range of 570°C ± 70°C (500°C to 640°C) during the crystal cooling process.

(2) During the prebake heating performed in the previous stage of epitaxial growth, SiP is dissolved and SF remains in the crystal.

(3) In the cooling process of crystal growth, when the residence time between the temperature range of 570℃±70℃ (500℃ to 640℃) is short, the size of SiP is small, so the size of SF generated is also small. , During the prebake process, SF (stacking faults) near the surface layer are annealed out, and when epitaxial growth is started, SF does not remain in the surface layer.

(4) On the other hand, when the residence time between the temperature range of 570°C ± 70°C (500°C to 640°C) is long during the cooling process in crystal growth, the size of SiP increases, resulting in SF (stacking fault). Because the size of is large, SF (stacking faults) near the surface layer are not annealed out during the prebake process. Then, SF remaining in the surface layer when epitaxial growth is started is propagated as SF in the epitaxial film.

Considering that SF of the epitaxial film in the low-resistivity substrate is formed in this process, it is important to predict the density of SiP precipitates that serve as nuclei that propagate as SF to the epitaxial film. Then, the relationship between the predicted size distribution of SiP and the stacking fault density of the epitaxial film is obtained, and the stacking fault of the epitaxial film is estimated from the relationship.

First, we will explain how to obtain the relationship between the predicted size distribution of SiP and the SF (stacking fault) density of the epitaxial film.

(1) The cooling curve during crystal growth is obtained by calculation.

(2) Calculate the generation and growth of SiP during cooling based on the phosphorus concentration and cooling curve.

(3) Determine the size distribution of SiP after cooling.

(4) The density of SF (stacking faults) of the epitaxial film for the corresponding phosphorus concentration and cooling curve is evaluated experimentally.

(5) Determine the relationship between the size distribution of SiP and SF (stacking fault) in the epitaxial film.

Hereinafter, each of the processes (1) to (5) will be described.

1 is a schematic diagram of an example of a single crystal pulling device by the CZ (Czochralski) method. The pulling device shown in FIG. 1 has a general structure, and a quartz crucible 3 filled with the raw material melt 2 is rotatably installed in the center of the furnace 1. Around the quartz crucible 3, a side heater 4 is installed to heat the quartz crucible 3 from the side and a bottom heater 5 is installed to heat the quartz crucible 3 from the bottom. Additionally, a radiation shield 6 is installed above the quartz crucible 3 for controlling the temperature of the raw material melt 2 and the pulled crystal 9 in the quartz crucible 3.

In the single crystal pulling device by the CZ method, the seed crystal 8 held at the lower end of the wire 7 is brought into contact with the liquid surface of the raw material melt 2 in the quartz crucible 3, and the quartz crucible 3 and the seed crystal ( The crystal 9 is grown by pulling the wire 7 while rotating each 8).

The structure of the puller used for crystal growth as shown in FIG. 1 is modeled using a mesh structure, the physical properties of each member are input, and the pulling speed corresponding to the length position of the crystal is input. Then, the surface temperature distribution of each member is calculated based on the heating value of the heater and the emissivity of each member. Meanwhile, the internal temperature distribution of each member is calculated by solving the heat conduction equation based on the surface temperature distribution and thermal conductivity of each member. In this way, the temperature distribution inside the pulled crystal is calculated. Additionally, by considering the pulling speed of the crystal, the cooling curve of the entire crystal, including the temperature distribution inside the crystal, is calculated.

These calculation processes can be calculated using comprehensive electrothermal analysis software commonly used by those skilled in the art. There are three types of comprehensive electrothermal analysis software, for example, 1) CGSim (STR), 2) CrysMAS (Crystal Growth Laboratory of the Fraunhofer Institute of Integrated Systems and Device Technology), and 3) FEMAG (FEMAG soft). can be exemplified. Additionally, CGSim is used in the calculation examples described below.

Next, calculate the process by which phosphorus atoms aggregate to form SiP during the cooling process. As disclosed in Non-Patent Document 2, it is thought that phosphorus atoms in silicon mainly exist at positions replacing silicon lattice points, and some exist in interstitial sites of silicon. The diffusion coefficient of the phosphorus atom present at the substitution site is well known, and it is known that SiP hardly moves in the temperature range where it is thought to occur. Meanwhile, atoms existing between lattices generally diffuse at high speed. Therefore, it is believed that interstitial phosphorus, rather than phosphorus present at substitution positions, forms SiP.

Therefore, first, the reaction of phosphorus during cooling of the crystal will be explained according to Non-Patent Document 2. Here, the reaction between phosphorus atoms and point defects in the silicon crystal is assumed as follows. As a form of phosphorus in silicon, the case where it exists at a position replacing a silicon atom in a lattice point was designated as P _S , and the case where it exists between the lattices of silicon was designated as _Pi . Additionally, the atomic vacancy is V, and the interstitial silicon is I.

P _S +V＝PV… (One)

P _S+ +I＋2e ^- =P _i- … (2)

Here, PV is the reactant between phosphorus and vacancy, P _s+ is the positively charged phosphorus at the substitution site, e is the electron, and P _i- is the negatively charged interstitial phosphorus. Additionally, in equation (1) representing the reaction with vacancy, it is assumed that the compound of vacancy and phosphorus is electrically neutral. And, in equation (2), since it is assumed that P _i , which is between lattices, is negatively charged, the change in charge is taken into consideration. For this assumption, refer to Non-Patent Document 2.

If the reaction constants in equations (1) and (2) are K _V and K _I , respectively, the following equations (3) and (4) are obtained according to the law of mass action.

C _V N/C _PV =K _V … (3)

C _I N/C _Pi =K _I (n _i /n) ² … (4)

Here, C _V is the vacancy concentration, N is the phosphorus concentration, C _PV is the PV concentration, C _I is the interstitial silicon concentration, C _Pi is the _Pi concentration, n is the electron concentration, and _ni is the intrinsic It is the electron concentration. Here, n _i is expressed by equation (5).

n _i (cm ^-3 )=1.568×10 ¹⁵ T ^3/2 exp[-{1.17-(4.9×10 ^-4 T ² /(T+655))}/2k _B T]… (5)

Here, T is the absolute temperature (K), and k _B is the Boltzmann constant 8.6257×10 ^-5 (eV/K).

The relationship between the electron concentration n and the donor impurity concentration N is expressed in the following equation (6).

n=N/2+[N ² /4+n _i ² ] ^1/2 ... (6)

Here, from equation (3), it can be seen that C _PV is proportional to N. Meanwhile, from equations (4) and (6), C _Pi changes as follows. From equation (6), the electron concentration n becomes n=n _i when N<<n _i , and n=N when N>>n _i . Therefore, when the phosphorus concentration is low, N<<n _i , C _Pi is proportional to N, and when the phosphorus concentration is high, when N>>n _i , C _Pi is proportional to the third power of N. . That is, when the phosphorus concentration N exceeds the intrinsic electron concentration, the interstitial phosphorus concentration C _Pi is expected to increase rapidly. This shows that at the phosphorus concentration N, which is the problem in the present invention, the interstitial phosphorus concentration C _Pi becomes dominant.

However, another reaction that occurs during crystal growth is the great annihilation reaction of silicon between vacancies and interstitials shown in equation (7).

V+I=0... （7）

And, the reaction rate of the large extinction reaction is expressed by equation (8).

dC _V /dt=dC _I /dt=-K _IV (C _V C _I -C _V ^eq C _I ^eq )… (8)

Here, C _V ^eq and C _I ^eq are the thermal equilibrium concentrations of vacancy and interstitial silicon, respectively.

Additionally, K _IV is expressed by equation (9).

K _IV =4πa _c (D _V +D _I )exp(-ΔG/k _B T)… (9)

Here, a _c =0.543×10 ^-7 cm, and D _V and D _I are the diffusion coefficients of vacancy and interstitial silicon, respectively. ΔG is a barrier to large extinction reactions, and since ΔG is generally zero, it is set to zero here.

Next, changes in the concentrations of C _V , C _I , C _PV , and C _Pi during the cooling process of the crystal are shown. V, PV, I, and P _i were assumed to change while maintaining a normal balance in the reactions of equations (1) and (2). That is, equations (3) and (4) are always satisfied.

First, the relationship between C _V and C _PV is shown. Here, since C _PV << N, the change in phosphorus concentration N due to the formation of PV is ignored. And, the sum of the concentrations of V and PV is taken as C _V ^T as shown in equation (10).

C _V ^T =C _V +C _{P V} … (10)

Then, equation (3) becomes equation (11).

(C _V ^T -C _PV )N/C _PV =K _V … (11)

In other words, if C _V ^T is known, C _PV can be obtained using equation (12).

C _PV =C _V ^T /(K _V /N+1)… (12)

Next, the relationship between the concentrations of _CI and C _Pi is obtained from equation (4). Here, since C _Pi <<N, the change in phosphorus concentration N due to the formation of _Pi is ignored. In addition, the ratio of the equilibrium concentration of P _i and the concentration of P _S is taken as R as shown in equation (13).

R=C _Pi ^eq /N… (13)

Here, since a new parameter called R is shown, the relationship with K _I is shown below. First, since equation (4) holds even when each component is at the equilibrium concentration, it can be written as equation (14).

C _I N/C _Pi =C _I ^eq N/C _Pi ^eq … (14)

thus,

C _I N/C _Pi =C _I ^eq /R… (15)

Additionally, from equations (13) and (14), it can be seen that the relationship between R and K _I is equation (16).

R=C _I ^eq (n/n _i ) ² /K _I … (16)

Additionally, the sum of the concentrations of I and P _i is taken as C _I ^T as shown in equation (17).

C _I ^T =C _I +C _Pi … (17)

Then, from equation (15), equation (18) is obtained.

C _Pi /N=R(C _I ^T -C _Pi )/C _I ^eq … (18)

If we expand and organize this, we get equation (19).

C _Pi =C _I ^T /{C _I ^eq /(NR)+1}… (19)

However, using the equations derived so far, changes in V, I, PV, and P _i during cooling can be calculated. Next, the specific calculation sequence is shown. Here, the concentration at the solid-liquid interface, that is, 1685K, is taken as the initial condition. And, at the solid-liquid interface, it is assumed that all concentrations are thermal equilibrium concentrations. That is, the initial concentration is given by the following equation (20).

C _V =C _V ^eq at 1685K

C _I =C _I ^eq at 1685K

C _PV =C _V ^eq N/K _V at 1685K

C _Pi =NR at 1685K … (20)

The changes in V and I during cooling are obtained using equation (8) for each decrease in temperature, and the changes in C _V and C _I are determined. Then, the changes in C _V ^T and C _I ^T are obtained from the changes in C _V and C _I , and C _PV and C _Pi are obtained from equations (12) and (19). By determining this for each temperature decrease step, the concentration changes of V, I, PV, and _Pi are determined.

Additionally, each temperature-dependent parameter is set as shown in Equation (21) to Equation (26).

C _V ^eq =6.49×10 ¹⁴ exp[-3.94{1/(k _B T)-1/(1685k _B )}]… (21)

C _I ^eq =4.84×10 ¹⁴ exp[-4.05{1/(k _B T)-1/(1685k _B )}]… (22)

D _V =4.45×10 ^-5 exp[-0.3{1/(k _B T)-1/(1685k _B )}]… (23)

D _I =5.0×10 ^-4 exp[-0.9{1/(k _B T)-1/(1685k _B )}]… (24)

K _V =9.61×10 ¹⁹ exp[-1.0{1/(k _B T)-1/(1685k _B )}]… (25)

K _I =3.5×10 ²⁰ exp[-1.2{1/(k _B T)-1/(1685k _B )}]… (26)

k _B here is 8.6257×10 ^-5 (eV/K).

Next, we describe a model representing the nucleation and growth process of SiP. As a nucleation rate model, the public cluster model proposed in Non-Patent Document 4 is referred to and applied to SiP.

In classical nucleation theory, nucleation is considered a process in which the energy barrier accompanying cluster formation is exceeded by thermal fluctuations. Here, SiP is assumed to be a sphere. Assuming that the nucleus is a sphere, the free energy change accompanying the generation of a particle of radius R is given as follows.

ΔG(R)=-(4πR ³ /3Ω)f+4πR ² σ … (27)

f=k _B Tln(C _Pi /C _Pi ^eq )… (28)

Here, Ω is the volume per molecule of SiP (4.08×10 ^-23 cm ³ ). In addition, f is the chemical potential of phosphorus, and -f represents the energy change of the system when one SiP is precipitated. The term 4πR ² σ represents surface energy, and σ is the surface energy per unit area of SiP (σ=556erg/cm ² ). Additionally, k _B in equations (27) and (28) is 1.381×10 ^-16 (erg/K).

ΔG(R) takes its maximum value as the radius increases. The radius at the local maximum is the critical radius _Rcri , and the local maximum of ΔG(R) is ΔG*. ΔG* represents the energy barrier accompanying cluster formation.

R _cri =2σΩ/f … (29)

ΔG*＝16πσ ³ Ω ² /(3f) ² … (30)

The frequency of nucleation is defined as the frequency at which a nucleus of the size R _cri is generated due to thermal fluctuations and the frequency at which another atom is added to the nucleus, thereby exceeding the maximum value and forming a precipitate. At that time, the normal nucleation rate I is expressed by equation (31).

I=βZρ ^eq ... (31)

Here, β is the capture rate of the element into the critical nucleus, and Z is called the Zeldovich factor and is a coefficient that corrects the ratio of the density in thermal equilibrium and the density in the steady state. ρ ^eq is the thermal equilibrium density of the critical core.

ρ ^eq =ρexp(-ΔG*/k _B T)… (32)

Here, ρ is the density of silicon sites (5×10 ²² cm ^-3 ).

β=4πR _cri D _Pi C _Pi … (33)

Here, D _Pi is the diffusion coefficient of interstitial phosphorus.

Z=f(12πΔG*k _B T) ^-1/2 … (34)

Therefore, each generation rate I is expressed by the following equation (35).

I=(4πR _cri D _Pi C _Pi )Zρexp(-ΔG*/k _B T)(1/sec·cm ³ )… (35)

That is, during cooling of the crystal, SiP is generated at the rate shown in equation (35). The density of SiP generated in the meantime is integrated every 30 seconds, and the growth of SiP generated in each time period and the absorption of interstitial phosphorus are calculated until cooling is completed.

The growth rate of SiP is expressed in equation (36).

dR/dt =ΩD _Pi (C _Pi -C _Pi ^eq )/R… (36)

With the initial size as _Rcri , the change in radius at each time step, dR, was obtained using equation (36), and the radius was determined as R=R+dR. The absorption flux of phosphorus by SiP is shown in equation (37).

J=4πRD _Pi (C _Pi -C _Pi ^eq )… (37)

The above equation (37) represents the interstitial phosphorus absorbed by one SiP. This is integrated and added to the change in interstitial phosphorus concentration. Here, D _Pi is given by equation (38).

D _Pi =3×10 ^-7 exp[-1.1{1/(k _B T)-1/(1685k _B )}]… (38)

Here, k _B is 8.6257×10 ^-5 (eV/K).

As described above, the concentrations of atomic vacancies V, interstitial silicon I, phosphorus and vacancy reactant PV, and interstitial phosphorus _Pi during the cooling process of the crystal are determined, and the generation and growth of SiP are calculated.

Next, the relationship between the size distribution of SiP estimated by calculation and the density of SF (stacking faults) in the epitaxial film under the corresponding experimental conditions is investigated.

<Experiment>

The crystals used for evaluation were two crystals, crystal (A) and crystal (B), and had a diameter of 200 mm. Figure 2 is a graph showing the resistivity at each position of crystal (A) and crystal (B) in direct motion. As shown in FIG. 2, the resistivity of crystal (A) changes from 0.9 mΩcm to 0.7 mΩcm, and the resistivity of crystal (B) changes from 0.75 mΩcm to 0.55 mΩcm. By using crystal (A) and crystal (B), the occurrence of defects in a wide range of resistivities is evaluated.

FIG. 3 is a graph showing the cooling curve at each position of the crystal (A) in the linear motion, and FIG. 4 is a graph showing the cooling curve at each position in the linear motion of the crystal (B).

<Epitaxial conditions>

The manufacturing conditions for the epitaxial film are as follows. First, as a prebake, a prebake for 60 seconds is performed in a hydrogen atmosphere at 1130°C. Afterwards, as epitaxial growth, a 3 µm epitaxial film is grown at 1130°C.

<SF: Stacking fault evaluation>

Stacking faults in the epitaxial silicon wafer prepared as described above are inspected. By etching, SF (stacking faults) can be detected, confirmed with the naked eye or under an optical microscope, and the density can be determined.

FIG. 5 is a graph showing the density of SF (stacking faults) after epitaxial growth when crystals at each linear position in crystal (A) and crystal (B) are used as a substrate. The results of this experiment are compared with SiP obtained by the calculation method described above.

Figures 6 and 7 are graphs showing the density of SiP calculated by the method described above for crystal (A) and crystal (B), respectively. Figure 6 shows the density and linearity of SiP with radii of >4, >6, >8, >10, >12, >14, and >16 nm, respectively, calculated under the manufacturing conditions of crystal (A). It indicates the relationship with the location. Figure 7 shows the same calculation results under the production conditions of crystal (B).

In addition, while Figures 6 and 7 show the number of SiPs per unit volume (pieces/cm ³ ), Figure 5, which is an experimental result, shows the density of SF (stacking faults) per unit area (pieces/cm ² ). . Therefore, the two cannot be directly compared. Therefore, think as follows.

First, SiP is dissolved in the process of hydrogen baking prior to epitaxial processing, leaving SF remaining, but small SF (stacking faults) near the surface layer disappear. And, the size of SF remaining after SiP is dissolved is determined by the size of SiP. Therefore, the longer the time it takes to pass 570°C ± 70°C, which is considered to be the generation/growth section of SiP, the larger the size of SiP becomes, and the more SF that does not disappear during the hydrogen bake. Here, it is assumed that the size of SF generated after SiP is dissolved is the same as the size of SiP.

Then, when a part of it is exposed to the surface, the density at which SF is transferred to the epitaxial film is D(r) (piece/cm 3 ) if the density of particles of radius r is D(r) (piece/cm ³ ), the number appearing on the surface is 2rD(r) This happens. Additionally, if the radius of SiP is smaller than the critical radius R _cri , it is believed that SF generated after dissolution of SiP is annihilated by hydrogen baking. So, from the critical radius R _cri where radius r is large, the number per area exposed to the surface was calculated. The density SF(R) (piece/cm ² ) at which particles of radius R or more appear on the surface is expressed as the following equation (39).

Here, SF(R) in equation (39) represents SiP of radius R or more, that is, represents the number of SFs per area exposed to the surface.

Figures 8 and 9 show the experimental results of the relationship between the density of SF (stacking fault) of the epitaxial film in crystal (A) and crystal (B) and the linear position, respectively, and the threshold values are 8, 10, 12, 14, This is a comparison of the relationship between SF (stacking fault) density and linear position based on calculations made at 16 nm. From Figures 8 and 9, it can be seen that the SF (stacking fault) density calculated with a threshold of 12 nm is consistent with the experimental results.

From the above results, it can be seen that the following method for predicting the occurrence of defects is effective in epitaxial silicon wafers manufactured by growing an epitaxial film using phosphorus-doped silicon as a substrate. Fig. 10 is a flow chart schematically showing the procedures of the defect occurrence prediction method.

First, as a preparatory step, temperature characteristics including a pulling device for producing a phosphorus-doped silicon single crystal are acquired (Step S1). Since the lifting device has a structure as shown in FIG. 1, for example, the capabilities of the side heater 4 and the bottom heater 5, the positional relationship between the radiation shield 6, etc., and the physical property values for each member are Use this to acquire information for electric heat analysis.

After that, the cooling curve of the crystal is calculated from the pulling speed for actually producing a phosphorus-doped silicon single crystal (Step S2).

Meanwhile, from the concentration of phosphorus doped in the silicon single crystal, at least the interstitial phosphorus concentration in each temperature process of the cooling curve is calculated (Step S3). As explained above, the phosphorus and silicon precipitates (SiP) that cause stacking faults (SF: stacking faults) in epitaxial silicon wafers are caused by interstitial phosphorus (P _i ) rather than phosphorus present at substitution positions. Because it is thought that

However, this is not limited to calculating only the concentration of interstitial phosphorus (P _i ). This is because during the cooling process of the crystal, interstitial phosphorus (P _i ) undergoes various reactions with vacancies (V), interstitial silicon (I), and the reactant between phosphorus and vacancies (PV). Therefore, in the calculation in Step S3, it is desirable to calculate not only the concentration of interstitial phosphorus but also the concentration of vacancies (V), interstitial silicon (I), and the reactant of phosphorus and vacancies (PV).

Afterwards, the size and density of phosphorus and silicon precipitates (SiP) at the time of completion of cooling are calculated from the degree of supersaturation of interstitial phosphorus (P _i ) of the crystal during cooling (Step S4).

Then, the density of defects in the silicon wafer after epitaxial growth is estimated from the size and density of phosphorus and silicon precipitates (SiP) at the time of completion of cooling (Step S5). In addition, in this estimation, experiments were conducted in advance on the relationship between the size and density of phosphorus silicon precipitates (SiP) and the density of defects in the silicon wafer after epitaxial growth, and the phosphorus silicon precipitates (SiP) to be detected were tested in advance. It is desirable to set a threshold value for the size of SiP). This is because the size of SF (stacking fault) that is annealed out varies depending on the prebake conditions performed in the previous stage of epitaxial growth.

In addition, as epitaxial conditions, when prebaking is performed for 60 seconds in a hydrogen atmosphere at 1130°C and then a 3 μm epitaxial film is grown at 1130°C, the critical value of the size of phosphorus and silicon precipitates (SiP) is When set to 12 nm, the SF (stacking fault) density is consistent with the experimental results.

The method for predicting the occurrence of defects described above can also be implemented as a method for manufacturing an epitaxial silicon wafer in which an epitaxial film is grown using phosphorus-doped silicon as a substrate.

In other words, the occurrence of defects is predicted based on the concentration of phosphorus doped in the silicon single crystal and the pulling speed of the crystal, and when the density of predicted defects does not meet the specified level, the pulling speed is adjusted to predict defects. It is conceivable to manufacture epitaxial silicon wafers under the condition that the density satisfies the specified level.

If the predicted density of defects does not meet the specified level, it is also considered to adjust the conditions of the prebake performed in all stages of epitaxial growth.

Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-mentioned embodiments.

1 to
2 Raw melt
3 Quartz Crucible
4 side heater
5 Bottom heater
6 Copy Shield
7 wire
8 seed crystals
9 decision

Claims (6)

A method for predicting the occurrence of defects in an epitaxial silicon wafer manufactured by growing an epitaxial film using a phosphorus-doped silicon single crystal as a substrate, comprising:
A thermal history calculation step of calculating a cooling curve of the silicon single crystal from temperature characteristics and a pulling speed including a pulling device for manufacturing the silicon single crystal;
a concentration calculation step of calculating at least an interstitial phosphorus concentration in each temperature process of the cooling curve from the concentration of phosphorus doped in the silicon single crystal;
A precipitate calculation step of calculating the size and density of phosphorus and silicon precipitates upon completion of cooling from the degree of supersaturation of interstitial phosphorus during cooling of the silicon single crystal;
A defect estimation step of estimating the density of defects in the silicon wafer after epitaxial growth from the size and density of the phosphorus silicon precipitate.
A method for predicting the occurrence of defects in an epitaxial silicon wafer, including a method. According to paragraph 1,
In the concentration calculation step, not only the concentration of interstitial phosphorus but also the concentration of vacancies, interstitial silicon, and reactants of phosphorus and vacancies are also calculated. According to paragraph 1,
In the defect estimation step, the density of defects in the epitaxially grown silicon wafer is estimated using the threshold value of the size of the phosphorus and silicon precipitates to be detected determined in a prior experiment. A method for predicting the occurrence of defects in According to paragraph 3,
A method for predicting the occurrence of defects in an epitaxial silicon wafer, wherein the critical value of the size of the phosphorus silicon precipitate is set to 12 nm. The density of defects predicted by predicting the occurrence of defects described in any one of paragraphs 1 to 4, and adjusting the pulling speed when the predicted density of defects does not satisfy the specified level. A method of producing an epitaxial silicon wafer, which includes manufacturing a silicon single crystal doped with phosphorus under conditions that satisfy the specified level, and growing an epitaxial film using the silicon single crystal as a substrate. According to clause 5,
Additionally, a method of manufacturing an epitaxial silicon wafer, which involves adjusting the conditions of the prebake performed in the previous stage of epitaxial growth.