KR101585683B1 - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for converting digital video data into analog data voltages to be displayed on a liquid crystal display panel using a linear single gamma reference voltage, And a plurality of reference voltage supply lines formed in a direction parallel to the data lines, wherein the plurality of liquid crystal cells are arranged in a matrix form A liquid crystal display panel having a pixel array arranged therein; A data driving circuit for converting digital video data into data voltages using linear single gamma compensating voltages whose voltages are higher as the gray level is higher, and a gate driving circuit for sequentially supplying gate pulses to the gate lines do.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device that converts digital video data into analog data voltages to be displayed on a liquid crystal display panel using a linear single gamma reference voltage.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a data driving circuit for supplying a data voltage to data lines of the liquid crystal display panel, gate lines (or scan lines) A timing controller for controlling the driving circuits, a module power supply circuit for generating driving voltages of the liquid crystal display panel, and the like.

The liquid crystal cells of the liquid crystal display panel alternately charge the positive analog data voltage and the negative analog data voltage higher than the common voltage. To this end, the data driving circuit converts the digital video data to positive / negative gamma compensation voltages to generate positive / negative analog data voltages. The positive / negative analog data voltages are supplied to the data lines of the liquid crystal display panel.

The module power supply circuit divides the high-potential power supply voltage Vdd as shown in FIG. 1 to generate a plurality of positive-polarity gamma reference voltages having a voltage level between the high-potential power supply voltage Vdd and the common voltage Vcom, Generates a plurality of negative gamma reference voltages having a voltage level between a voltage Vcom and a low potential supply voltage Vss. The data driver circuit includes a plurality of source drive integrated circuits (hereinafter referred to as "IC"). Each of the source drive ICs includes a first voltage divider circuit RS1, a second voltage divider circuit RS2, a first digital-analog converter (hereinafter referred to as "PDAC"), a second digital- Quot; NDAC "), a multiplexer (MUX), an output buffer (BUF), and the like. The first voltage dividing circuit RS1 divides the positive polarity gamma reference voltages by the number of gradations of data to generate positive polarity gamma compensation voltages. The second voltage dividing circuit RS2 divides the negative gamma reference voltages by the number of gradations of data to generate negative gamma compensation voltages. The PDAC converts the digital video data Data1 into positive gamma compensating voltages to generate a positive analog data voltage and the NDAC converts the digital video data Data1 into negative gamma compensating voltages to generate a negative analog data voltage . The multiplexer MUX alternately outputs the positive polarity analog data voltage and the negative polarity analog data voltage in response to the polarity control signal POL input from the timing controller and the polarity control signal / POL inverted. The output buffer BUF supplies the positive / negative polarity analog data voltages input from the multiplexer MUX to the data lines of the liquid crystal display panel.

Each of the source drive ICs incorporates a DAC (Digital to Analog Converter), ie PDAC and NDAC per pixel data, and a multiplexer that operates according to the polarity control signals (POL, / POL). In order to realize a high-quality image, if the color depth or resolution of the liquid crystal display device is increased, the number of DACs of the source driver IC increases by a factor of two. The polarity control signals POL and / POL are high in frequency because the logic is inverted in one horizontal period or two horizontal periods. Thus, in the conventional liquid crystal display device, the DAC circuit portion of the source drive IC becomes large, and thus the chip size is large and the heat generation is high. The module power circuit has high power consumption and high circuit cost due to the part that divides the high potential power supply voltage (Vdd) to generate the positive gamma reference voltages and the negative gamma reference voltages.

In recent years, in order to solve the horizontal crosstalk, smear noise, afterimage, and the like in the display image, a driving technique with no common voltage (Vcomless) has been proposed. However, in this Vcomless driving technique, since the source drive IC must include two DACs per one pixel data, the number of DACs increases by two times when the color data and the resolution increase.

Further, in the conventional liquid crystal display device, since the polarity control signals POL, / POL, the positive gamma reference voltage, the negative gamma reference voltage, and the like must be input to each of the source driver ICs, .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of reducing the number of DACs.

According to an aspect of the present invention, there is provided a liquid crystal display device including TFTs formed at intersections of a plurality of data lines and a plurality of gate lines and intersecting data lines and gate lines, A liquid crystal display panel having a plurality of reference voltage supply lines formed in a direction parallel to each other and having a pixel array in which a plurality of liquid crystal cells are arranged in a matrix; A data driving circuit for converting digital video data into data voltages using linear single gamma compensating voltages whose voltages are higher as the gray level is higher, and a gate driving circuit for sequentially supplying gate pulses to the gate lines do.

In the present invention, by inverting a liquid crystal display panel using a linear single DAC, the size of a DAC included in each of the source driver ICs compared with the conventional dual DAC driving is reduced to 1/2, and the multiplexer for selecting the output of the DAC is removed, Chip size, heat generation, circuit cost, etc. of the drive IC can be reduced and the liquid crystal driving voltage can be lowered to 40% or less. Furthermore, the present invention can reduce the voltage and number of gamma reference voltages to simplify the circuit configuration of the module power supply circuit, reduce power consumption and circuit cost, lower the number of gamma reference voltages, and eliminate polarity control signals, It is possible to greatly reduce the number of wirings connected to the semiconductor device.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 11. FIG.

3, the liquid crystal display according to the first embodiment of the present invention includes a liquid crystal display panel 100, a data driving circuit 103 connected to the data lines D1 to Dm of the liquid crystal display panel 100, A gate driving circuit 104 connected to the gate lines G1 to Gn of the liquid crystal display panel 100, a timing controller 101 for controlling the data driving circuit 103 and the gate driving circuit 104, And a module power supply circuit (102) for generating a driving voltage of the liquid crystal display panel (100).

The liquid crystal display panel 100 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 100 includes a pixel array for displaying video data.

TFTs formed at intersections of the data lines D1 to Dm, the gate lines G1 to Gn, the data lines D1 to Dm and the gate lines G1 to Gn are formed in the pixel array of the lower glass substrate, A pixel electrode of a liquid crystal cell connected to the TFT, a storage capacitor connected to the liquid crystal cell, and the like are formed. The lower glass substrate is formed with reference voltage supply lines spaced apart from each other by a distance wider than the interval of the adjacent data lines. The reference voltage supply lines are formed in a direction parallel to the data lines and are arranged one for each of three horizontally or four subpixels as shown in FIG. The reference voltage supply line is supplied with a predetermined reference voltage REF as shown in FIG. 4 and FIG. 7 is a circuit diagram showing a part of the pixel array equivalently. In FIG. 7, 'Clc' denotes a liquid crystal cell, 'Cst' denotes a storage capacitor, 'D1 to D3' denotes a data line, 'G1' and 'G2' denotes a gate line, and 'TFT1 to TFT6'

On the upper glass substrate of the liquid crystal display panel 100, a black matrix, a color filter, and the like are formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display device has no common electrode to which a common voltage is supplied. The liquid crystal cells charge the positive / negative analog data voltage according to the voltage difference of the data voltages supplied through the neighboring data lines or according to the voltage difference between the data voltage and the reference voltage. Such a liquid crystal display device is driven by a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode using the pixel array shown in FIG. This liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

The data driving circuit 103 includes a plurality of source drive ICs. Each of the source drive ICs converts the digital video data into an analog data voltage with only linear single gamma compensation voltages (Vs_gamma) as shown in FIG. The linear single gamma compensation voltages are determined by the voltage following the linear curve in which the voltage linearly increases and the inflection point has no linear curve as the gray level value increases as in the curve of FIG. The linear single gamma compensation voltages Vs_gamma are voltages divided between the high potential power supply voltage Vs_gamma and the low potential power supply voltage Vss. The high-potential power-supply voltage Vs_gamma is lower than the conventional high-potential power-supply voltage Vdd shown in FIG. Each of the source drive ICs may be mounted on a COG (Chip On Glass) process or a TCP (Tape Carrier Package) and adhered to a lower glass substrate by a TAB (Tape Automated Bonding) process.

The gate drive circuit 104 includes a plurality of gate drive ICs. The gate driving circuit 104 includes a shift register for sequentially shifting the gate driving voltage in response to the gate timing control signals GSP, GSC, and GOE from the timing controller 101, Pulse) are sequentially supplied. The gate drive ICs may be connected to gate lines of a lower glass substrate by a TAB process or may be formed directly on a lower glass substrate together with a pixel array by a GIP (Gate In Panel) process.

The timing controller 101 receives RGB digital video data, a vertical synchronizing signal Vsync, and a horizontal synchronizing signal from the system board 105 through an interface receiving circuit such as an LVDS (Low Voltage Differential Signaling) interface and a TMDS (Transition Minimized Differential Signaling) A timing signal such as a signal Hsync, a data enable signal DE, and a dot clock CLK. The timing controller 101 transmits the RGB digital video data to the source drive ICs of the data driving circuit 103 in a mini LVDS interface manner. The timing controller 101 generates data timing control signals SSP, SSC and SOE for controlling the operation timings of the source drive ICs using the timing signals Vsync, Hsync, DE and CLK, And generates gate timing control signals (GSP, GSC, GOE) for controlling the operation timing. The timing controller 101 controls the timing controller 101 so that the digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array of the liquid crystal display panel 100 at a frame frequency of 60 x i (i is a positive integer) And the frequency of the data timing control signal can be multiplied by a frame frequency reference of 60 x i Hz.

The conventional source driver IC selects the positive polarity analog data voltage and the negative polarity analog data voltage in response to the polarity control signal POL as shown in FIG. Therefore, in the conventional timing controller, a polarity control signal of high frequency for controlling the polarity of the data voltage outputted from the source drive IC is generated. On the other hand, the present invention generates a single polarity data voltage using a linear single gamma compensation voltage whose polarity is not separated as shown in FIG. The positive polarity data voltage and the negative polarity data voltage are determined according to the relative voltage difference between the neighboring data lines or the data line and the reference voltage supply line in each of the liquid crystal cells. Therefore, the timing controller 101 of the present invention does not generate a polarity control signal, and omits a multiplexer that alternately selects data voltages of different polarities in the source drive IC.

The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), and a source output enable (SOE). The source start pulse SSP controls the data sampling start timing of the data driving circuit 103. If the signal transmission system between the timing controller 101 and the data driving circuit 103 is a mini LVDS interface, the source start pulse SSP may be omitted. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driving circuit 103 on the basis of the rising or falling edge. The source output enable signal SOE controls the output timing of the data driving circuit.

The gate timing control signals GSP, GSC and SOE include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE) . The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 104. [

The system board 105 is connected to the RGB video data input from the broadcast receiving circuit or the external video source and outputs a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock CLK, To the timing controller 101 via the LVDS interface or the TMDS interface transmission circuit. The system board 105 is provided with a graphics processing circuit such as a scaler for interpolating and interpolating the resolution of RGB video data input from a broadcast receiving circuit or an external video source in accordance with the resolution of the liquid crystal display panel, And a power supply circuit for generating a voltage Vin to be supplied.

The module power supply circuit 102 includes a DC-DC conversion circuit including a boost converter, a regulator, a pulse width modulation IC, a PWM IC, and a charge pump. do. The module power supply circuit 102 adjusts a voltage Vin input from the system board 105 to generate driving voltages of the liquid crystal display panel 100. [ The driving voltages generated from the module power supply circuit 102 are applied to the gate high voltage Vgh and the gate low voltage Vgl, the high potential power supply voltage Vdd, the logic power supply voltage Vcc, SGi, i is a positive integer of 2 or more), and the like. The gate high voltage (Vgh) is the high logic voltage of the gate pulse set above the threshold voltage of the TFTs formed in the pixel array. The gate low voltage (Vgl) is the low logic voltage of the gate pulse set to a voltage less than the threshold voltage of the TFTs formed in the pixel array. Is supplied to the gate high voltage (Vgh) and the gate low voltage (Vgl) gate drive circuit (104). The linear single gamma reference voltages SGO to SGi are voltages divided in i steps between the low potential power supply voltage Vss and the conventional high potential power supply voltage Vdd as shown in Fig. The reference voltage REF supplied to the liquid crystal cells through the reference voltage supply line is set to about 1/3 Vdd or 2/3 Vdd voltage as shown in FIG. 4 when the reference voltage supply lines are arranged per three subpixels . Also, the reference voltage REF can be set to about a half Vdd voltage as shown in FIG. 4 when the reference voltage supply lines are arranged one for each of four subpixels.

5 and 6 show the source drive IC in detail.

Referring to Figs. 5 and 6, the source driver IC drives k (k is an integer smaller than m) data lines, respectively. Each of the source drive ICs includes a shift register 51, a data register 52, a first latch 53, a second latch 54, a single DAC 55, and an output circuit 56.

The shift register 51 generates a sampling signal in accordance with the reset clock of the mini-LVDS clock from the timing controller 101. Further, the shift register 51 transfers the carry signal CAR to the source drive IC of the next stage. The data register 52 temporarily stores the digital video data RGB from the timing controller 101 and then outputs the digital video data RGB to the first latch 53. The first latch 53 samples digital video data RGB from the data register 52 in response to a sampling signal sequentially input from the shift register 51 and latches the data RGB Simultaneously output. The second latch 54 latches the data input from the first latch 53 and then is latched simultaneously with the second latch 54 of the other source drive ICs during the low logic period of the source output enable signal SOE And outputs digital video data.

The linear single gamma compensation voltages SG0 to SGi are input to the single DAC 55 from the voltage dividing circuit 61. [ The voltage dividing circuit 61 divides the linear single gamma reference voltages SGO to SGi by the number of gradations of data. The single DAC 55 is constituted by a circuit as shown in Fig. 6, converts the digital video data Data1 into linear single gamma compensation voltages to generate analog data voltages, and supplies the analog data voltages to the output buffers 56 . The output buffer 56 includes an output buffer having an offset canceling function to supply the analog data voltage from the single DAC 55 to the data lines D1 to Dk.

7 is an equivalent circuit diagram showing a part of the pixel array of the liquid crystal display device shown in Fig.

Referring to FIG. 7, each of the liquid crystal cells receives data voltages from two neighboring data lines via two TFTs, or receives data voltages supplied from neighboring data lines and a reference voltage supply line and a reference voltage Ref ).

The first liquid crystal cell Clc (R) is connected to the first data line D1 and the first reference voltage supply line through the first and second TFTs TFT1 and TFT2 as liquid crystal cells of a red subpixel. The drain electrode of the first TFT (TFT1) is connected to the first data line D1, and the source electrode thereof is connected to the first pixel electrode of the first liquid crystal cell Clc (R). The gate electrode of the first TFT (TFT1) is connected to the first gate line G1. The drain electrode of the second TFT (TFT2) is connected to the first reference voltage supply line and its source electrode is connected to the second pixel electrode of the first liquid crystal cell (Clc (R)). The gate electrode of the second TFT (TFT2) is connected to the first gate line G1. The polarity of the data voltage charged in the first liquid crystal cell Clc (R) is determined according to the first data voltage R + relative to the reference voltage Ref.

The second liquid crystal cell Clc (G) is connected to the first reference voltage supply line and the second data line D2 through the third and fourth TFTs TFT3 and TFT4 as liquid crystal cells of a green subpixel. The drain electrode of the third TFT (TFT3) is connected to the first reference voltage supply line and its source electrode is connected to the first pixel electrode of the second liquid crystal cell Clc (G). The gate electrode of the third TFT (TFT3) is connected to the first gate line G1. The drain electrode of the fourth TFT (TFT4) is connected to the second data line D2, and the source electrode thereof is connected to the second pixel electrode of the second liquid crystal cell Clc (G). The gate electrode of the fourth TFT (TFT4) is connected to the first gate line G1. The polarity of the data voltage charged in the second liquid crystal cell Clc (G) is determined according to the second data voltage G + with respect to the reference voltage Ref.

The third liquid crystal cell Clc (B) is connected to the second data line D2 and the third data line D3 through the fifth and sixth TFTs TFT5 and TFT6 as liquid crystal cells of a blue subpixel. The drain electrode of the fifth TFT (TFT5) is connected to the second data line D2, and the source electrode thereof is connected to the first pixel electrode of the third liquid crystal cell Clc (B). The gate electrode of the fifth TFT (TFT5) is connected to the first gate line G1. The drain electrode of the sixth TFT (TFT6) is connected to the third data line D3, and the source electrode thereof is connected to the second pixel electrode of the third liquid crystal cell Clc (B). The gate electrode of the sixth TFT (TFT6) is connected to the first gate line G1. The polarity of the data voltage charged in the third liquid crystal cell Clc (B) is determined according to the third data voltage B- relative to the second data voltage G +.

The input of each group of source drive ICs is determined in the timing controller 101 in consideration of the polarity reversal of the data voltages to be actually charged in the subpixels. The timing controller 101 determines an input value of the source drive IC by a tone value input from an EEPROM (Electrically Erasable Programmable Read-Only Memory) storing a lookup table in which each input / output for each gradation is defined. On the other hand, the operation of the Vcomless-type pixel array as shown in FIG. 7 and variations thereof are described in Korean Patent Application No. 10-2008-0088979 (2008. 09.09), Korean Patent Application No. 10-2008 -0106149 (Oct. 28, 2008).

8 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention. 9 is an equivalent circuit diagram showing a part of the pixel array of the liquid crystal display device shown in Fig.

8 and 9, the liquid crystal display according to the second embodiment of the present invention includes a liquid crystal display panel 200, a data driving circuit (not shown) connected to the data lines D1 to Dm of the liquid crystal display panel 200, A gate driving circuit 204 connected to the gate lines G1 to Gn of the liquid crystal display panel 200, a timing controller 201 for controlling the data driving circuit 203 and the gate driving circuit 204 A module power supply circuit 202 for generating a driving voltage of the liquid crystal display panel 200, and an AC common voltage generating unit 206 for generating an AC common voltage.

The liquid crystal display panel 200 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 200 includes a pixel array for displaying video data.

TFTs formed at intersections of the data lines D1 to Dm, the gate lines G1 to Gn, the data lines D1 to Dm and the gate lines G1 to Gn are formed in the pixel array of the lower glass substrate, A pixel electrode of the liquid crystal cell Clc connected to the TFTs T1 to T12, a storage capacitor Cst connected to the liquid crystal cell, and the like are formed.

On the upper glass substrate of the liquid crystal display panel 200, a black matrix, a color filter, and the like are formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 200, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

A first common voltage Vcom_odd is supplied to the liquid crystal cells Clc arranged in the odd horizontal lines LINE # 1 and LINE # 3 of the pixel array on the upper glass substrate or the lower glass substrate of the liquid crystal display panel. One common electrode Ecom1 is formed. A second common voltage Vcom_even is supplied to the liquid crystal cells Clc arranged in the superior horizontal lines LINE # 2 and LINE # 4 of the pixel array on the upper glass substrate or the lower glass substrate of the liquid crystal display panel. Two common electrodes Ecom2 are formed. During the N (N is a positive integer) frame period, the first common voltage Vcom_odd is higher than the data voltage, while the second AC common voltage Vcom_even is lower than the data voltage. The potentials of the first and second common voltages Vcom_odd and Vcom_even are inverted every horizontal period and every frame. Therefore, during the (N + 1) th frame period, the first common voltage Vcom_odd changes to a voltage lower than the data voltage, while the second common voltage Vcom_even changes to a voltage higher than the data voltage. 10 and 11, the liquid crystal cells Clc are charged with a high positive polarity data voltage with respect to the first and second common voltages Vcom_odd and Vcom_even or a negative polarity data voltage with respect to the common voltages Vcom_odd and Vcom_even .

Such a liquid crystal display device may be driven by a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, or by an IPS (In Plane Switching) mode or an FFS And is driven by a horizontal electric field driving method. This liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light source of the backlight unit may include any one of HCFL, CCFL, EEFL, and LED, or two or more kinds of light sources.

The data driving circuit 203 includes a plurality of source drive ICs. Each of the source drive ICs converts the digital video data into the analog data voltage with the linear single gamma compensation voltages Vs_gamma whose voltage linearly increases as the gray level value increases as shown in FIG. The linear single gamma compensation voltages Vs_gamma are voltages divided between the high potential power supply voltage Vs_gamma and the low potential power supply voltage Vss. The high-potential power-supply voltage Vs_gamma is lower than the conventional high-potential power-supply voltage Vdd shown in FIG. Each of the source drive ICs may be mounted on a COG (Chip On Glass) process or a TCP (Tape Carrier Package) and adhered to a lower glass substrate by a TAB (Tape Automated Bonding) process. The circuit configuration of the source drive ICs is substantially the same as in Figs. 5 and 6. Fig.

The gate drive circuit 204 includes a plurality of gate drive ICs. The gate driving circuit 204 includes a shift register for sequentially shifting the gate driving voltage in response to the gate timing control signals GSP, GSC and GOE from the timing controller 201, Pulse) are sequentially supplied. The gate drive ICs may be connected to gate lines of a lower glass substrate by a TAB process or may be formed directly on a lower glass substrate together with a pixel array by a GIP (Gate In Panel) process.

The timing controller 201 receives RGB digital video data, a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, and a data enable signal Data Enable from the system board 205 through an interface receiving circuit such as an LVDS interface and a TMDS interface, , DE, and a dot clock (CLK). The timing controller 201 transmits the RGB digital video data to the source drive ICs of the data driving circuit 203 in a mini LVDS interface manner. The timing controller 201 generates data timing control signals SSP, SSC and SOE for controlling the operation timings of the source drive ICs using the timing signals Vsync, Hsync, DE and CLK, And generates gate timing control signals (GSP, GSC, GOE) for controlling the operation timing. The timing controller 201 also generates a control signal Cswing for controlling the output of the AC common voltage generator 206. [ The timing controller 201 supplies the gate timing control signal < RTI ID = 0.0 > (I) < / RTI > so that digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array of the liquid crystal display panel 200 at a frame frequency of 60 x i And the frequency of the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

The module power supply circuit 202 is constituted by a DC-DC conversion circuit including a boost converter, a regulator, a pulse width modulation IC, a PWM IC, and a charge pump. do. The module power supply circuit 202 adjusts a voltage Vin input from the system board 205 to generate driving voltages of the liquid crystal display panel 200. The driving voltages generated from the module power supply circuit 202 are applied to the gate high voltage Vgh and the gate low voltage Vgl, the high potential power supply voltage Vdd, the logic power supply voltage Vcc and the linear single gamma reference voltages SGO- SGi, first and second common voltages Vcom_odd and Vcom_even, and the like.

The AC common voltage generator 206 supplies the first common voltage Vcom_odd to the first common electrode Ecom1 under the control of the timing controller 201 and supplies the second common voltage Vcom_even to the second common electrode Ecom2 ). The AC common voltage generating unit 206 generates a common voltage Vcom that is supplied to the first and second common electrodes Ecom1 and Ecom2 in every horizontal period and every frame in response to the control signal Cswing input from the timing controller 201 Inverts the potentials of the voltages Vcom_odd and Vcom_even.

9, the pixel array includes liquid crystal cells of the odd horizontal lines LINE # 1 and LINE # 3 on which the first common electrode Ecom1 is formed, Liquid crystal cells. The first and second common electrodes Ecom1 and Ecom2 are separated with an insulating layer therebetween.

The connection relationship of the liquid crystal cells of the radial horizontal lines LINE # 1 and LINE # 3 will be described with reference to the first horizontal line LINE # 1 shown in FIG. 9, for example. The liquid crystal cells arranged in the first horizontal line LINE # 1 are referred to as a first liquid crystal cell Clc, a second liquid crystal cell Clc and a third liquid crystal cell Clc from left to right. The first liquid crystal cell Clc of the first horizontal line LINE1 is connected to the first data line D1 through the first TFT T1 and is connected to the first common electrode Ecom1. The drain electrode of the first TFT T1 is connected to the first data line D1 and its source electrode is connected to the pixel electrode of the first liquid crystal cell Clc. The gate electrode of the first TFT (T1) is connected to the second gate line (G2). The second liquid crystal cell Clc of the first horizontal line LINE1 is connected to the second data line D2 through the second TFT T2 and is connected to the first common electrode Ecom1. The drain electrode of the second TFT T2 is connected to the second data line D2 and the source electrode thereof is connected to the pixel electrode of the second liquid crystal cell Clc. The gate electrode of the second TFT T2 is connected to the first gate line G1. The third liquid crystal cell Clc of the first horizontal line LINE1 is connected to the third data line D3 through the third TFT T3 and is connected to the first common electrode Ecom1. The drain electrode of the third TFT T3 is connected to the third data line D3 and the source electrode thereof is connected to the pixel electrode of the third liquid crystal cell Clc. And the gate electrode of the third TFT T3 is connected to the second gate line G2.

The connection relationship of the liquid crystal cells of the excellent horizontal lines LINE # 2 and LINE # 4 will be described with reference to the second horizontal line LINE # 2 shown in FIG. 9, for example. The liquid crystal cells arranged in the second horizontal line LINE # 2 are referred to as the fourth liquid crystal cell Clc, the fifth liquid crystal cell Clc and the sixth liquid crystal cell Clc from the left to the right. The fourth liquid crystal cell Clc of the second horizontal line LINE2 is connected to the first data line D1 through the fourth TFT T4 and is connected to the second common electrode Ecom2. The drain electrode of the fourth TFT T4 is connected to the first data line D1 and the source electrode thereof is connected to the pixel electrode of the fourth liquid crystal cell Clc. And the gate electrode of the fourth TFT T4 is connected to the third gate line G3. The fifth liquid crystal cell Clc of the second horizontal line LINE2 is connected to the second data line D2 through the fifth TFT T5 and is connected to the second common electrode Ecom2. The drain electrode of the fifth TFT T5 is connected to the second data line D2 and the source electrode thereof is connected to the pixel electrode of the fifth liquid crystal cell Clc. And the gate electrode of the fifth TFT T5 is connected to the second gate line G2. The sixth liquid crystal cell Clc of the second horizontal line LINE2 is connected to the third data line D3 through the sixth TFT T6 and is connected to the second common electrode Ecom2. The drain electrode of the sixth TFT T6 is connected to the third data line D3 and the source electrode thereof is connected to the pixel electrode of the sixth liquid crystal cell Clc. And the gate electrode of the sixth TFT (T) is connected to the third gate line G3.

When a gate pulse, a data voltage, and first and second common voltages Vcom_odd and Vcom_even as shown in FIG. 10 are supplied to the pixel array as shown in FIG. 9, the liquid crystal cells of the pixel array are driven in the form of one dot. Here, the gradation versus transmittance characteristic of the liquid crystal cell for charging the high positive polarity data voltage with respect to the first common voltage Vcom_odd is the same as the solid line curve in FIG. The gradation versus transmittance characteristic of the liquid crystal cell for charging the lower negative data voltage with respect to the second common voltage Vcom_even is the same as the dotted line curve in FIG.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a graph showing a positive gamma compensation voltage and a negative gamma compensation voltage in a conventional liquid crystal display device.

2 is a circuit diagram showing a dual DAC, a multiplexer, an output circuit, and the like in a conventional source driver IC.

3 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

4 is a graph showing the linear single gamma compensation voltage of the present invention.

5 is a detailed block diagram of the source drive IC shown in FIG.

FIG. 6 is a circuit diagram showing the single DAC and the output buffer shown in FIG. 5 in detail.

7 is an equivalent circuit diagram showing a part of the pixel array of the liquid crystal display device shown in Fig.

8 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.

9 is an equivalent circuit diagram showing a part of the pixel array of the liquid crystal display device shown in Fig.

FIG. 10 is a waveform diagram showing an example of a gate pulse, a data voltage, and an AC common voltage for driving the liquid crystal display shown in FIG.

FIG. 11 is a graph showing the transmittance characteristic of each liquid crystal display device shown in FIG.

Description of the Related Art

10: liquid crystal display panel 11: timing controller

12: data driving circuit 13: gate driving circuit

15: DC-DC converter

Claims (8)

And a plurality of reference voltage supply lines formed in a direction parallel to the data lines, wherein the plurality of data lines and the plurality of gate lines intersect and are formed at intersections of the data lines and the gate lines, A liquid crystal display panel having a pixel array in which liquid crystal cells are arranged in a matrix form; A data driving circuit for converting the digital video data into a data voltage using the linear single gamma compensation voltages whose voltage increases as the gray level becomes higher, and supplying the data voltage to the data lines; And And a gate driving circuit for sequentially supplying gate pulses to the gate lines, The liquid crystal cells, A first TFT connected to the first data line and receiving a data voltage from the first data line through the first TFT, and a second TFT connected to one of the reference voltage supply lines, A liquid crystal cell; And a second TFT which is supplied with the reference voltage through a third TFT connected to one of the reference voltage supply lines and is supplied with a data voltage from the second data line through a fourth TFT connected to the second data line, A liquid crystal cell; And And a second TFT connected to the third data line receives a data voltage from the second data line through a fifth TFT connected to the second data line and receives a data voltage from the third data line through a sixth TFT connected to the third data line And a third liquid crystal cell. The method according to claim 1, Wherein the linear single gamma compensation voltages are generated by a partial pressure of a high potential power supply voltage and have a voltage level along a straight line without an inflection point. 3. The method of claim 2, Wherein the reference voltage supply lines include a reference voltage of 1/3 voltage relative to the high potential power supply voltage, a reference voltage of 1/2 voltage of the high potential power supply voltage, a reference voltage of 2/3 of the high potential power supply voltage Wherein at least one of the liquid crystal molecules is supplied. The method according to claim 1, The data drive circuit includes a plurality of source drive ICs, Each of the source drive ICs, And a single digital-to-analog converter for converting the digital video data into the data voltage only with the linear single gamma compensation voltages. delete A first common electrode formed on the odd horizontal lines while the plurality of liquid crystal cells are arranged in a matrix form, and a second common electrode formed on the odd-numbered horizontal lines, wherein the first common electrode and the second common electrode intersect with the data lines and the gate lines, A liquid crystal display panel having a pixel array having a second common electrode formed on excellent horizontal lines; A data driving circuit for converting the digital video data into a data voltage using only linear single gamma compensation voltages whose voltage increases as the gray level becomes higher, and supplying the data voltage to the data lines; And And a gate driving circuit for sequentially supplying gate pulses to the gate lines, The odd horizontal lines, A first liquid crystal cell connected to the first data line and the second gate line through the first TFT and connected to the first common electrode; A second liquid crystal cell connected to the second data line and the first gate line through a second TFT and connected to the first common electrode; And And a third liquid crystal cell connected to the third data line and the second gate line through a third TFT and connected to the first common electrode, The excellent horizontal lines include, A fourth liquid crystal cell connected to the first data line and the third gate line through a fourth TFT and connected to the second common electrode; A fifth liquid crystal cell connected to the second data line and the second gate line via a fifth TFT and connected to the second common electrode; And And a sixth liquid crystal cell connected to the third data line and the third gate line through a sixth TFT and connected to the second common electrode. delete delete

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